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mediatek: generate bootloader artifacts for mt7988_rfb
Switch to OpenWrt uImage.FIT bootmethod and include various bootloader
artifacts with the generated binaries.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit 035a88ae55)
This commit is contained in:
Daniel Golle
parent
35d123adfe
commit
ed370ec424
@ -1,134 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2022 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*/
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/dts-v1/;
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#include "mt7988a-rfb-spim-nand.dtsi"
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#include <dt-bindings/pinctrl/mt65xx.h>
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#include <dt-bindings/leds/common.h>
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/ {
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model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB";
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compatible = "mediatek,mt7988a-dsa-10g-spim-snand",
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"mediatek,mt7988a-rfb-snand",
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"mediatek,mt7988";
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chosen {
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bootargs = "console=ttyS0,115200n1 loglevel=8 \
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earlycon=uart8250,mmio32,0x11000000 \
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pci=pcie_bus_perf";
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};
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memory {
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reg = <0 0x40000000 0 0x40000000>;
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};
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};
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ð {
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pinctrl-0 = <&mdio0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&gmac0 {
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status = "okay";
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};
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&gmac1 {
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status = "okay";
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phy-mode = "internal";
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phy-connection-type = "internal";
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phy = <&int_2p5g_phy>;
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};
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&gmac2 {
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status = "okay";
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phy-mode = "usxgmii";
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phy-connection-type = "usxgmii";
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phy = <&phy8>;
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};
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&mdio_bus {
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/* external Aquantia AQR113C */
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phy0: ethernet-phy@0 {
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reg = <0>;
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compatible = "ethernet-phy-ieee802.3-c45";
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reset-gpios = <&pio 72 1>;
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reset-assert-us = <100000>;
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reset-deassert-us = <221000>;
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};
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/* external Aquantia AQR113C */
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phy8: ethernet-phy@8 {
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reg = <8>;
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compatible = "ethernet-phy-ieee802.3-c45";
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reset-gpios = <&pio 71 1>;
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reset-assert-us = <100000>;
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reset-deassert-us = <221000>;
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};
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/* external Maxlinear GPY211C */
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phy5: ethernet-phy@5 {
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reg = <5>;
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compatible = "ethernet-phy-ieee802.3-c45";
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phy-mode = "2500base-x";
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};
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/* external Maxlinear GPY211C */
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phy13: ethernet-phy@13 {
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reg = <13>;
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compatible = "ethernet-phy-ieee802.3-c45";
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phy-mode = "2500base-x";
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};
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};
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&int_2p5g_phy {
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pinctrl-names = "i2p5gbe-led";
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pinctrl-0 = <&i2p5gbe_led0_pins>;
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};
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&switch {
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status = "okay";
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};
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&gsw_phy0 {
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe0_led0_pins>;
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};
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&gsw_phy0_led0 {
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status = "okay";
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color = <LED_COLOR_ID_GREEN>;
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};
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&gsw_phy1 {
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe1_led0_pins>;
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};
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&gsw_phy1_led0 {
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status = "okay";
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color = <LED_COLOR_ID_GREEN>;
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};
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&gsw_phy2 {
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe2_led0_pins>;
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};
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&gsw_phy2_led0 {
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status = "okay";
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color = <LED_COLOR_ID_GREEN>;
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};
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&gsw_phy3 {
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe3_led0_pins>;
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};
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&gsw_phy3_led0 {
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status = "okay";
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color = <LED_COLOR_ID_GREEN>;
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};
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@ -0,0 +1,33 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2021 MediaTek Inc.
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* Author: Frank Wunderlich <frank-w@public-files.de>
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*/
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/dts-v1/;
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/plugin/;
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/ {
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compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
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fragment@0 {
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target = <&mmc0>;
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__overlay__ {
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&mmc0_pins_emmc_51>;
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pinctrl-1 = <&mmc0_pins_emmc_51>;
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bus-width = <8>;
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max-frequency = <200000000>;
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cap-mmc-highspeed;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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hs400-ds-delay = <0x12814>;
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vqmmc-supply = <®_1p8v>;
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vmmc-supply = <®_3p3v>;
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non-removable;
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no-sd;
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no-sdio;
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status = "okay";
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};
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};
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};
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@ -0,0 +1,41 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2022 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
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fragment@0 {
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target = <&mdio_bus>;
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <0>;
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/* external Aquantia AQR113C */
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phy0: ethernet-phy@0 {
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reg = <0>;
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compatible = "ethernet-phy-ieee802.3-c45";
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reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>;
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reset-assert-us = <100000>;
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reset-deassert-us = <221000>;
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};
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};
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};
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fragment@1 {
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target = <&gmac1>;
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__overlay__ {
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phy-mode = "usxgmii";
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phy-connection-type = "usxgmii";
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phy = <&phy0>;
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status = "okay";
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};
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};
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};
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@ -0,0 +1,30 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2022 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*/
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/dts-v1/;
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/plugin/;
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/ {
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compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
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fragment@0 {
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target = <&gmac1>;
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__overlay__ {
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phy-mode = "internal";
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phy-connection-type = "internal";
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phy = <&int_2p5g_phy>;
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status = "okay";
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};
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};
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fragment@1 {
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target = <&int_2p5g_phy>;
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__overlay__ {
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pinctrl-names = "i2p5gbe-led";
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pinctrl-0 = <&i2p5gbe_led0_pins>;
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};
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};
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};
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@ -0,0 +1,39 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2022 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
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fragment@0 {
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target = <&mdio_bus>;
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <0>;
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/* external Maxlinear GPY211C */
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phy13: ethernet-phy@13 {
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reg = <13>;
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compatible = "ethernet-phy-ieee802.3-c45";
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phy-mode = "2500base-x";
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};
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};
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};
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fragment@1 {
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target = <&gmac1>;
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__overlay__ {
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phy-mode = "2500base-x";
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phy-connection-type = "2500base-x";
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phy = <&phy13>;
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status = "okay";
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};
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};
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};
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@ -0,0 +1,47 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2022 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
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fragment@0 {
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target = <&i2c2>;
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__overlay__ {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_0_pins>;
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status = "okay";
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};
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};
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fragment@1 {
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target-path = "/";
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__overlay__ {
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sfp_esp1: sfp@1 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c2>;
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mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
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los-gpios = <&pio 81 GPIO_ACTIVE_HIGH>;
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tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>;
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maximum-power-milliwatt = <3000>;
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};
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};
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};
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fragment@2 {
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target = <&gmac1>;
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__overlay__ {
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phy-mode = "10gbase-r";
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managed = "in-band-status";
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sfp = <&sfp_esp1>;
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status = "okay";
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};
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};
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};
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@ -0,0 +1,41 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2022 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
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fragment@0 {
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target = <&mdio_bus>;
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <0>;
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/* external Aquantia AQR113C */
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phy8: ethernet-phy@8 {
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reg = <8>;
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compatible = "ethernet-phy-ieee802.3-c45";
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reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>;
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reset-assert-us = <100000>;
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reset-deassert-us = <221000>;
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};
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};
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};
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fragment@1 {
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target = <&gmac2>;
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__overlay__ {
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phy-mode = "usxgmii";
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phy-connection-type = "usxgmii";
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phy = <&phy8>;
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status = "okay";
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};
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};
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};
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@ -0,0 +1,39 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2022 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
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fragment@0 {
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target = <&mdio_bus>;
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <0>;
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/* external Maxlinear GPY211C */
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phy5: ethernet-phy@5 {
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reg = <5>;
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compatible = "ethernet-phy-ieee802.3-c45";
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phy-mode = "2500base-x";
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};
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};
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};
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fragment@1 {
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target = <&gmac2>;
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__overlay__ {
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phy-mode = "2500base-x";
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phy-connection-type = "2500base-x";
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phy = <&phy5>;
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status = "okay";
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};
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};
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};
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@ -0,0 +1,47 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2022 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
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fragment@0 {
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target = <&i2c1>;
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__overlay__ {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_sfp_pins>;
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status = "okay";
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};
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};
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fragment@1 {
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target-path = "/";
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__overlay__ {
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sfp_esp0: sfp@0 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>;
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los-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
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tx-disable-gpios = <&pio 29 GPIO_ACTIVE_HIGH>;
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maximum-power-milliwatt = <3000>;
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};
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};
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};
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fragment@2 {
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target = <&gmac2>;
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__overlay__ {
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phy-mode = "10gbase-r";
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managed = "in-band-status";
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sfp = <&sfp_esp0>;
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status = "okay";
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};
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};
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};
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@ -0,0 +1,31 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2023 MediaTek Inc.
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* Author: Frank Wunderlich <frank-w@public-files.de>
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
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fragment@1 {
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target-path = <&mmc0>;
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__overlay__ {
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&mmc0_pins_sdcard>;
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pinctrl-1 = <&mmc0_pins_sdcard>;
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cd-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
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bus-width = <4>;
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max-frequency = <52000000>;
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cap-sd-highspeed;
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_3p3v>;
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no-mmc;
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status = "okay";
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};
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};
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};
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@ -0,0 +1,69 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2022 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
|
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*/
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/dts-v1/;
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/plugin/;
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/ {
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compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
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fragment@0 {
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target = <&snand>;
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__overlay__ {
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status = "okay";
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flash@0 {
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compatible = "spi-nand";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <52000000>;
|
||||
spi-tx-buswidth = <4>;
|
||||
spi-rx-buswidth = <4>;
|
||||
mediatek,nmbm;
|
||||
mediatek,bmt-max-ratio = <1>;
|
||||
mediatek,bmt-max-reserved-blocks = <64>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "BL2";
|
||||
reg = <0x00000 0x0100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x0100000 0x0080000>;
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
label = "Factory";
|
||||
reg = <0x180000 0x0400000>;
|
||||
};
|
||||
|
||||
partition@580000 {
|
||||
label = "FIP";
|
||||
reg = <0x580000 0x0200000>;
|
||||
};
|
||||
|
||||
partition@780000 {
|
||||
label = "ubi";
|
||||
reg = <0x780000 0x7080000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target = <&bch>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1,70 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2022 MediaTek Inc.
|
||||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt7988a-rfb.dtsi"
|
||||
|
||||
&pio {
|
||||
spi0_flash_pins: spi0-pins {
|
||||
mux {
|
||||
function = "spi";
|
||||
groups = "spi0", "spi0_wp_hold";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_flash_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi_nand: spi_nand@0 {
|
||||
compatible = "spi-nand";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <52000000>;
|
||||
spi-tx-buswidth = <4>;
|
||||
spi-rx-buswidth = <4>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&spi_nand {
|
||||
mediatek,nmbm;
|
||||
mediatek,bmt-max-ratio = <1>;
|
||||
mediatek,bmt-max-reserved-blocks = <64>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "BL2";
|
||||
reg = <0x00000 0x0100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x0100000 0x0080000>;
|
||||
};
|
||||
|
||||
factory: partition@180000 {
|
||||
label = "Factory";
|
||||
reg = <0x180000 0x0400000>;
|
||||
};
|
||||
|
||||
partition@580000 {
|
||||
label = "FIP";
|
||||
reg = <0x580000 0x0200000>;
|
||||
};
|
||||
|
||||
partition@780000 {
|
||||
label = "ubi";
|
||||
reg = <0x780000 0x7080000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,64 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2022 MediaTek Inc.
|
||||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||
|
||||
fragment@0 {
|
||||
target = <&spi0>;
|
||||
__overlay__ {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_flash_pins>;
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "spi-nand";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <52000000>;
|
||||
spi-tx-buswidth = <4>;
|
||||
spi-rx-buswidth = <4>;
|
||||
mediatek,nmbm;
|
||||
mediatek,bmt-max-ratio = <1>;
|
||||
mediatek,bmt-max-reserved-blocks = <64>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "BL2";
|
||||
reg = <0x00000 0x0100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x0100000 0x0080000>;
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
label = "Factory";
|
||||
reg = <0x180000 0x0400000>;
|
||||
};
|
||||
|
||||
partition@580000 {
|
||||
label = "FIP";
|
||||
reg = <0x580000 0x0200000>;
|
||||
};
|
||||
|
||||
partition@780000 {
|
||||
label = "ubi";
|
||||
reg = <0x780000 0x7080000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,59 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2022 MediaTek Inc.
|
||||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||
|
||||
fragment@0 {
|
||||
target = <&spi2>;
|
||||
__overlay__ {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2_flash_pins>;
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-cal-enable;
|
||||
spi-cal-mode = "read-data";
|
||||
spi-cal-datalen = <7>;
|
||||
spi-cal-data = /bits/ 8 <
|
||||
0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */
|
||||
spi-cal-addrlen = <1>;
|
||||
spi-cal-addr = /bits/ 32 <0x0>;
|
||||
reg = <0>;
|
||||
spi-max-frequency = <52000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
|
||||
partition@00000 {
|
||||
label = "BL2";
|
||||
reg = <0x00000 0x0040000>;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x40000 0x0010000>;
|
||||
};
|
||||
partition@50000 {
|
||||
label = "Factory";
|
||||
reg = <0x50000 0x0200000>;
|
||||
};
|
||||
partition@250000 {
|
||||
label = "FIP";
|
||||
reg = <0x250000 0x0080000>;
|
||||
};
|
||||
partition@2D0000 {
|
||||
label = "firmware";
|
||||
reg = <0x2D0000 0x1D30000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -6,8 +6,35 @@
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt7988a.dtsi"
|
||||
#include <dt-bindings/pinctrl/mt65xx.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
|
||||
|
||||
/ {
|
||||
model = "MediaTek MT7988A Reference Board";
|
||||
compatible = "mediatek,mt7988a-rfb",
|
||||
"mediatek,mt7988";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200n1 loglevel=8 \
|
||||
earlycon=uart8250,mmio32,0x11000000 \
|
||||
pci=pcie_bus_perf";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
ð {
|
||||
pinctrl-0 = <&mdio0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
proc-supply = <&rt5190_buck3>;
|
||||
};
|
||||
@ -32,6 +59,50 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&switch {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gsw_phy0 {
|
||||
pinctrl-names = "gbe-led";
|
||||
pinctrl-0 = <&gbe0_led0_pins>;
|
||||
};
|
||||
|
||||
&gsw_phy0_led0 {
|
||||
status = "okay";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
&gsw_phy1 {
|
||||
pinctrl-names = "gbe-led";
|
||||
pinctrl-0 = <&gbe1_led0_pins>;
|
||||
};
|
||||
|
||||
&gsw_phy1_led0 {
|
||||
status = "okay";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
&gsw_phy2 {
|
||||
pinctrl-names = "gbe-led";
|
||||
pinctrl-0 = <&gbe2_led0_pins>;
|
||||
};
|
||||
|
||||
&gsw_phy2_led0 {
|
||||
status = "okay";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
&gsw_phy3 {
|
||||
pinctrl-names = "gbe-led";
|
||||
pinctrl-0 = <&gbe3_led0_pins>;
|
||||
};
|
||||
|
||||
&gsw_phy3_led0 {
|
||||
status = "okay";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
@ -89,26 +160,18 @@
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie2_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie3_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -124,44 +187,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pio {
|
||||
pcie0_pins: pcie0-pins {
|
||||
mux {
|
||||
function = "pcie";
|
||||
groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
|
||||
"pcie_wake_n0_0";
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_pins: pcie1-pins {
|
||||
mux {
|
||||
function = "pcie";
|
||||
groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
|
||||
"pcie_wake_n1_0";
|
||||
};
|
||||
};
|
||||
|
||||
pcie2_pins: pcie2-pins {
|
||||
mux {
|
||||
function = "pcie";
|
||||
groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
|
||||
"pcie_wake_n2_0";
|
||||
};
|
||||
};
|
||||
|
||||
pcie3_pins: pcie3-pins {
|
||||
mux {
|
||||
function = "pcie";
|
||||
groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
|
||||
"pcie_wake_n3_0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -152,6 +152,65 @@
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&lvts 0>;
|
||||
trips {
|
||||
cpu_trip_crit: crit {
|
||||
temperature = <125000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
|
||||
cpu_trip_hot: hot {
|
||||
temperature = <120000>;
|
||||
hysteresis = <2000>;
|
||||
type = "hot";
|
||||
};
|
||||
|
||||
cpu_trip_active_high: active-high {
|
||||
temperature = <115000>;
|
||||
hysteresis = <2000>;
|
||||
type = "active";
|
||||
};
|
||||
|
||||
cpu_trip_active_med: active-med {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "active";
|
||||
};
|
||||
|
||||
cpu_trip_active_low: active-low {
|
||||
temperature = <40000>;
|
||||
hysteresis = <2000>;
|
||||
type = "active";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
cpu-active-high {
|
||||
/* active: set fan to cooling level 2 */
|
||||
cooling-device = <&fan 3 3>;
|
||||
trip = <&cpu_trip_active_high>;
|
||||
};
|
||||
|
||||
cpu-active-low {
|
||||
/* active: set fan to cooling level 1 */
|
||||
cooling-device = <&fan 2 2>;
|
||||
trip = <&cpu_trip_active_med>;
|
||||
};
|
||||
|
||||
cpu-passive {
|
||||
/* passive: set fan to cooling level 0 */
|
||||
cooling-device = <&fan 1 1>;
|
||||
trip = <&cpu_trip_active_low>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupt-parent = <&gic>;
|
||||
@ -161,6 +220,24 @@
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
reg_1p8v: regulator-1p8v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
@ -386,6 +463,80 @@
|
||||
groups = "uart0";
|
||||
};
|
||||
};
|
||||
|
||||
snfi_pins: snfi-pins {
|
||||
mux {
|
||||
function = "flash";
|
||||
groups = "snfi";
|
||||
};
|
||||
};
|
||||
|
||||
spi0_pins: spi0-pins {
|
||||
mux {
|
||||
function = "spi";
|
||||
groups = "spi0";
|
||||
};
|
||||
};
|
||||
|
||||
spi0_flash_pins: spi0-flash-pins {
|
||||
mux {
|
||||
function = "spi";
|
||||
groups = "spi0", "spi0_wp_hold";
|
||||
};
|
||||
};
|
||||
|
||||
spi1_pins: spi1-pins {
|
||||
mux {
|
||||
function = "spi";
|
||||
groups = "spi1";
|
||||
};
|
||||
};
|
||||
|
||||
spi2_pins: spi2-pins {
|
||||
mux {
|
||||
function = "spi";
|
||||
groups = "spi2";
|
||||
};
|
||||
};
|
||||
|
||||
spi2_flash_pins: spi2-flash-pins {
|
||||
mux {
|
||||
function = "spi";
|
||||
groups = "spi2", "spi2_wp_hold";
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_pins: pcie0-pins {
|
||||
mux {
|
||||
function = "pcie";
|
||||
groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
|
||||
"pcie_wake_n0_0";
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_pins: pcie1-pins {
|
||||
mux {
|
||||
function = "pcie";
|
||||
groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
|
||||
"pcie_wake_n1_0";
|
||||
};
|
||||
};
|
||||
|
||||
pcie2_pins: pcie2-pins {
|
||||
mux {
|
||||
function = "pcie";
|
||||
groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
|
||||
"pcie_wake_n2_0";
|
||||
};
|
||||
};
|
||||
|
||||
pcie3_pins: pcie3-pins {
|
||||
mux {
|
||||
function = "pcie";
|
||||
groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
|
||||
"pcie_wake_n3_0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sgmiisys0: syscon@10060000 {
|
||||
@ -420,24 +571,24 @@
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
xfi_pextp0: xfi_pextp@11f20000 {
|
||||
compatible = "mediatek,mt7988-xfi_pextp",
|
||||
"mediatek,mt7988-xfi_pextp_0",
|
||||
xfi_pextp0: xfi-pextp@11f20000 {
|
||||
compatible = "mediatek,mt7988-xfi-pextp",
|
||||
"mediatek,mt7988-xfi-pextp_0",
|
||||
"syscon";
|
||||
reg = <0 0x11f20000 0 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
xfi_pextp1: xfi_pextp@11f30000 {
|
||||
compatible = "mediatek,mt7988-xfi_pextp",
|
||||
"mediatek,mt7988-xfi_pextp_1",
|
||||
xfi_pextp1: xfi-pextp@11f30000 {
|
||||
compatible = "mediatek,mt7988-xfi-pextp",
|
||||
"mediatek,mt7988-xfi-pextp_1",
|
||||
"syscon";
|
||||
reg = <0 0x11f30000 0 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
xfi_pll: xfi_pll@11f40000 {
|
||||
compatible = "mediatek,mt7988-xfi_pll", "syscon";
|
||||
xfi_pll: xfi-pll@11f40000 {
|
||||
compatible = "mediatek,mt7988-xfi-pll", "syscon";
|
||||
reg = <0 0x11f40000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -470,6 +621,35 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
snand: spi@11001000 {
|
||||
compatible = "mediatek,mt7986-snand";
|
||||
reg = <0 0x11001000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_SPINFI>,
|
||||
<&infracfg CLK_INFRA_NFI>;
|
||||
clock-names = "pad_clk", "nfi_clk";
|
||||
assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
|
||||
<&topckgen CLK_TOP_NFI1X_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
|
||||
<&topckgen CLK_TOP_MPLL_D8>;
|
||||
nand-ecc-engine = <&bch>;
|
||||
mediatek,quad-spi;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&snfi_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bch: ecc@11002000 {
|
||||
compatible = "mediatek,mt7686-ecc";
|
||||
reg = <0 0x11002000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topckgen CLK_TOP_NFI1X_SEL>;
|
||||
clock-names = "nfiecc_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@11003000 {
|
||||
compatible = "mediatek,mt7988-i2c",
|
||||
"mediatek,mt7981-i2c";
|
||||
@ -525,10 +705,118 @@
|
||||
<&infracfg CLK_INFRA_66M_SPI0_HCK>;
|
||||
clock-names = "parent-clk", "sel-clk", "spi-clk",
|
||||
"spi-hclk";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@11008000 {
|
||||
compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm";
|
||||
reg = <0 0x11008000 0 0x100>;
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topckgen CLK_TOP_MPLL_D2>,
|
||||
<&topckgen CLK_TOP_SPI_SEL>,
|
||||
<&infracfg CLK_INFRA_104M_SPI1>,
|
||||
<&infracfg CLK_INFRA_66M_SPI1_HCK>;
|
||||
clock-names = "parent-clk", "sel-clk", "spi-clk",
|
||||
"spi-hclk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi2: spi@11009000 {
|
||||
compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
|
||||
reg = <0 0x11009000 0 0x100>;
|
||||
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topckgen CLK_TOP_MPLL_D2>,
|
||||
<&topckgen CLK_TOP_SPI_SEL>,
|
||||
<&infracfg CLK_INFRA_104M_SPI2_BCK>,
|
||||
<&infracfg CLK_INFRA_66M_SPI2_HCK>;
|
||||
clock-names = "parent-clk", "sel-clk", "spi-clk",
|
||||
"spi-hclk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm: pwm@10048000 {
|
||||
compatible = "mediatek,mt7988-pwm";
|
||||
reg = <0 0x10048000 0 0x1000>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
|
||||
<&infracfg CLK_INFRA_66M_PWM_HCK>,
|
||||
<&infracfg CLK_INFRA_66M_PWM_CK1>,
|
||||
<&infracfg CLK_INFRA_66M_PWM_CK2>,
|
||||
<&infracfg CLK_INFRA_66M_PWM_CK3>,
|
||||
<&infracfg CLK_INFRA_66M_PWM_CK4>,
|
||||
<&infracfg CLK_INFRA_66M_PWM_CK5>,
|
||||
<&infracfg CLK_INFRA_66M_PWM_CK6>,
|
||||
<&infracfg CLK_INFRA_66M_PWM_CK7>,
|
||||
<&infracfg CLK_INFRA_66M_PWM_CK8>;
|
||||
clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
|
||||
"pwm4","pwm5","pwm6","pwm7","pwm8";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fan: pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
/* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
|
||||
cooling-levels = <0 128 255>;
|
||||
#cooling-cells = <2>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lvts: lvts@1100a000 {
|
||||
compatible = "mediatek,mt7988-lvts";
|
||||
#thermal-sensor-cells = <1>;
|
||||
reg = <0 0x1100a000 0 0x1000>;
|
||||
clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
|
||||
clock-names = "lvts_clk";
|
||||
nvmem-cells = <&lvts_calibration>;
|
||||
nvmem-cell-names = "e_data1";
|
||||
};
|
||||
|
||||
crypto: crypto@15600000 {
|
||||
compatible = "inside-secure,safexcel-eip197b";
|
||||
reg = <0 0x15600000 0 0x180000>;
|
||||
interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ring0", "ring1", "ring2", "ring3";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
afe: audio-controller@11210000 {
|
||||
compatible = "mediatek,mt79xx-audio";
|
||||
reg = <0 0x11210000 0 0x9000>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
|
||||
<&infracfg CLK_INFRA_AUD_26M>,
|
||||
<&infracfg CLK_INFRA_AUD_L>,
|
||||
<&infracfg CLK_INFRA_AUD_AUD>,
|
||||
<&infracfg CLK_INFRA_AUD_EG2>,
|
||||
<&topckgen CLK_TOP_AUD_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_I2S_M>;
|
||||
clock-names = "aud_bus_ck",
|
||||
"aud_26m_ck",
|
||||
"aud_l_ck",
|
||||
"aud_aud_ck",
|
||||
"aud_eg2_ck",
|
||||
"aud_sel",
|
||||
"aud_i2s_m";
|
||||
assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
|
||||
<&topckgen CLK_TOP_A1SYS_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_L_SEL>,
|
||||
<&topckgen CLK_TOP_A_TUNER_SEL>;
|
||||
assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
|
||||
<&topckgen CLK_TOP_APLL2_D4>,
|
||||
<&apmixedsys CLK_APMIXED_APLL2>,
|
||||
<&topckgen CLK_TOP_APLL2_D4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -554,6 +842,8 @@
|
||||
<&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
|
||||
clock-names = "pl_250m", "tl_26m", "peri_26m",
|
||||
"top_133m";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie2_pins>;
|
||||
status = "disabled";
|
||||
|
||||
phys = <&xphyu3port0 PHY_TYPE_PCIE>;
|
||||
@ -594,6 +884,8 @@
|
||||
<&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
|
||||
clock-names = "pl_250m", "tl_26m", "peri_26m",
|
||||
"top_133m";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie3_pins>;
|
||||
status = "disabled";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
@ -631,6 +923,8 @@
|
||||
<&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
|
||||
clock-names = "pl_250m", "tl_26m", "peri_26m",
|
||||
"top_133m";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie0_pins>;
|
||||
status = "disabled";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
@ -668,6 +962,8 @@
|
||||
<&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
|
||||
clock-names = "pl_250m", "tl_26m", "peri_26m",
|
||||
"top_133m";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie1_pins>;
|
||||
status = "disabled";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
@ -909,7 +1205,7 @@
|
||||
mediatek,pio = <&pio>;
|
||||
|
||||
gsw_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id03a2.9481";
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
phy-mode = "internal";
|
||||
nvmem-cells = <&phy_calibration_p0>;
|
||||
@ -934,7 +1230,7 @@
|
||||
};
|
||||
|
||||
gsw_phy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-id03a2.9481";
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
phy-mode = "internal";
|
||||
nvmem-cells = <&phy_calibration_p1>;
|
||||
@ -959,7 +1255,7 @@
|
||||
};
|
||||
|
||||
gsw_phy2: ethernet-phy@2 {
|
||||
compatible = "ethernet-phy-id03a2.9481";
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <2>;
|
||||
phy-mode = "internal";
|
||||
nvmem-cells = <&phy_calibration_p2>;
|
||||
@ -984,7 +1280,7 @@
|
||||
};
|
||||
|
||||
gsw_phy3: ethernet-phy@3 {
|
||||
compatible = "ethernet-phy-id03a2.9481";
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <3>;
|
||||
phy-mode = "internal";
|
||||
nvmem-cells = <&phy_calibration_p3>;
|
||||
@ -1096,19 +1392,19 @@
|
||||
mediatek,ethsys = <ðsys>;
|
||||
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
|
||||
mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
|
||||
mediatek,xfi_pextp = <&xfi_pextp0>, <&xfi_pextp1>;
|
||||
mediatek,xfi_pll = <&xfi_pll>;
|
||||
mediatek,xfi-pextp = <&xfi_pextp0>, <&xfi_pextp1>;
|
||||
mediatek,xfi-pll = <&xfi_pll>;
|
||||
mediatek,infracfg = <&topmisc>;
|
||||
mediatek,toprgu = <&watchdog>;
|
||||
#reset-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
gmac0: mac@0 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <0>;
|
||||
phy-mode = "internal";
|
||||
status = "disabled";
|
||||
|
||||
fixed-link {
|
||||
speed = <10000>;
|
||||
@ -1120,11 +1416,13 @@
|
||||
gmac1: mac@1 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac2: mac@2 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio_bus: mdio-bus {
|
||||
|
||||
@ -36,8 +36,8 @@ mediatek_setup_interfaces()
|
||||
mediatek,mt7986b-rfb)
|
||||
ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" eth1
|
||||
;;
|
||||
mediatek,mt7988a-dsa-10g-spim-snand)
|
||||
ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" "eth1 eth2"
|
||||
mediatek,mt7988a-rfb)
|
||||
ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3 eth1" eth2"
|
||||
;;
|
||||
mercusys,mr90x-v1)
|
||||
ucidef_set_interfaces_lan_wan "lan0 lan1 lan2" eth1
|
||||
|
||||
@ -22,7 +22,15 @@ define Build/mt7986-bl31-uboot
|
||||
cat $(STAGING_DIR_IMAGE)/mt7986_$1-u-boot.fip >> $@
|
||||
endef
|
||||
|
||||
define Build/mt7986-gpt
|
||||
define Build/mt7988-bl2
|
||||
cat $(STAGING_DIR_IMAGE)/mt7988-$1-bl2.img >> $@
|
||||
endef
|
||||
|
||||
define Build/mt7988-bl31-uboot
|
||||
cat $(STAGING_DIR_IMAGE)/mt7988_$1-u-boot.fip >> $@
|
||||
endef
|
||||
|
||||
define Build/mt798x-gpt
|
||||
cp $@ $@.tmp 2>/dev/null || true
|
||||
ptgen -g -o $@.tmp -a 1 -l 1024 \
|
||||
$(if $(findstring sdmmc,$1), \
|
||||
@ -136,7 +144,7 @@ define Device/bananapi_bpi-r3
|
||||
ARTIFACT/nor-bl31-uboot.fip := mt7986-bl31-uboot bananapi_bpi-r3-nor
|
||||
ARTIFACT/snand-preloader.bin := mt7986-bl2 spim-nand-ddr4
|
||||
ARTIFACT/snand-bl31-uboot.fip := mt7986-bl31-uboot bananapi_bpi-r3-snand
|
||||
ARTIFACT/sdcard.img.gz := mt7986-gpt sdmmc |\
|
||||
ARTIFACT/sdcard.img.gz := mt798x-gpt sdmmc |\
|
||||
pad-to 17k | mt7986-bl2 sdmmc-ddr4 |\
|
||||
pad-to 6656k | mt7986-bl31-uboot bananapi_bpi-r3-sdmmc |\
|
||||
$(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),\
|
||||
@ -148,7 +156,7 @@ define Device/bananapi_bpi-r3
|
||||
pad-to 50M | mt7986-bl31-uboot bananapi_bpi-r3-nor |\
|
||||
pad-to 51M | mt7986-bl2 emmc-ddr4 |\
|
||||
pad-to 52M | mt7986-bl31-uboot bananapi_bpi-r3-emmc |\
|
||||
pad-to 56M | mt7986-gpt emmc |\
|
||||
pad-to 56M | mt798x-gpt emmc |\
|
||||
$(if $(CONFIG_TARGET_ROOTFS_SQUASHFS),\
|
||||
pad-to 64M | append-image squashfs-sysupgrade.itb | check-size |\
|
||||
) \
|
||||
@ -282,23 +290,67 @@ define Device/mediatek_mt7986b-rfb
|
||||
endef
|
||||
TARGET_DEVICES += mediatek_mt7986b-rfb
|
||||
|
||||
define Device/mediatek_mt7988a-rfb-nand
|
||||
define Device/mediatek_mt7988a-rfb
|
||||
DEVICE_VENDOR := MediaTek
|
||||
DEVICE_MODEL := MT7988a nand rfb
|
||||
DEVICE_DTS := mt7988a-dsa-10g-spim-nand
|
||||
DEVICE_MODEL := MT7988A rfb
|
||||
DEVICE_DTS := mt7988a-rfb
|
||||
DEVICE_DTS_OVERLAY:= \
|
||||
mt7988a-rfb-emmc \
|
||||
mt7988a-rfb-sd \
|
||||
mt7988a-rfb-snfi-nand \
|
||||
mt7988a-rfb-spim-nand \
|
||||
mt7988a-rfb-spim-nor \
|
||||
mt7988a-rfb-eth1-aqr \
|
||||
mt7988a-rfb-eth1-i2p5g-phy \
|
||||
mt7988a-rfb-eth1-mxl \
|
||||
mt7988a-rfb-eth1-sfp \
|
||||
mt7988a-rfb-eth2-aqr \
|
||||
mt7988a-rfb-eth2-mxl \
|
||||
mt7988a-rfb-eth2-sfp
|
||||
DEVICE_DTS_DIR := $(DTS_DIR)/
|
||||
KERNEL_LOADADDR := 0x48000000
|
||||
SUPPORTED_DEVICES := mediatek,mt7988a-rfb
|
||||
UBINIZE_OPTS := -E 5
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
IMAGE_SIZE := 65536k
|
||||
DEVICE_DTC_FLAGS := --pad 4096
|
||||
DEVICE_DTS_LOADADDR := 0x45f00000
|
||||
DEVICE_PACKAGES := kmod-sfp
|
||||
KERNEL_LOADADDR := 0x46000000
|
||||
KERNEL := kernel-bin | gzip
|
||||
KERNEL_INITRAMFS := kernel-bin | lzma | \
|
||||
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
|
||||
KERNEL_INITRAMFS_SUFFIX := .itb
|
||||
KERNEL_IN_UBI := 1
|
||||
IMAGES += factory.bin
|
||||
IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE)
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m
|
||||
IMAGES := sysupgrade.itb
|
||||
IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | pad-rootfs | append-metadata
|
||||
ARTIFACTS := \
|
||||
emmc-gpt.bin emmc-preloader.bin emmc-bl31-uboot.fip \
|
||||
nor-preloader.bin nor-bl31-uboot.fip \
|
||||
sdcard.img.gz \
|
||||
snand-preloader.bin snand-bl31-uboot.fip
|
||||
ARTIFACT/emmc-gpt.bin := mt798x-gpt emmc
|
||||
ARTIFACT/emmc-preloader.bin := mt7988-bl2 emmc-comb
|
||||
ARTIFACT/emmc-bl31-uboot.fip := mt7988-bl31-uboot rfb-emmc
|
||||
ARTIFACT/nor-preloader.bin := mt7988-bl2 nor-comb
|
||||
ARTIFACT/nor-bl31-uboot.fip := mt7988-bl31-uboot rfb-nor
|
||||
ARTIFACT/snand-preloader.bin := mt7988-bl2 spim-nand-comb
|
||||
ARTIFACT/snand-bl31-uboot.fip := mt7988-bl31-uboot rfb-snand
|
||||
ARTIFACT/sdcard.img.gz := mt798x-gpt sdmmc |\
|
||||
pad-to 17k | mt7988-bl2 sdmmc-comb |\
|
||||
pad-to 6656k | mt7988-bl31-uboot rfb-sd |\
|
||||
$(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),\
|
||||
pad-to 12M | append-image-stage initramfs.itb | check-size 44m |\
|
||||
) \
|
||||
pad-to 44M | mt7988-bl2 spim-nand-comb |\
|
||||
pad-to 45M | mt7988-bl31-uboot rfb-snand |\
|
||||
pad-to 51M | mt7988-bl2 nor-comb |\
|
||||
pad-to 51M | mt7988-bl31-uboot rfb-nor |\
|
||||
pad-to 55M | mt7988-bl2 emmc-comb |\
|
||||
pad-to 56M | mt7988-bl31-uboot rfb-emmc |\
|
||||
pad-to 62M | mt798x-gpt emmc |\
|
||||
$(if $(CONFIG_TARGET_ROOTFS_SQUASHFS),\
|
||||
pad-to 64M | append-image squashfs-sysupgrade.itb | check-size |\
|
||||
) \
|
||||
gzip
|
||||
endef
|
||||
TARGET_DEVICES += mediatek_mt7988a-rfb-nand
|
||||
TARGET_DEVICES += mediatek_mt7988a-rfb
|
||||
|
||||
define Device/mercusys_mr90x-v1
|
||||
DEVICE_VENDOR := Mercusys
|
||||
@ -352,7 +404,7 @@ define Device/tplink_tl-xdr-common
|
||||
KERNEL_INITRAMFS := kernel-bin | lzma | \
|
||||
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
|
||||
IMAGE/sysupgrade.itb := append-kernel | \
|
||||
fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata
|
||||
fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | append-metadata
|
||||
DEVICE_PACKAGES := kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware
|
||||
ARTIFACTS := preloader.bin bl31-uboot.fip
|
||||
ARTIFACT/preloader.bin := mt7986-bl2 spim-nand-ddr3
|
||||
|
||||
Loading…
Reference in New Issue
Block a user