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generic: 5.15: backport mirror mode and LAG feature for qca8k
Backport LAG and mirror mode feature for qca8k. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
This commit is contained in:
Ansuel Smith
Daniel Golle
parent
bd0db6017b
commit
ec818e5d29
@ -0,0 +1,162 @@
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From 2c1bdbc7e7560d7de754cad277d968d56bb1899e Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Tue, 23 Nov 2021 03:59:10 +0100
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Subject: net: dsa: qca8k: add support for mirror mode
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The switch supports mirror mode. Only one port can set as mirror port and
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every other port can set to both ingress and egress mode. The mirror
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port is disabled and reverted to normal operation once every port is
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removed from sending packet to it.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca8k.c | 95 +++++++++++++++++++++++++++++++++++++++++++++++++
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drivers/net/dsa/qca8k.h | 4 +++
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2 files changed, 99 insertions(+)
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diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
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index 67742fbd80409..bd9d756f40011 100644
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--- a/drivers/net/dsa/qca8k.c
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+++ b/drivers/net/dsa/qca8k.c
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@@ -2022,6 +2022,99 @@ qca8k_port_mdb_del(struct dsa_switch *ds, int port,
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return qca8k_fdb_search_and_del(priv, BIT(port), addr, vid);
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}
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+static int
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+qca8k_port_mirror_add(struct dsa_switch *ds, int port,
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+ struct dsa_mall_mirror_tc_entry *mirror,
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+ bool ingress)
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+{
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+ struct qca8k_priv *priv = ds->priv;
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+ int monitor_port, ret;
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+ u32 reg, val;
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+
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+ /* Check for existent entry */
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+ if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
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+ return -EEXIST;
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+
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+ ret = regmap_read(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, &val);
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+ if (ret)
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+ return ret;
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+
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+ /* QCA83xx can have only one port set to mirror mode.
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+ * Check that the correct port is requested and return error otherwise.
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+ * When no mirror port is set, the values is set to 0xF
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+ */
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+ monitor_port = FIELD_GET(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
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+ if (monitor_port != 0xF && monitor_port != mirror->to_local_port)
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+ return -EEXIST;
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+
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+ /* Set the monitor port */
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+ val = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM,
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+ mirror->to_local_port);
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+ ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
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+ QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
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+ if (ret)
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+ return ret;
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+
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+ if (ingress) {
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+ reg = QCA8K_PORT_LOOKUP_CTRL(port);
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+ val = QCA8K_PORT_LOOKUP_ING_MIRROR_EN;
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+ } else {
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+ reg = QCA8K_REG_PORT_HOL_CTRL1(port);
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+ val = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN;
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+ }
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+
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+ ret = regmap_update_bits(priv->regmap, reg, val, val);
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+ if (ret)
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+ return ret;
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+
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+ /* Track mirror port for tx and rx to decide when the
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+ * mirror port has to be disabled.
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+ */
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+ if (ingress)
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+ priv->mirror_rx |= BIT(port);
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+ else
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+ priv->mirror_tx |= BIT(port);
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+
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+ return 0;
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+}
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+
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+static void
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+qca8k_port_mirror_del(struct dsa_switch *ds, int port,
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+ struct dsa_mall_mirror_tc_entry *mirror)
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+{
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+ struct qca8k_priv *priv = ds->priv;
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+ u32 reg, val;
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+ int ret;
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+
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+ if (mirror->ingress) {
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+ reg = QCA8K_PORT_LOOKUP_CTRL(port);
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+ val = QCA8K_PORT_LOOKUP_ING_MIRROR_EN;
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+ } else {
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+ reg = QCA8K_REG_PORT_HOL_CTRL1(port);
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+ val = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN;
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+ }
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+
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+ ret = regmap_clear_bits(priv->regmap, reg, val);
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+ if (ret)
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+ goto err;
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+
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+ if (mirror->ingress)
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+ priv->mirror_rx &= ~BIT(port);
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+ else
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+ priv->mirror_tx &= ~BIT(port);
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+
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+ /* No port set to send packet to mirror port. Disable mirror port */
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+ if (!priv->mirror_rx && !priv->mirror_tx) {
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+ val = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, 0xF);
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+ ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
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+ QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
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+ if (ret)
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+ goto err;
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+ }
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+err:
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+ dev_err(priv->dev, "Failed to del mirror port from %d", port);
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+}
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+
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static int
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qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
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struct netlink_ext_ack *extack)
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@@ -2132,6 +2225,8 @@ static const struct dsa_switch_ops qca8k_switch_ops = {
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.port_fdb_dump = qca8k_port_fdb_dump,
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.port_mdb_add = qca8k_port_mdb_add,
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.port_mdb_del = qca8k_port_mdb_del,
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+ .port_mirror_add = qca8k_port_mirror_add,
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+ .port_mirror_del = qca8k_port_mirror_del,
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.port_vlan_filtering = qca8k_port_vlan_filtering,
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.port_vlan_add = qca8k_port_vlan_add,
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.port_vlan_del = qca8k_port_vlan_del,
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diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
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index 40ec8012622f7..7c87a968c0104 100644
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--- a/drivers/net/dsa/qca8k.h
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+++ b/drivers/net/dsa/qca8k.h
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@@ -180,6 +180,7 @@
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#define QCA8K_ATU_AGE_TIME(x) FIELD_PREP(QCA8K_ATU_AGE_TIME_MASK, (x))
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#define QCA8K_REG_GLOBAL_FW_CTRL0 0x620
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#define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10)
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+#define QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM GENMASK(7, 4)
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#define QCA8K_REG_GLOBAL_FW_CTRL1 0x624
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#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK GENMASK(30, 24)
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#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK GENMASK(22, 16)
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@@ -201,6 +202,7 @@
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#define QCA8K_PORT_LOOKUP_STATE_LEARNING QCA8K_PORT_LOOKUP_STATE(0x3)
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#define QCA8K_PORT_LOOKUP_STATE_FORWARD QCA8K_PORT_LOOKUP_STATE(0x4)
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#define QCA8K_PORT_LOOKUP_LEARN BIT(20)
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+#define QCA8K_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
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#define QCA8K_REG_GLOBAL_FC_THRESH 0x800
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#define QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK GENMASK(24, 16)
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@@ -305,6 +307,8 @@ struct qca8k_ports_config {
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struct qca8k_priv {
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u8 switch_id;
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u8 switch_revision;
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+ u8 mirror_rx;
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+ u8 mirror_tx;
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bool legacy_phy_port_mapping;
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struct qca8k_ports_config ports_config;
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struct regmap *regmap;
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--
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cgit 1.2.3-1.el7
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@ -0,0 +1,295 @@
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From def975307c01191b6f0170048c3724b0ed3348af Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Tue, 23 Nov 2021 03:59:11 +0100
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Subject: net: dsa: qca8k: add LAG support
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Add LAG support to this switch. In Documentation this is described as
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trunk mode. A max of 4 LAGs are supported and each can support up to 4
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port. The current tx mode supported is Hash mode with both L2 and L2+3
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mode.
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When no port are present in the trunk, the trunk is disabled in the
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switch.
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When a port is disconnected, the traffic is redirected to the other
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available port.
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The hash mode is global and each LAG require to have the same hash mode
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set. To change the hash mode when multiple LAG are configured, it's
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required to remove each LAG and set the desired hash mode to the last.
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An error is printed when it's asked to set a not supported hadh mode.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca8k.c | 177 ++++++++++++++++++++++++++++++++++++++++++++++++
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drivers/net/dsa/qca8k.h | 33 +++++++++
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2 files changed, 210 insertions(+)
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diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
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index bd9d756f40011..6516df08a5d5f 100644
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--- a/drivers/net/dsa/qca8k.c
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+++ b/drivers/net/dsa/qca8k.c
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@@ -1336,6 +1336,9 @@ qca8k_setup(struct dsa_switch *ds)
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ds->ageing_time_min = 7000;
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ds->ageing_time_max = 458745000;
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+ /* Set max number of LAGs supported */
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+ ds->num_lag_ids = QCA8K_NUM_LAGS;
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+
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return 0;
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}
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@@ -2203,6 +2206,178 @@ qca8k_get_tag_protocol(struct dsa_switch *ds, int port,
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return DSA_TAG_PROTO_QCA;
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}
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+static bool
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+qca8k_lag_can_offload(struct dsa_switch *ds,
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+ struct net_device *lag,
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+ struct netdev_lag_upper_info *info)
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+{
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+ struct dsa_port *dp;
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+ int id, members = 0;
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+
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+ id = dsa_lag_id(ds->dst, lag);
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+ if (id < 0 || id >= ds->num_lag_ids)
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+ return false;
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+
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+ dsa_lag_foreach_port(dp, ds->dst, lag)
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+ /* Includes the port joining the LAG */
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+ members++;
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+
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+ if (members > QCA8K_NUM_PORTS_FOR_LAG)
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+ return false;
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+
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+ if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
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+ return false;
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+
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+ if (info->hash_type != NETDEV_LAG_HASH_L2 ||
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+ info->hash_type != NETDEV_LAG_HASH_L23)
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+ return false;
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+
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+ return true;
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+}
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+
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+static int
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+qca8k_lag_setup_hash(struct dsa_switch *ds,
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+ struct net_device *lag,
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+ struct netdev_lag_upper_info *info)
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+{
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+ struct qca8k_priv *priv = ds->priv;
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+ bool unique_lag = true;
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+ int i, id;
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+ u32 hash;
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+
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+ id = dsa_lag_id(ds->dst, lag);
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+
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+ switch (info->hash_type) {
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+ case NETDEV_LAG_HASH_L23:
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+ hash |= QCA8K_TRUNK_HASH_SIP_EN;
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+ hash |= QCA8K_TRUNK_HASH_DIP_EN;
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+ fallthrough;
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+ case NETDEV_LAG_HASH_L2:
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+ hash |= QCA8K_TRUNK_HASH_SA_EN;
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+ hash |= QCA8K_TRUNK_HASH_DA_EN;
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+ break;
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+ default: /* We should NEVER reach this */
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+ return -EOPNOTSUPP;
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+ }
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+
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+ /* Check if we are the unique configured LAG */
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+ dsa_lags_foreach_id(i, ds->dst)
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+ if (i != id && dsa_lag_dev(ds->dst, i)) {
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+ unique_lag = false;
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+ break;
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+ }
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+
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+ /* Hash Mode is global. Make sure the same Hash Mode
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+ * is set to all the 4 possible lag.
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+ * If we are the unique LAG we can set whatever hash
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+ * mode we want.
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+ * To change hash mode it's needed to remove all LAG
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+ * and change the mode with the latest.
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+ */
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+ if (unique_lag) {
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+ priv->lag_hash_mode = hash;
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+ } else if (priv->lag_hash_mode != hash) {
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+ netdev_err(lag, "Error: Mismateched Hash Mode across different lag is not supported\n");
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+ return -EOPNOTSUPP;
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+ }
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+
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+ return regmap_update_bits(priv->regmap, QCA8K_TRUNK_HASH_EN_CTRL,
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+ QCA8K_TRUNK_HASH_MASK, hash);
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+}
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+
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+static int
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+qca8k_lag_refresh_portmap(struct dsa_switch *ds, int port,
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+ struct net_device *lag, bool delete)
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+{
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+ struct qca8k_priv *priv = ds->priv;
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+ int ret, id, i;
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+ u32 val;
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+
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+ id = dsa_lag_id(ds->dst, lag);
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+
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+ /* Read current port member */
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+ ret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0, &val);
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+ if (ret)
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+ return ret;
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+
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+ /* Shift val to the correct trunk */
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+ val >>= QCA8K_REG_GOL_TRUNK_SHIFT(id);
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+ val &= QCA8K_REG_GOL_TRUNK_MEMBER_MASK;
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+ if (delete)
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+ val &= ~BIT(port);
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+ else
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+ val |= BIT(port);
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+
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+ /* Update port member. With empty portmap disable trunk */
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+ ret = regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0,
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+ QCA8K_REG_GOL_TRUNK_MEMBER(id) |
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+ QCA8K_REG_GOL_TRUNK_EN(id),
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+ !val << QCA8K_REG_GOL_TRUNK_SHIFT(id) |
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+ val << QCA8K_REG_GOL_TRUNK_SHIFT(id));
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+
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+ /* Search empty member if adding or port on deleting */
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+ for (i = 0; i < QCA8K_NUM_PORTS_FOR_LAG; i++) {
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+ ret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id), &val);
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+ if (ret)
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+ return ret;
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||||||
|
+
|
||||||
|
+ val >>= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i);
|
||||||
|
+ val &= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK;
|
||||||
|
+
|
||||||
|
+ if (delete) {
|
||||||
|
+ /* If port flagged to be disabled assume this member is
|
||||||
|
+ * empty
|
||||||
|
+ */
|
||||||
|
+ if (val != QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK)
|
||||||
|
+ continue;
|
||||||
|
+
|
||||||
|
+ val &= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK;
|
||||||
|
+ if (val != port)
|
||||||
|
+ continue;
|
||||||
|
+ } else {
|
||||||
|
+ /* If port flagged to be enabled assume this member is
|
||||||
|
+ * already set
|
||||||
|
+ */
|
||||||
|
+ if (val == QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK)
|
||||||
|
+ continue;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ /* We have found the member to add/remove */
|
||||||
|
+ break;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ /* Set port in the correct port mask or disable port if in delete mode */
|
||||||
|
+ return regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id),
|
||||||
|
+ QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(id, i) |
|
||||||
|
+ QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(id, i),
|
||||||
|
+ !delete << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i) |
|
||||||
|
+ port << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i));
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int
|
||||||
|
+qca8k_port_lag_join(struct dsa_switch *ds, int port,
|
||||||
|
+ struct net_device *lag,
|
||||||
|
+ struct netdev_lag_upper_info *info)
|
||||||
|
+{
|
||||||
|
+ int ret;
|
||||||
|
+
|
||||||
|
+ if (!qca8k_lag_can_offload(ds, lag, info))
|
||||||
|
+ return -EOPNOTSUPP;
|
||||||
|
+
|
||||||
|
+ ret = qca8k_lag_setup_hash(ds, lag, info);
|
||||||
|
+ if (ret)
|
||||||
|
+ return ret;
|
||||||
|
+
|
||||||
|
+ return qca8k_lag_refresh_portmap(ds, port, lag, false);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int
|
||||||
|
+qca8k_port_lag_leave(struct dsa_switch *ds, int port,
|
||||||
|
+ struct net_device *lag)
|
||||||
|
+{
|
||||||
|
+ return qca8k_lag_refresh_portmap(ds, port, lag, true);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static const struct dsa_switch_ops qca8k_switch_ops = {
|
||||||
|
.get_tag_protocol = qca8k_get_tag_protocol,
|
||||||
|
.setup = qca8k_setup,
|
||||||
|
@@ -2236,6 +2411,8 @@ static const struct dsa_switch_ops qca8k_switch_ops = {
|
||||||
|
.phylink_mac_link_down = qca8k_phylink_mac_link_down,
|
||||||
|
.phylink_mac_link_up = qca8k_phylink_mac_link_up,
|
||||||
|
.get_phy_flags = qca8k_get_phy_flags,
|
||||||
|
+ .port_lag_join = qca8k_port_lag_join,
|
||||||
|
+ .port_lag_leave = qca8k_port_lag_leave,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int qca8k_read_switch_id(struct qca8k_priv *priv)
|
||||||
|
diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
|
||||||
|
index 7c87a968c0104..ab4a417b25a9c 100644
|
||||||
|
--- a/drivers/net/dsa/qca8k.h
|
||||||
|
+++ b/drivers/net/dsa/qca8k.h
|
||||||
|
@@ -15,6 +15,8 @@
|
||||||
|
#define QCA8K_NUM_PORTS 7
|
||||||
|
#define QCA8K_NUM_CPU_PORTS 2
|
||||||
|
#define QCA8K_MAX_MTU 9000
|
||||||
|
+#define QCA8K_NUM_LAGS 4
|
||||||
|
+#define QCA8K_NUM_PORTS_FOR_LAG 4
|
||||||
|
|
||||||
|
#define PHY_ID_QCA8327 0x004dd034
|
||||||
|
#define QCA8K_ID_QCA8327 0x12
|
||||||
|
@@ -122,6 +124,14 @@
|
||||||
|
#define QCA8K_REG_EEE_CTRL 0x100
|
||||||
|
#define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2)
|
||||||
|
|
||||||
|
+/* TRUNK_HASH_EN registers */
|
||||||
|
+#define QCA8K_TRUNK_HASH_EN_CTRL 0x270
|
||||||
|
+#define QCA8K_TRUNK_HASH_SIP_EN BIT(3)
|
||||||
|
+#define QCA8K_TRUNK_HASH_DIP_EN BIT(2)
|
||||||
|
+#define QCA8K_TRUNK_HASH_SA_EN BIT(1)
|
||||||
|
+#define QCA8K_TRUNK_HASH_DA_EN BIT(0)
|
||||||
|
+#define QCA8K_TRUNK_HASH_MASK GENMASK(3, 0)
|
||||||
|
+
|
||||||
|
/* ACL registers */
|
||||||
|
#define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8))
|
||||||
|
#define QCA8K_PORT_VLAN_CVID_MASK GENMASK(27, 16)
|
||||||
|
@@ -204,6 +214,28 @@
|
||||||
|
#define QCA8K_PORT_LOOKUP_LEARN BIT(20)
|
||||||
|
#define QCA8K_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
|
||||||
|
|
||||||
|
+#define QCA8K_REG_GOL_TRUNK_CTRL0 0x700
|
||||||
|
+/* 4 max trunk first
|
||||||
|
+ * first 6 bit for member bitmap
|
||||||
|
+ * 7th bit is to enable trunk port
|
||||||
|
+ */
|
||||||
|
+#define QCA8K_REG_GOL_TRUNK_SHIFT(_i) ((_i) * 8)
|
||||||
|
+#define QCA8K_REG_GOL_TRUNK_EN_MASK BIT(7)
|
||||||
|
+#define QCA8K_REG_GOL_TRUNK_EN(_i) (QCA8K_REG_GOL_TRUNK_EN_MASK << QCA8K_REG_GOL_TRUNK_SHIFT(_i))
|
||||||
|
+#define QCA8K_REG_GOL_TRUNK_MEMBER_MASK GENMASK(6, 0)
|
||||||
|
+#define QCA8K_REG_GOL_TRUNK_MEMBER(_i) (QCA8K_REG_GOL_TRUNK_MEMBER_MASK << QCA8K_REG_GOL_TRUNK_SHIFT(_i))
|
||||||
|
+/* 0x704 for TRUNK 0-1 --- 0x708 for TRUNK 2-3 */
|
||||||
|
+#define QCA8K_REG_GOL_TRUNK_CTRL(_i) (0x704 + (((_i) / 2) * 4))
|
||||||
|
+#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK GENMASK(3, 0)
|
||||||
|
+#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK BIT(3)
|
||||||
|
+#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK GENMASK(2, 0)
|
||||||
|
+#define QCA8K_REG_GOL_TRUNK_ID_SHIFT(_i) (((_i) / 2) * 16)
|
||||||
|
+#define QCA8K_REG_GOL_MEM_ID_SHIFT(_i) ((_i) * 4)
|
||||||
|
+/* Complex shift: FIRST shift for port THEN shift for trunk */
|
||||||
|
+#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j) (QCA8K_REG_GOL_MEM_ID_SHIFT(_j) + QCA8K_REG_GOL_TRUNK_ID_SHIFT(_i))
|
||||||
|
+#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(_i, _j) (QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j))
|
||||||
|
+#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(_i, _j) (QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j))
|
||||||
|
+
|
||||||
|
#define QCA8K_REG_GLOBAL_FC_THRESH 0x800
|
||||||
|
#define QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK GENMASK(24, 16)
|
||||||
|
#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK, x)
|
||||||
|
@@ -309,6 +341,7 @@ struct qca8k_priv {
|
||||||
|
u8 switch_revision;
|
||||||
|
u8 mirror_rx;
|
||||||
|
u8 mirror_tx;
|
||||||
|
+ u8 lag_hash_mode;
|
||||||
|
bool legacy_phy_port_mapping;
|
||||||
|
struct qca8k_ports_config ports_config;
|
||||||
|
struct regmap *regmap;
|
||||||
|
--
|
||||||
|
cgit 1.2.3-1.el7
|
||||||
|
|
||||||
@ -0,0 +1,45 @@
|
|||||||
|
From 0898ca67b86e14207d4feb3f3fea8b87cec5aab1 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Ansuel Smith <ansuelsmth@gmail.com>
|
||||||
|
Date: Tue, 23 Nov 2021 16:44:46 +0100
|
||||||
|
Subject: net: dsa: qca8k: fix warning in LAG feature
|
||||||
|
|
||||||
|
Fix warning reported by bot.
|
||||||
|
Make sure hash is init to 0 and fix wrong logic for hash_type in
|
||||||
|
qca8k_lag_can_offload.
|
||||||
|
|
||||||
|
Reported-by: kernel test robot <lkp@intel.com>
|
||||||
|
Fixes: def975307c01 ("net: dsa: qca8k: add LAG support")
|
||||||
|
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
||||||
|
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
|
||||||
|
Link: https://lore.kernel.org/r/20211123154446.31019-1-ansuelsmth@gmail.com
|
||||||
|
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
||||||
|
---
|
||||||
|
drivers/net/dsa/qca8k.c | 4 ++--
|
||||||
|
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||||
|
|
||||||
|
diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
|
||||||
|
index 6516df08a5d5f..d04b25eca2503 100644
|
||||||
|
--- a/drivers/net/dsa/qca8k.c
|
||||||
|
+++ b/drivers/net/dsa/qca8k.c
|
||||||
|
@@ -2228,7 +2228,7 @@ qca8k_lag_can_offload(struct dsa_switch *ds,
|
||||||
|
if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
|
||||||
|
return false;
|
||||||
|
|
||||||
|
- if (info->hash_type != NETDEV_LAG_HASH_L2 ||
|
||||||
|
+ if (info->hash_type != NETDEV_LAG_HASH_L2 &&
|
||||||
|
info->hash_type != NETDEV_LAG_HASH_L23)
|
||||||
|
return false;
|
||||||
|
|
||||||
|
@@ -2242,8 +2242,8 @@ qca8k_lag_setup_hash(struct dsa_switch *ds,
|
||||||
|
{
|
||||||
|
struct qca8k_priv *priv = ds->priv;
|
||||||
|
bool unique_lag = true;
|
||||||
|
+ u32 hash = 0;
|
||||||
|
int i, id;
|
||||||
|
- u32 hash;
|
||||||
|
|
||||||
|
id = dsa_lag_id(ds->dst, lag);
|
||||||
|
|
||||||
|
--
|
||||||
|
cgit 1.2.3-1.el7
|
||||||
|
|
||||||
Loading…
Reference in New Issue
Block a user