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layerscape: update kernel to LSDK-20.04-V5.4-update-290520
Update kernel from LSDK-20.04-V5.4 to LSDK-20.04-V5.4-update-290520. Only two patches added for Layerscape. LSDK kernel link https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: maurerr <mariusd84@gmail.com>
This commit is contained in:
Biwen Li
maurerr
parent
6a8694ff1e
commit
eb11760595
@ -0,0 +1,189 @@
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From eba73069e7f6ac3bcb3669d980994ec42ddd810a Mon Sep 17 00:00:00 2001
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From: Yuantian Tang <andy.tang@nxp.com>
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Date: Thu, 16 Apr 2020 17:40:06 +0800
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Subject: [PATCH] arm64: dts: lx2160a: add more thermal zone support
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There are 7 thermal zones in lx2160a soc. Add the
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rest thermal zone node to enable them.
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Also correct one of the values for tmu-calibration property.
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Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
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---
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.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 130 +++++++++++++++++-
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1 file changed, 125 insertions(+), 5 deletions(-)
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diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
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index cab7468c3..fe9b8bf4d 100644
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--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
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@@ -440,19 +440,19 @@
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};
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thermal-zones {
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- core_thermal1: core-thermal1 {
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+ cluster6-7 {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 0>;
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trips {
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- core_cluster_alert: core-cluster-alert {
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+ cluster6_7_alert: cluster6-7-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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- core_cluster_crit: core-cluster-crit {
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+ cluster6_7_crit: cluster6-7-crit {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "critical";
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@@ -461,7 +461,7 @@
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cooling-maps {
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map0 {
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- trip = <&core_cluster_alert>;
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+ trip = <&cluster6_7_alert>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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@@ -482,6 +482,126 @@
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};
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};
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};
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+
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+ ddr-cluster5 {
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+ polling-delay-passive = <1000>;
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+ polling-delay = <5000>;
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+ thermal-sensors = <&tmu 1>;
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+
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+ trips {
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+ ddr-cluster5-alert {
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+ temperature = <85000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+
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+ ddr-cluster5-crit {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+ };
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+ };
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+
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+ wriop {
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+ polling-delay-passive = <1000>;
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+ polling-delay = <5000>;
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+ thermal-sensors = <&tmu 2>;
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+
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+ trips {
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+ wriop-alert {
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+ temperature = <85000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+
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+ wriop-crit {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+ };
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+ };
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+
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+ dce-qbman-hsio2 {
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+ polling-delay-passive = <1000>;
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+ polling-delay = <5000>;
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+ thermal-sensors = <&tmu 3>;
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+
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+ trips {
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+ dce-qbman-alert {
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+ temperature = <85000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+
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+ dce-qbman-crit {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+ };
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+ };
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+
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+ ccn-dpaa-tbu {
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+ polling-delay-passive = <1000>;
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+ polling-delay = <5000>;
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+ thermal-sensors = <&tmu 4>;
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+
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+ trips {
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+ ccn-dpaa-alert {
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+ temperature = <85000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+
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+ ccn-dpaa-crit {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+ };
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+ };
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+
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+ cluster4-hsio3 {
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+ polling-delay-passive = <1000>;
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+ polling-delay = <5000>;
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+ thermal-sensors = <&tmu 5>;
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+
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+ trips {
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+ clust4-hsio3-alert {
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+ temperature = <85000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+
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+ clust4-hsio3-crit {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+ };
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+ };
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+
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+ cluster2-3 {
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+ polling-delay-passive = <1000>;
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+ polling-delay = <5000>;
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+ thermal-sensors = <&tmu 6>;
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+
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+ trips {
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+ cluster2-3-alert {
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+ temperature = <85000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+
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+ cluster2-3-crit {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+ };
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+ };
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};
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soc {
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@@ -760,7 +880,7 @@
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/* Calibration data group 1 */
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<0x00000000 0x00000035
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/* Calibration data group 2 */
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- 0x00010001 0x00000154>;
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+ 0x00000001 0x00000154>;
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little-endian;
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#thermal-sensor-cells = <1>;
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};
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--
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2.17.1
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@ -0,0 +1,85 @@
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From da5a7765a20d34508036ba8ed1db87e546abcf4b Mon Sep 17 00:00:00 2001
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From: Yuantian Tang <andy.tang@nxp.com>
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Date: Mon, 25 May 2020 17:33:22 +0800
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Subject: [PATCH] thermal: qoriq: Update the settings for TMUv2
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For TMU v2, TMSAR registers need to be set properly to get the
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accurate temperature values.
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Also the temperature read needs to be converted to degree Celsius
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since it is in degrees Kelvin.
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Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
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---
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drivers/thermal/qoriq_thermal.c | 21 +++++++++++++++++++--
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1 file changed, 19 insertions(+), 2 deletions(-)
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diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
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index ba7d6105a..8b371fd3d 100644
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--- a/drivers/thermal/qoriq_thermal.c
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+++ b/drivers/thermal/qoriq_thermal.c
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@@ -23,6 +23,7 @@
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#define TMTMIR_DEFAULT 0x0000000f
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#define TIER_DISABLE 0x0
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#define TEUMR0_V2 0x51009c00
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+#define TMSARA_V2 0xe
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#define TMU_VER1 0x1
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#define TMU_VER2 0x2
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@@ -35,6 +36,13 @@ struct qoriq_tmu_site_regs {
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u8 res0[0x8];
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};
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+struct qoriq_tmu_tmsar {
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+ u32 res0;
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+ u32 tmsar;
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+ u32 res1;
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+ u32 res2;
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+};
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+
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struct qoriq_tmu_regs_v1 {
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u32 tmr; /* Mode Register */
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u32 tsr; /* Status Register */
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@@ -95,7 +103,9 @@ struct qoriq_tmu_regs_v2 {
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u32 tscfgr; /* Sensor Configuration Register */
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u8 res6[0x78];
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struct qoriq_tmu_site_regs site[SITES_MAX];
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- u8 res7[0x9f8];
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+ u8 res10[0x100];
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+ struct qoriq_tmu_tmsar tmsar[16];
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+ u8 res7[0x7f8];
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u32 ipbrr0; /* IP Block Revision Register 0 */
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u32 ipbrr1; /* IP Block Revision Register 1 */
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u8 res8[0x300];
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@@ -158,7 +168,10 @@ static int tmu_get_temp(void *p, int *temp)
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u32 val;
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val = tmu_read(qdata, &qdata->regs->site[qsensor->id].tritsr);
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- *temp = (val & 0xff) * 1000;
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+ if (qdata->ver == TMU_VER1)
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+ *temp = (val & 0xff) * 1000;
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+ else
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+ *temp = (val & 0x1ff) * 1000 - 273150;
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return 0;
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}
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@@ -319,6 +332,8 @@ static int qoriq_tmu_calibration(struct platform_device *pdev)
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static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)
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{
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+ int i;
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+
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/* Disable interrupt, using polling instead */
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tmu_write(data, TIER_DISABLE, &data->regs->tier);
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@@ -328,6 +343,8 @@ static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)
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} else {
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tmu_write(data, TMTMIR_DEFAULT, &data->regs_v2->tmtmir);
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tmu_write(data, TEUMR0_V2, &data->regs_v2->teumr0);
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+ for (i = 0; i < 7; i++)
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+ tmu_write(data, TMSARA_V2, &data->regs_v2->tmsar[i].tmsar);
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}
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/* Disable monitoring */
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--
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2.17.1
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