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octeon: Add MMC support for EdgeRouter ER8
this is a backport of a series posted on the lmo mailing list Signed-off-by: Jonathan Thibault <jonathan@navigue.com> SVN-Revision: 44901
This commit is contained in:
John Crispin
parent
3006bc6904
commit
e9b6602a84
@ -148,6 +148,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT_7=y
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# CONFIG_MIPS_MACHINE is not set
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# CONFIG_MIPS_PARAVIRT is not set
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CONFIG_MIPS_PGD_C0_CONTEXT=y
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CONFIG_MMC=y
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CONFIG_MMC_BLOCK=y
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CONFIG_MMC_OCTEON=y
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# CONFIG_MMC_TIFM_SD is not set
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CONFIG_MODULES_USE_ELF_REL=y
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CONFIG_MODULES_USE_ELF_RELA=y
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# CONFIG_MTD_CFI_INTELEXT is not set
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@ -0,0 +1,25 @@
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diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
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index a42110e..01130e9 100644
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--- a/arch/mips/cavium-octeon/setup.c
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+++ b/arch/mips/cavium-octeon/setup.c
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@@ -51,6 +51,9 @@ extern void pci_console_init(const char *arg);
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static unsigned long long MAX_MEMORY = 512ull << 20;
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+DEFINE_SEMAPHORE(octeon_bootbus_sem);
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+EXPORT_SYMBOL(octeon_bootbus_sem);
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+
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struct octeon_boot_descriptor *octeon_boot_desc_ptr;
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struct cvmx_bootinfo *octeon_bootinfo;
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diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
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index 0415965..de9f74e 100644
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--- a/arch/mips/include/asm/octeon/octeon.h
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+++ b/arch/mips/include/asm/octeon/octeon.h
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@@ -335,4 +335,6 @@ void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t);
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extern void octeon_fixup_irqs(void);
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+extern struct semaphore octeon_bootbus_sem;
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+
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#endif /* __ASM_OCTEON_OCTEON_H */
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@ -0,0 +1,105 @@
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diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h
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index e2c122c..35d7cbd 100644
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--- a/arch/mips/include/asm/octeon/octeon-model.h
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+++ b/arch/mips/include/asm/octeon/octeon-model.h
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@@ -45,6 +45,7 @@
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*/
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#define OCTEON_FAMILY_MASK 0x00ffff00
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+#define OCTEON_PRID_MASK 0x00ffffff
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/* Flag bits in top byte */
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/* Ignores revision in model checks */
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@@ -63,6 +64,46 @@
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#define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000
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/* Match all cnf7XXX Octeon models. */
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#define OM_MATCH_F7XXX_FAMILY_MODELS 0x80000000
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+/* Match all cn7XXX Octeon models. */
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+#define OM_MATCH_7XXX_FAMILY_MODELS 0x10000000
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+#define OM_MATCH_FAMILY_MODELS (OM_MATCH_5XXX_FAMILY_MODELS | \
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+ OM_MATCH_6XXX_FAMILY_MODELS | \
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+ OM_MATCH_F7XXX_FAMILY_MODELS | \
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+ OM_MATCH_7XXX_FAMILY_MODELS)
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+/*
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+ * CN7XXX models with new revision encoding
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+ */
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+
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+#define OCTEON_CN73XX_PASS1_0 0x000d9700
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+#define OCTEON_CN73XX (OCTEON_CN73XX_PASS1_0 | OM_IGNORE_REVISION)
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+#define OCTEON_CN73XX_PASS1_X (OCTEON_CN73XX_PASS1_0 | \
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+ OM_IGNORE_MINOR_REVISION)
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+
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+#define OCTEON_CN70XX_PASS1_0 0x000d9600
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+#define OCTEON_CN70XX_PASS1_1 0x000d9601
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+#define OCTEON_CN70XX_PASS1_2 0x000d9602
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+
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+#define OCTEON_CN70XX_PASS2_0 0x000d9608
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+
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+#define OCTEON_CN70XX (OCTEON_CN70XX_PASS1_0 | OM_IGNORE_REVISION)
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+#define OCTEON_CN70XX_PASS1_X (OCTEON_CN70XX_PASS1_0 | \
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+ OM_IGNORE_MINOR_REVISION)
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+#define OCTEON_CN70XX_PASS2_X (OCTEON_CN70XX_PASS2_0 | \
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+ OM_IGNORE_MINOR_REVISION)
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+
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+#define OCTEON_CN71XX OCTEON_CN70XX
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+
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+#define OCTEON_CN78XX_PASS1_0 0x000d9500
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+#define OCTEON_CN78XX_PASS1_1 0x000d9501
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+#define OCTEON_CN78XX_PASS2_0 0x000d9508
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+
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+#define OCTEON_CN78XX (OCTEON_CN78XX_PASS1_0 | OM_IGNORE_REVISION)
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+#define OCTEON_CN78XX_PASS1_X (OCTEON_CN78XX_PASS1_0 | \
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+ OM_IGNORE_MINOR_REVISION)
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+#define OCTEON_CN78XX_PASS2_X (OCTEON_CN78XX_PASS2_0 | \
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+ OM_IGNORE_MINOR_REVISION)
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+
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+#define OCTEON_CN76XX (0x000d9540 | OM_CHECK_SUBMODEL)
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/*
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* CNF7XXX models with new revision encoding
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@@ -217,6 +258,10 @@
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#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION)
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#define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
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#define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
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+#define OCTEON_CNF7XXX (OCTEON_CNF71XX_PASS1_0 | \
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+ OM_MATCH_F7XXX_FAMILY_MODELS)
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+#define OCTEON_CN7XXX (OCTEON_CN78XX_PASS1_0 | \
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+ OM_MATCH_7XXX_FAMILY_MODELS)
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/* These are used to cover entire families of OCTEON processors */
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#define OCTEON_FAM_1 (OCTEON_CN3XXX)
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@@ -288,9 +333,16 @@ static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
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((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL) \
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&& __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_REV_MASK)) || \
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((((arg_model) & (OM_MATCH_5XXX_FAMILY_MODELS)) == OM_MATCH_5XXX_FAMILY_MODELS) \
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- && ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0)) || \
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+ && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN58XX_PASS1_0) \
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+ && ((chip_model & OCTEON_PRID_MASK) < OCTEON_CN63XX_PASS1_0)) || \
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((((arg_model) & (OM_MATCH_6XXX_FAMILY_MODELS)) == OM_MATCH_6XXX_FAMILY_MODELS) \
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- && ((chip_model) >= OCTEON_CN63XX_PASS1_0)) || \
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+ && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN63XX_PASS1_0) \
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+ && ((chip_model & OCTEON_PRID_MASK) < OCTEON_CNF71XX_PASS1_0)) || \
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+ ((((arg_model) & (OM_MATCH_F7XXX_FAMILY_MODELS)) == OM_MATCH_F7XXX_FAMILY_MODELS) \
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+ && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CNF71XX_PASS1_0) \
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+ && ((chip_model & OCTEON_PRID_MASK) < OCTEON_CN78XX_PASS1_0)) || \
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+ ((((arg_model) & (OM_MATCH_7XXX_FAMILY_MODELS)) == OM_MATCH_7XXX_FAMILY_MODELS) \
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+ && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN78XX_PASS1_0)) || \
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((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
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&& (((chip_model) & OCTEON_58XX_MODEL_MASK) < ((arg_model) & OCTEON_58XX_MODEL_MASK))) \
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)))
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@@ -326,6 +378,15 @@ static inline int __octeon_is_model_runtime__(uint32_t model)
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#define OCTEON_IS_COMMON_BINARY() 1
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#undef OCTEON_MODEL
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+#define OCTEON_IS_OCTEON1() OCTEON_IS_MODEL(OCTEON_CN3XXX)
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+#define OCTEON_IS_OCTEONPLUS() OCTEON_IS_MODEL(OCTEON_CN5XXX)
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+#define OCTEON_IS_OCTEON2() \
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+ (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))
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+
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+#define OCTEON_IS_OCTEON3() OCTEON_IS_MODEL(OCTEON_CN7XXX)
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+
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+#define OCTEON_IS_OCTEON1PLUS() (OCTEON_IS_OCTEON1() || OCTEON_IS_OCTEONPLUS())
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+
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const char *octeon_model_get_string(uint32_t chip_id);
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const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer);
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