From e5eefed084d1ec1fcfe9840693ceb12c759d26aa Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sun, 30 Sep 2012 11:43:40 +0000 Subject: [PATCH] ignore the last page on bcma based SoCs SVN-Revision: 33598 --- ...MIPS-BCM47XX-ignore-last-memory-page.patch | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 target/linux/brcm47xx/patches-3.3/191-MIPS-BCM47XX-ignore-last-memory-page.patch diff --git a/target/linux/brcm47xx/patches-3.3/191-MIPS-BCM47XX-ignore-last-memory-page.patch b/target/linux/brcm47xx/patches-3.3/191-MIPS-BCM47XX-ignore-last-memory-page.patch new file mode 100644 index 00000000000..9f7d5dcdb4f --- /dev/null +++ b/target/linux/brcm47xx/patches-3.3/191-MIPS-BCM47XX-ignore-last-memory-page.patch @@ -0,0 +1,33 @@ +--- a/arch/mips/bcm47xx/prom.c ++++ b/arch/mips/bcm47xx/prom.c +@@ -27,6 +27,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -59,6 +60,7 @@ static __init void prom_init_mem(void) + { + unsigned long mem; + unsigned long max; ++ struct cpuinfo_mips *c = ¤t_cpu_data; + + /* Figure out memory size by finding aliases. + * +@@ -87,6 +89,14 @@ static __init void prom_init_mem(void) + break; + } + ++ /* Ignoring the last page when ddr size is 128M. Cached ++ * accesses to last page is causing the processor to prefetch ++ * using address above 128M stepping out of the ddr address ++ * space. ++ */ ++ if (c->cputype == CPU_74K && (mem == (128 << 20))) ++ mem -= 0x1000; ++ + add_memory_region(0, mem, BOOT_MEM_RAM); + } +