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uboot: support boards with tantos switch and small code and format cleanups

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SVN-Revision: 13308
This commit is contained in:
Thomas Langer 2008-11-21 18:47:33 +00:00
parent 0f26e35e37
commit e59c8dd866
1 changed files with 185 additions and 149 deletions
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84
package/uboot-ifxmips/files/drivers/ifx_sw.c
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@ -53,6 +53,8 @@
#define SW_WRITE_REG(reg, value) *((volatile u32*)reg) = (u32)value #define SW_WRITE_REG(reg, value) *((volatile u32*)reg) = (u32)value
#define SW_READ_REG(reg, value) value = (u32)*((volatile u32*)reg) #define SW_READ_REG(reg, value) value = (u32)*((volatile u32*)reg)
#define TANTOS_CHIP_ID 0x2599
typedef struct typedef struct
{ {
union union
@ -115,6 +117,7 @@ static void danube_dma_init(void);
int danube_switch_initialize(bd_t * bis) int danube_switch_initialize(bd_t * bis)
{ {
struct eth_device *dev; struct eth_device *dev;
unsigned short chipid;
#if 0 #if 0
printf("Entered danube_switch_initialize()\n"); printf("Entered danube_switch_initialize()\n");
@ -160,9 +163,13 @@ int danube_switch_initialize(bd_t * bis)
eth_register(dev); eth_register(dev);
#if 0 while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
printf("Leaving danube_switch_initialize()\n"); *DANUBE_PPE_ETOP_MDIO_ACC =0xc1010000;
#endif while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
chipid = (unsigned short)(*DANUBE_PPE_ETOP_MDIO_ACC & 0xffff);
if (chipid != TANTOS_CHIP_ID) // not tantos switch.
{
while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
*DANUBE_PPE_ETOP_MDIO_ACC =0x8001840F; *DANUBE_PPE_ETOP_MDIO_ACC =0x8001840F;
while((*DANUBE_PPE_ETOP_MDIO_ACC)&0x80000000); while((*DANUBE_PPE_ETOP_MDIO_ACC)&0x80000000);
@ -183,6 +190,49 @@ int danube_switch_initialize(bd_t * bis)
while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
*DANUBE_PPE_ETOP_MDIO_ACC =0x80334000; *DANUBE_PPE_ETOP_MDIO_ACC =0x80334000;
#endif #endif
}
else // Tantos switch chip
{
//printf("Tantos Switch detected!!\n\r");
while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
*DANUBE_PPE_ETOP_MDIO_ACC =0x80a10004;
while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
*DANUBE_PPE_ETOP_MDIO_ACC =0x80c10004;
while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
*DANUBE_PPE_ETOP_MDIO_ACC =0x80f50773;
/* Software workaround. */
/* PHY reset from P0 to P4. */
while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
mdelay(1);
*DANUBE_PPE_ETOP_MDIO_ACC =0x81218000;
while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
mdelay(1);
/* P0 */
*DANUBE_PPE_ETOP_MDIO_ACC =0x81200400;
while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
mdelay(1);
/* P1 */
*DANUBE_PPE_ETOP_MDIO_ACC =0x81200420;
while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
mdelay(1);
/* P2 */
*DANUBE_PPE_ETOP_MDIO_ACC =0x81200440;
while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
mdelay(1);
/* P3 */
*DANUBE_PPE_ETOP_MDIO_ACC =0x81200460;
while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
mdelay(1);
/* p4 */
*DANUBE_PPE_ETOP_MDIO_ACC =0x81200480;
while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
mdelay(1);
}
return 1; return 1;
} }
@ -194,8 +244,7 @@ int danube_switch_init(struct eth_device *dev, bd_t * bis)
tx_num=0; tx_num=0;
rx_num=0; rx_num=0;
/* Reset DMA /* Reset DMA */
*/
// serial_puts("i \n\0"); // serial_puts("i \n\0");
*DANUBE_DMA_CS=RX_CHAN_NO; *DANUBE_DMA_CS=RX_CHAN_NO;
@ -299,12 +348,9 @@ Done:
int danube_switch_recv(struct eth_device *dev) int danube_switch_recv(struct eth_device *dev)
{ {
int length = 0; int length = 0;
danube_rx_descriptor_t * rx_desc; danube_rx_descriptor_t * rx_desc;
int anchor_num=0;
int i;
for (;;) for (;;)
{ {
rx_desc = KSEG1ADDR(&rx_des_ring[rx_num]); rx_desc = KSEG1ADDR(&rx_des_ring[rx_num]);
@ -314,7 +360,6 @@ int danube_switch_recv(struct eth_device *dev)
break; break;
} }
length = rx_desc->status.field.DataLen; length = rx_desc->status.field.DataLen;
if (length) if (length)
{ {
@ -342,10 +387,8 @@ int danube_switch_recv(struct eth_device *dev)
static void danube_init_switch_chip(int mode) static void danube_init_switch_chip(int mode)
{ {
int i;
/*get and set mac address for MAC*/ /*get and set mac address for MAC*/
static unsigned char addr[6]; char *tmp;
char *tmp,*end;
tmp = getenv ("ethaddr"); tmp = getenv ("ethaddr");
if (NULL == tmp) { if (NULL == tmp) {
printf("Can't get environment ethaddr!!!\n"); printf("Can't get environment ethaddr!!!\n");
@ -358,7 +401,7 @@ static void danube_init_switch_chip(int mode)
*DANUBE_PPE32_ENET_MAC_CFG = 0x187; *DANUBE_PPE32_ENET_MAC_CFG = 0x187;
// turn on port0, set to rmii and turn off port1. // turn on port0, set to rmii and turn off port1.
if(mode==REV_MII_MODE) if (mode==REV_MII_MODE)
{ {
*DANUBE_PPE32_ETOP_CFG = (*DANUBE_PPE32_ETOP_CFG & 0xfffffffc) | 0x0000000a; *DANUBE_PPE32_ETOP_CFG = (*DANUBE_PPE32_ETOP_CFG & 0xfffffffc) | 0x0000000a;
} }
@ -368,24 +411,21 @@ static void danube_init_switch_chip(int mode)
} }
*DANUBE_PPE32_ETOP_IG_PLEN_CTRL = 0x4005ee; // set packetlen. *DANUBE_PPE32_ETOP_IG_PLEN_CTRL = 0x4005ee; // set packetlen.
*ENET_MAC_CFG|=1<<11;/*enable the crc*/ *ENET_MAC_CFG |= 1<<11; /*enable the crc*/
return; return;
} }
static void danube_dma_init(void) static void danube_dma_init(void)
{ {
int i;
// serial_puts("d \n\0"); // serial_puts("d \n\0");
*DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/ *DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
/* Reset DMA /* Reset DMA */
*/
*DANUBE_DMA_CTRL|=1; *DANUBE_DMA_CTRL|=1;
*DANUBE_DMA_IRNEN=0;/*disable all the interrupts first*/ *DANUBE_DMA_IRNEN=0;/*disable all the interrupts first*/
/* Clear Interrupt Status Register /* Clear Interrupt Status Register */
*/
*DANUBE_DMA_IRNCR=0xfffff; *DANUBE_DMA_IRNCR=0xfffff;
/*disable all the dma interrupts*/ /*disable all the dma interrupts*/
*DANUBE_DMA_IRNEN=0; *DANUBE_DMA_IRNEN=0;
@ -416,8 +456,4 @@ static void danube_dma_init(void)
return; return;
} }
#endif #endif