mirror of
https://github.com/openwrt/openwrt.git
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mediatek: add basic mt7988 device tree support
This add basic device tree support for mediatek MT7988 SoC
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit e3a681bab4)
This commit is contained in:
Sam Shih
Daniel Golle
parent
670dedbbd7
commit
e458cfc214
@ -0,0 +1,200 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2022 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*/
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/dts-v1/;
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#include "mt7988a-rfb-spim-nand.dtsi"
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#include <dt-bindings/pinctrl/mt65xx.h>
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/ {
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model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB";
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compatible = "mediatek,mt7988a-dsa-10g-spim-snand",
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"mediatek,mt7988a-rfb-snand",
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"mediatek,mt7988";
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chosen {
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bootargs = "console=ttyS0,115200n1 loglevel=8 \
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earlycon=uart8250,mmio32,0x11000000 \
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pci=pcie_bus_perf";
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};
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memory {
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reg = <0 0x40000000 0 0x40000000>;
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};
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};
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ð {
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pinctrl-0 = <&mdio0_pins>;
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pinctrl-names = "default";
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status = "okay";
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-mode = "internal";
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fixed-link {
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speed = <10000>;
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full-duplex;
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pause;
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};
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};
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-mode = "internal";
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phy-connection-type = "internal";
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phy = <&phy15>;
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};
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gmac2: mac@2 {
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compatible = "mediatek,eth-mac";
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reg = <2>;
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phy-mode = "10gbase-kr";
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phy-connection-type = "10gbase-kr";
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phy = <&phy8>;
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};
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mdio0: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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/* external Aquantia AQR113C */
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phy0: ethernet-phy@0 {
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reg = <0>;
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compatible = "ethernet-phy-ieee802.3-c45";
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reset-gpios = <&pio 72 1>;
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reset-assert-us = <100000>;
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reset-deassert-us = <221000>;
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};
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/* external Aquantia AQR113C */
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phy8: ethernet-phy@8 {
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reg = <8>;
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compatible = "ethernet-phy-ieee802.3-c45";
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reset-gpios = <&pio 71 1>;
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reset-assert-us = <100000>;
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reset-deassert-us = <221000>;
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};
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/* external Maxlinear GPY211C */
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phy5: ethernet-phy@5 {
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reg = <5>;
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compatible = "ethernet-phy-ieee802.3-c45";
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phy-mode = "2500base-x";
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};
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/* external Maxlinear GPY211C */
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phy13: ethernet-phy@13 {
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reg = <13>;
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compatible = "ethernet-phy-ieee802.3-c45";
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phy-mode = "2500base-x";
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};
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/* internal 2.5G PHY */
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phy15: ethernet-phy@15 {
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reg = <15>;
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pinctrl-names = "i2p5gbe-led";
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pinctrl-0 = <&i2p5gbe_led0_pins>;
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compatible = "ethernet-phy-ieee802.3-c45";
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phy-mode = "internal";
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};
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};
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};
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&switch {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan0";
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phy-mode = "internal";
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phy-handle = <&gsw_phy0>;
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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phy-mode = "internal";
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phy-handle = <&gsw_phy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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phy-mode = "internal";
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phy-handle = <&gsw_phy2>;
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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phy-mode = "internal";
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phy-handle = <&gsw_phy3>;
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};
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port@6 {
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reg = <6>;
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ethernet = <&gmac0>;
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phy-mode = "internal";
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fixed-link {
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speed = <10000>;
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full-duplex;
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pause;
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};
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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gsw_phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-id03a2.9481";
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reg = <0>;
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phy-mode = "internal";
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe0_led0_pins>;
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nvmem-cells = <&phy_calibration_p0>;
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nvmem-cell-names = "phy-cal-data";
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};
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gsw_phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-id03a2.9481";
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reg = <1>;
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phy-mode = "internal";
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe1_led0_pins>;
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nvmem-cells = <&phy_calibration_p1>;
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nvmem-cell-names = "phy-cal-data";
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};
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gsw_phy2: ethernet-phy@2 {
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compatible = "ethernet-phy-id03a2.9481";
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reg = <2>;
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phy-mode = "internal";
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe2_led0_pins>;
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nvmem-cells = <&phy_calibration_p2>;
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nvmem-cell-names = "phy-cal-data";
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};
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gsw_phy3: ethernet-phy@3 {
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compatible = "ethernet-phy-id03a2.9481";
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reg = <3>;
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phy-mode = "internal";
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe3_led0_pins>;
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nvmem-cells = <&phy_calibration_p3>;
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nvmem-cell-names = "phy-cal-data";
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};
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};
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};
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@ -0,0 +1,70 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2022 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*/
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/dts-v1/;
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#include "mt7988a-rfb.dtsi"
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&pio {
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spi0_flash_pins: spi0-pins {
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mux {
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function = "spi";
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groups = "spi0", "spi0_wp_hold";
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};
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};
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_flash_pins>;
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status = "okay";
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spi_nand: spi_nand@0 {
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compatible = "spi-nand";
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reg = <0>;
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spi-max-frequency = <52000000>;
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spi-tx-buswidth = <4>;
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spi-rx-buswidth = <4>;
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};
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};
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&spi_nand {
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mediatek,nmbm;
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mediatek,bmt-max-ratio = <1>;
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mediatek,bmt-max-reserved-blocks = <64>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "BL2";
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reg = <0x00000 0x0100000>;
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read-only;
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};
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partition@100000 {
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label = "u-boot-env";
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reg = <0x0100000 0x0080000>;
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};
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factory: partition@180000 {
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label = "Factory";
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reg = <0x180000 0x0400000>;
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};
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partition@580000 {
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label = "FIP";
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reg = <0x580000 0x0200000>;
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};
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partition@780000 {
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label = "ubi";
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reg = <0x780000 0x7080000>;
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};
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};
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};
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@ -0,0 +1,175 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2022 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*/
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/dts-v1/;
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#include "mt7988a.dtsi"
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#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
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&cpu0 {
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proc-supply = <&rt5190_buck3>;
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};
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&cpu1 {
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proc-supply = <&rt5190_buck3>;
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};
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&cpu2 {
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proc-supply = <&rt5190_buck3>;
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};
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&cpu3 {
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proc-supply = <&rt5190_buck3>;
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};
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&cci {
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proc-supply = <&rt5190_buck3>;
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};
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ð {
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status = "okay";
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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status = "okay";
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rt5190a_64: rt5190a@64 {
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compatible = "richtek,rt5190a";
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reg = <0x64>;
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/*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/
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vin2-supply = <&rt5190_buck1>;
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vin3-supply = <&rt5190_buck1>;
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vin4-supply = <&rt5190_buck1>;
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regulators {
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rt5190_buck1: buck1 {
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regulator-name = "rt5190a-buck1";
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regulator-min-microvolt = <5090000>;
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regulator-max-microvolt = <5090000>;
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regulator-allowed-modes =
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<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck2 {
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regulator-name = "vcore";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <1400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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rt5190_buck3: buck3 {
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regulator-name = "vproc";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <1400000>;
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regulator-boot-on;
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};
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buck4 {
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regulator-name = "rt5190a-buck4";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <850000>;
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regulator-allowed-modes =
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<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo {
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regulator-name = "rt5190a-ldo";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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};
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&pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_pins>;
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status = "okay";
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};
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&pcie1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie1_pins>;
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status = "okay";
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};
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&pcie2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie2_pins>;
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status = "disabled";
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};
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&pcie3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie3_pins>;
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status = "okay";
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};
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&ssusb0 {
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status = "okay";
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};
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&ssusb1 {
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status = "okay";
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};
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&tphy {
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status = "okay";
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};
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&pio {
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pcie0_pins: pcie0-pins {
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mux {
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function = "pcie";
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groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
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"pcie_wake_n0_0";
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};
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};
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pcie1_pins: pcie1-pins {
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mux {
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function = "pcie";
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groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
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"pcie_wake_n1_0";
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};
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};
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pcie2_pins: pcie2-pins {
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mux {
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function = "pcie";
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groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
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"pcie_wake_n2_0";
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};
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};
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pcie3_pins: pcie3-pins {
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mux {
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function = "pcie";
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groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
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"pcie_wake_n3_0";
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};
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};
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};
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&spi0 {
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status = "disabled";
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};
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&uart0 {
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status = "okay";
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};
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&watchdog {
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status = "okay";
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};
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&xphy {
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status = "okay";
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};
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@ -0,0 +1,853 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2023 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/ti-syscon.h>
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#include <dt-bindings/clock/mediatek,mt7988-clk.h>
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#include <dt-bindings/pinctrl/mt65xx.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "mediatek,mt7988";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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clk40m: oscillator@0 {
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compatible = "fixed-clock";
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clock-frequency = <40000000>;
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#clock-cells = <0>;
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clock-output-names = "clkxtal";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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enable-method = "psci";
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reg = <0x0>;
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clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
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<&topckgen CLK_TOP_XTAL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster0_opp>;
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mediatek,cci = <&cci>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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enable-method = "psci";
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reg = <0x1>;
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clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
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<&topckgen CLK_TOP_XTAL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster0_opp>;
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mediatek,cci = <&cci>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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enable-method = "psci";
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reg = <0x2>;
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clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
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<&topckgen CLK_TOP_XTAL>;
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clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
mediatek,cci = <&cci>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a73";
|
||||
enable-method = "psci";
|
||||
reg = <0x3>;
|
||||
clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
|
||||
<&topckgen CLK_TOP_XTAL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
mediatek,cci = <&cci>;
|
||||
};
|
||||
|
||||
cluster0_opp: opp_table0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = <850000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <1100000000>;
|
||||
opp-microvolt = <850000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <1500000000>;
|
||||
opp-microvolt = <850000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <1800000000>;
|
||||
opp-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cci: cci {
|
||||
compatible = "mediatek,mt7988-cci",
|
||||
"mediatek,mt8183-cci";
|
||||
clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
|
||||
<&topckgen CLK_TOP_XTAL>;
|
||||
clock-names = "cci", "intermediate";
|
||||
operating-points-v2 = <&cci_opp>;
|
||||
};
|
||||
|
||||
cci_opp: opp_table_cci {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <480000000>;
|
||||
opp-microvolt = <850000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <660000000>;
|
||||
opp-microvolt = <850000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <900000000>;
|
||||
opp-microvolt = <850000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <1080000000>;
|
||||
opp-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a73-pmu";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
|
||||
secmon_reserved: secmon@43000000 {
|
||||
reg = <0 0x43000000 0 0x30000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
gic: interrupt-controller@c000000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt-controller;
|
||||
reg = <0 0x0c000000 0 0x40000>, /* GICD */
|
||||
<0 0x0c080000 0 0x200000>, /* GICR */
|
||||
<0 0x0c400000 0 0x2000>, /* GICC */
|
||||
<0 0x0c410000 0 0x1000>, /* GICH */
|
||||
<0 0x0c420000 0 0x2000>; /* GICV */
|
||||
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
phyfw: phy-firmware@f000000 {
|
||||
compatible = "mediatek,2p5gphy-fw";
|
||||
reg = <0 0x0f000000 0 0x8000>,
|
||||
<0 0x0f100000 0 0x20000>,
|
||||
<0 0x0f0f0000 0 0x200>;
|
||||
};
|
||||
|
||||
infracfg: infracfg@10001000 {
|
||||
compatible = "mediatek,mt7988-infracfg", "syscon";
|
||||
reg = <0 0x10001000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
topckgen: topckgen@1001b000 {
|
||||
compatible = "mediatek,mt7988-topckgen", "syscon";
|
||||
reg = <0 0x1001b000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
watchdog: watchdog@1001c000 {
|
||||
compatible = "mediatek,mt7988-wdt",
|
||||
"mediatek,mt6589-wdt",
|
||||
"syscon";
|
||||
reg = <0 0x1001c000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
apmixedsys: apmixedsys@1001e000 {
|
||||
compatible = "mediatek,mt7988-apmixedsys";
|
||||
reg = <0 0x1001e000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pio: pinctrl@1001f000 {
|
||||
compatible = "mediatek,mt7988-pinctrl";
|
||||
reg = <0 0x1001f000 0 0x1000>,
|
||||
<0 0x11c10000 0 0x1000>,
|
||||
<0 0x11d00000 0 0x1000>,
|
||||
<0 0x11d20000 0 0x1000>,
|
||||
<0 0x11e00000 0 0x1000>,
|
||||
<0 0x11f00000 0 0x1000>,
|
||||
<0 0x1000b000 0 0x1000>;
|
||||
reg-names = "gpio_base", "iocfg_tr_base",
|
||||
"iocfg_br_base", "iocfg_rb_base",
|
||||
"iocfg_lb_base", "iocfg_tl_base", "eint";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pio 0 0 83>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&gic>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
mdio0_pins: mdio0-pins {
|
||||
mux {
|
||||
function = "eth";
|
||||
groups = "mdc_mdio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "mdc_mdio0";
|
||||
drive-strength = <MTK_DRIVE_8mA>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0-pins-g0 {
|
||||
mux {
|
||||
function = "i2c";
|
||||
groups = "i2c0_1";
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1-pins-g0 {
|
||||
mux {
|
||||
function = "i2c";
|
||||
groups = "i2c1_0";
|
||||
};
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2-pins-g0 {
|
||||
mux {
|
||||
function = "i2c";
|
||||
groups = "i2c2_1";
|
||||
};
|
||||
};
|
||||
|
||||
gbe0_led0_pins: gbe0-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe0_led0";
|
||||
};
|
||||
};
|
||||
|
||||
gbe1_led0_pins: gbe1-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe1_led0";
|
||||
};
|
||||
};
|
||||
|
||||
gbe2_led0_pins: gbe2-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe2_led0";
|
||||
};
|
||||
};
|
||||
|
||||
gbe3_led0_pins: gbe3-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe3_led0";
|
||||
};
|
||||
};
|
||||
|
||||
i2p5gbe_led0_pins: 2p5gbe-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "2p5gbe_led0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
boottrap: boottrap@1001f6f0 {
|
||||
compatible = "mediatek,boottrap";
|
||||
reg = <0 0x1001f6f0 0 0x4>;
|
||||
};
|
||||
|
||||
sgmiisys0: syscon@10060000 {
|
||||
compatible = "mediatek,mt7988-sgmiisys",
|
||||
"mediatek,mt7988-sgmiisys_0",
|
||||
"syscon";
|
||||
reg = <0 0x10060000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sgmiisys1: syscon@10070000 {
|
||||
compatible = "mediatek,mt7988-sgmiisys",
|
||||
"mediatek,mt7988-sgmiisys_1",
|
||||
"syscon";
|
||||
reg = <0 0x10070000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
usxgmiisys0: usxgmiisys@10080000 {
|
||||
compatible = "mediatek,mt7988-usxgmiisys",
|
||||
"mediatek,mt7988-usxgmiisys_0",
|
||||
"syscon";
|
||||
reg = <0 0x10080000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
usxgmiisys1: usxgmiisys@10081000 {
|
||||
compatible = "mediatek,mt7988-usxgmiisys",
|
||||
"mediatek,mt7988-usxgmiisys_1",
|
||||
"syscon";
|
||||
reg = <0 0x10081000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
xfi_pextp0: xfi_pextp@11f20000 {
|
||||
compatible = "mediatek,mt7988-xfi_pextp",
|
||||
"mediatek,mt7988-xfi_pextp_0",
|
||||
"syscon";
|
||||
reg = <0 0x11f20000 0 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
xfi_pextp1: xfi_pextp@11f30000 {
|
||||
compatible = "mediatek,mt7988-xfi_pextp",
|
||||
"mediatek,mt7988-xfi_pextp_1",
|
||||
"syscon";
|
||||
reg = <0 0x11f30000 0 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
xfi_pll: xfi_pll@11f40000 {
|
||||
compatible = "mediatek,mt7988-xfi_pll", "syscon";
|
||||
reg = <0 0x11f40000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
mcusys: mcusys@100e0000 {
|
||||
compatible = "mediatek,mt7988-mcusys", "syscon";
|
||||
reg = <0 0x100e0000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart0: serial@11000000 {
|
||||
compatible = "mediatek,mt7986-uart",
|
||||
"mediatek,mt6577-uart";
|
||||
reg = <0 0x11000000 0 0x100>;
|
||||
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
||||
/*
|
||||
* 8250-mtk driver don't control "baud" clock since commit
|
||||
* e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
|
||||
* still need to be passed to the driver to prevent probe fail
|
||||
*/
|
||||
clocks = <&topckgen CLK_TOP_UART_SEL>,
|
||||
<&infracfg CLK_INFRA_52M_UART0_CK>;
|
||||
clock-names = "baud", "bus";
|
||||
assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
|
||||
<&infracfg CLK_INFRA_MUX_UART0_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
|
||||
<&topckgen CLK_TOP_UART_SEL>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@11003000 {
|
||||
compatible = "mediatek,mt7988-i2c",
|
||||
"mediatek,mt7981-i2c";
|
||||
reg = <0 0x11003000 0 0x1000>,
|
||||
<0 0x10217080 0 0x80>;
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-div = <1>;
|
||||
clocks = <&infracfg CLK_INFRA_I2C_BCK>,
|
||||
<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@11004000 {
|
||||
compatible = "mediatek,mt7988-i2c",
|
||||
"mediatek,mt7981-i2c";
|
||||
reg = <0 0x11004000 0 0x1000>,
|
||||
<0 0x10217100 0 0x80>;
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-div = <1>;
|
||||
clocks = <&infracfg CLK_INFRA_I2C_BCK>,
|
||||
<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@11005000 {
|
||||
compatible = "mediatek,mt7988-i2c",
|
||||
"mediatek,mt7981-i2c";
|
||||
reg = <0 0x11005000 0 0x1000>,
|
||||
<0 0x10217180 0 0x80>;
|
||||
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-div = <1>;
|
||||
clocks = <&infracfg CLK_INFRA_I2C_BCK>,
|
||||
<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@11007000 {
|
||||
compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
|
||||
reg = <0 0x11007000 0 0x100>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topckgen CLK_TOP_MPLL_D2>,
|
||||
<&topckgen CLK_TOP_SPI_SEL>,
|
||||
<&infracfg CLK_INFRA_104M_SPI0>,
|
||||
<&infracfg CLK_INFRA_66M_SPI0_HCK>;
|
||||
clock-names = "parent-clk", "sel-clk", "spi-clk",
|
||||
"spi-hclk";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie2: pcie@11280000 {
|
||||
compatible = "mediatek,mt7988-pcie",
|
||||
"mediatek,mt7986-pcie",
|
||||
"mediatek,mt8192-pcie";
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
reg = <0 0x11280000 0 0x2000>;
|
||||
reg-names = "pcie-mac";
|
||||
linux,pci-domain = <3>;
|
||||
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x81000000 0x00 0x20000000 0x00
|
||||
0x20000000 0x00 0x00200000>,
|
||||
<0x82000000 0x00 0x20200000 0x00
|
||||
0x20200000 0x00 0x07e00000>;
|
||||
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
|
||||
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
|
||||
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
|
||||
<&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
|
||||
clock-names = "pl_250m", "tl_26m", "peri_26m",
|
||||
"top_133m";
|
||||
status = "disabled";
|
||||
|
||||
phys = <&xphyu3port0 PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc2 0>,
|
||||
<0 0 0 2 &pcie_intc2 1>,
|
||||
<0 0 0 3 &pcie_intc2 2>,
|
||||
<0 0 0 4 &pcie_intc2 3>;
|
||||
pcie_intc2: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
pcie3: pcie@11290000 {
|
||||
compatible = "mediatek,mt7988-pcie",
|
||||
"mediatek,mt7986-pcie",
|
||||
"mediatek,mt8192-pcie";
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
reg = <0 0x11290000 0 0x2000>;
|
||||
reg-names = "pcie-mac";
|
||||
linux,pci-domain = <2>;
|
||||
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x81000000 0x00 0x28000000 0x00
|
||||
0x28000000 0x00 0x00200000>,
|
||||
<0x82000000 0x00 0x28200000 0x00
|
||||
0x28200000 0x00 0x07e00000>;
|
||||
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
|
||||
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
|
||||
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
|
||||
<&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
|
||||
clock-names = "pl_250m", "tl_26m", "peri_26m",
|
||||
"top_133m";
|
||||
status = "disabled";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc3 0>,
|
||||
<0 0 0 2 &pcie_intc3 1>,
|
||||
<0 0 0 3 &pcie_intc3 2>,
|
||||
<0 0 0 4 &pcie_intc3 3>;
|
||||
pcie_intc3: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0: pcie@11300000 {
|
||||
compatible = "mediatek,mt7988-pcie",
|
||||
"mediatek,mt7986-pcie",
|
||||
"mediatek,mt8192-pcie";
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
reg = <0 0x11300000 0 0x2000>;
|
||||
reg-names = "pcie-mac";
|
||||
linux,pci-domain = <0>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x81000000 0x00 0x30000000 0x00
|
||||
0x30000000 0x00 0x00200000>,
|
||||
<0x82000000 0x00 0x30200000 0x00
|
||||
0x30200000 0x00 0x07e00000>;
|
||||
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
|
||||
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
|
||||
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
|
||||
<&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
|
||||
clock-names = "pl_250m", "tl_26m", "peri_26m",
|
||||
"top_133m";
|
||||
status = "disabled";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
|
||||
<0 0 0 2 &pcie_intc0 1>,
|
||||
<0 0 0 3 &pcie_intc0 2>,
|
||||
<0 0 0 4 &pcie_intc0 3>;
|
||||
pcie_intc0: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1: pcie@11310000 {
|
||||
compatible = "mediatek,mt7988-pcie",
|
||||
"mediatek,mt7986-pcie",
|
||||
"mediatek,mt8192-pcie";
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
reg = <0 0x11310000 0 0x2000>;
|
||||
reg-names = "pcie-mac";
|
||||
linux,pci-domain = <1>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x81000000 0x00 0x38000000 0x00
|
||||
0x38000000 0x00 0x00200000>,
|
||||
<0x82000000 0x00 0x38200000 0x00
|
||||
0x38200000 0x00 0x07e00000>;
|
||||
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
|
||||
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
|
||||
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
|
||||
<&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
|
||||
clock-names = "pl_250m", "tl_26m", "peri_26m",
|
||||
"top_133m";
|
||||
status = "disabled";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
|
||||
<0 0 0 2 &pcie_intc1 1>,
|
||||
<0 0 0 3 &pcie_intc1 2>,
|
||||
<0 0 0 4 &pcie_intc1 3>;
|
||||
pcie_intc1: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
ssusb0: usb@11190000 {
|
||||
compatible = "mediatek,mt7988-xhci",
|
||||
"mediatek,mtk-xhci";
|
||||
reg = <0 0x11190000 0 0x2e00>,
|
||||
<0 0x11193e00 0 0x0100>;
|
||||
reg-names = "mac", "ippc";
|
||||
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&xphyu2port0 PHY_TYPE_USB2>,
|
||||
<&xphyu3port0 PHY_TYPE_USB3>;
|
||||
clocks = <&infracfg CLK_INFRA_USB_SYS>,
|
||||
<&infracfg CLK_INFRA_USB_XHCI>,
|
||||
<&infracfg CLK_INFRA_USB_REF>,
|
||||
<&infracfg CLK_INFRA_66M_USB_HCK>,
|
||||
<&infracfg CLK_INFRA_133M_USB_HCK>;
|
||||
clock-names = "sys_ck",
|
||||
"xhci_ck",
|
||||
"ref_ck",
|
||||
"mcu_ck",
|
||||
"dma_ck";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
mediatek,p0_speed_fixup;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssusb1: usb@11200000 {
|
||||
compatible = "mediatek,mt7988-xhci",
|
||||
"mediatek,mtk-xhci";
|
||||
reg = <0 0x11200000 0 0x2e00>,
|
||||
<0 0x11203e00 0 0x0100>;
|
||||
reg-names = "mac", "ippc";
|
||||
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&tphyu2port0 PHY_TYPE_USB2>,
|
||||
<&tphyu3port0 PHY_TYPE_USB3>;
|
||||
clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
|
||||
<&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
|
||||
<&infracfg CLK_INFRA_USB_CK_P1>,
|
||||
<&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
|
||||
<&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
|
||||
clock-names = "sys_ck",
|
||||
"xhci_ck",
|
||||
"ref_ck",
|
||||
"mcu_ck",
|
||||
"dma_ck";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tphy: tphy@11c50000 {
|
||||
compatible = "mediatek,mt7988",
|
||||
"mediatek,generic-tphy-v2";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
tphyu2port0: usb-phy@11c50000 {
|
||||
reg = <0 0x11c50000 0 0x700>;
|
||||
clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
|
||||
clock-names = "ref";
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
tphyu3port0: usb-phy@11c50700 {
|
||||
reg = <0 0x11c50700 0 0x900>;
|
||||
clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
|
||||
clock-names = "ref";
|
||||
#phy-cells = <1>;
|
||||
mediatek,usb3-pll-ssc-delta;
|
||||
mediatek,usb3-pll-ssc-delta1;
|
||||
};
|
||||
};
|
||||
|
||||
topmisc: topmisc@11d10000 {
|
||||
compatible = "mediatek,mt7988-topmisc", "syscon",
|
||||
"mediatek,mt7988-power-controller";
|
||||
reg = <0 0x11d10000 0 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
xphy: xphy@11e10000 {
|
||||
compatible = "mediatek,mt7988",
|
||||
"mediatek,xsphy";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
xphyu2port0: usb-phy@11e10000 {
|
||||
reg = <0 0x11e10000 0 0x400>;
|
||||
clocks = <&infracfg CLK_INFRA_USB_UTMI>;
|
||||
clock-names = "ref";
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
xphyu3port0: usb-phy@11e13000 {
|
||||
reg = <0 0x11e13400 0 0x500>;
|
||||
clocks = <&infracfg CLK_INFRA_USB_PIPE>;
|
||||
clock-names = "ref";
|
||||
#phy-cells = <1>;
|
||||
mediatek,syscon-type = <&topmisc 0x218 0>;
|
||||
};
|
||||
};
|
||||
|
||||
efuse: efuse@11f50000 {
|
||||
compatible = "mediatek,efuse";
|
||||
reg = <0 0x11f50000 0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
lvts_calibration: calib@918 {
|
||||
reg = <0x918 0x28>;
|
||||
};
|
||||
phy_calibration_p0: calib@940 {
|
||||
reg = <0x940 0x10>;
|
||||
};
|
||||
phy_calibration_p1: calib@954 {
|
||||
reg = <0x954 0x10>;
|
||||
};
|
||||
phy_calibration_p2: calib@968 {
|
||||
reg = <0x968 0x10>;
|
||||
};
|
||||
phy_calibration_p3: calib@97c {
|
||||
reg = <0x97c 0x10>;
|
||||
};
|
||||
cpufreq_calibration: calib@278 {
|
||||
reg = <0x278 0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
ethsys: syscon@15000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mediatek,mt7988-ethsys", "syscon";
|
||||
reg = <0 0x15000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
switch: switch@15020000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mediatek,mt7988-switch";
|
||||
reg = <0 0x15020000 0 0x8000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <ðrst 0>;
|
||||
};
|
||||
|
||||
ethwarp: syscon@15031000 {
|
||||
compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
|
||||
reg = <0 0x15031000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
ethrst: reset-controller {
|
||||
compatible = "ti,syscon-reset";
|
||||
#reset-cells = <1>;
|
||||
ti,reset-bits = <
|
||||
0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
eth: ethernet@15100000 {
|
||||
compatible = "mediatek,mt7988-eth";
|
||||
reg = <0 0x15100000 0 0x80000>,
|
||||
<0 0x15400000 0 0x380000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <ðsys CLK_ETHDMA_XGP1_EN>,
|
||||
<ðsys CLK_ETHDMA_XGP2_EN>,
|
||||
<ðsys CLK_ETHDMA_XGP3_EN>,
|
||||
<ðsys CLK_ETHDMA_FE_EN>,
|
||||
<ðsys CLK_ETHDMA_GP2_EN>,
|
||||
<ðsys CLK_ETHDMA_GP1_EN>,
|
||||
<ðsys CLK_ETHDMA_GP3_EN>,
|
||||
<ðsys CLK_ETHDMA_ESW_EN>,
|
||||
<ðsys CLK_ETHDMA_CRYPT0_EN>,
|
||||
<&sgmiisys0 CLK_SGM0_TX_EN>,
|
||||
<&sgmiisys0 CLK_SGM0_RX_EN>,
|
||||
<&sgmiisys1 CLK_SGM1_TX_EN>,
|
||||
<&sgmiisys1 CLK_SGM1_RX_EN>,
|
||||
<ðwarp CLK_ETHWARP_WOCPU2_EN>,
|
||||
<ðwarp CLK_ETHWARP_WOCPU1_EN>,
|
||||
<ðwarp CLK_ETHWARP_WOCPU0_EN>,
|
||||
<&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
|
||||
<&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
|
||||
<&topckgen CLK_TOP_SGM_0_SEL>,
|
||||
<&topckgen CLK_TOP_SGM_1_SEL>,
|
||||
<&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>,
|
||||
<&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>,
|
||||
<&topckgen CLK_TOP_ETH_GMII_SEL>,
|
||||
<&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
|
||||
<&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
|
||||
<&topckgen CLK_TOP_ETH_SYS_SEL>,
|
||||
<&topckgen CLK_TOP_ETH_XGMII_SEL>,
|
||||
<&topckgen CLK_TOP_ETH_MII_SEL>,
|
||||
<&topckgen CLK_TOP_NETSYS_SEL>,
|
||||
<&topckgen CLK_TOP_NETSYS_500M_SEL>,
|
||||
<&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
|
||||
<&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
|
||||
<&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
|
||||
<&topckgen CLK_TOP_NETSYS_WARP_SEL>;
|
||||
clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
|
||||
"gp3", "esw", "crypto", "sgmii_tx250m",
|
||||
"sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
|
||||
"ethwarp_wocpu2", "ethwarp_wocpu1",
|
||||
"ethwarp_wocpu0", "top_usxgmii0_sel",
|
||||
"top_usxgmii1_sel", "top_sgm0_sel",
|
||||
"top_sgm1_sel", "top_xfi_phy0_xtal_sel",
|
||||
"top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
|
||||
"top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
|
||||
"top_eth_sys_sel", "top_eth_xgmii_sel",
|
||||
"top_eth_mii_sel", "top_netsys_sel",
|
||||
"top_netsys_500m_sel", "top_netsys_pao_2x_sel",
|
||||
"top_netsys_sync_250m_sel",
|
||||
"top_netsys_ppefb_250m_sel",
|
||||
"top_netsys_warp_sel";
|
||||
assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
|
||||
<&topckgen CLK_TOP_NETSYS_GSW_SEL>,
|
||||
<&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
|
||||
<&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
|
||||
<&topckgen CLK_TOP_SGM_0_SEL>,
|
||||
<&topckgen CLK_TOP_SGM_1_SEL>;
|
||||
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
|
||||
<&topckgen CLK_TOP_NET1PLL_D4>,
|
||||
<&topckgen CLK_TOP_NET1PLL_D8_D4>,
|
||||
<&topckgen CLK_TOP_NET1PLL_D8_D4>,
|
||||
<&apmixedsys CLK_APMIXED_SGMPLL>,
|
||||
<&apmixedsys CLK_APMIXED_SGMPLL>;
|
||||
mediatek,ethsys = <ðsys>;
|
||||
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
|
||||
mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
|
||||
mediatek,xfi_pextp = <&xfi_pextp0>, <&xfi_pextp1>;
|
||||
mediatek,xfi_pll = <&xfi_pll>;
|
||||
mediatek,infracfg = <&topmisc>;
|
||||
mediatek,toprgu = <&watchdog>;
|
||||
#reset-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -26,6 +26,9 @@ mediatek_setup_interfaces()
|
||||
mediatek,mt7986b-rfb)
|
||||
ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" eth1
|
||||
;;
|
||||
mediatek,mt7988a-dsa-10g-spim-snand)
|
||||
ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" "eth1 eth2"
|
||||
;;
|
||||
tplink,tl-xdr4288|\
|
||||
tplink,tl-xdr6088)
|
||||
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" eth1
|
||||
|
||||
@ -360,6 +360,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_MT6380=y
|
||||
CONFIG_REGULATOR_RT5190A=y
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
CONFIG_RESET_TI_SYSCON=y
|
||||
CONFIG_RFS_ACCEL=y
|
||||
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
|
||||
CONFIG_RPS=y
|
||||
|
||||
@ -206,6 +206,24 @@ define Device/mediatek_mt7986b-rfb
|
||||
endef
|
||||
TARGET_DEVICES += mediatek_mt7986b-rfb
|
||||
|
||||
define Device/mediatek_mt7988a-rfb-nand
|
||||
DEVICE_VENDOR := MediaTek
|
||||
DEVICE_MODEL := MT7988a nand rfb
|
||||
DEVICE_DTS := mt7988a-dsa-10g-spim-nand
|
||||
DEVICE_DTS_DIR := $(DTS_DIR)/
|
||||
KERNEL_LOADADDR := 0x48000000
|
||||
SUPPORTED_DEVICES := mediatek,mt7988a-rfb
|
||||
UBINIZE_OPTS := -E 5
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
IMAGE_SIZE := 65536k
|
||||
KERNEL_IN_UBI := 1
|
||||
IMAGES += factory.bin
|
||||
IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE)
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += mediatek_mt7988a-rfb-nand
|
||||
|
||||
define Device/tplink_tl-xdr-common
|
||||
DEVICE_VENDOR := TP-Link
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
|
||||
Loading…
Reference in New Issue
Block a user