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lantiq: VGV7510KW22 - enable the IP101A phy
The RJ45 WAN port is used for xDSL as well as the IP101A. The pins 1,2,3,6 of the RJ45 are connected to the IP101A and the pins 4,5 are connected to the xdsl chip. Drop the ip101a-rst node. It can't be controlled and is not required at all. Signed-off-by: Mathias Kresin <dev@kresin.me>
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parent
4d5db712e3
commit
db66b157db
@ -49,11 +49,6 @@
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pinctrl-0 = <&state_default>;
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state_default: pinmux {
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ip101a-rst {
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lantiq,pins = "io46";
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lantiq,output = <0>;
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lantiq,pull = <1>;
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};
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gphy-leds {
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lantiq,groups = "gphy0 led0", "gphy0 led1",
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"gphy1 led0", "gphy1 led1";
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@ -213,11 +208,33 @@
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};
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};
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wan: interface@1 {
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compatible = "lantiq,xrx200-pdi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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mtd-mac-address = <&boardconfig 0x16>;
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mtd-mac-address-increment = <2>;
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lantiq,wan;
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ethernet@0 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <0>;
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phy-mode = "mii";
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phy-handle = <&phy1>;
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};
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};
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mdio@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "lantiq,xrx200-mdio";
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phy1: ethernet-phy@1 {
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reg = <0x1>;
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compatible = "ethernet-phy-id0243.0c54", "ethernet-phy-ieee802.3-c22";
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};
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phy11: ethernet-phy@11 {
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reg = <0x11>;
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compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
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@ -23,6 +23,7 @@ CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
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CONFIG_HAVE_DMA_CONTIGUOUS=y
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CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
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CONFIG_HZ_PERIODIC=y
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CONFIG_ICPLUS_PHY=y
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CONFIG_INPUT=y
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CONFIG_INPUT_EVDEV=y
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CONFIG_INPUT_POLLDEV=y
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