From db0e6e264d7c3626772ae889a70eb4a5d14df2ed Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Wed, 19 Feb 2014 12:15:32 +0000 Subject: [PATCH] ar71xx: add kernel support for the TP-Link TL-WDR4900 v2.0 board Patch-by: TenNinjas Patchwork: http://patchwork.openwrt.org/patch/4848/ [juhosg: - rename and refresh kernel patch, - merge the board setup code into mach-archer-c7.c and drop mach-tl-wdr49000-v2.c] Signed-off-by: Gabor Juhos SVN-Revision: 39635 --- .../files/arch/mips/ath79/mach-archer-c7.c | 31 ++++++++++++++++--- .../704-MIPS-ath79-TL-WDR4900v2-support.patch | 23 ++++++++++++++ 2 files changed, 50 insertions(+), 4 deletions(-) create mode 100644 target/linux/ar71xx/patches-3.10/704-MIPS-ath79-TL-WDR4900v2-support.patch diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c index 3f9f0623dda..dc5034114fc 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c @@ -1,7 +1,8 @@ /* - * TP-LINK Archer C7 board support + * TP-LINK Archer C7/TL-WDR4900 v2 board support * * Copyright (c) 2013 Gabor Juhos + * Copyright (c) 2014 施康成 * * Based on the Qualcomm Atheros AP135/AP136 reference board support code * Copyright (c) 2012 Qualcomm Atheros @@ -24,12 +25,13 @@ #include #include #include -//#include +#include #include #include #include "common.h" +#include "dev-ap9x-pci.h" #include "dev-eth.h" #include "dev-gpio-buttons.h" #include "dev-leds-gpio.h" @@ -57,6 +59,7 @@ #define ARCHER_C7_KEYS_DEBOUNCE_INTERVAL (3 * ARCHER_C7_KEYS_POLL_INTERVAL) #define ARCHER_C7_WMAC_CALDATA_OFFSET 0x1000 +#define ARCHER_C7_PCIE_CALDATA_OFFSET 0x5000 static const char *archer_c7_part_probes[] = { "tp-link", @@ -196,7 +199,7 @@ static void __init archer_c7_gmac_setup(void) iounmap(base); } -static void __init archer_c7_setup(void) +static void __init common_setup(bool pcie_slot) { u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); @@ -212,7 +215,13 @@ static void __init archer_c7_setup(void) ath79_init_mac(tmpmac, mac, -1); ath79_register_wmac(art + ARCHER_C7_WMAC_CALDATA_OFFSET, tmpmac); - ath79_register_pci(); + if (pcie_slot) { + ath79_register_pci(); + } else { + ath79_init_mac(tmpmac, mac, -1); + ap9x_pci_setup_wmac_led_pin(0, 0); + ap91_pci_init(art + ARCHER_C7_PCIE_CALDATA_OFFSET, tmpmac); + } mdiobus_register_board_info(archer_c7_mdio0_info, ARRAY_SIZE(archer_c7_mdio0_info)); @@ -247,5 +256,19 @@ static void __init archer_c7_setup(void) ath79_register_usb(); } +static void __init archer_c7_setup(void) +{ + common_setup(true); +} + MIPS_MACHINE(ATH79_MACH_ARCHER_C7, "ARCHER-C7", "TP-LINK Archer C7", archer_c7_setup); + +static void __init tl_wdr4900_v2_setup(void) +{ + common_setup(false); +} + +MIPS_MACHINE(ATH79_MACH_TL_WDR4900_V2, "TL-WDR4900-v2", "TP-LINK TL-WDR4900 v2", + tl_wdr4900_v2_setup) + diff --git a/target/linux/ar71xx/patches-3.10/704-MIPS-ath79-TL-WDR4900v2-support.patch b/target/linux/ar71xx/patches-3.10/704-MIPS-ath79-TL-WDR4900v2-support.patch new file mode 100644 index 00000000000..1292b1da7f4 --- /dev/null +++ b/target/linux/ar71xx/patches-3.10/704-MIPS-ath79-TL-WDR4900v2-support.patch @@ -0,0 +1,23 @@ +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -108,6 +108,7 @@ enum ath79_mach_type { + ATH79_MACH_TL_WA901ND_V3, /* TP-LINK TL-WA901ND v3 */ + ATH79_MACH_TL_WDR3500, /* TP-LINK TL-WDR3500 */ + ATH79_MACH_TL_WDR4300, /* TP-LINK TL-WDR4300 */ ++ ATH79_MACH_TL_WDR4900_V2, /* TP-LINK TL-WDR4900 v2 */ + ATH79_MACH_TL_WR1041N_V2, /* TP-LINK TL-WR1041N v2 */ + ATH79_MACH_TL_WR1043ND, /* TP-LINK TL-WR1043ND */ + ATH79_MACH_TL_WR1043ND_V2, /* TP-LINK TL-WR1043ND v2 */ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -549,8 +549,9 @@ config ATH79_MACH_EAP7660D + select ATH79_DEV_M25P80 + + config ATH79_MACH_ARCHER_C7 +- bool "TP-LINK Archer C7 board support" ++ bool "TP-LINK Archer C7/TL-WDR4900 v2 board support" + select SOC_QCA955X ++ select ATH79_DEV_AP9X_PCI if PCI + select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO