From d62241cf5a208ef7e5637074093f1c9fede113e1 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 1 Feb 2025 05:03:50 +0000 Subject: [PATCH] mediatek: mt7622: fix SATA on BPi-R64 A commit which made their way into Linux stable down to 5.15 broke the SATA support on the BPi-R64. Fix this by importing a (still pending) patch re-adding the 'syscon' compatible to the pciesys clock-controller which also contains phy-mode bits referenced by the ahci_mtk driver expecting to access them using syscon_regmap_lookup_by_phandle(). Signed-off-by: Daniel Golle (cherry picked from commit 69890e16b37d59b55ba64633522c727f957cb2fd) --- ...ek-mt7622-readd-syscon-to-pciesys-no.patch | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 target/linux/mediatek/patches-5.15/116-arm64-dts-mediatek-mt7622-readd-syscon-to-pciesys-no.patch diff --git a/target/linux/mediatek/patches-5.15/116-arm64-dts-mediatek-mt7622-readd-syscon-to-pciesys-no.patch b/target/linux/mediatek/patches-5.15/116-arm64-dts-mediatek-mt7622-readd-syscon-to-pciesys-no.patch new file mode 100644 index 00000000000..56899977151 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/116-arm64-dts-mediatek-mt7622-readd-syscon-to-pciesys-no.patch @@ -0,0 +1,33 @@ +From 98bc223d174c7f544e8f6c4f0caa8fa144f2f4dc Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Fri, 28 Jun 2024 12:55:40 +0200 +Subject: [PATCH 2/2] arm64: dts: mediatek: mt7622: readd syscon to pciesys + node + +Sata node reference the pciesys with the property mediatek,phy-node +and that is used as a syscon to access the pciesys regs. + +Readd the syscon compatible to pciesys node to restore correct +functionality of the SATA interface. + +Fixes: 3ba5a6159434 ("arm64: dts: mediatek: mt7622: fix clock controllers") +Reported-by: Frank Wunderlich +Co-developed-by: Frank Wunderlich +Signed-off-by: Frank Wunderlich +Signed-off-by: Christian Marangi +Cc: stable@vger.kernel.org +--- + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -779,7 +779,7 @@ + }; + + pciesys: clock-controller@1a100800 { +- compatible = "mediatek,mt7622-pciesys"; ++ compatible = "mediatek,mt7622-pciesys", "syscon"; + reg = <0 0x1a100800 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>;