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realtek: Copy all BPDUs to the kernel
In order to receive STP information at the kernel level, we make sure that all Bridge Protocol Data Units are copied to the CPU-Port. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This commit is contained in:
Birger Koblitz
Daniel Golle
parent
9d396fc1e8
commit
d22923be66
@ -154,6 +154,14 @@ static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
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priv->r->vlan_fwd_on_inner(i, true);
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}
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static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
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{
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int i;
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for (i = 0; i < priv->cpu_port; i++)
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priv->r->set_receive_management_action(i, BPDU, COPY2CPU);
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}
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static int rtl83xx_setup(struct dsa_switch *ds)
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{
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int i;
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@ -191,6 +199,8 @@ static int rtl83xx_setup(struct dsa_switch *ds)
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rtl83xx_vlan_setup(priv);
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rtl83xx_setup_bpdu_traps(priv);
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ds->configure_vlan_while_not_filtering = true;
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priv->r->l2_learning_setup();
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@ -1673,6 +1673,26 @@ void rtl838x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)
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sw_w32(algomsk, RTL838X_TRK_HASH_CTRL + (algoidx << 2));
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}
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void rtl838x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action)
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{
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switch(type) {
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case BPDU:
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sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
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RTL838X_RMA_BPDU_CTRL + ((port >> 4) << 2));
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break;
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case PTP:
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sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
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RTL838X_RMA_PTP_CTRL + ((port >> 4) << 2));
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break;
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case LLTP:
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sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
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RTL838X_RMA_LLTP_CTRL + ((port >> 4) << 2));
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break;
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default:
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break;
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}
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}
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const struct rtl838x_reg rtl838x_reg = {
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.mask_port_reg_be = rtl838x_mask_port_reg,
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.set_port_reg_be = rtl838x_set_port_reg,
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@ -1756,6 +1776,7 @@ const struct rtl838x_reg rtl838x_reg = {
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.route_write = rtl838x_route_write,
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.l3_setup = rtl838x_l3_setup,
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.set_distribution_algorithm = rtl838x_set_distribution_algorithm,
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.set_receive_management_action = rtl838x_set_receive_management_action,
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};
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irqreturn_t rtl838x_switch_irq(int irq, void *dev_id)
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@ -11,8 +11,10 @@
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#define RTL838X_MAC_PORT_CTRL(port) (0xd560 + (((port) << 7)))
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#define RTL839X_MAC_PORT_CTRL(port) (0x8004 + (((port) << 7)))
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#define RTL930X_MAC_PORT_CTRL(port) (0x3260 + (((port) << 6)))
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#define RTL931X_MAC_PORT_CTRL (0x6004)
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#define RTL930X_MAC_L2_PORT_CTRL(port) (0x3268 + (((port) << 6)))
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#define RTL931X_MAC_PORT_CTRL(port) (0x6004 + (((port) << 7)))
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#define RTL931X_MAC_L2_PORT_CTRL (0x6000)
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#define RTL838X_RST_GLB_CTRL_0 (0x003c)
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@ -132,7 +134,7 @@
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#define RTL838X_MAC_LINK_SPD_STS(p) (0xa190 + (((p >> 4) << 2)))
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#define RTL839X_MAC_LINK_SPD_STS(p) (0x03a0 + (((p >> 4) << 2)))
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#define RTL930X_MAC_LINK_SPD_STS(p) (0xCB18 + (((p >> 3) << 2)))
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#define RTL931X_MAC_LINK_SPD_STS(p) (0x0ED0 + (((p >> 3) << 2)))
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#define RTL931X_MAC_LINK_SPD_STS (0x0ED0)
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#define RTL838X_MAC_LINK_DUP_STS (0xa19c)
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#define RTL839X_MAC_LINK_DUP_STS (0x03b0)
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#define RTL930X_MAC_LINK_DUP_STS (0xCB28)
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@ -245,15 +247,11 @@
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#define RTL930X_L2_PORT_SABLK_CTRL (0x905c)
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#define RTL930X_L2_PORT_DABLK_CTRL (0x9060)
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#define RTL838X_RMA_BPDU_FLD_PMSK (0x4348)
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#define RTL930X_RMA_BPDU_FLD_PMSK (0x9F18)
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#define RTL931X_RMA_BPDU_FLD_PMSK (0x8950)
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#define RTL839X_RMA_BPDU_FLD_PMSK (0x125C)
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#define RTL838X_L2_PORT_LM_ACT(p) (0x3208 + ((p) << 2))
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#define RTL838X_VLAN_PORT_FWD (0x3A78)
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#define RTL839X_VLAN_PORT_FWD (0x27AC)
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#define RTL930X_VLAN_PORT_FWD (0x834C)
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#define RTL931X_VLAN_PORT_FWD (0x95CC)
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#define RTL838X_VLAN_FID_CTRL (0x3aa8)
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/* Port Mirroring */
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@ -370,10 +368,76 @@
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#define RTL838X_ATK_PRVNT_STS (0x5B1C)
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/* 802.1X */
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#define RTL838X_RMA_BPDU_FLD_PMSK (0x4348)
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#define RTL930X_RMA_BPDU_FLD_PMSK (0x9F18)
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#define RTL931X_RMA_BPDU_FLD_PMSK (0x8950)
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#define RTL839X_RMA_BPDU_FLD_PMSK (0x125C)
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#define RTL838X_SPCL_TRAP_CTRL (0x6980)
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#define RTL838X_SPCL_TRAP_EAPOL_CTRL (0x6988)
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#define RTL839X_SPCL_TRAP_EAPOL_CTRL (0x105C)
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#define RTL838X_SPCL_TRAP_ARP_CTRL (0x698C)
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#define RTL838X_SPCL_TRAP_IGMP_CTRL (0x6984)
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#define RTL838X_SPCL_TRAP_IPV6_CTRL (0x6994)
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#define RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL (0x6998)
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#define RTL839X_SPCL_TRAP_CTRL (0x1054)
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#define RTL839X_SPCL_TRAP_EAPOL_CTRL (0x105C)
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#define RTL839X_SPCL_TRAP_ARP_CTRL (0x1060)
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#define RTL839X_SPCL_TRAP_IGMP_CTRL (0x1058)
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#define RTL839X_SPCL_TRAP_IPV6_CTRL (0x1064)
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#define RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL (0x1068)
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#define RTL839X_SPCL_TRAP_SWITCH_IPV4_ADDR_CTRL (0x106C)
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#define RTL839X_SPCL_TRAP_CRC_CTRL (0x1070)
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/* special port action controls */
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/*
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values:
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0 = FORWARD (default)
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1 = DROP
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2 = TRAP2CPU
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3 = FLOOD IN ALL PORT
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Register encoding.
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offset = CTRL + (port >> 4) << 2
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value/mask = 3 << ((port&0xF) << 1)
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*/
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typedef enum {
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BPDU = 0,
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PTP,
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PTP_UDP,
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PTP_ETH2,
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LLTP,
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EAPOL,
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GRATARP,
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} rma_ctrl_t;
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typedef enum {
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FORWARD = 0,
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DROP,
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TRAP2CPU,
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FLOODALL,
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TRAP2MASTERCPU,
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COPY2CPU,
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} action_type_t;
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#define RTL838X_RMA_BPDU_CTRL (0x4330)
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#define RTL839X_RMA_BPDU_CTRL (0x122C)
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#define RTL930X_RMA_BPDU_CTRL (0x9E7C)
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#define RTL931X_RMA_BPDU_CTRL (0x881C)
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#define RTL838X_RMA_PTP_CTRL (0x4338)
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#define RTL839X_RMA_PTP_CTRL (0x123C)
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#define RTL930X_RMA_PTP_CTRL (0x9E88)
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#define RTL931X_RMA_PTP_CTRL (0x8834)
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#define RTL838X_RMA_LLTP_CTRL (0x4340)
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#define RTL839X_RMA_LLTP_CTRL (0x124C)
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#define RTL930X_RMA_LLTP_CTRL (0x9EFC)
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#define RTL931X_RMA_LLTP_CTRL (0x8918)
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#define RTL930X_RMA_EAPOL_CTRL (0x9F08)
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#define RTL931X_RMA_EAPOL_CTRL (0x8930)
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#define RTL931X_TRAP_ARP_GRAT_PORT_ACT (0x8C04)
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/* QoS */
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#define RTL838X_QM_INTPRI2QID_CTRL (0x5F00)
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@ -414,23 +478,37 @@
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#define RTL838X_METER_GLB_CTRL (0x4B08)
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#define RTL839X_METER_GLB_CTRL (0x1300)
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#define RTL930X_METER_GLB_CTRL (0xa0a0)
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#define RTL931X_METER_GLB_CTRL (0x411C)
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#define RTL839X_ACL_CTRL (0x1288)
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#define RTL838X_ACL_BLK_LOOKUP_CTRL (0x6100)
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#define RTL839X_ACL_BLK_LOOKUP_CTRL (0x1280)
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#define RTL930X_PIE_BLK_LOOKUP_CTRL (0xa5a0)
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#define RTL931X_PIE_BLK_LOOKUP_CTRL (0x4180)
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#define RTL838X_ACL_BLK_PWR_CTRL (0x6104)
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#define RTL839X_PS_ACL_PWR_CTRL (0x049c)
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#define RTL838X_ACL_BLK_TMPLTE_CTRL(block) (0x6108 + ((block) << 2))
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#define RTL839X_ACL_BLK_TMPLTE_CTRL(block) (0x128c + ((block) << 2))
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#define RTL930X_PIE_BLK_TMPLTE_CTRL(block) (0xa624 + ((block) << 2))
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#define RTL931X_PIE_BLK_TMPLTE_CTRL(block) (0x4214 + ((block) << 2))
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#define RTL838X_ACL_BLK_GROUP_CTRL (0x615C)
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#define RTL839X_ACL_BLK_GROUP_CTRL (0x12ec)
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#define RTL838X_ACL_CLR_CTRL (0x6168)
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#define RTL839X_ACL_CLR_CTRL (0x12fc)
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#define RTL930X_PIE_CLR_CTRL (0xa66c)
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#define RTL931X_PIE_CLR_CTRL (0x42D8)
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#define RTL838X_DMY_REG27 (0x3378)
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#define RTL838X_ACL_PORT_LOOKUP_CTRL(p) (0x616C + (((p) << 2)))
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#define RTL930X_ACL_PORT_LOOKUP_CTRL(p) (0xA784 + (((p) << 2)))
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#define RTL931X_ACL_PORT_LOOKUP_CTRL(p) (0x44F8 + (((p) << 2)))
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#define RTL930X_PIE_BLK_PHASE_CTRL (0xA5A4)
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// PIE actions
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@ -477,6 +555,7 @@
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#define PIE_BLOCK_SIZE 128
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#define MAX_PIE_ENTRIES (18 * PIE_BLOCK_SIZE)
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#define N_FIXED_FIELDS 12
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#define N_FIXED_FIELDS_RTL931X 14
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#define MAX_COUNTERS 2048
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#define MAX_ROUTES 512
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#define MAX_HOST_ROUTES 1536
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@ -929,6 +1008,7 @@ struct rtl838x_reg {
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void (*set_l3_router_mac)(u32 idx, struct rtl93xx_rt_mac *m);
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void (*set_l3_egress_intf)(int idx, struct rtl838x_l3_intf *intf);
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void (*set_distribution_algorithm)(int group, int algoidx, u32 algomask);
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void (*set_receive_management_action)(int port, rma_ctrl_t type, action_type_t action);
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};
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struct rtl838x_switch_priv {
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@ -1797,6 +1797,26 @@ void rtl839x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)
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sw_w32(algomsk, RTL839X_TRK_HASH_CTRL + (algoidx << 2));
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}
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void rtl839x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action)
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{
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switch(type) {
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case BPDU:
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sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
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RTL839X_RMA_BPDU_CTRL + ((port >> 4) << 2));
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break;
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case PTP:
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sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
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RTL839X_RMA_PTP_CTRL + ((port >> 4) << 2));
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break;
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case LLTP:
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sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
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RTL839X_RMA_LLTP_CTRL + ((port >> 4) << 2));
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break;
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default:
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break;
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}
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}
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const struct rtl838x_reg rtl839x_reg = {
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.mask_port_reg_be = rtl839x_mask_port_reg_be,
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.set_port_reg_be = rtl839x_set_port_reg_be,
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@ -1880,4 +1900,5 @@ const struct rtl838x_reg rtl839x_reg = {
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.route_write = rtl839x_route_write,
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.l3_setup = rtl839x_l3_setup,
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.set_distribution_algorithm = rtl839x_set_distribution_algorithm,
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.set_receive_management_action = rtl839x_set_receive_management_action,
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};
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