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ramips: rt3883: add inital support for the DIR-645 board
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 33843
This commit is contained in:
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@ -62,11 +62,12 @@ enum ramips_mach_type {
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RAMIPS_MACH_WR6202, /* Accton WR6202 */
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RAMIPS_MACH_XDXRN502J, /* unknown XDX-RN502J */
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RAMIPS_MACH_UR_336UN, /* UPVEL ROUTER */
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/* RT3352 based machines */
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RAMIPS_MACH_ALL5002, /* Allnet ALL5002 */
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RAMIPS_MACH_DIR_615_H1,
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/* RT3662 based machines */
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RAMIPS_MACH_DIR_645, /* D-Link DIR-645 */
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RAMIPS_MACH_RT_N56U, /* Asus RT-N56U */
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};
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@ -8,6 +8,11 @@ config RT3883_MACH_RT_N56U
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select RALINK_DEV_GPIO_BUTTONS
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select RALINK_DEV_GPIO_LEDS
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config RT3883_MACH_DIR_645
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bool "D-Link DIR-645 support"
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select RALINK_DEV_GPIO_BUTTONS
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select RALINK_DEV_GPIO_LEDS
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endmenu
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endif
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@ -11,4 +11,5 @@ obj-y := irq.o setup.o devices.o rt3883.o clock.o
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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obj-$(CONFIG_RT3883_MACH_DIR_645) += mach-dir-645.o
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obj-$(CONFIG_RT3883_MACH_RT_N56U) += mach-rt-n56u.o
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147
target/linux/ramips/files/arch/mips/ralink/rt3883/mach-dir-645.c
Normal file
147
target/linux/ramips/files/arch/mips/ralink/rt3883/mach-dir-645.c
Normal file
@ -0,0 +1,147 @@
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/*
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* D-Link DIR-645 board support
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*
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* Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/rtl8367.h>
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#include <linux/ethtool.h>
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#include <linux/rt2x00_platform.h>
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#include <linux/spi/spi.h>
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#include <asm/mach-ralink/machine.h>
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#include <asm/mach-ralink/dev-gpio-buttons.h>
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#include <asm/mach-ralink/dev-gpio-leds.h>
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#include <asm/mach-ralink/rt3883.h>
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#include <asm/mach-ralink/rt3883_regs.h>
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#include <asm/mach-ralink/ramips_eth_platform.h>
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#include "devices.h"
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#define DIR_645_GPIO_LED_INET 0
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#define DIR_645_GPIO_LED_WPS 26
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#define DIR_645_GPIO_BUTTON_RESET 9
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#define DIR_645_GPIO_BUTTON_WPS 14
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#define DIR_645_GPIO_USB_POWER 30
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#define DIR_645_GPIO_RTL8367_SCK 2
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#define DIR_645_GPIO_RTL8367_SDA 1
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#define DIR_645_KEYS_POLL_INTERVAL 20
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#define DIR_645_KEYS_DEBOUNCE_INTERVAL (3 * DIR_645_KEYS_POLL_INTERVAL)
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static struct gpio_led dir_645_leds_gpio[] __initdata = {
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{
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.name = "d-link:green:inet",
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.gpio = DIR_645_GPIO_LED_INET,
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.active_low = 1,
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},
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{
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.name = "d-link:green:wps",
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.gpio = DIR_645_GPIO_LED_WPS,
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.active_low = 1,
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},
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};
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static struct gpio_keys_button dir_645_gpio_buttons[] __initdata = {
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{
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.desc = "reset",
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.type = EV_KEY,
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.code = KEY_RESTART,
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.debounce_interval = DIR_645_KEYS_DEBOUNCE_INTERVAL,
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.gpio = DIR_645_GPIO_BUTTON_RESET,
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.active_low = 1,
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},
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{
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.desc = "wps",
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.type = EV_KEY,
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.code = KEY_WPS_BUTTON,
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.debounce_interval = DIR_645_KEYS_DEBOUNCE_INTERVAL,
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.gpio = DIR_645_GPIO_BUTTON_WPS,
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.active_low = 1,
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}
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};
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static struct rtl8367_extif_config dir_645_rtl8367_extif1_cfg = {
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.txdelay = 1,
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.rxdelay = 0,
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.mode = RTL8367_EXTIF_MODE_RGMII,
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.ability = {
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.force_mode = 1,
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.txpause = 1,
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.rxpause = 1,
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.link = 1,
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.duplex = 1,
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.speed = RTL8367_PORT_SPEED_1000,
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}
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};
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static struct rtl8367_platform_data dir_645_rtl8367_data = {
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.gpio_sda = DIR_645_GPIO_RTL8367_SDA,
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.gpio_sck = DIR_645_GPIO_RTL8367_SCK,
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.extif1_cfg = &dir_645_rtl8367_extif1_cfg,
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};
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static struct platform_device dir_645_rtl8367_device = {
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.name = RTL8367B_DRIVER_NAME,
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.id = -1,
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.dev = {
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.platform_data = &dir_645_rtl8367_data,
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}
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};
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static struct spi_board_info dir_645_spi_info[] = {
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{
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.bus_num = 0,
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.chip_select = 0,
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.max_speed_hz = 25000000,
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.modalias = "m25p80",
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}
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};
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static void __init dir_645_gpio_init(void)
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{
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rt3883_gpio_init(RT3883_GPIO_MODE_I2C |
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RT3883_GPIO_MODE_UART0(RT3883_GPIO_MODE_GPIO) |
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RT3883_GPIO_MODE_JTAG |
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RT3883_GPIO_MODE_PCI(RT3883_GPIO_MODE_PCI_FNC));
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}
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static void __init dir_645_init(void)
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{
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dir_645_gpio_init();
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rt3883_register_spi(dir_645_spi_info,
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ARRAY_SIZE(dir_645_spi_info));
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ramips_register_gpio_leds(-1, ARRAY_SIZE(dir_645_leds_gpio),
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dir_645_leds_gpio);
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ramips_register_gpio_buttons(-1, DIR_645_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(dir_645_gpio_buttons),
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dir_645_gpio_buttons);
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platform_device_register(&dir_645_rtl8367_device);
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rt3883_wlan_data.disable_5ghz = 1;
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rt3883_register_wlan();
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rt3883_eth_data.speed = SPEED_1000;
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rt3883_eth_data.duplex = DUPLEX_FULL;
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rt3883_eth_data.tx_fc = 1;
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rt3883_eth_data.rx_fc = 1;
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rt3883_register_ethernet();
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rt3883_register_wdt(false);
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rt3883_register_usbhost();
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}
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MIPS_MACHINE(RAMIPS_MACH_DIR_645, "DIR-645", "D-Link DIR-645", dir_645_init);
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@ -61,6 +61,7 @@ CONFIG_IMAGE_CMDLINE_HACK=y
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_IRQ_CPU=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_M25PXX_USE_FAST_READ=y
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CONFIG_MDIO_BOARDINFO=y
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# CONFIG_MII is not set
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CONFIG_MIPS=y
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@ -70,6 +71,7 @@ CONFIG_MIPS_MT_DISABLED=y
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CONFIG_MIPS_RALINK=y
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# CONFIG_MTD_CFI_INTELEXT is not set
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CONFIG_MTD_CMDLINE_PARTS=y
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CONFIG_MTD_M25P80=y
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CONFIG_MTD_PHYSMAP=y
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CONFIG_NEED_DMA_MAP_STATE=y
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CONFIG_NEED_PER_CPU_KM=y
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@ -90,8 +92,10 @@ CONFIG_RALINK_DEV_GPIO_LEDS=y
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# CONFIG_RALINK_RT305X is not set
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CONFIG_RALINK_RT3883=y
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CONFIG_RAMIPS_WDT=y
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CONFIG_RT3883_MACH_DIR_645=y
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CONFIG_RT3883_MACH_RT_N56U=y
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CONFIG_RTL8366_SMI=y
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CONFIG_RTL8367B_PHY=y
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CONFIG_RTL8367_PHY=y
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# CONFIG_SCSI_DMA is not set
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CONFIG_SERIAL_8250_NR_UARTS=4
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@ -99,6 +103,9 @@ CONFIG_SERIAL_8250_RT288X=y
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# CONFIG_SLAB is not set
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CONFIG_SLUB=y
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CONFIG_SOC_RT3883=y
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CONFIG_SPI=y
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CONFIG_SPI_MASTER=y
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CONFIG_SPI_RAMIPS=y
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CONFIG_SWCONFIG=y
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CONFIG_SYS_HAS_CPU_MIPS32_R1=y
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CONFIG_SYS_HAS_CPU_MIPS32_R2=y
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