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atheros: v3.18: cleanup register headers
AFAIK, no one AR2315+ chip (AR2315, AR2316, AR2317, AR2318) does not contain IR block, so remove IR registers definitions. Also remove few unused macroses. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> SVN-Revision: 44722
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@ -629,7 +629,7 @@
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+#endif /* __ASM_MACH_ATH25_WAR_H */
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-ath25/ar2315_regs.h
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@@ -0,0 +1,511 @@
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@@ -0,0 +1,470 @@
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+/*
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+ * Register definitions for AR2315+
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+ *
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@ -852,17 +852,6 @@
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+#define AR2315_GISR_ETHERNET 0x0040
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+
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+/*
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+ * Interrupt routing from IO to the processor IP bits
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+ * Define our inter mask and level
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+ */
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+#define AR2315_INTR_MISCIO SR_IBIT3
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+#define AR2315_INTR_WLAN0 SR_IBIT4
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+#define AR2315_INTR_ENET0 SR_IBIT5
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+#define AR2315_INTR_LOCALPCI SR_IBIT6
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+#define AR2315_INTR_WMACPOLL SR_IBIT7
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+#define AR2315_INTR_COMPARE SR_IBIT8
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+
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+/*
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+ * Timers
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+ */
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+#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
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@ -1110,40 +1099,10 @@
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+#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
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+#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
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+
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+/*
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+ * IR Interface Registers
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+ */
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+#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
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+
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+#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
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+
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+#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
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+#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
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+#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
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+#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
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+#define AR2315_IRCTL_SAMPLECLK_SHFT 1
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+#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
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+#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
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+
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+#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
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+#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
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+#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
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+
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+#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
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+#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
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+#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
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+#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
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+#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
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+#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
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+#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
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+#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
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+#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
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+#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
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+
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+#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-ath25/ar5312_regs.h
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@@ -0,0 +1,235 @@
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@@ -0,0 +1,224 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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@ -1184,6 +1143,10 @@
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+
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+/*
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+ * Address Map
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+ *
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+ * The AR5312 supports 2 enet MACS, even though many reference boards only
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+ * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet
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+ * PHY or PHY switch. The AR2312 supports 1 enet MAC.
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+ */
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+#define AR5312_WLAN0 0x18000000
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+#define AR5312_WLAN1 0x18500000
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@ -1196,15 +1159,6 @@
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+#define AR5312_FLASH 0x1e000000
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+
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+/*
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+ * AR5312_NUM_ENET_MAC defines the number of ethernet MACs that
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+ * should be considered available. The AR5312 supports 2 enet MACS,
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+ * even though many reference boards only actually use 1 of them
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+ * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
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+ * The AR2312 supports 1 enet MAC.
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+ */
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+#define AR5312_NUM_ENET_MAC 2
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+
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+/*
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+ * Need these defines to determine true number of ethernet MACs
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+ */
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+#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
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@ -1215,12 +1169,6 @@
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+#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
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+#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
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+
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+/*
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+ * AR5312_NUM_WMAC defines the number of Wireless MACs that\
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+ * should be considered available.
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+ */
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+#define AR5312_NUM_WMAC 2
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+
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+/* Reset/Timer Block Address Map */
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+#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
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+#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
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