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mediatek: update patch add PWM support for MT7981
Update patch with version submitted upstream. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
Daniel Golle
parent
7cbe34170e
commit
c68c71eaa9
@ -1,6 +1,6 @@
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From 947b535ebfe161e1725f1030a09de10d1460371c Mon Sep 17 00:00:00 2001
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From 73d20ebc21c562fbe79d02fa0fa38e095e716fa9 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Mon, 23 Jan 2023 20:47:34 +0000
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Date: Wed, 19 Apr 2023 20:25:51 +0100
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Subject: [PATCH] pwm: mediatek: Add support for MT7981
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The PWM unit on MT7981 uses different register offsets than previous
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@ -10,27 +10,20 @@ used for a temperature controlled fan.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/pwm/pwm-mediatek.c | 54 ++++++++++++++++++++++++++++++++------
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1 file changed, 46 insertions(+), 8 deletions(-)
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drivers/pwm/pwm-mediatek.c | 41 ++++++++++++++++++++++++++++++--------
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1 file changed, 33 insertions(+), 8 deletions(-)
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--- a/drivers/pwm/pwm-mediatek.c
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+++ b/drivers/pwm/pwm-mediatek.c
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@@ -34,10 +34,14 @@
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#define PWM_CLK_DIV_MAX 7
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+#define REG_V1 1
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+#define REG_V2 2
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+
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struct pwm_mediatek_of_data {
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@@ -38,6 +38,7 @@ struct pwm_mediatek_of_data {
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unsigned int num_pwms;
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bool pwm45_fixup;
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bool has_ck_26m_sel;
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+ u8 reg_ver;
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+ const unsigned int *reg_offset;
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};
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/**
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@@ -59,10 +63,14 @@ struct pwm_mediatek_chip {
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@@ -59,10 +60,14 @@ struct pwm_mediatek_chip {
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const struct pwm_mediatek_of_data *soc;
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};
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@ -40,169 +33,86 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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};
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+static const unsigned int mtk_pwm_reg_offset_v2[] = {
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+ 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x1c0, 0x200, 0x0240
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+ 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
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+};
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+
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static inline struct pwm_mediatek_chip *
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to_pwm_mediatek_chip(struct pwm_chip *chip)
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{
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@@ -111,7 +119,19 @@ static inline void pwm_mediatek_writel(s
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@@ -111,7 +116,7 @@ static inline void pwm_mediatek_writel(s
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unsigned int num, unsigned int offset,
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u32 value)
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{
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- writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
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+ u32 pwm_offset;
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+
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+ switch (chip->soc->reg_ver) {
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+ case REG_V2:
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+ pwm_offset = mtk_pwm_reg_offset_v2[num];
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+ break;
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+
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+ case REG_V1:
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+ default:
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+ pwm_offset = mtk_pwm_reg_offset_v1[num];
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+ }
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+
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+ writel(value, chip->regs + pwm_offset + offset);
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+ writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
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}
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static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
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@@ -146,7 +166,7 @@ static int pwm_mediatek_config(struct pw
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if (clkdiv > PWM_CLK_DIV_MAX) {
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pwm_mediatek_clk_disable(chip, pwm);
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- dev_err(chip->dev, "period %d not supported\n", period_ns);
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+ dev_err(chip->dev, "period of %d ns not supported\n", period_ns);
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return -EINVAL;
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}
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@@ -221,24 +241,20 @@ static int pwm_mediatek_probe(struct pla
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if (IS_ERR(pc->regs))
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return PTR_ERR(pc->regs);
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- pc->clk_pwms = devm_kcalloc(&pdev->dev, pc->soc->num_pwms,
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+ pc->clk_pwms = devm_kmalloc_array(&pdev->dev, pc->soc->num_pwms,
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sizeof(*pc->clk_pwms), GFP_KERNEL);
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if (!pc->clk_pwms)
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return -ENOMEM;
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pc->clk_top = devm_clk_get(&pdev->dev, "top");
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- if (IS_ERR(pc->clk_top)) {
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- dev_err(&pdev->dev, "clock: top fail: %ld\n",
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- PTR_ERR(pc->clk_top));
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- return PTR_ERR(pc->clk_top);
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- }
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+ if (IS_ERR(pc->clk_top))
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+ return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_top),
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+ "Failed to get top clock\n");
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pc->clk_main = devm_clk_get(&pdev->dev, "main");
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- if (IS_ERR(pc->clk_main)) {
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- dev_err(&pdev->dev, "clock: main fail: %ld\n",
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- PTR_ERR(pc->clk_main));
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- return PTR_ERR(pc->clk_main);
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- }
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+ if (IS_ERR(pc->clk_main))
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+ return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_main),
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+ "Failed to get main clock\n");
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for (i = 0; i < pc->soc->num_pwms; i++) {
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char name[8];
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@@ -246,11 +262,9 @@ static int pwm_mediatek_probe(struct pla
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snprintf(name, sizeof(name), "pwm%d", i + 1);
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pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
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- if (IS_ERR(pc->clk_pwms[i])) {
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- dev_err(&pdev->dev, "clock: %s fail: %ld\n",
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- name, PTR_ERR(pc->clk_pwms[i]));
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- return PTR_ERR(pc->clk_pwms[i]);
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- }
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+ if (IS_ERR(pc->clk_pwms[i]))
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+ return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i]),
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+ "Failed to get %s clock\n", name);
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}
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pc->chip.dev = &pdev->dev;
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@@ -258,10 +272,8 @@ static int pwm_mediatek_probe(struct pla
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pc->chip.npwm = pc->soc->num_pwms;
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ret = devm_pwmchip_add(&pdev->dev, &pc->chip);
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- if (ret < 0) {
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- dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
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- return ret;
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- }
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+ if (ret < 0)
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+ return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");
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return 0;
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}
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@@ -270,48 +282,63 @@ static const struct pwm_mediatek_of_data
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@@ -270,48 +275,63 @@ static const struct pwm_mediatek_of_data
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.num_pwms = 8,
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.pwm45_fixup = false,
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.has_ck_26m_sel = false,
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+ .reg_ver = REG_V1,
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+ .reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct pwm_mediatek_of_data mt7622_pwm_data = {
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.num_pwms = 6,
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.pwm45_fixup = false,
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.has_ck_26m_sel = true,
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+ .reg_ver = REG_V1,
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+ .reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct pwm_mediatek_of_data mt7623_pwm_data = {
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.num_pwms = 5,
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.pwm45_fixup = true,
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.has_ck_26m_sel = false,
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+ .reg_ver = REG_V1,
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+ .reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct pwm_mediatek_of_data mt7628_pwm_data = {
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.num_pwms = 4,
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.pwm45_fixup = true,
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.has_ck_26m_sel = false,
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+ .reg_ver = REG_V1,
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+ .reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct pwm_mediatek_of_data mt7629_pwm_data = {
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.num_pwms = 1,
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.pwm45_fixup = false,
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.has_ck_26m_sel = false,
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+ .reg_ver = REG_V1,
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+ .reg_offset = mtk_pwm_reg_offset_v1,
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};
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-static const struct pwm_mediatek_of_data mt8183_pwm_data = {
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- .num_pwms = 4,
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+static const struct pwm_mediatek_of_data mt7981_pwm_data = {
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+ .num_pwms = 3,
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static const struct pwm_mediatek_of_data mt8183_pwm_data = {
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.num_pwms = 4,
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.pwm45_fixup = false,
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.has_ck_26m_sel = true,
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+ .reg_ver = REG_V2,
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+ .reg_offset = mtk_pwm_reg_offset_v1,
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+};
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+
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+static const struct pwm_mediatek_of_data mt7981_pwm_data = {
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+ .num_pwms = 3,
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+ .pwm45_fixup = false,
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+ .has_ck_26m_sel = true,
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+ .reg_offset = mtk_pwm_reg_offset_v2,
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};
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static const struct pwm_mediatek_of_data mt7986_pwm_data = {
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.num_pwms = 2,
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.pwm45_fixup = false,
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.has_ck_26m_sel = true,
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+ .reg_ver = REG_V1,
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+};
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+
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+static const struct pwm_mediatek_of_data mt8183_pwm_data = {
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+ .num_pwms = 4,
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+ .pwm45_fixup = false,
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+ .has_ck_26m_sel = true,
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+ .reg_ver = REG_V1,
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+ .reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct pwm_mediatek_of_data mt8516_pwm_data = {
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.num_pwms = 5,
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.pwm45_fixup = false,
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.has_ck_26m_sel = true,
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+ .reg_ver = REG_V1,
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+ .reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct of_device_id pwm_mediatek_of_match[] = {
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@@ -320,6 +347,7 @@ static const struct of_device_id pwm_med
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@@ -320,6 +340,7 @@ static const struct of_device_id pwm_med
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{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
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{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
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{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
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