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lantiq: add pcie endianess switch for slave devices
The Fritzbox 3490, 5490 and 7490 devices have a Renesas µPD720202 USB3 PCIe device, which requires an endian switch for PCIe slave devices. The flag and setting is not implemented in the available patches. Since adding this setting would break other devices, a DTB setting lantiq,switch-pcie-endianess is added for selective enablement. Signed-off-by: Daniel Kestrel <kestrel1974@t-online.de>
This commit is contained in:
Daniel Kestrel
Hauke Mehrtens
parent
3702cc719b
commit
c34651c423
@ -3913,6 +3913,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */
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+#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */
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+#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */
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+#define IFX_RCU_AHB_BE_XBAR_S 0x00000008 /* Configure AHB slave port that connects to XBAR in big endian */
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+#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE
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+
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+#define IFX_PMU1_MODULE_PCIE_PHY (0)
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@ -4159,7 +4160,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+}
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+
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+#endif /* IFXMIPS_PCIE_VR9_H */
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+
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--- a/arch/mips/pci/pci-legacy.c
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+++ b/arch/mips/pci/pci-legacy.c
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@@ -305,3 +305,30 @@ char *__init pcibios_setup(char *str)
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@ -39,7 +39,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
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#include "ifxmips_pcie.h"
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#include "ifxmips_pcie_reg.h"
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@@ -40,6 +47,10 @@
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@@ -40,6 +47,11 @@
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static DEFINE_SPINLOCK(ifx_pcie_lock);
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u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG);
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@ -47,10 +47,11 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
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+static struct phy *ltq_pcie_phy;
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+static struct reset_control *ltq_pcie_reset;
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+static struct regmap *ltq_rcu_regmap;
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+static bool switch_pcie_endianess;
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static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {
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{
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@@ -82,6 +93,22 @@ void ifx_pcie_debug(const char *fmt, ...
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@@ -82,6 +94,22 @@ void ifx_pcie_debug(const char *fmt, ...
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printk("%s", buf);
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}
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@ -73,7 +74,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
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static inline int pcie_ltssm_enable(int pcie_port)
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{
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@@ -988,10 +1015,22 @@ int ifx_pcie_bios_plat_dev_init(struct
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@@ -988,10 +1016,26 @@ int ifx_pcie_bios_plat_dev_init(struct
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static int
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pcie_rc_initialize(int pcie_port)
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{
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@ -88,6 +89,10 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
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+#ifdef CONFIG_IFX_PCIE_HW_SWAP
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+ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,
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+ IFX_RCU_AHB_BE_PCIE_S);
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+ if (switch_pcie_endianess) {
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+ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_XBAR_S,
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+ IFX_RCU_AHB_BE_XBAR_S);
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+ }
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+#else
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+ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,
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+ 0x0);
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@ -98,7 +103,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
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pcie_ep_gpio_rst_init(pcie_port);
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@@ -1000,26 +1039,21 @@ pcie_rc_initialize(int pcie_port)
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@@ -1000,26 +1044,21 @@ pcie_rc_initialize(int pcie_port)
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* reset PCIe PHY will solve this issue
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*/
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for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) {
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@ -135,7 +140,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
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/* Enable PCIe PHY and Clock */
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pcie_core_pmu_setup(pcie_port);
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@@ -1035,6 +1069,10 @@ pcie_rc_initialize(int pcie_port)
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@@ -1035,6 +1074,10 @@ pcie_rc_initialize(int pcie_port)
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/* Once link is up, break out */
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if (pcie_app_loigc_setup(pcie_port) == 0)
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break;
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@ -146,7 +151,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
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}
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if (i >= IFX_PCIE_PHY_LOOP_CNT) {
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printk(KERN_ERR "%s link up failed!!!!!\n", __func__);
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@@ -1045,17 +1083,67 @@ pcie_rc_initialize(int pcie_port)
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@@ -1045,17 +1088,74 @@ pcie_rc_initialize(int pcie_port)
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return 0;
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}
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@ -199,6 +204,13 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
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+ return PTR_ERR(ltq_pcie_reset);
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+ }
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+
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+ if (of_property_read_bool(node, "lantiq,switch-pcie-endianess")) {
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+ switch_pcie_endianess = true;
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+ dev_info(&pdev->dev, "switch pcie endianess requested\n");
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+ } else {
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+ switch_pcie_endianess = false;
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+ }
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+
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+ ltq_rcu_regmap = syscon_regmap_lookup_by_phandle(node, "lantiq,rcu");
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+ if (IS_ERR(ltq_rcu_regmap))
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+ return PTR_ERR(ltq_rcu_regmap);
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@ -216,7 +228,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
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for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){
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if (pcie_rc_initialize(pcie_port) == 0) {
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IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n",
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@@ -1067,6 +1155,7 @@ static int __init ifx_pcie_bios_init(voi
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@@ -1067,6 +1167,7 @@ static int __init ifx_pcie_bios_init(voi
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return -ENOMEM;
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}
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ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;
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@ -224,7 +236,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
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register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);
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/* XXX, clear error status */
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@@ -1083,6 +1172,30 @@ static int __init ifx_pcie_bios_init(voi
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@@ -1083,6 +1184,30 @@ static int __init ifx_pcie_bios_init(voi
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return 0;
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}
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@ -266,7 +278,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
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#define IFX_REG_R32 ltq_r32
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#define IFX_REG_W32 ltq_w32
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#define CONFIG_IFX_PCIE_HW_SWAP
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@@ -53,21 +51,6 @@
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@@ -54,21 +52,6 @@
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#define OUT ((volatile u32*)(IFX_GPIO + 0x0070))
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@ -288,7 +300,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
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static inline void pcie_ahb_pmu_setup(void)
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{
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/* Enable AHB bus master/slave */
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@@ -79,24 +62,6 @@ static inline void pcie_ahb_pmu_setup(vo
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@@ -80,24 +63,6 @@ static inline void pcie_ahb_pmu_setup(vo
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//AHBS_PMU_SETUP(IFX_PMU_ENABLE);
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}
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@ -313,7 +325,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
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static inline void pcie_phy_pmu_enable(int pcie_port)
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{
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struct clk *clk;
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@@ -115,17 +80,6 @@ static inline void pcie_phy_pmu_disable(
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@@ -116,17 +81,6 @@ static inline void pcie_phy_pmu_disable(
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// PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE);
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}
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@ -331,7 +343,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
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static inline void pcie_pdi_pmu_enable(int pcie_port)
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{
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/* Enable PDI to access PCIe PHY register */
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@@ -135,65 +89,6 @@ static inline void pcie_pdi_pmu_enable(i
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@@ -136,65 +90,6 @@ static inline void pcie_pdi_pmu_enable(i
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//PDI_PMU_SETUP(IFX_PMU_ENABLE);
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}
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