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fix bcm47xx cache fixes
SVN-Revision: 1224
This commit is contained in:
Felix Fietkau
parent
0d5dc78367
commit
c32d608d9d
@ -1,3 +1,125 @@
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diff -urN linux.old/arch/mips/mm/tlbex-mips32.S linux.dev/arch/mips/mm/tlbex-mips32.S
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--- linux.old/arch/mips/mm/tlbex-mips32.S 2005-05-28 17:42:03.000000000 +0200
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+++ linux.dev/arch/mips/mm/tlbex-mips32.S 2005-05-28 21:48:55.000000000 +0200
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@@ -90,6 +90,9 @@
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.set noat
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LEAF(except_vec0_r4000)
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.set mips3
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+#ifdef CONFIG_BCM4704
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+ nop
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+#endif
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#ifdef CONFIG_SMP
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mfc0 k1, CP0_CONTEXT
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la k0, pgd_current
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diff -urN linux.old/arch/mips/mm/pg-r4k.c linux.dev/arch/mips/mm/pg-r4k.c
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--- linux.old/arch/mips/mm/pg-r4k.c 2005-01-19 15:09:29.000000000 +0100
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+++ linux.dev/arch/mips/mm/pg-r4k.c 2005-05-28 21:57:52.000000000 +0200
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@@ -180,6 +180,7 @@
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static inline void build_cdex_s(void)
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{
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+#if !defined(CONFIG_BCM4704) && !defined(CONFIG_BCM4710)
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union mips_instruction mi;
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if ((store_offset & (cpu_scache_line_size() - 1)))
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@@ -192,10 +193,12 @@
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mi.c_format.simmediate = store_offset;
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emit_instruction(mi);
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+#endif
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}
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static inline void build_cdex_p(void)
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{
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+#if !defined(CONFIG_BCM4704) && !defined(CONFIG_BCM4710)
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union mips_instruction mi;
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if (store_offset & (cpu_dcache_line_size() - 1))
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@@ -218,6 +221,7 @@
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mi.c_format.simmediate = store_offset;
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emit_instruction(mi);
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+#endif
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}
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static void __build_store_reg(int reg)
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diff -urN linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h
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--- linux.old/include/asm-mips/stackframe.h 2002-11-29 00:53:15.000000000 +0100
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+++ linux.dev/include/asm-mips/stackframe.h 2005-05-28 21:53:03.000000000 +0200
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@@ -172,6 +172,46 @@
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rfe; \
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.set pop
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+#elif defined(CONFIG_BCM4710) || defined(CONFIG_BCM4704)
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+
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+#define RESTORE_SOME \
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+ .set push; \
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+ .set reorder; \
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+ mfc0 t0, CP0_STATUS; \
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+ .set pop; \
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+ ori t0, 0x1f; \
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+ xori t0, 0x1f; \
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+ mtc0 t0, CP0_STATUS; \
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+ li v1, 0xff00; \
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+ and t0, v1; \
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+ lw v0, PT_STATUS(sp); \
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+ nor v1, $0, v1; \
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+ and v0, v1; \
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+ or v0, t0; \
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+ ori v1, v0, ST0_IE; \
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+ xori v1, v1, ST0_IE; \
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+ mtc0 v1, CP0_STATUS; \
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+ mtc0 v0, CP0_STATUS; \
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+ lw v1, PT_EPC(sp); \
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+ mtc0 v1, CP0_EPC; \
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+ lw $31, PT_R31(sp); \
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+ lw $28, PT_R28(sp); \
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+ lw $25, PT_R25(sp); \
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+ lw $7, PT_R7(sp); \
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+ lw $6, PT_R6(sp); \
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+ lw $5, PT_R5(sp); \
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+ lw $4, PT_R4(sp); \
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+ lw $3, PT_R3(sp); \
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+ lw $2, PT_R2(sp)
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+
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+#define RESTORE_SP_AND_RET \
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+ lw sp, PT_R29(sp); \
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+ nop; \
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+ nop; \
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+ .set mips3; \
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+ eret; \
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+ .set mips0
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+
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#else
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#define RESTORE_SOME \
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diff -urN linux.old/arch/mips/mm/tlbex-r4k.S linux.dev/arch/mips/mm/tlbex-r4k.S
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--- linux.old/arch/mips/mm/tlbex-r4k.S 2005-05-28 17:42:03.000000000 +0200
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+++ linux.dev/arch/mips/mm/tlbex-r4k.S 2005-05-29 15:04:43.000000000 +0200
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@@ -168,6 +168,9 @@
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.set noat
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LEAF(except_vec0_r4000)
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.set mips3
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+#ifdef CONFIG_BCM4704
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+ nop
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+#endif
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GET_PGD(k0, k1) # get pgd pointer
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mfc0 k0, CP0_BADVADDR # Get faulting address
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srl k0, k0, _PGDIR_SHIFT # get pgd only bits
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diff -urN linux.old/arch/mips/kernel/entry.S linux.dev/arch/mips/kernel/entry.S
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--- linux.old/arch/mips/kernel/entry.S 2003-08-25 13:44:40.000000000 +0200
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+++ linux.dev/arch/mips/kernel/entry.S 2005-06-01 20:10:36.000000000 +0200
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@@ -100,6 +100,10 @@
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* and R4400 SC and MC versions.
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*/
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NESTED(except_vec3_generic, 0, sp)
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+#ifdef CONFIG_BCM4710
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+ nop
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+ nop
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+#endif
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#if R5432_CP0_INTERRUPT_WAR
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mfc0 k0, CP0_INDEX
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#endif
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diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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--- linux.old/arch/mips/mm/c-r4k.c 2005-06-01 18:42:44.000000000 +0200
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--- linux.old/arch/mips/mm/c-r4k.c 2005-06-01 18:42:44.000000000 +0200
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+++ linux.dev/arch/mips/mm/c-r4k.c 2005-06-01 18:49:07.000000000 +0200
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+++ linux.dev/arch/mips/mm/c-r4k.c 2005-06-01 18:49:07.000000000 +0200
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@ -280,3 +402,119 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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while (1) {
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while (1) {
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flush_dcache_line(a); /* Hit_Writeback_Inv_D */
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flush_dcache_line(a); /* Hit_Writeback_Inv_D */
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if (a == end)
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if (a == end)
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diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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--- linux.old/arch/mips/mm/c-r4k.c 2005-06-11 19:39:17.000000000 +0200
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+++ linux.dev/arch/mips/mm/c-r4k.c 2005-06-11 19:54:48.000000000 +0200
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@@ -1083,6 +1083,19 @@
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static inline void coherency_setup(void)
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{
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change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
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+
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+#if defined(CONFIG_BCM4310) || defined(CONFIG_BCM4704) || defined(CONFIG_BCM5365)
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+ if (BCM330X(current_cpu_data.processor_id)) {
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+ uint32 cm;
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+
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+ cm = read_c0_diag();
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+ /* Enable icache */
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+ cm |= (1 << 31);
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+ /* Enable dcache */
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+ cm |= (1 << 30);
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+ write_c0_diag(cm);
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+ }
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+#endif
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/*
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* c0_status.cu=0 specifies that updates by the sc instruction use
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@@ -1104,6 +1117,42 @@
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}
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+#ifdef CONFIG_BCM4704
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+static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
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+{
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+ unsigned long ic_lsize = current_cpu_data.icache.linesz;
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+ int i;
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+ for (i = 0; i < nbytes; i += ic_lsize)
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+ fill_icache_line((addr + i));
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+}
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+
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+/*
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+ * This must be run from the cache on 4704A0
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+ * so there are no mips core BIU ops in progress
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+ * when the PFC is enabled.
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+ */
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+#define PFC_CR0 0xff400000 /* control reg 0 */
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+#define PFC_CR1 0xff400004 /* control reg 1 */
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+static void __init enable_pfc(u32 mode)
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+{
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+ /* write range */
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+ *(volatile u32 *)PFC_CR1 = 0xffff0000;
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+
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+ /* enable */
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+ *(volatile u32 *)PFC_CR0 = mode;
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+}
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+
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+void check_enable_mips_pfc(int val)
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+{
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+ /* enable prefetch cache */
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+ if (BCM330X(current_cpu_data.processor_id)
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+ && (read_c0_diag() & (1 << 29))) {
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+ mips32_icache_fill((unsigned long) &enable_pfc, 64);
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+ enable_pfc(val);
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+ }
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+}
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+#endif
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+
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void __init ld_mmu_r4xx0(void)
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{
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extern void build_clear_page(void);
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@@ -1159,47 +1208,9 @@
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build_clear_page();
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build_copy_page();
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-}
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-
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-#ifdef CONFIG_BCM4704
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-static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
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-{
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- unsigned long ic_lsize = current_cpu_data.icache.linesz;
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- int i;
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- for (i = 0; i < nbytes; i += ic_lsize)
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- fill_icache_line((addr + i));
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-}
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-
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-/*
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- * This must be run from the cache on 4704A0
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- * so there are no mips core BIU ops in progress
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- * when the PFC is enabled.
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- */
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-#define PFC_CR0 0xff400000 /* control reg 0 */
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-#define PFC_CR1 0xff400004 /* control reg 1 */
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-static void __init enable_pfc(u32 mode)
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-{
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- /* write range */
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- *(volatile u32 *)PFC_CR1 = 0xffff0000;
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-
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- /* enable */
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- *(volatile u32 *)PFC_CR0 = mode;
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-}
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-#endif
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-
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-
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-void check_enable_mips_pfc(int val)
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-{
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-
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+
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#ifdef CONFIG_BCM4704
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- struct cpuinfo_mips *c = ¤t_cpu_data;
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-
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- /* enable prefetch cache */
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- if (((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) == PRID_IMP_BCM3302)
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- && (read_c0_diag() & (1 << 29))) {
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- mips32_icache_fill((unsigned long) &enable_pfc, 64);
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- enable_pfc(val);
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- }
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+ check_enable_mips_pfc(0x15);
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#endif
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}
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@ -1,122 +0,0 @@
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diff -urN linux.old/arch/mips/mm/tlbex-mips32.S linux.dev/arch/mips/mm/tlbex-mips32.S
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--- linux.old/arch/mips/mm/tlbex-mips32.S 2005-05-28 17:42:03.000000000 +0200
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+++ linux.dev/arch/mips/mm/tlbex-mips32.S 2005-05-28 21:48:55.000000000 +0200
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@@ -90,6 +90,9 @@
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.set noat
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LEAF(except_vec0_r4000)
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.set mips3
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+#ifdef CONFIG_BCM4704
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+ nop
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+#endif
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#ifdef CONFIG_SMP
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mfc0 k1, CP0_CONTEXT
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la k0, pgd_current
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diff -urN linux.old/arch/mips/mm/pg-r4k.c linux.dev/arch/mips/mm/pg-r4k.c
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--- linux.old/arch/mips/mm/pg-r4k.c 2005-01-19 15:09:29.000000000 +0100
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+++ linux.dev/arch/mips/mm/pg-r4k.c 2005-05-28 21:57:52.000000000 +0200
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@@ -180,6 +180,7 @@
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static inline void build_cdex_s(void)
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{
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+#if !defined(CONFIG_BCM4704) && !defined(CONFIG_BCM4710)
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union mips_instruction mi;
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if ((store_offset & (cpu_scache_line_size() - 1)))
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@@ -192,10 +193,12 @@
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mi.c_format.simmediate = store_offset;
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emit_instruction(mi);
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+#endif
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}
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static inline void build_cdex_p(void)
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{
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+#if !defined(CONFIG_BCM4704) && !defined(CONFIG_BCM4710)
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union mips_instruction mi;
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if (store_offset & (cpu_dcache_line_size() - 1))
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@@ -218,6 +221,7 @@
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mi.c_format.simmediate = store_offset;
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emit_instruction(mi);
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+#endif
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}
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static void __build_store_reg(int reg)
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diff -urN linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h
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--- linux.old/include/asm-mips/stackframe.h 2002-11-29 00:53:15.000000000 +0100
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+++ linux.dev/include/asm-mips/stackframe.h 2005-05-28 21:53:03.000000000 +0200
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@@ -172,6 +172,46 @@
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rfe; \
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.set pop
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+#elif defined(CONFIG_BCM4710) || defined(CONFIG_BCM4704)
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+
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+#define RESTORE_SOME \
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+ .set push; \
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+ .set reorder; \
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+ mfc0 t0, CP0_STATUS; \
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+ .set pop; \
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+ ori t0, 0x1f; \
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+ xori t0, 0x1f; \
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+ mtc0 t0, CP0_STATUS; \
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+ li v1, 0xff00; \
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+ and t0, v1; \
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+ lw v0, PT_STATUS(sp); \
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+ nor v1, $0, v1; \
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+ and v0, v1; \
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+ or v0, t0; \
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+ ori v1, v0, ST0_IE; \
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+ xori v1, v1, ST0_IE; \
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+ mtc0 v1, CP0_STATUS; \
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+ mtc0 v0, CP0_STATUS; \
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+ lw v1, PT_EPC(sp); \
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+ mtc0 v1, CP0_EPC; \
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+ lw $31, PT_R31(sp); \
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+ lw $28, PT_R28(sp); \
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+ lw $25, PT_R25(sp); \
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+ lw $7, PT_R7(sp); \
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+ lw $6, PT_R6(sp); \
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+ lw $5, PT_R5(sp); \
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+ lw $4, PT_R4(sp); \
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+ lw $3, PT_R3(sp); \
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+ lw $2, PT_R2(sp)
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||||||
+
|
|
||||||
+#define RESTORE_SP_AND_RET \
|
|
||||||
+ lw sp, PT_R29(sp); \
|
|
||||||
+ nop; \
|
|
||||||
+ nop; \
|
|
||||||
+ .set mips3; \
|
|
||||||
+ eret; \
|
|
||||||
+ .set mips0
|
|
||||||
+
|
|
||||||
#else
|
|
||||||
|
|
||||||
#define RESTORE_SOME \
|
|
||||||
diff -urN linux.old/arch/mips/mm/tlbex-r4k.S linux.dev/arch/mips/mm/tlbex-r4k.S
|
|
||||||
--- linux.old/arch/mips/mm/tlbex-r4k.S 2005-05-28 17:42:03.000000000 +0200
|
|
||||||
+++ linux.dev/arch/mips/mm/tlbex-r4k.S 2005-05-29 15:04:43.000000000 +0200
|
|
||||||
@@ -168,6 +168,9 @@
|
|
||||||
.set noat
|
|
||||||
LEAF(except_vec0_r4000)
|
|
||||||
.set mips3
|
|
||||||
+#ifdef CONFIG_BCM4704
|
|
||||||
+ nop
|
|
||||||
+#endif
|
|
||||||
GET_PGD(k0, k1) # get pgd pointer
|
|
||||||
mfc0 k0, CP0_BADVADDR # Get faulting address
|
|
||||||
srl k0, k0, _PGDIR_SHIFT # get pgd only bits
|
|
||||||
diff -urN linux.old/arch/mips/kernel/entry.S linux.dev/arch/mips/kernel/entry.S
|
|
||||||
--- linux.old/arch/mips/kernel/entry.S 2003-08-25 13:44:40.000000000 +0200
|
|
||||||
+++ linux.dev/arch/mips/kernel/entry.S 2005-06-01 20:10:36.000000000 +0200
|
|
||||||
@@ -100,6 +100,10 @@
|
|
||||||
* and R4400 SC and MC versions.
|
|
||||||
*/
|
|
||||||
NESTED(except_vec3_generic, 0, sp)
|
|
||||||
+#ifdef CONFIG_BCM4710
|
|
||||||
+ nop
|
|
||||||
+ nop
|
|
||||||
+#endif
|
|
||||||
#if R5432_CP0_INTERRUPT_WAR
|
|
||||||
mfc0 k0, CP0_INDEX
|
|
||||||
#endif
|
|
||||||
Loading…
Reference in New Issue
Block a user