From c2635d9b1142340c66611021f31fe51f64bf5cd7 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Tue, 20 Jun 2023 01:58:37 +0200 Subject: [PATCH] ipq806x: 5.15: drop useless kernel patches and dts files Drop useless 5.15 kernel patches and files now that we moved to kernel 6.1 by default. Signed-off-by: Christian Marangi --- target/linux/ipq806x/config-5.15 | 507 ---------- .../arm/boot/dts/qcom-ipq8062-wg2600hp3.dts | 510 ---------- .../boot/dts/qcom-ipq8064-ad7200-c2600.dtsi | 402 -------- .../arch/arm/boot/dts/qcom-ipq8064-ad7200.dts | 135 --- .../arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 134 --- .../arch/arm/boot/dts/qcom-ipq8064-ap161.dts | 172 ---- .../arm/boot/dts/qcom-ipq8064-asus-onhub.dts | 92 -- .../arch/arm/boot/dts/qcom-ipq8064-c2600.dts | 119 --- .../arch/arm/boot/dts/qcom-ipq8064-d7800.dts | 394 -------- .../arch/arm/boot/dts/qcom-ipq8064-db149.dts | 179 ---- .../arm/boot/dts/qcom-ipq8064-ea7500-v1.dts | 91 -- .../arch/arm/boot/dts/qcom-ipq8064-ea8500.dts | 128 --- .../arm/boot/dts/qcom-ipq8064-eax500.dtsi | 232 ----- .../arch/arm/boot/dts/qcom-ipq8064-g10.dts | 292 ------ .../arch/arm/boot/dts/qcom-ipq8064-onhub.dtsi | 491 ---------- .../arch/arm/boot/dts/qcom-ipq8064-r7500.dts | 327 ------- .../arm/boot/dts/qcom-ipq8064-r7500v2.dts | 387 -------- .../boot/dts/qcom-ipq8064-tplink-onhub.dts | 209 ---- .../arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts | 315 ------ .../arm/boot/dts/qcom-ipq8064-vr2600v.dts | 424 -------- .../arm/boot/dts/qcom-ipq8064-wg2600hp.dts | 463 --------- .../arch/arm/boot/dts/qcom-ipq8064-wpq864.dts | 473 --------- .../arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts | 539 ---------- .../arch/arm/boot/dts/qcom-ipq8065-ac400i.dts | 318 ------ .../arm/boot/dts/qcom-ipq8065-nbg6817.dts | 332 ------- .../arm/boot/dts/qcom-ipq8065-nighthawk.dtsi | 466 --------- .../arch/arm/boot/dts/qcom-ipq8065-r7800.dts | 48 - .../boot/dts/qcom-ipq8065-rt4230w-rev6.dts | 418 -------- .../arm/boot/dts/qcom-ipq8065-tr4400-v2.dts | 432 -------- .../arch/arm/boot/dts/qcom-ipq8065-xr450.dts | 50 - .../arch/arm/boot/dts/qcom-ipq8065-xr500.dts | 50 - .../boot/dts/qcom-ipq8068-cryptid-common.dtsi | 236 ----- .../arm/boot/dts/qcom-ipq8068-ecw5410.dts | 329 ------- .../arch/arm/boot/dts/qcom-ipq8068-mr42.dts | 228 ----- .../arch/arm/boot/dts/qcom-ipq8068-mr52.dts | 254 ----- ...arch-arm-force-ZRELADDR-on-arch-qcom.patch | 62 -- ...Mangle-bootloader-s-kernel-arguments.patch | 280 ------ ...806x-fix-wrong-naming-for-gcc_pxo_pl.patch | 109 --- ...806x-convert-parent_names-to-parent_.patch | 921 ------------------ ...q806x-use-ARRAY_SIZE-for-num_parents.patch | 325 ------ ...pq806x-add-additional-freq-nss-cores.patch | 88 -- ...806x-add-unusued-flag-for-critical-c.patch | 65 -- ...om-clk-rcg-add-clk_rcg_floor_ops-ops.patch | 69 -- ...806x-add-additional-freq-for-sdc-tab.patch | 38 - ...ngs-clock-add-ipq8064-ce5-clk-define.patch | 39 - ...-gcc-ipq806x-add-CryptoEngine-clocks.patch | 304 ------ ...indings-reset-add-ipq8064-ce5-resets.patch | 29 - ...-gcc-ipq806x-add-CryptoEngine-resets.patch | 30 - ...mac-add-missing-sgmii-configure-for-.patch | 151 --- ...mac-reset-force-speed-bit-for-ipq806.patch | 110 --- ...conflicts-with-OpenWrt-auto-mounting.patch | 25 - ...-syscon-and-cxo-pxo-clock-to-gcc-nod.patch | 48 - ...lace-gcc-PXO-with-pxo_board-fixed-cl.patch | 29 - ...8064-add-multiple-missing-pin-defini.patch | 101 -- ...ipq8064-add-gsbi6-missing-definition.patch | 67 -- ...8064-add-specific-dtsi-with-smb208-r.patch | 66 -- ...8064-add-missing-snps-dwmac-compatib.patch | 56 -- ...m-ipq8064-disable-usb-phy-by-default.patch | 37 - ...8064-fix-and-add-some-missing-gsbi-n.patch | 94 -- ...pq8064-add-speedbin-efuse-nvmem-node.patch | 28 - ...Add-support-for-mmio-usage-to-sfpb-m.patch | 71 -- ...-dts-qcom-ipq8064-add-missing-hwlock.patch | 31 - ...-ipq8064-add-missing-smem-compatible.patch | 30 - ...dts-qcom-ipq8064-add-v2-dtsi-variant.patch | 129 --- ...dts-qcom-ipq8064-add-ipq8062-variant.patch | 67 -- ...dts-qcom-ipq8064-add-ipq8065-variant.patch | 67 -- ...add-saw-for-l2-cache-and-kraitcc-for.patch | 95 -- ...add-opp-table-for-cpu-and-l2-for-ipq.patch | 268 ----- ...add-multiple-missing-binding-for-cpu.patch | 153 --- ...-wrong-nad_pins-definition-for-ipq80.patch | 29 - ...-MDIO-dedicated-controller-node-for-.patch | 188 ---- ...-clock-add-pcm-reset-for-ipq806x-lcc.patch | 29 - ...com-lcc-ipq806x-add-reset-definition.patch | 48 - ...m-lcc-ipq806x-convert-to-parent-data.patch | 217 ----- ...ns-init-debugfs-only-with-successful.patch | 41 - ...tsens-simplify-debugfs-init-function.patch | 54 - ...t-devfreq_get_freq_range-symbol-with.patch | 113 --- ...pu-based-scaling-support-to-passive-.patch | 461 --------- ...ve-Reduce-duplicate-code-when-passiv.patch | 110 --- ...ve-Keep-cpufreq_policy-for-possible-.patch | 232 ----- ...ve-Return-non-error-when-not-support.patch | 31 - ...ernel-warning-with-cpufreq-passive-r.patch | 31 - ...x-cpufreq-passive-unregister-errorin.patch | 85 -- ...ernel-panic-with-cpu-based-scaling-t.patch | 34 - ...work-freq_table-to-be-local-to-devfr.patch | 269 ----- ...Mute-warning-on-governor-PROBE_DEFER.patch | 28 - ...-L2-Krait-Cache-devfreq-scaling-driv.patch | 242 ----- ...-krait-cache-compatible-for-ipq806x-.patch | 50 - ...eq-add-ipq806x-fabric-scaling-driver.patch | 203 ---- ...com-add-fab-scaling-node-for-ipq806x.patch | 48 - ...m_nandc-reorder-qcom_nand_host-struc.patch | 268 ----- ...m_nandc-add-support-for-unprotected-.patch | 406 -------- ...com-clk-hfpll-use-poll_timeout-macro.patch | 41 - ...it-add-apq-ipq8064-errata-workaround.patch | 86 -- ...vm_-hw_register_mux_parent_data_tabl.patch | 46 - ...-kpss-xcc-convert-to-parent-data-API.patch | 70 -- ...-rpmcc-missing-clocks-for-apq-ipq806.patch | 61 -- ...m-clk-rpm-convert-to-parent_data-API.patch | 78 -- ...kpss-xcc-register-it-as-clk-provider.patch | 61 -- ...c-use-devm-variant-for-clk-notifier-.patch | 27 - ...c-fix-wrong-parent-order-for-seconda.patch | 46 - ...c-also-enable-secondary-mux-and-div-.patch | 68 -- ...c-handle-secondary-mux-sourcing-out-.patch | 48 - ...t-cc-convert-to-devm_clk_hw_register.patch | 104 -- ...-krait-cc-convert-to-parent_data-API.patch | 414 -------- ...t-cc-handle-qsb-clock-defined-in-DTS.patch | 47 - ...ait-cc-register-REAL-qsb-fixed-clock.patch | 36 - ...ait-cc-drop-pr_info-and-use-dev_info.patch | 44 - ...c-rework-mux-reset-logic-and-reset-h.patch | 88 -- ...m-clk-krait-generilize-div-functions.patch | 156 --- ...ipq806x-remove-cc_register_board-for.patch | 31 - ...-handle-ret-from-parse-with-codeword.patch | 55 -- ...q8064-disable-mmc-ddr-1_8v-for-sdcc1.patch | 28 - .../850-soc-add-qualcomm-syscon.patch | 121 --- .../900-arm-add-cmdline-override.patch | 37 - 115 files changed, 19268 deletions(-) delete mode 100644 target/linux/ipq806x/config-5.15 delete mode 100644 target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts delete mode 100644 target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi delete mode 100644 target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts delete mode 100644 target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap148.dts delete mode 100644 target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap161.dts delete mode 100644 target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-asus-onhub.dts delete mode 100644 target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-c2600.dts delete mode 100644 target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts delete mode 100644 target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-db149.dts delete mode 100644 target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts delete mode 100644 target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts delete mode 100644 target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi delete mode 100644 target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts delete mode 100644 target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-onhub.dtsi delete mode 100644 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target/linux/ipq806x/patches-5.15/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch delete mode 100644 target/linux/ipq806x/patches-5.15/0067-generic-Mangle-bootloader-s-kernel-arguments.patch delete mode 100644 target/linux/ipq806x/patches-5.15/100-v5.18-04-linux-next-clk-qcom-gcc-ipq806x-fix-wrong-naming-for-gcc_pxo_pl.patch delete mode 100644 target/linux/ipq806x/patches-5.15/100-v5.18-05-linux-next-clk-qcom-gcc-ipq806x-convert-parent_names-to-parent_.patch delete mode 100644 target/linux/ipq806x/patches-5.15/100-v5.18-06-linux-next-clk-qcom-gcc-ipq806x-use-ARRAY_SIZE-for-num_parents.patch delete mode 100644 target/linux/ipq806x/patches-5.15/100-v5.18-07-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-nss-cores.patch delete mode 100644 target/linux/ipq806x/patches-5.15/100-v5.18-08-linux-next-clk-qcom-gcc-ipq806x-add-unusued-flag-for-critical-c.patch delete mode 100644 target/linux/ipq806x/patches-5.15/100-v5.18-09-linux-next-clk-qcom-clk-rcg-add-clk_rcg_floor_ops-ops.patch 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target/linux/ipq806x/patches-5.15/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch delete mode 100644 target/linux/ipq806x/patches-5.15/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch delete mode 100644 target/linux/ipq806x/patches-5.15/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch delete mode 100644 target/linux/ipq806x/patches-5.15/122-05-clk-qcom-clk-krait-generilize-div-functions.patch delete mode 100644 target/linux/ipq806x/patches-5.15/123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch delete mode 100644 target/linux/ipq806x/patches-5.15/130-6.1-mtd-rawnand-qcom-handle-ret-from-parse-with-codeword.patch delete mode 100644 target/linux/ipq806x/patches-5.15/131-6.2-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch delete mode 100644 target/linux/ipq806x/patches-5.15/850-soc-add-qualcomm-syscon.patch delete mode 100644 target/linux/ipq806x/patches-5.15/900-arm-add-cmdline-override.patch diff --git a/target/linux/ipq806x/config-5.15 b/target/linux/ipq806x/config-5.15 deleted file mode 100644 index 1f456b2ce9f..00000000000 --- a/target/linux/ipq806x/config-5.15 +++ /dev/null @@ -1,507 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_APQ_GCC_8084 is not set -# CONFIG_APQ_MMCC_8084 is not set -CONFIG_AR8216_PHY=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -# CONFIG_ARCH_IPQ40XX is not set -CONFIG_ARCH_KEEP_MEMBLOCK=y -# CONFIG_ARCH_MDM9615 is not set -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MSM8960=y -CONFIG_ARCH_MSM8974=y -CONFIG_ARCH_MSM8X60=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_QCOM=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_ATAG_DTB_COMPAT=y -# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y -CONFIG_ARM_CPUIDLE=y -CONFIG_ARM_CPU_SUSPEND=y -# CONFIG_ARM_CPU_TOPOLOGY is not set -CONFIG_ARM_CRYPTO=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_IPQ806X_FAB_DEVFREQ=y -CONFIG_ARM_KRAIT_CACHE_DEVFREQ=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -# CONFIG_ARM_QCOM_CPUFREQ_HW is not set -CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y -CONFIG_ARM_QCOM_SPM_CPUIDLE=y -# CONFIG_ARM_SMMU is not set -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_AT803X_PHY=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BOUNCE=y -# CONFIG_CACHE_L2X0 is not set -CONFIG_CLKSRC_QCOM=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE_OVERRIDE=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_QCOM=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CRC8=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DEV_QCOM_RNG=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_GPIO=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DEVFREQ_GOV_PASSIVE=y -# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set -# CONFIG_DEVFREQ_GOV_POWERSAVE is not set -# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set -# CONFIG_DEVFREQ_GOV_USERSPACE is not set -# CONFIG_DEVFREQ_THERMAL is not set -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DTC=y -CONFIG_DT_IDLE_STATES=y -# CONFIG_DWMAC_GENERIC is not set -CONFIG_DWMAC_IPQ806X=y -# CONFIG_DWMAC_QCOM_ETHQOS is not set -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_ETHERNET_PACKET_MANGLE=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GLOB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_CDEV=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HIGHMEM=y -# CONFIG_HIGHPTE is not set -CONFIG_HOTPLUG_CPU=y -CONFIG_HWMON=y -CONFIG_HWSPINLOCK=y -CONFIG_HWSPINLOCK_QCOM=y -CONFIG_HW_RANDOM=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y -# CONFIG_I2C_QCOM_CCI is not set -CONFIG_I2C_QUP=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y -# CONFIG_IPQ_APSS_PLL is not set -# CONFIG_IPQ_GCC_4019 is not set -# CONFIG_IPQ_GCC_6018 is not set -CONFIG_IPQ_GCC_806X=y -# CONFIG_IPQ_GCC_8074 is not set -# CONFIG_IPQ_LCC_806X is not set -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_KMAP_LOCAL=y -CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y -CONFIG_KPSS_XCC=y -CONFIG_KRAITCC=y -CONFIG_KRAIT_CLOCKS=y -CONFIG_KRAIT_L2_ACCESSORS=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_GPIO=y -CONFIG_MDIO_IPQ8064=y -# CONFIG_MDM_GCC_9615 is not set -# CONFIG_MDM_LCC_9615 is not set -CONFIG_MEMFD_CREATE=y -# CONFIG_MFD_HI6421_SPMI is not set -CONFIG_MFD_QCOM_RPM=y -# CONFIG_MFD_SPMI_PMIC is not set -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_ARMMMCI=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_MINORS=16 -CONFIG_MMC_CQHCI=y -CONFIG_MMC_QCOM_DML=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_IO_ACCESSORS=y -CONFIG_MMC_SDHCI_MSM=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MSM_GCC_8660=y -# CONFIG_MSM_GCC_8916 is not set -# CONFIG_MSM_GCC_8939 is not set -# CONFIG_MSM_GCC_8960 is not set -# CONFIG_MSM_GCC_8974 is not set -# CONFIG_MSM_GCC_8994 is not set -# CONFIG_MSM_GCC_8996 is not set -# CONFIG_MSM_GCC_8998 is not set -# CONFIG_MSM_GPUCC_8998 is not set -# CONFIG_MSM_IOMMU is not set -# CONFIG_MSM_LCC_8960 is not set -# CONFIG_MSM_MMCC_8960 is not set -# CONFIG_MSM_MMCC_8974 is not set -# CONFIG_MSM_MMCC_8996 is not set -# CONFIG_MSM_MMCC_8998 is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_QCOM=y -CONFIG_MTD_QCOMSMEM_PARTS=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEON=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_QCA8K=y -CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y -CONFIG_NET_DSA_TAG_QCA=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NLS=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -CONFIG_NVMEM_QCOM_QFPROM=y -# CONFIG_NVMEM_SPMI_SDAM is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PAGE_POOL=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_DW=y -CONFIG_PCIE_DW_HOST=y -CONFIG_PCIE_QCOM=y -CONFIG_PCI_DEBUG=y -CONFIG_PCI_DISABLE_COMMON_QUIRKS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCS_XPCS=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -# CONFIG_PHY_QCOM_APQ8064_SATA is not set -# CONFIG_PHY_QCOM_IPQ4019_USB is not set -CONFIG_PHY_QCOM_IPQ806X_SATA=y -# CONFIG_PHY_QCOM_IPQ806X_USB is not set -# CONFIG_PHY_QCOM_PCIE2 is not set -# CONFIG_PHY_QCOM_QMP is not set -# CONFIG_PHY_QCOM_QUSB2 is not set -# CONFIG_PHY_QCOM_USB_HS_28NM is not set -# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set -# CONFIG_PHY_QCOM_USB_SS is not set -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_APQ8064 is not set -# CONFIG_PINCTRL_APQ8084 is not set -# CONFIG_PINCTRL_IPQ4019 is not set -# CONFIG_PINCTRL_IPQ6018 is not set -CONFIG_PINCTRL_IPQ8064=y -# CONFIG_PINCTRL_IPQ8074 is not set -# CONFIG_PINCTRL_MDM9615 is not set -CONFIG_PINCTRL_MSM=y -# CONFIG_PINCTRL_MSM8226 is not set -# CONFIG_PINCTRL_MSM8660 is not set -# CONFIG_PINCTRL_MSM8916 is not set -# CONFIG_PINCTRL_MSM8960 is not set -# CONFIG_PINCTRL_MSM8976 is not set -# CONFIG_PINCTRL_MSM8994 is not set -# CONFIG_PINCTRL_MSM8996 is not set -# CONFIG_PINCTRL_MSM8998 is not set -# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set -# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set -# CONFIG_PINCTRL_QCS404 is not set -# CONFIG_PINCTRL_SC7180 is not set -# CONFIG_PINCTRL_SDM660 is not set -# CONFIG_PINCTRL_SDM845 is not set -# CONFIG_PINCTRL_SM8150 is not set -# CONFIG_PINCTRL_SM8250 is not set -CONFIG_PM_DEVFREQ=y -# CONFIG_PM_DEVFREQ_EVENT is not set -CONFIG_PM_OPP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_MSM=y -CONFIG_POWER_SUPPLY=y -CONFIG_PPS=y -CONFIG_PRINTK_TIME=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -# CONFIG_QCOM_A53PLL is not set -CONFIG_QCOM_ADM=y -CONFIG_QCOM_BAM_DMA=y -CONFIG_QCOM_CLK_RPM=y -# CONFIG_QCOM_COMMAND_DB is not set -# CONFIG_QCOM_CPR is not set -# CONFIG_QCOM_EBI2 is not set -# CONFIG_QCOM_GENI_SE is not set -CONFIG_QCOM_GSBI=y -CONFIG_QCOM_HFPLL=y -# CONFIG_QCOM_IOMMU is not set -# CONFIG_QCOM_LLCC is not set -# CONFIG_QCOM_OCMEM is not set -# CONFIG_QCOM_PDC is not set -# CONFIG_QCOM_RMTFS_MEM is not set -CONFIG_QCOM_RPMCC=y -# CONFIG_QCOM_RPMH is not set -CONFIG_QCOM_SCM=y -# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set -CONFIG_QCOM_SMEM=y -# CONFIG_QCOM_SMSM is not set -CONFIG_QCOM_SOCINFO=y -CONFIG_QCOM_TCSR=y -CONFIG_QCOM_TSENS=y -CONFIG_QCOM_WDT=y -# CONFIG_QCS_GCC_404 is not set -# CONFIG_QCS_Q6SSTOP_404 is not set -# CONFIG_QCS_TURING_404 is not set -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_RCU_CPU_STALL_TIMEOUT=21 -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -# CONFIG_REGULATOR_QCOM_LABIBB is not set -CONFIG_REGULATOR_QCOM_RPM=y -# CONFIG_REGULATOR_QCOM_SPMI is not set -# CONFIG_REGULATOR_QCOM_USB_VBUS is not set -# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set -CONFIG_RESET_CONTROLLER=y -# CONFIG_RESET_QCOM_AOSS is not set -# CONFIG_RESET_QCOM_PDC is not set -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -# CONFIG_SC_DISPCC_7180 is not set -# CONFIG_SC_GCC_7180 is not set -# CONFIG_SC_GPUCC_7180 is not set -# CONFIG_SC_LPASS_CORECC_7180 is not set -# CONFIG_SC_MSS_7180 is not set -# CONFIG_SC_VIDEOCC_7180 is not set -# CONFIG_SDM_CAMCC_845 is not set -# CONFIG_SDM_DISPCC_845 is not set -# CONFIG_SDM_GCC_660 is not set -# CONFIG_SDM_GCC_845 is not set -# CONFIG_SDM_GPUCC_845 is not set -# CONFIG_SDM_LPASSCC_845 is not set -# CONFIG_SDM_VIDEOCC_845 is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_MSM=y -CONFIG_SERIAL_MSM_CONSOLE=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -# CONFIG_SM_GCC_8150 is not set -# CONFIG_SM_GCC_8250 is not set -# CONFIG_SM_GPUCC_8150 is not set -# CONFIG_SM_GPUCC_8250 is not set -# CONFIG_SM_VIDEOCC_8150 is not set -# CONFIG_SM_VIDEOCC_8250 is not set -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOC_BUS=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_QUP=y -CONFIG_SPMI=y -# CONFIG_SPMI_HISI3670 is not set -CONFIG_SPMI_MSM_PMIC_ARB=y -# CONFIG_SPMI_PMIC_CLKDIV is not set -CONFIG_SRCU=y -CONFIG_STMMAC_ETH=y -CONFIG_STMMAC_PLATFORM=y -CONFIG_SWCONFIG=y -CONFIG_SWCONFIG_LEDS=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -# CONFIG_UCLAMP_TASK is not set -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts deleted file mode 100644 index c55287a4f12..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts +++ /dev/null @@ -1,510 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8062-smb208.dtsi" -#include - -/ { - model = "NEC Platforms Aterm WG2600HP3"; - compatible = "nec,wg2600hp3", "qcom,ipq8062", "qcom,ipq8064"; - - memory { - device_type = "memory"; - reg = <0x42000000 0x1e000000>; - }; - - aliases { - label-mac-device = &gmac2; - - led-boot = &led_power_green; - led-failsafe = &led_power_red; - led-running = &led_power_green; - led-upgrade = &led_power_red; - }; - - keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&buttons_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - mode0 { - label = "mode0"; - gpios = <&qcom_pinmux 40 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - - mode1 { - label = "mode1"; - gpios = <&qcom_pinmux 41 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - - pinctrl-0 = <&leds_pins>; - pinctrl-names = "default"; - - led_power_green: power_green { - label = "green:power"; - gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>; - }; - - led_power_red: power_red { - label = "red:power"; - gpios = <&qcom_pinmux 35 GPIO_ACTIVE_HIGH>; - }; - - active_green { - label = "green:active"; - gpios = <&qcom_pinmux 42 GPIO_ACTIVE_HIGH>; - }; - - active_red { - label = "red:active"; - gpios = <&qcom_pinmux 38 GPIO_ACTIVE_HIGH>; - }; - - wlan2g_green { - label = "green:wlan2g"; - gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy1tpt"; - }; - - wlan2g_red { - label = "red:wlan2g"; - gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; - }; - - wlan5g_green { - label = "green:wlan5g"; - gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tpt"; - }; - - wlan5g_red { - label = "red:wlan5g"; - gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>; - }; - - tv_green { - label = "green:tv"; - gpios = <&qcom_pinmux 46 GPIO_ACTIVE_HIGH>; - }; - - tv_red { - label = "red:tv"; - gpios = <&qcom_pinmux 36 GPIO_ACTIVE_HIGH>; - }; - - converter_green { - label = "green:converter"; - gpios = <&qcom_pinmux 43 GPIO_ACTIVE_HIGH>; - }; - - converter_red { - label = "red:converter"; - gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -/* nand_pins are used for leds_pins, empty the node - * from ipq8064.dtsi - */ -&nand_pins { - /delete-property/ disable; - /delete-property/ pullups; - /delete-property/ hold; -}; - -&qcom_pinmux { - pinctrl-0 = <&akro_pins>; - pinctrl-names = "default"; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs { - pins = "gpio20"; - drive-strength = <10>; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - buttons_pins: buttons_pins { - mux { - pins = "gpio22", "gpio24", "gpio40", - "gpio41"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - leds_pins: leds_pins { - mux { - pins = "gpio14", "gpio15", "gpio35", - "gpio36", "gpio38", "gpio42", - "gpio43", "gpio46", "gpio55", - "gpio56", "gpio57", "gpio58"; - function = "gpio"; - bias-pull-down; - }; - - akro2 { - pins = "gpio15", "gpio35", "gpio38", - "gpio42", "gpio43", "gpio46", - "gpio55", "gpio56", "gpio57", - "gpio58"; - drive-strength = <2>; - }; - - akro4 { - pins = "gpio14", "gpio36"; - drive-strength = <4>; - }; - }; - - /* - * Stock firmware has the following settings, so let's do the same. - * I don't sure why these are required. - */ - akro_pins: akro_pinmux { - akro { - pins = "gpio17", "gpio26", "gpio47"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - reset { - pins = "gpio45"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - output-low; - }; - - gmac0_rgmii { - pins = "gpio25"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - }; -}; - -&gsbi5 { - status = "okay"; - qcom,mode = ; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SBL1"; - reg = <0x0000000 0x0020000>; - read-only; - }; - - partition@20000 { - label = "MIBIB"; - reg = <0x0020000 0x0020000>; - read-only; - }; - - partition@40000 { - label = "SBL2"; - reg = <0x0040000 0x0040000>; - read-only; - }; - - partition@80000 { - label = "SBL3"; - reg = <0x0080000 0x0080000>; - read-only; - }; - - partition@100000 { - label = "DDRCONFIG"; - reg = <0x0100000 0x0010000>; - read-only; - }; - - partition@110000 { - label = "SSD"; - reg = <0x0110000 0x0010000>; - read-only; - }; - - partition@120000 { - label = "TZ"; - reg = <0x0120000 0x0080000>; - read-only; - }; - - partition@1a0000 { - label = "RPM"; - reg = <0x01a0000 0x0080000>; - read-only; - }; - - partition@220000 { - label = "APPSBL"; - reg = <0x0220000 0x0080000>; - read-only; - }; - - partition@2a0000 { - label = "APPSBLENV"; - reg = <0x02a0000 0x0010000>; - read-only; - }; - - factory: partition@2b0000 { - label = "PRODUCTDATA"; - reg = <0x02b0000 0x0030000>; - read-only; - }; - - partition@2e0000 { - label = "ART"; - reg = <0x02e0000 0x0040000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - precal_ART_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_ART_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - partition@320000 { - label = "TP"; - reg = <0x0320000 0x0040000>; - read-only; - }; - - partition@360000 { - label = "TINY"; - reg = <0x0360000 0x0500000>; - read-only; - }; - - partition@860000 { - compatible = "denx,uimage"; - label = "firmware"; - reg = <0x0860000 0x17a0000>; - }; - }; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "qcom,ath10k"; - reg = <0x00010000 0 0 0 0>; - - qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3"; - - nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&pcie1 { - status = "okay"; - force_gen1 = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "qcom,ath10k"; - reg = <0x00010000 0 0 0 0>; - - ieee80211-freq-limit = <2400000 2483000>; - qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3"; - - nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x04 0x80080080 /* PAD0_MODE */ - 0x0c 0x06000000 /* PAD6_MODE */ - 0x10 0x002613a0 /* PWS_REG */ - 0x50 0xcc36cc36 /* LED_CTRL0 */ - 0x54 0xca36ca36 /* LED_CTRL1 */ - 0x58 0xc936c936 /* LED_CTRL2 */ - 0x5c 0x03ffff00 /* LED_CTRL3 */ - 0x7c 0x0000004e /* PORT0_STATUS */ - 0x94 0x0000004e /* PORT6_STATUS */ - 0xe0 0xc74164de /* SGMII_CTRL */ - 0xe4 0x0006a545 /* MAC_PWR_SEL */ - >; - }; -}; - -&gmac1 { - status = "okay"; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - phy-mode = "rgmii"; - qcom,id = <1>; - mdiobus = <&mdio0>; - nvmem-cells = <&macaddr_factory_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - mdiobus = <&mdio0>; - nvmem-cells = <&macaddr_factory_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&factory { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_factory_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_factory_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - macaddr_PRODUCTDATA_c: macaddr@c { - reg = <0xc 0x6>; - }; - - macaddr_PRODUCTDATA_12: macaddr@12 { - reg = <0x12 0x6>; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi deleted file mode 100644 index 3494b2bde2f..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi +++ /dev/null @@ -1,402 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -#include - -/ { - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - ramoops@42100000 { - compatible = "ramoops"; - reg = <0x42100000 0x40000>; - record-size = <0x4000>; - console-size = <0x4000>; - ftrace-size = <0x4000>; - pmsg-size = <0x4000>; - }; - }; - - aliases { - mdio-gpio0 = &mdio0; - label-mac-device = &gmac2; - }; -}; - -&qcom_pinmux { - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs { - pins = "gpio20"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - usb0_pwr_en_pin: usb0_pwr_en_pin { - mux { - pins = "gpio25"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - output-high; - }; - }; - - usb1_pwr_en_pin: usb1_pwr_en_pin { - mux { - pins = "gpio23"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - output-high; - }; - }; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SBL1"; - reg = <0x0 0x20000>; - read-only; - }; - - partition@20000 { - label = "MIBIB"; - reg = <0x20000 0x20000>; - read-only; - }; - - partition@40000 { - label = "SBL2"; - reg = <0x40000 0x20000>; - read-only; - }; - - partition@60000 { - label = "SBL3"; - reg = <0x60000 0x30000>; - read-only; - }; - - partition@90000 { - label = "DDRCONFIG"; - reg = <0x90000 0x10000>; - read-only; - }; - - partition@a0000 { - label = "SSD"; - reg = <0xa0000 0x10000>; - read-only; - }; - - partition@b0000 { - label = "TZ"; - reg = <0xb0000 0x30000>; - read-only; - }; - - partition@e0000 { - label = "RPM"; - reg = <0xe0000 0x20000>; - read-only; - }; - - partition@100000 { - label = "fs-uboot"; - reg = <0x100000 0x70000>; - read-only; - }; - - partition@170000 { - label = "uboot-env"; - reg = <0x170000 0x40000>; - read-only; - }; - - partition@1b0000 { - label = "radio"; - reg = <0x1b0000 0x40000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - precal_radio_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_radio_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - partition@1f0000 { - label = "os-image"; - reg = <0x1f0000 0x400000>; - }; - - partition@5f0000 { - label = "rootfs"; - reg = <0x5f0000 0x1900000>; - }; - - defaultmac: partition@1ef0000 { - label = "default-mac"; - reg = <0x1ef0000 0x00200>; - read-only; - }; - - partition@1ef0200 { - label = "pin"; - reg = <0x1ef0200 0x00200>; - read-only; - }; - - partition@1ef0400 { - label = "product-info"; - reg = <0x1ef0400 0x0fc00>; - read-only; - }; - - partition@1f00000 { - label = "partition-table"; - reg = <0x1f00000 0x10000>; - read-only; - }; - - partition@1f10000 { - label = "soft-version"; - reg = <0x1f10000 0x10000>; - read-only; - }; - - partition@1f20000 { - label = "support-list"; - reg = <0x1f20000 0x10000>; - read-only; - }; - - partition@1f30000 { - label = "profile"; - reg = <0x1f30000 0x10000>; - read-only; - }; - - partition@1f40000 { - label = "default-config"; - reg = <0x1f40000 0x10000>; - read-only; - }; - - partition@1f50000 { - label = "user-config"; - reg = <0x1f50000 0x40000>; - read-only; - }; - - partition@1f90000 { - label = "qos-db"; - reg = <0x1f90000 0x40000>; - read-only; - }; - - partition@1fd0000 { - label = "usb-config"; - reg = <0x1fd0000 0x10000>; - read-only; - }; - - partition@1fe0000 { - label = "log"; - reg = <0x1fe0000 0x20000>; - read-only; - }; - }; - }; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb0_pwr_en_pin>; - pinctrl-names = "default"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; - - pinctrl-0 = <&usb1_pwr_en_pin>; - pinctrl-names = "default"; -}; - -&pcie0 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_defaultmac_8>, <&precal_radio_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(-1)>; - }; - }; -}; - -&pcie1 { - status = "okay"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_defaultmac_8>, <&precal_radio_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_defaultmac_8>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_defaultmac_8>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&defaultmac { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_defaultmac_8: macaddr@8 { - reg = <0x8 0x6>; - }; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts deleted file mode 100644 index 6cb21fc4f3f..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts +++ /dev/null @@ -1,135 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8064-ad7200-c2600.dtsi" - -/ { - model = "TP-Link Talon AD7200"; - compatible = "tplink,ad7200", "qcom,ipq8064"; - - aliases { - led-boot = &led_status; - led-failsafe = &led_status; - led-running = &led_status; - led-upgrade = &led_status; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - led_enable { - label = "led-enable"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - lan { - label = "blue:lan"; - gpios = <&qcom_pinmux 2 GPIO_ACTIVE_HIGH>; - }; - - usb1 { - label = "blue:usb1"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - wlan5g { - label = "blue:wlan5g"; - gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>; - }; - - usb3 { - label = "blue:usb3"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; - }; - - wlan2g { - label = "blue:wlan2g"; - gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>; - }; - - wan_orange { - label = "orange:wan"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; - }; - - wan_blue { - label = "blue:wan"; - gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "blue:wps"; - gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; - }; - - wlan60g { - label = "blue:wlan60g"; - gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; - }; - - led_status: status { - label = "blue:status"; - gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio53", "gpio54", "gpio67"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio2", "gpio8", "gpio15", "gpio16", "gpio17", "gpio26", - "gpio33", "gpio55", "gpio56", "gpio66"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; - -&pcie2 { - status = "okay"; - max-link-speed = <1>; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap148.dts deleted file mode 100644 index d3b7c44877e..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +++ /dev/null @@ -1,134 +0,0 @@ -#include "qcom-ipq8064-v1.0.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ8064/AP-148"; - compatible = "qcom,ipq8064-ap148", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - aliases { - mdio-gpio0 = &mdio0; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&flash { - partitions { - compatible = "qcom,smem-part"; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; - max-link-speed = <1>; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "qcom,smem-part"; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap161.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap161.dts deleted file mode 100644 index 02ddbf31180..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap161.dts +++ /dev/null @@ -1,172 +0,0 @@ -#include "qcom-ipq8064-v1.0.dtsi" - -/ { - model = "Qualcomm IPQ8064/AP161"; - compatible = "qcom,ipq8064-ap161", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - aliases { - mdio-gpio0 = &mdio0; - }; -}; - -&qcom_pinmux { - rgmii2_pins: rgmii2-pins { - mux { - pins = "gpio27", "gpio28", "gpio29", - "gpio30", "gpio31", "gpio32", - "gpio51", "gpio52", "gpio59", - "gpio60", "gpio61", "gpio62", - "gpio2", "gpio66"; - }; - }; -}; - -&flash { - partitions { - compatible = "qcom,smem-part"; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; - max-link-speed = <1>; -}; - -&pcie2 { - status = "okay"; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "qcom,smem-part"; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x20080 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - qca,phy-rgmii-en; - qca,txclk-delay-en; - qca,rxclk-delay-en; - }; - - phy3: ethernet-phy@3 { - device_type = "ethernet-phy"; - reg = <3>; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <0>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - mdiobus = <&mdio0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - mdiobus = <&mdio0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - mdiobus = <&mdio0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-asus-onhub.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-asus-onhub.dts deleted file mode 100644 index 442bcf19a67..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-asus-onhub.dts +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2014 The ChromiumOS Authors - */ - -#include "qcom-ipq8064-onhub.dtsi" -#include -#include -#include - -/ { - model = "ASUS OnHub"; - compatible = "asus,onhub", "google,arkham", "qcom,ipq8064"; -}; - -&qcom_pinmux { - ap3223_pins: ap3223_pinmux { - pins = "gpio22"; - function = "gpio"; - bias-none; - }; - - i2c7_pins: i2c7_pinmux { - mux { - pins = "gpio8", "gpio9"; - function = "gsbi7"; - }; - data { - pins = "gpio8"; - bias-disable; - }; - clk { - pins = "gpio9"; - bias-disable; - }; - }; -}; - -&gsbi7 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi7_i2c { - status = "okay"; - clock-frequency = <100000>; - pinctrl-0 = <&i2c7_pins>; - pinctrl-names = "default"; - - ap3223@1c { - compatible = "dynaimage,ap3223"; - reg = <0x1c>; - - pinctrl-0 = <&ap3223_pins>; - pinctrl-names = "default"; - - int-gpio = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>; - }; - - led-controller@32 { - compatible = "national,lp5523"; - reg = <0x32>; - clock-mode = /bits/ 8 <1>; - #address-cells = <1>; - #size-cells = <0>; - - led@4 { - reg = <4>; - color = ; - chan-name = "green:status"; - linux,default-trigger = "default-on"; - led-cur = /bits/ 8 <0xfa>; - max-cur = /bits/ 8 <0xff>; - }; - - led@5 { - reg = <5>; - color = ; - chan-name = "blue:status"; - led-cur = /bits/ 8 <0xfa>; - max-cur = /bits/ 8 <0xff>; - }; - - led@8 { - reg = <8>; - color = ; - chan-name = "red:status"; - led-cur = /bits/ 8 <0xfa>; - max-cur = /bits/ 8 <0xff>; - }; - }; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-c2600.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-c2600.dts deleted file mode 100644 index cef1aba3444..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-c2600.dts +++ /dev/null @@ -1,119 +0,0 @@ -#include "qcom-ipq8064-ad7200-c2600.dtsi" - -/ { - model = "TP-Link Archer C2600"; - compatible = "tplink,c2600", "qcom,ipq8064"; - - aliases { - led-boot = &power; - led-failsafe = &general; - led-running = &power; - led-upgrade = &general; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 49 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - ledswitch { - label = "ledswitch"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - lan { - label = "white:lan"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>; - }; - - usb4 { - label = "white:usb_4"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "white:usb_2"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "white:wps"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - wan_amber { - label = "amber:wan"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; - }; - - wan_white { - label = "white:wan"; - gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>; - }; - - power: power { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - general: general { - label = "white:general"; - gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio16", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio26", "gpio33", - "gpio53", "gpio66"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts deleted file mode 100644 index b8273c614ae..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts +++ /dev/null @@ -1,394 +0,0 @@ -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -#include - -/ { - model = "Netgear Nighthawk X4 D7800"; - compatible = "netgear,d7800", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - rsvd@5fe00000 { - reg = <0x5fe00000 0x200000>; - reusable; - }; - }; - - aliases { - mdio-gpio0 = &mdio0; - - led-boot = &power_white; - led-failsafe = &power_amber; - led-running = &power_white; - led-upgrade = &power_amber; - }; - - chosen { - bootargs = "rootfstype=squashfs noinitrd"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - usb1 { - label = "white:usb1"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "white:usb2"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - power_amber: power_amber { - label = "amber:power"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - wan_white { - label = "white:wan"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - wan_amber { - label = "amber:wan"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "white:wps"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - - esata { - label = "white:esata"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - - power_white: power_white { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - wifi { - label = "white:wifi"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", - "gpio24","gpio26", "gpio53", "gpio64"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - usb0_pwr_en_pins: usb0_pwr_en_pins { - mux { - pins = "gpio15"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; - - usb1_pwr_en_pins: usb1_pwr_en_pins { - mux { - pins = "gpio16", "gpio68"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; -}; - -&sata_phy { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb0_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; - - pinctrl-0 = <&usb1_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&pcie0 { - status = "okay"; - reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_art_6>, <&precal_art_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(1)>; - }; - }; -}; - -&pcie1 { - status = "okay"; - reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_art_6>, <&precal_art_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(2)>; - }; - }; -}; - -&pcie2 { - status = "okay"; - reset-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie2_pins>; - pinctrl-names = "default"; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot-partitions = <0x0 0x1180000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - qcadata@0 { - label = "qcadata"; - reg = <0x0000000 0x0c80000>; - read-only; - }; - - APPSBL@c80000 { - label = "APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - APPSBLENV@1180000 { - label = "APPSBLENV"; - reg = <0x1180000 0x0080000>; - read-only; - }; - - art@1200000 { - label = "art"; - reg = <0x1200000 0x0140000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - precal_art_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_art_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - artbak: art@1340000 { - label = "artbak"; - reg = <0x1340000 0x0140000>; - read-only; - }; - - kernel@1480000 { - label = "kernel"; - reg = <0x1480000 0x0400000>; - }; - - ubi@1880000 { - label = "ubi"; - reg = <0x1880000 0x6080000>; - }; - - reserve@7900000 { - label = "reserve"; - reg = <0x7900000 0x0700000>; - read-only; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_art_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_art_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-db149.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-db149.dts deleted file mode 100644 index f628df919b4..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-db149.dts +++ /dev/null @@ -1,179 +0,0 @@ -#include "qcom-ipq8064-v1.0.dtsi" - -/ { - model = "Qualcomm IPQ8064/DB149"; - compatible = "qcom,ipq8064-db149", "qcom,ipq8064"; - - aliases { - serial0 = &gsbi2_serial; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; -}; - -&qcom_pinmux { - rgmii0_pins: rgmii0_pins { - mux { - pins = "gpio2", "gpio66"; - drive-strength = <8>; - bias-disable; - }; - }; -}; - -&gsbi2 { - qcom,mode = ; - status = "okay"; - - gsbi2_serial: serial@12490000 { - status = "okay"; - }; -}; - -&gsbi4 { - status = "disabled"; -}; - -&gsbi4_serial { - status = "disabled"; -}; - -&flash { - m25p,fast-read; - - partition@0 { - label = "lowlevel_init"; - reg = <0x0 0x1b0000>; - }; - - partition@1 { - label = "u-boot"; - reg = <0x1b0000 0x80000>; - }; - - partition@2 { - label = "u-boot-env"; - reg = <0x230000 0x40000>; - }; - - partition@3 { - label = "caldata"; - reg = <0x270000 0x40000>; - }; - - partition@4 { - label = "firmware"; - reg = <0x2b0000 0x1d50000>; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pcie2 { - status = "okay"; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; - - phy6: ethernet-phy@6 { - reg = <6>; - }; - - phy7: ethernet-phy@7 { - reg = <7>; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <0>; - phy-handle = <&phy4>; - - pinctrl-0 = <&rgmii0_pins>; - pinctrl-names = "default"; -}; - -&gmac1 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <1>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - phy-handle = <&phy6>; -}; - -&gmac3 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <3>; - phy-handle = <&phy7>; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts deleted file mode 100644 index 9d82d52d273..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8064-eax500.dtsi" - -/ { - model = "Linksys EA7500 V1 WiFi Router"; - compatible = "linksys,ea7500-v1", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0xe000000>; - device_type = "memory"; - }; - - aliases { - led-boot = &led_power; - led-failsafe = &led_power; - led-running = &led_power; - led-upgrade = &led_power; - }; - - chosen { - /* look for root deviceblock nbr in this bootarg */ - find-rootblock = "ubi.mtd="; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - led_power: power { - label = "white:power"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio65", "gpio68"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio6"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; - -&partitions { - partition@5f80000 { - label = "sysdiag"; - reg = <0x5f80000 0x100000>; - }; - - partition@6080000 { - label = "syscfg"; - reg = <0x6080000 0x1f80000>; - }; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts deleted file mode 100644 index 1c6a4bdacd0..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts +++ /dev/null @@ -1,128 +0,0 @@ -#include "qcom-ipq8064-eax500.dtsi" - -/ { - model = "Linksys EA8500 WiFi Router"; - compatible = "linksys,ea8500", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - aliases { - mdio-gpio0 = &mdio0; - - led-boot = &led_power; - led-failsafe = &led_power; - led-running = &led_power; - led-upgrade = &led_power; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - wps { - label = "green:wps"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - }; - - led_power: power { - label = "white:power"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - wifi { - label = "green:wifi"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio65", "gpio67", "gpio68"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio6", "gpio53", "gpio54"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; - -&sata_phy { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&partitions { - partition@5f80000 { - label = "syscfg"; - reg = <0x5f80000 0x2080000>; - }; -}; - -&mdio0 { - phy4: ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - qcom,phy_mdio_addr = <4>; - qcom,poll_required = <1>; - qcom,rgmii_delay = <0>; - qcom,emulation = <0>; -}; - -/* LAN */ -&gmac2 { - qcom,phy_mdio_addr = <0>; /* none */ - qcom,poll_required = <0>; /* no polling */ - qcom,rgmii_delay = <0>; - qcom,emulation = <0>; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi deleted file mode 100644 index 910bd86bc5f..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -#include - -/ { - chosen { - bootargs = "console=ttyMSM0,115200n8"; - /* append to bootargs adding the root deviceblock nbr from bootloader */ - append-rootblock = "ubi.mtd="; - }; -}; - -&qcom_pinmux { - /* eax500 routers reuse the pcie2 reset pin for switch reset pin */ - switch_reset: switch_reset_pins { - mux { - pins = "gpio63"; - function = "gpio"; - drive-strength = <12>; - bias-pull-up; - }; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - - max-link-speed = <1>; -}; - -&pcie1 { - status = "okay"; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot-partitions = <0x0 0x0c80000>; - - partitions: partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SBL1"; - reg = <0x0000000 0x0040000>; - read-only; - }; - - partition@40000 { - label = "MIBIB"; - reg = <0x0040000 0x0140000>; - read-only; - }; - - partition@180000 { - label = "SBL2"; - reg = <0x0180000 0x0140000>; - read-only; - }; - - partition@2c0000 { - label = "SBL3"; - reg = <0x02c0000 0x0280000>; - read-only; - }; - - partition@540000 { - label = "DDRCONFIG"; - reg = <0x0540000 0x0120000>; - read-only; - }; - - partition@660000 { - label = "SSD"; - reg = <0x0660000 0x0120000>; - read-only; - }; - - partition@780000 { - label = "TZ"; - reg = <0x0780000 0x0280000>; - read-only; - }; - - partition@a00000 { - label = "RPM"; - reg = <0x0a00000 0x0280000>; - read-only; - }; - - art: partition@c80000 { - label = "art"; - reg = <0x0c80000 0x0140000>; - read-only; - }; - - partition@dc0000 { - label = "APPSBL"; - reg = <0x0dc0000 0x0100000>; - read-only; - }; - - partition@ec0000 { - label = "u_env"; - reg = <0x0ec0000 0x0040000>; - }; - - partition@f00000 { - label = "s_env"; - reg = <0x0f00000 0x0040000>; - }; - - partition@f40000 { - label = "devinfo"; - reg = <0x0f40000 0x0040000>; - }; - - partition@f80000 { - label = "kernel1"; - reg = <0x0f80000 0x2800000>; /* 4 MB, spill to rootfs */ - }; - - partition@1380000 { - label = "rootfs1"; - reg = <0x1380000 0x2400000>; - }; - - partition@3780000 { - label = "kernel2"; - reg = <0x3780000 0x2800000>; - }; - - partition@3b80000 { - label = "rootfs2"; - reg = <0x3b80000 0x2400000>; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - /* Switch from documentation require at least 10ms for reset */ - reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>; - reset-post-delay-us = <12000>; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x00010 0x2613a0 /* PWS_REG */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; -}; - -&gmac1 { - status = "okay"; - - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts deleted file mode 100644 index 63a72b53ae7..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts +++ /dev/null @@ -1,292 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -#include -#include - -/ { - compatible = "asrock,g10", "qcom,ipq8064"; - model = "ASRock G10"; - - aliases { - ethernet0 = &gmac1; - ethernet1 = &gmac0; - - led-boot = &led_status_blue; - led-failsafe = &led_status_amber; - led-running = &led_status_blue; - led-upgrade = &led_status_amber; - }; - - chosen { - bootargs-override = "console=ttyMSM0,115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - /* - * this is a bit misleading. Because there are about seven - * multicolor LEDs connected all wired together in parallel. - */ - - status_yellow { - label = "yellow:status"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - led_status_amber: status_amber { - label = "amber:status"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - led_status_blue: status_blue { - label = "blue:status"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - /* - * LED is declared in vendors boardfile but it's not - * working and the manual doesn't mention anything - * about the LED being white. - - status_white { - label = "white:status"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - */ - }; - - i2c-gpio { - #address-cells = <1>; - #size-cells = <0>; - - compatible = "i2c-gpio"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>, /* sda */ - <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,delay-us = <5>; - i2c-gpio,scl-output-only; - - mcu@50 { - reg = <0x50>; - compatible = "sonix,sn8f25e21"; - }; - }; - - keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - ir-remote { - label = "ir-remote"; - gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps5g { - label = "wps5g"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps2g { - label = "wps2g"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&gmac1 { - status = "okay"; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - phy-mode = "rgmii"; - qcom,id = <1>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gsbi4_serial { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot-partitions = <0x0 0x1200000>; - - partitions { - compatible = "qcom,smem-part"; - }; - }; -}; - -&pcie0 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi5g: wifi@1,0 { - reg = <0x00010000 0 0 0 0>; - compatible = "qcom,ath10k"; - qcom,ath10k-calibration-variant = "ASRock-G10"; - }; - }; -}; - -&pcie1 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi2g: wifi@1,0 { - reg = <0x00010000 0 0 0 0>; - compatible = "qcom,ath10k"; - qcom,ath10k-calibration-variant = "ASRock-G10"; - }; - }; -}; - -&qcom_pinmux { - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio26"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio15", "gpio16", "gpio64", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - uart0_pins: uart0_pins { - mux { - pins = "gpio10", "gpio11"; - function = "gsbi4"; - drive-strength = <10>; - bias-disable; - }; - }; -}; - -&rpm { - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "default"; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&tcsr { - qcom,usb-ctrl-select = ; -}; - -/delete-node/ &pcie2_pins; -/delete-node/ &pcie2; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-onhub.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-onhub.dtsi deleted file mode 100644 index 549c4620261..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-onhub.dtsi +++ /dev/null @@ -1,491 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2014 The ChromiumOS Authors - */ - -#include "qcom-ipq8064-smb208.dtsi" -#include -#include -#include - -/ { - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac2; - mdio-gpio0 = &mdio; - serial0 = &gsbi4_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - dev { - label = "dev"; - gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - mdio: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, - <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0xaa545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - - soc { - rng@1a500000 { - status = "disabled"; - }; - - sound { - compatible = "google,storm-audio"; - qcom,model = "ipq806x-storm"; - cpu = <&lpass>; - codec = <&max98357a>; - }; - - lpass: lpass@28100000 { - status = "okay"; - pinctrl-names = "default", "idle"; - pinctrl-0 = <&mi2s_default>; - pinctrl-1 = <&mi2s_idle>; - }; - - max98357a: max98357a { - compatible = "maxim,max98357a"; - #sound-dai-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmode_pins>; - sdmode-gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - rgmii0_pins: rgmii0_pins { - mux { - pins = "gpio2", "gpio66"; - drive-strength = <8>; - bias-disable; - }; - }; - mi2s_pins { - mi2s_default: mi2s_default { - dout { - pins = "gpio32"; - function = "mi2s"; - drive-strength = <16>; - bias-disable; - }; - sync { - pins = "gpio27"; - function = "mi2s"; - drive-strength = <16>; - bias-disable; - }; - clk { - pins = "gpio28"; - function = "mi2s"; - drive-strength = <16>; - bias-disable; - }; - }; - mi2s_idle: mi2s_idle { - dout { - pins = "gpio32"; - function = "mi2s"; - drive-strength = <2>; - bias-pull-down; - }; - sync { - pins = "gpio27"; - function = "mi2s"; - drive-strength = <2>; - bias-pull-down; - }; - clk { - pins = "gpio28"; - function = "mi2s"; - drive-strength = <2>; - bias-pull-down; - }; - }; - }; - - mdio_pins: mdio_pins { - mux { - pins = "gpio0", "gpio1"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - rst { - pins = "gpio26"; - output-low; - }; - }; - - sdmode_pins: sdmode_pinmux { - pins = "gpio25"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - - sdcc1_pins: sdcc1_pinmux { - mux { - pins = "gpio38", "gpio39", "gpio40", - "gpio41", "gpio42", "gpio43", - "gpio44", "gpio45", "gpio46", - "gpio47"; - function = "sdc1"; - }; - cmd { - pins = "gpio45"; - drive-strength = <10>; - bias-pull-up; - }; - data { - pins = "gpio38", "gpio39", "gpio40", - "gpio41", "gpio43", "gpio44", - "gpio46", "gpio47"; - drive-strength = <10>; - bias-pull-up; - }; - clk { - pins = "gpio42"; - drive-strength = <16>; - bias-pull-down; - }; - }; - - i2c1_pins: i2c1_pinmux { - pins = "gpio53", "gpio54"; - function = "gsbi1"; - bias-disable; - }; - - rpm_i2c_pinmux: rpm_i2c_pinmux { - mux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - drive-strength = <12>; - bias-disable; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - /delete-property/ bias-none; - /delete-property/ drive-strength; - }; - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - cs { - pins = "gpio20"; - drive-strength = <10>; - bias-pull-up; - }; - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - fw_pinmux { - wp { - pins = "gpio17"; - output-low; - }; - }; - - button_pins: button_pins { - recovery { - pins = "gpio16"; - function = "gpio"; - bias-none; - }; - developer { - pins = "gpio15"; - function = "gpio"; - bias-none; - }; - }; - - spi6_pins: spi6_pins { - mux { - pins = "gpio55", "gpio56", "gpio58"; - function = "gsbi6"; - bias-pull-down; - }; - data { - pins = "gpio55", "gpio56"; - drive-strength = <10>; - }; - cs { - pins = "gpio57"; - drive-strength = <10>; - bias-pull-up; - output-high; - }; - clk { - pins = "gpio58"; - drive-strength = <12>; - }; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <0>; - phy-handle = <&phy1>; - - pinctrl-0 = <&rgmii0_pins>; - pinctrl-names = "default"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - phy-handle = <&phy0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gsbi1 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi1_i2c { - status = "okay"; - - clock-frequency = <100000>; - - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - powered-while-suspended; - }; -}; - -&gsbi4 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi4_serial { - status = "okay"; -}; - -&gsbi5 { - status = "okay"; - qcom,mode = ; - - spi4: spi@1a280000 { - status = "okay"; - spi-max-frequency = <50000000>; - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 0>; - - flash: flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; -}; - -&gsbi6 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi6_spi { - status = "okay"; - spi-max-frequency = <25000000>; - - pinctrl-0 = <&spi6_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>; - - dmas = <&adm_dma 8 0xb>, - <&adm_dma 7 0x14>; - dma-names = "rx", "tx"; - - /* - * This "spidev" was included in the manufacturer device tree. I suspect - * it's the (unused) Zigbee radio -- SiliconLabs EM3581 Zigbee? There's - * no driver or binding for this at the moment. - */ - spidev@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <25000000>; - }; -}; - -&pcie0 { - status = "okay"; - - pcie@0 { - reg = <0 0 0 0 0>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - - ath10k@0,0 { - reg = <0 0 0 0 0>; - device_type = "pci"; - qcom,ath10k-sa-gpio = <2 3 4 0>; - qcom,ath10k-sa-gpio-func = <5 5 5 0>; - }; - }; -}; - -&pcie1 { - status = "okay"; - - pcie@0 { - reg = <0 0 0 0 0>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - - ath10k@0,0 { - reg = <0 0 0 0 0>; - device_type = "pci"; - qcom,ath10k-sa-gpio = <2 3 4 0>; - qcom,ath10k-sa-gpio-func = <5 5 5 0>; - }; - }; -}; - -&pcie2 { - status = "okay"; - - pcie@0 { - reg = <0 0 0 0 0>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - - ath10k@0,0 { - reg = <0 0 0 0 0>; - device_type = "pci"; - }; - }; -}; - -&rpm { - pinctrl-0 = <&rpm_i2c_pinmux>; - pinctrl-names = "default"; -}; - -&sdcc1 { - status = "okay"; - pinctrl-0 = <&sdcc1_pins>; - pinctrl-names = "default"; - /delete-property/ mmc-ddr-1_8v; -}; - -&tcsr { - compatible = "qcom,tcsr-ipq8064", "qcom,tcsr", "syscon"; - qcom,usb-ctrl-select = ; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts deleted file mode 100644 index 7bea5b6bceb..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts +++ /dev/null @@ -1,327 +0,0 @@ -#include "qcom-ipq8064-v1.0.dtsi" - -#include -#include - -/ { - model = "Netgear Nighthawk X4 R7500"; - compatible = "netgear,r7500", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0xe000000>; - device_type = "memory"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - aliases { - mdio-gpio0 = &mdio0; - - led-boot = &power_white; - led-failsafe = &power_amber; - led-running = &power_white; - led-upgrade = &power_amber; - }; - - chosen { - bootargs = "rootfstype=squashfs noinitrd"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - usb1 { - label = "white:usb1"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "white:usb2"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - power_amber: power_amber { - label = "amber:power"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - wan_white { - label = "white:wan"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - wan_amber { - label = "amber:wan"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "white:wps"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - - esata { - label = "white:esata"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - - power_white: power_white { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - wifi { - label = "white:wifi"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", - "gpio24","gpio26", "gpio53", "gpio64"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; - -&gsbi5 { - status = "disabled"; - - spi@1a280000 { - status = "disabled"; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; - max-link-speed = <1>; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot-partitions = <0x0 0x1180000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - qcadata@0 { - label = "qcadata"; - reg = <0x0000000 0x0c80000>; - read-only; - }; - - APPSBL@c80000 { - label = "APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - APPSBLENV@1180000 { - label = "APPSBLENV"; - reg = <0x1180000 0x0080000>; - read-only; - }; - - art: art@1200000 { - label = "art"; - reg = <0x1200000 0x0140000>; - read-only; - }; - - kernel@1340000 { - label = "kernel"; - reg = <0x1340000 0x0400000>; - }; - - ubi@1740000 { - label = "ubi"; - reg = <0x1740000 0x1600000>; - }; - - netgear@2d40000 { - label = "netgear"; - reg = <0x2d40000 0x0c00000>; - read-only; - }; - - reserve@3940000 { - label = "reserve"; - reg = <0x3940000 0x46c0000>; - read-only; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_art_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_art_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&tcsr { - qcom,usb-ctrl-select = ; - compatible = "qcom,tcsr"; -}; - -&adm_dma { - status = "okay"; -}; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts deleted file mode 100644 index 6f0ba09c872..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts +++ /dev/null @@ -1,387 +0,0 @@ -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -#include - -/ { - model = "Netgear Nighthawk X4 R7500v2"; - compatible = "netgear,r7500v2", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - rsvd@5fe00000 { - reg = <0x5fe00000 0x200000>; - reusable; - }; - }; - - aliases { - mdio-gpio0 = &mdio0; - - led-boot = &power; - led-failsafe = &power; - led-running = &power; - led-upgrade = &power; - }; - - chosen { - bootargs = "rootfstype=squashfs noinitrd"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - usb1 { - label = "amber:usb1"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb3 { - label = "amber:usb3"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - status { - label = "amber:status"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - internet { - label = "white:internet"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - wan { - label = "white:wan"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "white:wps"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - - esata { - label = "white:esata"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - - power: power { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - wifi { - label = "white:wifi"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", - "gpio24","gpio26", "gpio53", "gpio64"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - usb0_pwr_en_pins: usb0_pwr_en_pins { - mux { - pins = "gpio15"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; - - usb1_pwr_en_pins: usb1_pwr_en_pins { - mux { - pins = "gpio16", "gpio68"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; -}; - -&sata_phy { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb0_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; - - pinctrl-0 = <&usb1_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&pcie0 { - status = "okay"; - reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_art_6>, <&precal_art_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(1)>; - }; - }; -}; - -&pcie1 { - status = "okay"; - reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_art_6>, <&precal_art_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(2)>; - }; - }; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot-partitions = <0x0 0x1180000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - qcadata@0 { - label = "qcadata"; - reg = <0x0000000 0x0c80000>; - read-only; - }; - - APPSBL@c80000 { - label = "APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - APPSBLENV@1180000 { - label = "APPSBLENV"; - reg = <0x1180000 0x0080000>; - read-only; - }; - - art@1200000 { - label = "art"; - reg = <0x1200000 0x0140000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - precal_art_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_art_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - artbak: art@1340000 { - label = "artbak"; - reg = <0x1340000 0x0140000>; - read-only; - }; - - kernel@1480000 { - label = "kernel"; - reg = <0x1480000 0x0400000>; - }; - - ubi@1880000 { - label = "ubi"; - reg = <0x1880000 0x6080000>; - }; - - reserve@7900000 { - label = "reserve"; - reg = <0x7900000 0x0700000>; - read-only; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0xaa545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_art_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_art_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-tplink-onhub.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-tplink-onhub.dts deleted file mode 100644 index 6adc6be4aec..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-tplink-onhub.dts +++ /dev/null @@ -1,209 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2014 The ChromiumOS Authors - */ - -#include "qcom-ipq8064-onhub.dtsi" -#include -#include -#include - -/ { - model = "TP-Link OnHub"; - compatible = "tplink,onhub", "google,whirlwind-sp5", "qcom,ipq8064"; -}; - -&qcom_pinmux { - i2c7_pins: i2c7_pinmux { - mux { - pins = "gpio8", "gpio9"; - function = "gsbi7"; - }; - data { - pins = "gpio8"; - bias-disable; - }; - clk { - pins = "gpio9"; - bias-disable; - }; - }; -}; - -&gsbi7 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi7_i2c { - status = "okay"; - clock-frequency = <100000>; - pinctrl-0 = <&i2c7_pins>; - pinctrl-names = "default"; - - led-controller@32 { - compatible = "national,lp5523"; - reg = <0x32>; - clock-mode = /bits/ 8 <1>; - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - color = ; - chan-name = "red:status-0"; - linux,default-trigger = "default-on"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@1 { - reg = <1>; - color = ; - chan-name = "green:status-0"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@2 { - reg = <2>; - color = ; - chan-name = "blue:status-0"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@3 { - reg = <3>; - color = ; - chan-name = "red:status-1"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@4 { - reg = <4>; - color = ; - chan-name = "green:status-1"; - linux,default-trigger = "default-on"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@5 { - reg = <5>; - color = ; - chan-name = "blue:status-1"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@6 { - reg = <6>; - color = ; - chan-name = "red:status-2"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@7 { - reg = <7>; - color = ; - chan-name = "green:status-2"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@8 { - reg = <8>; - color = ; - chan-name = "blue:status-2"; - linux,default-trigger = "default-on"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - }; - - led-controller@33 { - compatible = "national,lp5523"; - reg = <0x33>; - clock-mode = /bits/ 8 <1>; - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - color = ; - chan-name = "red:status-3"; - linux,default-trigger = "default-on"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@1 { - reg = <1>; - color = ; - chan-name = "green:status-3"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@2 { - reg = <2>; - color = ; - chan-name = "blue:status-3"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@3 { - reg = <3>; - color = ; - chan-name = "red:status-4"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@4 { - reg = <4>; - color = ; - chan-name = "green:status-4"; - linux,default-trigger = "default-on"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@5 { - reg = <5>; - color = ; - chan-name = "blue:status-4"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@6 { - reg = <6>; - color = ; - chan-name = "red:status-5"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@7 { - reg = <7>; - color = ; - chan-name = "green:status-5"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - - led@8 { - reg = <8>; - color = ; - chan-name = "blue:status-5"; - linux,default-trigger = "default-on"; - led-cur = /bits/ 8 <0x64>; - max-cur = /bits/ 8 <0x78>; - }; - }; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts deleted file mode 100644 index 90927ddb856..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts +++ /dev/null @@ -1,315 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -#include -#include - -/ { - model = "Ubiquiti UniFi AC HD"; - compatible = "ubnt,unifi-ac-hd", "qcom,ipq8064"; - - aliases { - label-mac-device = &gmac2; - led-boot = &led_dome_white; - led-failsafe = &led_dome_white; - led-running = &led_dome_blue; - led-upgrade = &led_dome_blue; - mdio-gpio0 = &mdio0; - ethernet0 = &gmac2; - ethernet1 = &gmac1; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - led_dome_blue: dome_blue { - label = "blue:dome"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - led_dome_white: dome_white { - label = "white:dome"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio68"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio9", "gpio53"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - output-low; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - drive-strength = <10>; - bias-none; - }; - - cs { - pins = "gpio20"; - drive-strength = <12>; - }; - }; -}; - -&CPU_SPC { - status = "disabled"; -}; - -&gsbi5 { - status = "okay"; - - qcom,mode = ; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - cs-gpios = <&qcom_pinmux 20 0>; - - flash@0 { - compatible = "mx25u25635f", "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SBL1"; - reg = <0x0 0x20000>; - read-only; - }; - - partition@20000 { - label = "MIBIB"; - reg = <0x20000 0x10000>; - read-only; - }; - - partition@30000 { - label = "SBL2"; - reg = <0x30000 0x20000>; - read-only; - }; - - partition@50000 { - label = "SBL3"; - reg = <0x50000 0x30000>; - read-only; - }; - - partition@80000 { - label = "DDRCONFIG"; - reg = <0x80000 0x10000>; - read-only; - }; - - partition@90000 { - label = "SSD"; - reg = <0x90000 0x10000>; - read-only; - }; - - partition@a0000 { - label = "TZ"; - reg = <0xa0000 0x30000>; - read-only; - }; - - partition@d0000 { - label = "RPM"; - reg = <0xd0000 0x20000>; - read-only; - }; - - partition@f0000 { - label = "APPSBL"; - reg = <0xf0000 0xc0000>; - read-only; - }; - - partition@1b0000 { - label = "APPSBLENV"; - reg = <0x1b0000 0x10000>; - read-only; - }; - - eeprom: partition@1c0000 { - label = "EEPROM"; - reg = <0x1c0000 0x10000>; - read-only; - }; - - partition@1d0000 { - label = "bootselect"; - reg = <0x1d0000 0x10000>; - }; - - partition@1e0000 { - compatible = "denx,fit"; - label = "firmware"; - reg = <0x1e0000 0xe70000>; - }; - - partition@1050000 { - label = "kernel1"; - reg = <0x1050000 0xe70000>; - read-only; - }; - - partition@1ec0000 { - label = "debug"; - reg = <0x1ec0000 0x100000>; - read-only; - }; - - partition@1fc0000 { - label = "cfg"; - reg = <0x1fc0000 0x40000>; - read-only; - }; - }; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&nand { - status = "okay"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy4: ethernet-phy@4 { - reg = <4>; - }; - - phy5: ethernet-phy@5 { - reg = <5>; - }; -}; - -&gmac1 { - status = "okay"; - - mdiobus = <&mdio0>; - phy-handle = <&phy5>; - phy-mode = "sgmii"; - qcom,id = <1>; - - nvmem-cells = <&macaddr_eeprom_6>; - nvmem-cell-names = "mac-address"; -}; - -&gmac2 { - status = "okay"; - - mdiobus = <&mdio0>; - phy-handle = <&phy4>; - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_eeprom_0>; - nvmem-cell-names = "mac-address"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&tcsr { - status = "okay"; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&eeprom { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_eeprom_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_eeprom_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts deleted file mode 100644 index b0db8c88635..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts +++ /dev/null @@ -1,424 +0,0 @@ -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -#include - -/ { - model = "TP-Link Archer VR2600v"; - compatible = "tplink,vr2600v", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - aliases { - mdio-gpio0 = &mdio0; - - led-boot = &power; - led-failsafe = &general; - led-running = &power; - led-upgrade = &general; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - dect { - label = "dect"; - gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - ledswitch { - label = "ledswitch"; - gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - dsl { - label = "white:dsl"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb { - label = "white:usb"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - lan { - label = "white:lan"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - wlan2g { - label = "white:wlan2g"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; - }; - - wlan5g { - label = "white:wlan5g"; - gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>; - }; - - power: power { - label = "white:power"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - phone { - label = "white:phone"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - }; - - wan { - label = "white:wan"; - gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; - }; - - general: general { - label = "white:general"; - gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio17", - "gpio26", "gpio53", "gpio56", "gpio66"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio54", "gpio64", "gpio65", "gpio67", "gpio68"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs { - pins = "gpio20"; - drive-strength = <10>; - bias-pull-up; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; - - spi4: spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SBL1"; - reg = <0x0 0x20000>; - read-only; - }; - - partition@20000 { - label = "MIBIB"; - reg = <0x20000 0x20000>; - read-only; - }; - - partition@40000 { - label = "SBL2"; - reg = <0x40000 0x40000>; - read-only; - }; - - partition@80000 { - label = "SBL3"; - reg = <0x80000 0x80000>; - read-only; - }; - - partition@100000 { - label = "DDRCONFIG"; - reg = <0x100000 0x10000>; - read-only; - }; - - partition@110000 { - label = "SSD"; - reg = <0x110000 0x10000>; - read-only; - }; - - partition@120000 { - label = "TZ"; - reg = <0x120000 0x80000>; - read-only; - }; - - partition@1a0000 { - label = "RPM"; - reg = <0x1a0000 0x80000>; - read-only; - }; - - partition@220000 { - label = "APPSBL"; - reg = <0x220000 0x80000>; - read-only; - }; - - partition@2a0000 { - label = "APPSBLENV"; - reg = <0x2a0000 0x40000>; - read-only; - }; - - partition@2e0000 { - label = "OLDART"; - reg = <0x2e0000 0x40000>; - read-only; - }; - - partition@320000 { - label = "firmware"; - reg = <0x320000 0xc60000>; - compatible = "openwrt,uimage"; - openwrt,offset = <512>; /* account for pad-extra 512 */ - }; - - /* hole 0xf80000 - 0xfaf100 */ - - partition@faf100 { - label = "default-mac"; - reg = <0xfaf100 0x00200>; - read-only; - - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_defaultmac_0: macaddr@0 { - reg = <0x0 0x6>; - }; - }; - - partition@fc0000 { - label = "ART"; - reg = <0xfc0000 0x40000>; - read-only; - - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - precal_ART_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_ART_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - }; - }; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_defaultmac_0>, <&precal_ART_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(-1)>; - }; - }; -}; - -&pcie1 { - status = "okay"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_defaultmac_0>, <&precal_ART_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_defaultmac_0>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_defaultmac_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts deleted file mode 100644 index 431c9cd9af8..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts +++ /dev/null @@ -1,463 +0,0 @@ -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -#include - -/ { - model = "NEC Aterm WG2600HP"; - compatible = "nec,wg2600hp", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - aliases { - mdio-gpio0 = &mdio0; - - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - led-upgrade = &power_green; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - bridge { - label = "bridge"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - - converter { - label = "converter"; - gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - converter_green { - label = "green:converter"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>; - }; - - power_red: power_red { - label = "red:power"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - active_green { - label = "green:active"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - active_red { - label = "red:active"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - power_green: power_green { - label = "green:power"; - gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>; - }; - - converter_red { - label = "red:converter"; - gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>; - }; - - wlan2g_green { - label = "green:wlan2g"; - gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; - }; - - wlan2g_red { - label = "red:wlan2g"; - gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; - }; - - wlan5g_green { - label = "green:wlan5g"; - gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>; - }; - - wlan5g_red { - label = "red:wlan5g"; - gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>; - }; - - tv_green { - label = "green:tv"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - - tv_red { - label = "red:tv"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&CPU_SPC { - status = "disabled"; -}; - -&adm_dma { - status = "okay"; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x06000000 /* PAD0_MODE */ - 0x0000c 0x00080080 /* PAD6_MODE */ - 0x000e4 0x0006a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x0000004e /* PORT0_STATUS */ - 0x00094 0x0000004e /* PORT6_STATUS */ - >; - }; - - ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_PRODUCTDATA_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_PRODUCTDATA_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gsbi5 { - status = "okay"; - - qcom,mode = ; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - SBL1@0 { - label = "SBL1"; - reg = <0x0 0x20000>; - read-only; - }; - - MIBIB@20000 { - label = "MIBIB"; - reg = <0x20000 0x20000>; - read-only; - }; - - SBL2@40000 { - label = "SBL2"; - reg = <0x40000 0x40000>; - read-only; - }; - - SBL3@80000 { - label = "SBL3"; - reg = <0x80000 0x80000>; - read-only; - }; - - DDRCONFIG@100000 { - label = "DDRCONFIG"; - reg = <0x100000 0x10000>; - read-only; - }; - - SSD@110000 { - label = "SSD"; - reg = <0x110000 0x10000>; - read-only; - }; - - TZ@120000 { - label = "TZ"; - reg = <0x120000 0x80000>; - read-only; - }; - - RPM@1a0000 { - label = "RPM"; - reg = <0x1a0000 0x80000>; - read-only; - }; - - APPSBL@220000 { - label = "APPSBL"; - reg = <0x220000 0x80000>; - read-only; - }; - - APPSBLENV@2a0000 { - label = "APPSBLENV"; - reg = <0x2a0000 0x10000>; - }; - - PRODUCTDATA: PRODUCTDATA@2b0000 { - label = "PRODUCTDATA"; - reg = <0x2b0000 0x30000>; - read-only; - }; - - ART@2e0000 { - label = "ART"; - reg = <0x2e0000 0x40000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - precal_ART_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_ART_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - TP@320000 { - label = "TP"; - reg = <0x320000 0x40000>; - read-only; - }; - - TINY@360000 { - label = "TINY"; - reg = <0x360000 0x500000>; - read-only; - }; - - firmware@860000 { - compatible = "denx,uimage"; - label = "firmware"; - reg = <0x860000 0x17a0000>; - }; - }; - }; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&pcie1 { - status = "okay"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio16", "gpio54", "gpio24", "gpio25"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio14", - "gpio15", "gpio55", "gpio56", "gpio57", "gpio58", - "gpio64", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs { - pins = "gpio20"; - drive-strength = <10>; - bias-pull-up; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - usb_pwr_en_pins: usb_pwr_en_pins { - mux { - pins = "gpio22"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - output-high; - }; - }; -}; - -&PRODUCTDATA { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_PRODUCTDATA_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_PRODUCTDATA_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - macaddr_PRODUCTDATA_c: macaddr@c { - reg = <0xc 0x6>; - }; - - macaddr_PRODUCTDATA_12: macaddr@12 { - reg = <0x12 0x6>; - }; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts deleted file mode 100644 index 359b4cd470c..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts +++ /dev/null @@ -1,473 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (C) 2017 Christian Mehlis - * Copyright (C) 2018 Mathias Kresin - * All rights reserved. - */ - -#include "qcom-ipq8064-v1.0.dtsi" - -#include -#include - -/ { - compatible = "compex,wpq864", "qcom,ipq8064"; - model = "Compex WPQ864"; - - aliases { - mdio-gpio0 = &mdio0; - ethernet0 = &gmac1; - ethernet1 = &gmac0; - - led-boot = &led_pass; - led-failsafe = &led_fail; - led-running = &led_pass; - led-upgrade = &led_pass; - }; - - leds { - compatible = "gpio-leds"; - - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - rss4 { - label = "green:rss4"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - rss3 { - label = "green:rss3"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - rss2 { - label = "orange:rss2"; - gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>; - }; - - rss1 { - label = "red:rss1"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - led_pass: pass { - label = "green:pass"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - }; - - led_fail: fail { - label = "green:fail"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - usb { - label = "green:usb"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb-pcie { - label = "green:usb-pcie"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - beeper { - compatible = "gpio-beeper"; - - pinctrl-0 = <&beeper_pins>; - pinctrl-names = "default"; - - gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; - }; -}; - -&rpm { - pinctrl-0 = <&rpm_pins>; - pinctrl-names = "default"; -}; - -&nand { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - mt29f2g08abbeah4@0 { - compatible = "qcom,nandcs"; - - reg = <0>; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x10c0000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "0:SBL1"; - reg = <0x0000000 0x0040000>; - read-only; - }; - - partition@40000 { - label = "0:MIBIB"; - reg = <0x0040000 0x0140000>; - read-only; - }; - - partition@180000 { - label = "0:SBL2"; - reg = <0x0180000 0x0140000>; - read-only; - }; - - partition@2c0000 { - label = "0:SBL3"; - reg = <0x02c0000 0x0280000>; - read-only; - }; - - partition@540000 { - label = "0:DDRCONFIG"; - reg = <0x0540000 0x0120000>; - read-only; - }; - - partition@660000 { - label = "0:SSD"; - reg = <0x0660000 0x0120000>; - read-only; - }; - - partition@780000 { - label = "0:TZ"; - reg = <0x0780000 0x0280000>; - read-only; - }; - - partition@a00000 { - label = "0:RPM"; - reg = <0x0a00000 0x0280000>; - read-only; - }; - - partition@c80000 { - label = "0:APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - partition@1180000 { - label = "0:APPSBLENV"; - reg = <0x1180000 0x0080000>; - }; - - partition@1200000 { - label = "0:ART"; - reg = <0x1200000 0x0140000>; - }; - - partition@1340000 { - label = "ubi"; - reg = <0x1340000 0x4000000>; - }; - - partition@5340000 { - label = "0:BOOTCONFIG"; - reg = <0x5340000 0x0060000>; - }; - - partition@53a0000 { - label = "0:SBL2_1"; - reg = <0x53a0000 0x0140000>; - read-only; - }; - - partition@54e0000 { - label = "0:SBL3_1"; - reg = <0x54e0000 0x0280000>; - read-only; - }; - - partition@5760000 { - label = "0:DDRCONFIG_1"; - reg = <0x5760000 0x0120000>; - read-only; - }; - - partition@5880000 { - label = "0:SSD_1"; - reg = <0x5880000 0x0120000>; - read-only; - }; - - partition@59a0000 { - label = "0:TZ_1"; - reg = <0x59a0000 0x0280000>; - read-only; - }; - - partition@5c20000 { - label = "0:RPM_1"; - reg = <0x5c20000 0x0280000>; - read-only; - }; - - partition@5ea0000 { - label = "0:BOOTCONFIG1"; - reg = <0x5ea0000 0x0060000>; - }; - - partition@5f00000 { - label = "0:APPSBL_1"; - reg = <0x5f00000 0x0500000>; - read-only; - }; - - partition@6400000 { - label = "ubi_1"; - reg = <0x6400000 0x4000000>; - }; - - partition@a400000 { - label = "unused"; - reg = <0xa400000 0x5c00000>; - }; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - phy-mode = "rgmii"; - qcom,id = <1>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gsbi4_serial { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - -&flash { - compatible = "jedec,spi-nor"; -}; - -&sata_phy { - status = "disabled"; -}; - -&sata { - status = "disabled"; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; - - rx_eq = <2>; - tx_deamp_3_5db = <32>; - mpll = <160>; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; - - rx_eq = <2>; - tx_deamp_3_5db = <32>; - mpll = <160>; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; -}; - -&pcie1 { - status = "okay"; -}; - -&pcie2 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; -}; - -&qcom_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinctrl0 { - pcie0_pcie2_perst { - pins = "gpio3"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - output-high; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio22", - "gpio23", "gpio24", "gpio25", "gpio53"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio54"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - beeper_pins: beeper_pins { - mux { - pins = "gpio55"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - rpm_pins: rpm_pins { - mux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - drive-strength = <10>; - bias-disable; - }; - }; - - uart0_pins: uart0_pins { - mux { - pins = "gpio10", "gpio11"; - function = "gsbi4"; - drive-strength = <10>; - bias-disable; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19"; - function = "gsbi5"; - drive-strength = <10>; - bias-pull-down; - }; - - clk { - pins = "gpio21"; - function = "gsbi5"; - drive-strength = <12>; - bias-pull-down; - }; - - cs { - pins = "gpio20"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - }; - }; -}; - -&tcsr { - qcom,usb-ctrl-select = ; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts deleted file mode 100644 index 39fd81fe553..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts +++ /dev/null @@ -1,539 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -#include - -/ { - model = "Buffalo WXR-2533DHP"; - compatible = "buffalo,wxr-2533dhp", "qcom,ipq8064"; - - memory@42000000 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - aliases { - led-boot = &power; - led-failsafe = &diag; - led-running = &power; - led-upgrade = &power; - }; - - chosen { - /* use "ubi_rootfs" volume in "ubi" partition as rootfs */ - bootargs = "ubi.block=0,1 root=/dev/ubiblock0_1 rootfstype=squashfs"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - usb { - label = "green:usb"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "usbport"; - trigger-sources = <&hub_port0 &hub_port1>; - }; - - guestport { - label = "green:guestport"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - diag: diag { - label = "orange:diag"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - internet_orange { - label = "orange:internet"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; - }; - - internet_white { - label = "white:internet"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - wireless_orange { - label = "orange:wireless"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - wireless_white { - label = "white:wireless"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - - router_orange { - label = "orange:router"; - gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>; - }; - - router_white { - label = "white:router"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; - }; - - power: power { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - power { - label = "power"; - gpios = <&qcom_pinmux 58 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - eject { - label = "eject"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - guest { - label = "guest"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - ap { - label = "ap"; - gpios = <&qcom_pinmux 55 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - - router { - label = "router"; - gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - - auto { - label = "auto"; - gpios = <&qcom_pinmux 57 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - }; -}; - -&nand { - status = "okay"; - - cs@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - ubi@0 { - label = "ubi"; - reg = <0x0000000 0x4000000>; - }; - - rootfs_1@4000000 { - label = "rootfs_1"; - reg = <0x4000000 0x4000000>; - }; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x07600000 /* PAD0_MODE */ - 0x00008 0x01000000 /* PAD5_MODE */ - 0x0000c 0x00000080 /* PAD6_MODE */ - 0x00050 0xcc35cc35 /* LED_CTRL0 */ - 0x00054 0xca35ca35 /* LED_CTRL1 */ - 0x00058 0xc935c935 /* LED_CTRL2 */ - 0x0005c 0x03ffff00 /* LED_CTRL3 */ - 0x000e4 0x0006a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x0000007e /* PORT0_STATUS */ - 0x00094 0x0000007e /* PORT6_STATUS */ - >; - }; - - ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_ART_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_ART_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gsbi4_serial { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - -&gsbi5 { - status = "okay"; - qcom,mode = ; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - SBL1@0 { - label = "SBL1"; - reg = <0x0 0x10000>; - read-only; - }; - - MIBIB@10000 { - label = "MIBIB"; - reg = <0x10000 0x20000>; - read-only; - }; - - SBL2@30000 { - label = "SBL2"; - reg = <0x30000 0x30000>; - read-only; - }; - - SBL3@60000 { - label = "SBL3"; - reg = <0x60000 0x30000>; - read-only; - }; - - DDRCONFIG@90000 { - label = "DDRCONFIG"; - reg = <0x90000 0x10000>; - read-only; - }; - - SSD@a0000 { - label = "SSD"; - reg = <0xa0000 0x10000>; - read-only; - }; - - TZ@b0000 { - label = "TZ"; - reg = <0xb0000 0x30000>; - read-only; - }; - - RPM@e0000 { - label = "RPM"; - reg = <0xe0000 0x20000>; - read-only; - }; - - APPSBL@100000 { - label = "APPSBL"; - reg = <0x100000 0x70000>; - read-only; - }; - - APPSBLENV@170000 { - label = "APPSBLENV"; - reg = <0x170000 0x10000>; - read-only; - }; - - ART@180000 { - label = "ART"; - reg = <0x180000 0x40000>; - read-only; - - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_ART_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_ART_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - macaddr_ART_18: macaddr@18 { - reg = <0x18 0x6>; - }; - - macaddr_ART_1e: macaddr@1e { - reg = <0x1e 0x6>; - }; - - precal_ART_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_ART_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - BOOTCONFIG@1c0000 { - label = "BOOTCONFIG"; - reg = <0x1c0000 0x10000>; - read-only; - }; - - APPSBL_1@1d0000 { - label = "APPSBL_1"; - reg = <0x1d0000 0x70000>; - read-only; - }; - }; - }; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&dwc3_0 { - #address-cells = <1>; - #size-cells = <0>; - - hub_port0: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; -}; - -&dwc3_1 { - #address-cells = <1>; - #size-cells = <0>; - - hub_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; -}; - -&pcie0 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_ART_1e>, <&precal_ART_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&pcie1 { - status = "okay"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_ART_18>, <&precal_ART_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54", "gpio55", "gpio56", "gpio57", - "gpio58", "gpio64", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio22", - "gpio23", "gpio24", "gpio25", "gpio26", "gpio53"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - uart0_pins: uart0_pins { - mux { - pins = "gpio10", "gpio11"; - function = "gsbi4"; - drive-strength = <12>; - bias-disable; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs{ - pins = "gpio20"; - drive-strength = <10>; - bias-pull-up; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - usb_pwr_en_pins: usb_pwr_en_pins { - mux{ - pins = "gpio68"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - output-high; - }; - }; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-ac400i.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-ac400i.dts deleted file mode 100644 index 7151f8de525..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-ac400i.dts +++ /dev/null @@ -1,318 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8065-smb208.dtsi" -#include - -/ { - model = "Nokia AC400i"; - compatible = "nokia,ac400i", "qcom,ipq8065", "qcom,ipq8064"; - - aliases { - mdio-gpio0 = &mdio0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; - - led-boot = &pwr_red; - led-failsafe = &pwr_red; - led-running = &pwr_green; - led-upgrade = &pwr_green; - }; - - chosen { - bootargs-override = " console=ttyMSM0,115200n8 ubi.mtd=ubi root=/dev/ubiblock0_2"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - 5g_red { - label = "red:5g"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_HIGH>; - }; - - 5g_green { - label = "green:5g"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - - 2g_red { - label = "red:2g"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - }; - - 2g_green { - label = "green:2g"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; - }; - - eth1_red { - label = "red:eth1"; - gpios = <&qcom_pinmux 68 GPIO_ACTIVE_HIGH>; - }; - - eth1_green { - label = "green:eth1"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>; - }; - - eth2_red { - label = "red:eth2"; - gpios = <&qcom_pinmux 67 GPIO_ACTIVE_HIGH>; - }; - - eth2_green { - label = "green:eth2"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>; - }; - - ctrl_red { - label = "red:ctrl"; - gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; - }; - - ctrl_green { - label = "green:ctrl"; - gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; - }; - - pwr_red: pwr_red { - label = "red:pwr"; - gpios = <&qcom_pinmux 2 GPIO_ACTIVE_LOW>; - }; - - pwr_green: pwr_green { - label = "green:pwr"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19"; - function = "gsbi5"; - drive-strength = <10>; - bias-pull-down; - }; - - clk { - pins = "gpio21"; - function = "gsbi5"; - drive-strength = <12>; - bias-pull-down; - }; - - cs { - pins = "gpio20"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio65", "gpio64", - "gpio53", "gpio54", - "gpio68", "gpio22", - "gpio67", "gpio23", - "gpio55", "gpio56", - "gpio2", "gpio26"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio15"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; - - spi4: spi@1a280000 { - status = "okay"; - spi-max-frequency = <50000000>; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - m25p80@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - partitions { - compatible = "qcom,smem-part"; - }; - }; - }; -}; - -&usb3_0 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "qcom,ath10k"; - status = "okay"; - reg = <0x00010000 0 0 0 0>; - qcom,ath10k-calibration-variant = "Nokia-AC400i"; - }; - }; -}; - -&pcie1 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "qcom,ath10k"; - status = "okay"; - reg = <0x00010000 0 0 0 0>; - qcom,ath10k-calibration-variant = "Nokia-AC400i"; - }; - }; -}; - -&mdio0 { - status = "okay"; - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - -}; - -//POE -&gmac0 { - status = "okay"; - qcom,id = <0>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - mdiobus = <&mdio0>; - phy-handle = <&phy0>; - phy-mode = "rgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -//LAN1 -&gmac1 { - status = "okay"; - qcom,id = <1>; - - mdiobus = <&mdio0>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&nand { - status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - rootfs@0 { - label = "rootfs"; - reg = <0x0000000 0x4000000>; - }; - - rootfs_1@4000000 { - label = "rootfs_1"; - reg = <0x4000000 0x4000000>; - }; - - cfg@8000000 { - label = "cfg"; - reg = <0x8000000 0x8000000>; - }; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts deleted file mode 100644 index 162b28d27fb..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts +++ /dev/null @@ -1,332 +0,0 @@ -#include "qcom-ipq8065-smb208.dtsi" - -#include - -/ { - model = "ZyXEL NBG6817"; - compatible = "zyxel,nbg6817", "qcom,ipq8065", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - aliases { - mdio-gpio0 = &mdio0; - sdcc1 = &sdcc1; - - led-boot = &power; - led-failsafe = &power; - led-running = &power; - led-upgrade = &power; - }; - - chosen { - bootargs = "rootfstype=squashfs,ext4 rootwait noinitrd fstools_ignore_partname=1"; - append-rootblock = "root=/dev/mmcblk0p"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - internet { - label = "white:internet"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - - power: power { - label = "white:power"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - wifi2g { - label = "amber:wifi2g"; - gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>; - }; - - /* wifi2g amber from the manual is missing */ - - wifi5g { - label = "amber:wifi5g"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - - /* wifi5g amber from the manual is missing */ - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio53", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio9", "gpio26", "gpio33", "gpio64"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - mdio0_pins: mdio0-pins { - clk { - pins = "gpio1"; - input-disable; - }; - }; - - rgmii2_pins: rgmii2-pins { - tx { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ; - input-disable; - }; - }; - - spi_pins: spi_pins { - cs { - pins = "gpio20"; - drive-strength = <12>; - }; - }; - - usb0_pwr_en_pins: usb0_pwr_en_pins { - mux { - pins = "gpio16", "gpio17"; - function = "gpio"; - drive-strength = <12>; - }; - - pwr { - pins = "gpio17"; - bias-pull-down; - output-high; - }; - - ovc { - pins = "gpio16"; - bias-pull-up; - }; - }; - - usb1_pwr_en_pins: usb1_pwr_en_pins { - mux { - pins = "gpio14", "gpio15"; - function = "gpio"; - drive-strength = <12>; - }; - - pwr { - pins = "gpio14"; - bias-pull-down; - output-high; - }; - - ovc { - pins = "gpio15"; - bias-pull-up; - }; - }; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; - - spi4: spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - m25p80@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <51200000>; - reg = <0>; - - partitions { - compatible = "qcom,smem-part"; - }; - }; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb0_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; - - pinctrl-0 = <&usb1_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&pcie0 { - status = "okay"; - reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; -}; - -&pcie1 { - status = "okay"; - reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; - max-link-speed = <1>; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0xaa545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - 0x00970 0x1e864443 /* QM_PORT0_CTRL0 */ - 0x00974 0x000001c6 /* QM_PORT0_CTRL1 */ - 0x00978 0x19008643 /* QM_PORT1_CTRL0 */ - 0x0097c 0x000001c6 /* QM_PORT1_CTRL1 */ - 0x00980 0x19008643 /* QM_PORT2_CTRL0 */ - 0x00984 0x000001c6 /* QM_PORT2_CTRL1 */ - 0x00988 0x19008643 /* QM_PORT3_CTRL0 */ - 0x0098c 0x000001c6 /* QM_PORT3_CTRL1 */ - 0x00990 0x19008643 /* QM_PORT4_CTRL0 */ - 0x00994 0x000001c6 /* QM_PORT4_CTRL1 */ - 0x00998 0x1e864443 /* QM_PORT5_CTRL0 */ - 0x0099c 0x000001c6 /* QM_PORT5_CTRL1 */ - 0x009a0 0x1e864443 /* QM_PORT6_CTRL0 */ - 0x009a4 0x000001c6 /* QM_PORT6_CTRL1 */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - qca,ar8327-initvals = < - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x0000c 0x80 /* PAD6_MODE */ - >; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - qcom,phy_mdio_addr = <4>; - qcom,poll_required = <0>; - qcom,rgmii_delay = <1>; - qcom,phy_mii_type = <0>; - qcom,emulation = <0>; - qcom,irq = <255>; - mdiobus = <&mdio0>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - qcom,phy_mdio_addr = <0>; /* none */ - qcom,poll_required = <0>; /* no polling */ - qcom,rgmii_delay = <0>; - qcom,phy_mii_type = <1>; - qcom,emulation = <0>; - qcom,irq = <258>; - mdiobus = <&mdio0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&amba { - sdcc1: sdcc@12400000 { - status = "okay"; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi deleted file mode 100644 index 2328c497ea1..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi +++ /dev/null @@ -1,466 +0,0 @@ -#include "qcom-ipq8065-smb208.dtsi" - -#include - -/ { - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - rsvd@5fe00000 { - reg = <0x5fe00000 0x200000>; - reusable; - }; - - ramoops@42100000 { - compatible = "ramoops"; - reg = <0x42100000 0x40000>; - record-size = <0x4000>; - console-size = <0x4000>; - ftrace-size = <0x4000>; - pmsg-size = <0x4000>; - }; - }; - - aliases { - label-mac-device = &gmac2; - - led-boot = &power_white; - led-failsafe = &power_amber; - led-running = &power_white; - led-upgrade = &power_amber; - - mdio-gpio0 = &mdio0; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds: leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - power_white: power_white { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - power_amber: power_amber { - label = "amber:power"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - wan_white { - label = "white:wan"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - wan_amber { - label = "amber:wan"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - wifi { - label = "white:wifi"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "white:wps"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", - "gpio22", "gpio23", "gpio24", - "gpio26", "gpio53", "gpio64"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - mdio0_pins: mdio0-pins { - clk { - pins = "gpio1"; - input-disable; - }; - }; - - rgmii2_pins: rgmii2-pins { - tx { - pins = "gpio27", "gpio28", "gpio29", - "gpio30", "gpio31", "gpio32"; - input-disable; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs { - pins = "gpio20"; - drive-strength = <10>; - bias-pull-up; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - spi6_pins: spi6_pins { - mux { - pins = "gpio55", "gpio56", "gpio58"; - function = "gsbi6"; - bias-pull-down; - }; - - mosi { - pins = "gpio55"; - drive-strength = <12>; - }; - - miso { - pins = "gpio56"; - drive-strength = <14>; - }; - - cs { - pins = "gpio57"; - drive-strength = <12>; - bias-pull-up; - }; - - clk { - pins = "gpio58"; - drive-strength = <12>; - }; - - reset { - pins = "gpio33"; - drive-strength = <10>; - bias-pull-down; - output-high; - }; - }; - - usb0_pwr_en_pins: usb0_pwr_en_pins { - mux { - pins = "gpio15"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; - - usb1_pwr_en_pins: usb1_pwr_en_pins { - mux { - pins = "gpio16", "gpio68"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot-partitions = <0x0 0x1180000>; - - partitions: partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "qcadata"; - reg = <0x0000000 0x0c80000>; - read-only; - }; - - partition@c80000 { - label = "APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - partition@1180000 { - label = "APPSBLENV"; - reg = <0x1180000 0x0080000>; - read-only; - }; - - art: partition@1200000 { - label = "art"; - reg = <0x1200000 0x0140000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - precal_art_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_art_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - partition@1340000 { - label = "artbak"; - reg = <0x1340000 0x0140000>; - read-only; - }; - - partition@1480000 { - label = "kernel"; - reg = <0x1480000 0x0400000>; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0xaa545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - 0x00970 0x1e864443 /* QM_PORT0_CTRL0 */ - 0x00974 0x000001c6 /* QM_PORT0_CTRL1 */ - 0x00978 0x19008643 /* QM_PORT1_CTRL0 */ - 0x0097c 0x000001c6 /* QM_PORT1_CTRL1 */ - 0x00980 0x19008643 /* QM_PORT2_CTRL0 */ - 0x00984 0x000001c6 /* QM_PORT2_CTRL1 */ - 0x00988 0x19008643 /* QM_PORT3_CTRL0 */ - 0x0098c 0x000001c6 /* QM_PORT3_CTRL1 */ - 0x00990 0x19008643 /* QM_PORT4_CTRL0 */ - 0x00994 0x000001c6 /* QM_PORT4_CTRL1 */ - 0x00998 0x1e864443 /* QM_PORT5_CTRL0 */ - 0x0099c 0x000001c6 /* QM_PORT5_CTRL1 */ - 0x009a0 0x1e864443 /* QM_PORT6_CTRL0 */ - 0x009a4 0x000001c6 /* QM_PORT6_CTRL1 */ - >; - qca,ar8327-vlans = < - 0x1 0x5e /* VLAN1 Ports 1/2/3/4/6 */ - 0x2 0x21 /* VLAN2 Ports 0/5 */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - qca,ar8327-initvals = < - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x0000c 0x80 /* PAD6_MODE */ - >; - }; -}; - -&gmac1 { - status = "okay"; - - phy-mode = "rgmii"; - qcom,id = <1>; - qcom,phy_mdio_addr = <4>; - qcom,poll_required = <0>; - qcom,rgmii_delay = <1>; - qcom,phy_mii_type = <0>; - qcom,emulation = <0>; - qcom,irq = <255>; - mdiobus = <&mdio0>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_art_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <2>; - qcom,phy_mdio_addr = <0>; /* none */ - qcom,poll_required = <0>; /* no polling */ - qcom,rgmii_delay = <0>; - qcom,phy_mii_type = <1>; - qcom,emulation = <0>; - qcom,irq = <258>; - mdiobus = <&mdio0>; - - nvmem-cells = <&macaddr_art_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&sata_phy { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb0_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; - - pinctrl-0 = <&usb1_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&pcie0 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi0: wifi@1,0 { - compatible = "pci168c,0046"; - reg = <0x00010000 0 0 0 0>; - }; - }; -}; - -&pcie1 { - status = "okay"; - - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi1: wifi@1,0 { - compatible = "pci168c,0046"; - reg = <0x00010000 0 0 0 0>; - }; - }; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-r7800.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-r7800.dts deleted file mode 100644 index bf7c963944b..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-r7800.dts +++ /dev/null @@ -1,48 +0,0 @@ -#include "qcom-ipq8065-nighthawk.dtsi" - -/ { - model = "Netgear Nighthawk X4S R7800"; - compatible = "netgear,r7800", "qcom,ipq8065", "qcom,ipq8064"; -}; - -&leds { - usb1 { - label = "white:usb1"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "white:usb2"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - esata { - label = "white:esata"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; -}; - -&partitions { - partition@1880000 { - label = "ubi"; - reg = <0x1880000 0x6080000>; - }; - - partition@7900000 { - label = "reserve"; - reg = <0x7900000 0x0700000>; - read-only; - }; -}; - -&wifi0 { - nvmem-cells = <&macaddr_art_6>, <&precal_art_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(1)>; -}; - -&wifi1 { - nvmem-cells = <&macaddr_art_6>, <&precal_art_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(2)>; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts deleted file mode 100644 index 8d9601b6324..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts +++ /dev/null @@ -1,418 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "qcom-ipq8065-smb208.dtsi" -#include - -/ { - model = "Askey RT4230W REV6"; - compatible = "askey,rt4230w-rev6", "qcom,ipq8065", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x3e000000>; - device_type = "memory"; - }; - - aliases { - led-boot = &ledctrl3; - led-failsafe = &ledctrl1; - led-running = &ledctrl2; - led-upgrade = &ledctrl3; - }; - - chosen { - bootargs = "rootfstype=squashfs noinitrd"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - ledctrl1: ledctrl1 { - label = "ledctrl1"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - ledctrl2: ledctrl2 { - label = "ledctrl2"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - ledctrl3: ledctrl3 { - label = "ledctrl3"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio54", "gpio68"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio22", "gpio23", "gpio24"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - rgmii2_pins: rgmii2-pins { - mux { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", - "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62"; - function = "rgmii2"; - drive-strength = <8>; - bias-disable; - }; - - tx { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32"; - input-disable; - }; - }; - - spi_pins: spi_pins { - cs { - pins = "gpio20"; - drive-strength = <12>; - }; - }; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "everspin,mr25h256"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <40000000>; - reg = <0>; - }; - }; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - qcom,boot-partitions = <0x0 0x1180000 0x1340000 0x10c0000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "0:SBL1"; - reg = <0x0000000 0x0040000>; - read-only; - }; - - partition@40000 { - label = "0:MIBIB"; - reg = <0x0040000 0x0140000>; - read-only; - }; - - partition@180000 { - label = "0:SBL2"; - reg = <0x0180000 0x0140000>; - read-only; - }; - - partition@2c0000 { - label = "0:SBL3"; - reg = <0x02c0000 0x0280000>; - read-only; - }; - - partition@540000 { - label = "0:DDRCONFIG"; - reg = <0x0540000 0x0120000>; - read-only; - }; - - partition@660000 { - label = "0:SSD"; - reg = <0x0660000 0x0120000>; - read-only; - }; - - partition@780000 { - label = "0:TZ"; - reg = <0x0780000 0x0280000>; - read-only; - }; - - partition@a00000 { - label = "0:RPM"; - reg = <0x0a00000 0x0280000>; - read-only; - }; - - partition@c80000 { - label = "0:APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - partition@1180000 { - label = "0:APPSBLENV"; - reg = <0x1180000 0x0080000>; - }; - - partition@1200000 { - label = "0:ART"; - reg = <0x1200000 0x0140000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_ART_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_ART_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - precal_ART_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_ART_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - partition@1340000 { - label = "0:BOOTCONFIG"; - reg = <0x1340000 0x0060000>; - read-only; - }; - - partition@13a0000 { - label = "0:SBL2_1"; - reg = <0x13a0000 0x0140000>; - read-only; - }; - - partition@14e0000 { - label = "0:SBL3_1"; - reg = <0x14e0000 0x0280000>; - read-only; - }; - - partition@1760000 { - label = "0:DDRCONFIG_1"; - reg = <0x1760000 0x0120000>; - read-only; - }; - - partition@1880000 { - label = "0:SSD_1"; - reg = <0x1880000 0x0120000>; - read-only; - }; - - partition@19a0000 { - label = "0:TZ_1"; - reg = <0x19a0000 0x0280000>; - read-only; - }; - - partition@1c20000 { - label = "0:RPM_1"; - reg = <0x1c20000 0x0280000>; - read-only; - }; - - partition@1ea0000 { - label = "0:BOOTCONFIG1"; - reg = <0x1ea0000 0x0060000>; - read-only; - }; - - partition@1f00000 { - label = "0:APPSBL_1"; - reg = <0x1f00000 0x0500000>; - read-only; - }; - - partition@2400000 { - label = "ubi"; - reg = <0x2400000 0x1a000000>; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0x0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0xaa545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - 0x00050 0xcf02cf02 /* LED_CTRL_0 */ - 0x00054 0xc832c832 /* LED_CTRL_1 */ - >; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <0>; - - nvmem-cells = <&macaddr_ART_0>; - nvmem-cell-names = "mac-address"; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <1>; - - nvmem-cells = <&macaddr_ART_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi0: wifi@1,0 { - compatible = "pci168c,0046"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&precal_ART_1000>; - nvmem-cell-names = "pre-calibration"; - }; - }; -}; - -&pcie1 { - status = "okay"; - reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi1: wifi@1,0 { - compatible = "pci168c,0046"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&precal_ART_5000>; - nvmem-cell-names = "pre-calibration"; - }; - }; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts deleted file mode 100644 index 7b236af253e..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts +++ /dev/null @@ -1,432 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "qcom-ipq8065-smb208.dtsi" -#include - -/ { - model = "Arris TR4400 v2"; - compatible = "arris,tr4400-v2", "qcom,ipq8065", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - aliases { - led-boot = &led_status_blue; - led-failsafe = &led_status_red; - led-running = &led_status_blue; - led-upgrade = &led_status_red; - }; - - chosen { - bootargs = "rootfstype=squashfs noinitrd"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - led_status_red: status_red { - label = "red:status"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - led_status_blue: status_blue { - label = "blue:status"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - rgmii2_pins: rgmii2-pins { - tx { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32"; - input-disable; - }; - }; - - spi_pins: spi_pins { - cs { - pins = "gpio20"; - drive-strength = <12>; - }; - }; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "everspin,mr25h256"; - spi-max-frequency = <40000000>; - reg = <0>; - }; - }; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x10c0000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "0:SBL1"; - reg = <0x0000000 0x0040000>; - read-only; - }; - partition@40000 { - label = "0:MIBIB"; - reg = <0x0040000 0x0140000>; - read-only; - }; - partition@180000 { - label = "0:SBL2"; - reg = <0x0180000 0x0140000>; - read-only; - }; - partition@2c0000 { - label = "0:SBL3"; - reg = <0x02c0000 0x0280000>; - read-only; - }; - partition@540000 { - label = "0:DDRCONFIG"; - reg = <0x0540000 0x0120000>; - read-only; - }; - partition@660000 { - label = "0:SSD"; - reg = <0x0660000 0x0120000>; - read-only; - }; - partition@780000 { - label = "0:TZ"; - reg = <0x0780000 0x0280000>; - read-only; - }; - partition@a00000 { - label = "0:RPM"; - reg = <0x0a00000 0x0280000>; - read-only; - }; - partition@c80000 { - label = "0:APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - partition@1180000 { - label = "0:APPSBLENV"; - reg = <0x1180000 0x0080000>; - }; - partition@1200000 { - label = "0:ART"; - reg = <0x1200000 0x0140000>; - read-only; - - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - precal_ART_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - precal_ART_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - stock_partition@1340000 { - label = "stock_rootfs"; - reg = <0x1340000 0x4000000>; - }; - partition@5340000 { - label = "0:BOOTCONFIG"; - reg = <0x5340000 0x0060000>; - read-only; - }; - partition@53a0000 { - label = "0:SBL2_1"; - reg = <0x53a0000 0x0140000>; - read-only; - }; - partition@54e0000 { - label = "0:SBL3_1"; - reg = <0x54e0000 0x0280000>; - read-only; - }; - partition@5760000 { - label = "0:DDRCONFIG_1"; - reg = <0x5760000 0x0120000>; - read-only; - }; - partition@5880000 { - label = "0:SSD_1"; - reg = <0x5880000 0x0120000>; - read-only; - }; - partition@59a0000 { - label = "0:TZ_1"; - reg = <0x59a0000 0x0280000>; - read-only; - }; - partition@5c20000 { - label = "0:RPM_1"; - reg = <0x5c20000 0x0280000>; - read-only; - }; - partition@5ea0000 { - label = "0:BOOTCONFIG1"; - reg = <0x5ea0000 0x0060000>; - read-only; - }; - partition@5f00000 { - label = "0:APPSBL_1"; - reg = <0x5f00000 0x0500000>; - read-only; - }; - stock_partition@6400000 { - label = "stock_rootfs_1"; - reg = <0x6400000 0x4000000>; - }; - stock_partition@a400000 { - label = "stock_fw_env"; - reg = <0xa400000 0x0100000>; - }; - stock_partition@a500000 { - label = "stock_config"; - reg = <0xa500000 0x0800000>; - }; - stock_partition@ad00000 { - label = "stock_PKI"; - reg = <0xad00000 0x0200000>; - }; - stock_partition@af00000 { - label = "stock_scfgmgr"; - reg = <0xaf00000 0x0100000>; - }; - - partition@6400000 { - label = "fw_env"; - reg = <0x6400000 0x0100000>; - - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_fw_env_0: macaddr@0 { - reg = <0x00 0x6>; - }; - macaddr_fw_env_6: macaddr@6 { - reg = <0x06 0x6>; - }; - macaddr_fw_env_c: macaddr@c { - reg = <0x0c 0x6>; - }; - macaddr_fw_env_12: macaddr@12 { - reg = <0x12 0x6>; - }; - macaddr_fw_env_18: macaddr@18 { - reg = <0x18 0x6>; - }; - }; - partition@6500000 { - label = "ubi"; - reg = <0x6500000 0x9b00000>; - }; - partition@1340000 { - label = "extra"; - reg = <0x1340000 0x4000000>; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - ethernet-phy@0 { - reg = <0x0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0xaa545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy7: ethernet-phy@7 { - reg = <7>; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <0>; - - nvmem-cells = <&macaddr_fw_env_18>; - nvmem-cell-names = "mac-address"; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <1>; - - nvmem-cells = <&macaddr_fw_env_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac3 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <3>; - phy-handle = <&phy7>; - - nvmem-cells = <&macaddr_fw_env_6>; - nvmem-cell-names = "mac-address"; -}; - -&adm_dma { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi0: wifi@1,0 { - compatible = "pci168c,0046"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&precal_ART_1000>, <&macaddr_fw_env_12>; - nvmem-cell-names = "pre-calibration", "mac-address"; - }; - }; -}; - -&pcie1 { - status = "okay"; - reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi1: wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&precal_ART_5000>, <&macaddr_fw_env_c>; - nvmem-cell-names = "pre-calibration", "mac-address"; - }; - }; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-xr450.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-xr450.dts deleted file mode 100644 index 4353aec7ac0..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-xr450.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8065-nighthawk.dtsi" - -/ { - model = "Netgear Nighthawk XR450"; - compatible = "netgear,xr450", "qcom,ipq8065", "qcom,ipq8064"; - -}; - -&leds { - usb1 { - label = "white:usb1"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "white:usb2"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; -}; - -&partitions { - partition@1880000 { - label = "ubi"; - reg = <0x1880000 0xce00000>; - }; - - partition@e680000 { - label = "reserve"; - reg = <0xe680000 0x0780000>; - read-only; - }; -}; - -&wifi0 { - nvmem-cells = <&macaddr_art_c>, <&precal_art_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; -}; - -&wifi1 { - nvmem-cells = <&macaddr_art_0>, <&precal_art_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; -}; - -&art { - macaddr_art_c: macaddr@c { - reg = <0xc 0x6>; - }; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-xr500.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-xr500.dts deleted file mode 100644 index f584735e155..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-xr500.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8065-nighthawk.dtsi" - -/ { - model = "Netgear Nighthawk XR500"; - compatible = "netgear,xr500", "qcom,ipq8065", "qcom,ipq8064"; - -}; - -&leds { - usb1 { - label = "white:usb1"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "white:usb2"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; -}; - -&partitions { - partition@1880000 { - label = "ubi"; - reg = <0x1880000 0xce00000>; - }; - - partition@e680000 { - label = "reserve"; - reg = <0xe680000 0x0780000>; - read-only; - }; -}; - -&wifi0 { - nvmem-cells = <&macaddr_art_c>, <&precal_art_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; -}; - -&wifi1 { - nvmem-cells = <&macaddr_art_0>, <&precal_art_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; -}; - -&art { - macaddr_art_c: macaddr@c { - reg = <0xc 0x6>; - }; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi deleted file mode 100644 index a8f43591f90..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT - -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -/ { - memory { - device_type = "memory"; - linux,usable-memory = <0x41500000 0x1ea00000>; - reg = <0x40000000 0x20000000>; - }; - - cpus { - idle-states { - CPU_SPC: spc { - status = "disabled"; - }; - }; - }; - - chosen { - bootargs-append = " console=ttyMSM0,115200n8 ubi.mtd=ubi ubi.mtd=art"; - }; -}; - -&qcom_pinmux { - mdio0_pins_active: mdio0_pins_active { - mux { - pins = "gpio0", "gpio1"; - function = "mdio"; - drive-strength = <2>; - bias-pull-down; - output-low; - }; - - clk { - pins = "gpio1"; - input-disable; - }; - }; - - phy_active: phy_active { - phy { - pins = "gpio6", "gpio7"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - output-high; - }; - }; - - uart1_pins: uart1_pins { - mux { - pins = "gpio51", "gpio52"; - function = "gsbi1"; - drive-strength = <4>; - bias-disable; - }; - }; -}; - -&gsbi1 { - status = "okay"; - qcom,mode = ; - - serial@12450000 { - status = "okay"; - - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; - }; -}; - -&pcie0 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - - bridge@0,0 { - reg = <0x0 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi0: wifi@1,0 { - compatible = "qcom,ath10k"; - status = "okay"; - reg = <0x10000 0 0 0 0>; - }; - }; -}; - -&pcie1 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - - bridge@0,0 { - reg = <0x0 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi1: wifi@1,0 { - compatible = "qcom,ath10k"; - status = "okay"; - reg = <0x10000 0 0 0 0>; - }; - }; -}; - -&pcie2 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - - bridge@0,0 { - reg = <0x0 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi2: wifi@1,0 { - compatible = "qcom,ath10k"; - status = "okay"; - reg = <0x10000 0 0 0 0>; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&nand { - status = "okay"; - - nand@0 { - compatible = "qcom,nandcs"; - - reg = <0>; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot-partitions = <0x0 0x2140000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "sbl1"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "mibib"; - reg = <0x40000 0x140000>; - read-only; - }; - - partition@180000 { - label = "sbl2"; - reg = <0x180000 0x140000>; - read-only; - }; - - partition@2c0000 { - label = "sbl3"; - reg = <0x2c0000 0x280000>; - read-only; - }; - - partition@540000 { - label = "ddrconfig"; - reg = <0x540000 0x120000>; - read-only; - }; - - partition@660000 { - label = "ssd"; - reg = <0x660000 0x120000>; - read-only; - }; - - partition@780000 { - label = "tz"; - reg = <0x780000 0x280000>; - read-only; - }; - - partition@a00000 { - label = "rpm"; - reg = <0xa00000 0x280000>; - read-only; - }; - - partition@1fc0000 { - label = "u-boot"; - reg = <0x1fc0000 0x180000>; - read-only; - }; - - partition@21c0000 { - label = "bootkernel1"; - reg = <0x21c0000 0xa80000>; - }; - - partition@2c40000 { - label = "bootkernel2"; - reg = <0x2c40000 0xa80000>; - }; - - partition@36c0000 { - label = "ubi"; - reg = <0x36c0000 0x46c0000>; - }; - - partition@7d80000 { - label = "art"; - reg = <0x7d80000 0x200000>; - read-only; - }; - }; - }; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts deleted file mode 100644 index 50c1d37c292..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts +++ /dev/null @@ -1,329 +0,0 @@ -#include "qcom-ipq8064-v2.0-smb208.dtsi" - -#include -#include - -/ { - model = "Edgecore ECW5410"; - compatible = "edgecore,ecw5410", "qcom,ipq8064"; - - reserved-memory { - nss@40000000 { - reg = <0x40000000 0x1000000>; - no-map; - }; - - smem: smem@41000000 { - reg = <0x41000000 0x200000>; - no-map; - }; - - wifi_dump@44000000 { - reg = <0x44000000 0x600000>; - no-map; - }; - }; - - cpus { - idle-states { - CPU_SPC: spc { - status = "disabled"; - }; - }; - }; - - aliases { - serial1 = &gsbi1_serial; - ethernet0 = &gmac2; - ethernet1 = &gmac3; - - led-boot = &led_power_green; - led-failsafe = &led_power_red; - led-running = &led_power_green; - led-upgrade = &led_power_green; - }; - - chosen { - bootargs-append = " console=ttyMSM0,115200n8 root=/dev/ubiblock0_1"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - led_power_green: power_green { - label = "green:power"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; - }; - - wlan2g_green { - label = "green:wlan2g"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>; - }; - - wlan2g_yellow { - label = "yellow:wlan2g"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; - }; - - wlan5g_green { - label = "green:wlan5g"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; - }; - - led_power_red: power_red { - label = "red:power"; - gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>; - }; - - wlan5g_yellow { - label = "yellow:wlan5g"; - gpios = <&qcom_pinmux 59 GPIO_ACTIVE_LOW>; - }; - }; -}; - - -&qcom_pinmux { - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19"; - function = "gsbi5"; - drive-strength = <10>; - bias-pull-down; - }; - - clk { - pins = "gpio21"; - function = "gsbi5"; - drive-strength = <12>; - bias-pull-down; - }; - - cs { - pins = "gpio20"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio16", "gpio23", "gpio24", "gpio26", - "gpio28", "gpio59"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio25"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - uart1_pins: uart1_pins { - mux { - pins = "gpio51", "gpio52", "gpio53", "gpio54"; - function = "gsbi1"; - drive-strength = <12>; - bias-none; - }; - }; -}; - -&gsbi1 { - qcom,mode = ; - status = "okay"; - - serial@12450000 { - status = "okay"; - - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; - }; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; - - spi4: spi@1a280000 { - status = "okay"; - spi-max-frequency = <50000000>; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - m25p80@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - partitions { - compatible = "qcom,smem-part"; - }; - }; - }; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "qcom,ath10k"; - status = "okay"; - reg = <0x00010000 0 0 0 0>; - qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L"; - }; - }; -}; - -&pcie2 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "qcom,ath10k"; - status = "okay"; - reg = <0x00010000 0 0 0 0>; - qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L"; - }; - }; -}; - -&nand { - status = "okay"; - - nand@0 { - compatible = "qcom,nandcs"; - - reg = <0>; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - rootfs1@0 { - label = "rootfs1"; - reg = <0x0000000 0x4000000>; - }; - - rootfs2@4000000 { - label = "rootfs2"; - reg = <0x4000000 0x4000000>; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&gmac2 { - status = "okay"; - - qcom,id = <2>; - mdiobus = <&mdio0>; - - phy-mode = "sgmii"; - phy-handle = <&phy1>; -}; - -&gmac3 { - status = "okay"; - - qcom,id = <3>; - mdiobus = <&mdio0>; - - phy-mode = "sgmii"; - phy-handle = <&phy0>; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr42.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr42.dts deleted file mode 100644 index cfbfafb1793..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr42.dts +++ /dev/null @@ -1,228 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT - -#include "qcom-ipq8068-cryptid-common.dtsi" - -#include - -/ { - model = "Meraki MR42"; - compatible = "meraki,mr42", "qcom,ipq8064"; - - aliases { - serial1 = &gsbi1_serial; - ethernet0 = &gmac3; - - led-boot = &led_active; - led-failsafe = &led_power; - led-running = &led_active; - led-upgrade = &led_active; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - led_power: power { - label = "orange:power"; - gpios = <&qcom_pinmux 31 GPIO_ACTIVE_HIGH>; - }; - - led_active: active { - label = "white:active"; - gpios = <&qcom_pinmux 32 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&gmac3 { - status = "okay"; - - qcom,id = <3>; - mdiobus = <&mdio0>; - - phy-mode = "sgmii"; - phy-handle = <&phy2>; - - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; -}; - -&gsbi2 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi2_i2c { - status = "okay"; - - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - ina2xx@40 { - compatible = "ina219"; - shunt-resistor = <40000>; - reg = <0x40>; - }; - - eeprom@56 { - compatible = "atmel,24c64"; - pagesize = <32>; - reg = <0x56>; - read-only; - #address-cells = <1>; - #size-cells = <1>; - - mac_address: mac-address@66 { - reg = <0x66 0x6>; - }; - }; -}; - -&gsbi6 { - qcom,mode = ; - status = "okay"; -}; - -&gsbi6_i2c { - status = "okay"; - - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - tlc591xx@40 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,tlc59108"; - reg = <0x40>; - - red@0 { - label = "red:user"; - reg = <0x0>; - }; - - green@1 { - label = "green:user"; - reg = <0x1>; - }; - - blue@2 { - label = "blue:user"; - reg = <0x2>; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins_active>, <&phy_active>; - pinctrl-names = "default"; - - phy2: ethernet-phy2 { - reg = <2>; - - reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - reset-assert-us = <24000>; - - eee-broken-100tx; - eee-broken-1000t; - }; -}; - -&qcom_pinmux { - i2c0_pins: i2c0_pins { - mux { - pins = "gpio24", "gpio25"; - function = "gsbi2"; - drive-strength = <2>; - bias-pull-up; - input; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio26"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - i2c1_pins: i2c1_pins { - mux { - pins = "gpio29", "gpio30"; - function = "gsbi6"; - drive-strength = <2>; - bias-pull-up; - input; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio31", "gpio32"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-low; - }; - }; -}; - -&wifi0 { - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; -}; - -&wifi1 { - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <2>; -}; - -&wifi2 { - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <3>; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr52.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr52.dts deleted file mode 100644 index f81e3ef690d..00000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr52.dts +++ /dev/null @@ -1,254 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT - -#include "qcom-ipq8068-cryptid-common.dtsi" - -#include - -/ { - model = "Meraki MR52"; - compatible = "meraki,mr52", "qcom,ipq8064"; - - aliases { - serial1 = &gsbi1_serial; - mdio-gpio0 = &mdio_gpio0; - ethernet0 = &gmac2; - ethernet1 = &gmac3; - - led-boot = &led_active; - led-failsafe = &led_power; - led-running = &led_active; - led-upgrade = &led_active; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - led_power: power { - label = "orange:power"; - gpios = <&qcom_pinmux 19 GPIO_ACTIVE_HIGH>; - }; - - lan2_green { - label = "green:lan2"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - lan1_green { - label = "green:lan1"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - - led_active: active { - label = "white:active"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; - }; - - lan2_orange { - label = "orange:lan2"; - gpios = <&qcom_pinmux 60 GPIO_ACTIVE_HIGH>; - }; - - lan1_orange { - label = "orange:lan1"; - gpios = <&qcom_pinmux 62 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&gmac2 { - status = "okay"; - - qcom,id = <2>; - mdiobus = <&mdio0>; - - phy-mode = "sgmii"; - phy-handle = <&phy0>; - - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; -}; - -&gmac3 { - status = "okay"; - - qcom,id = <3>; - mdiobus = <&mdio_gpio0>; - - phy-mode = "sgmii"; - phy-handle = <&phy4>; - - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; -}; - -&gsbi7 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi7_i2c { - status = "okay"; - - pinctrl-0 = <&i2c_pins>; - pinctrl-names = "default"; - - ina2xx@45 { - compatible = "ina219"; - shunt-resistor = <80000>; - reg = <0x45>; - }; - - tlc591xx@49 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,tlc59108"; - reg = <0x49>; - - red@0 { - label = "red:user"; - reg = <0x0>; - }; - - green@1 { - label = "green:user"; - reg = <0x1>; - }; - - blue@2 { - label = "blue:user"; - reg = <0x2>; - }; - }; - - eeprom@52 { - compatible = "atmel,24c64"; - pagesize = <32>; - reg = <0x52>; - read-only; - #address-cells = <1>; - #size-cells = <1>; - - mac_address: mac-address@66 { - reg = <0x66 0x6>; - }; - }; -}; - -&qcom_pinmux { - i2c_pins: i2c_pins { - mux { - pins = "gpio8", "gpio9"; - function = "gsbi7"; - drive-strength = <2>; - bias-pull-up; - input; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio19", "gpio26"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-low; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio25"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - input; - }; - }; -}; - -&soc { - mdio_gpio0: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - status = "okay"; - - pinctrl-0 = <&mdio0_pins_active>, <&phy_active>; - pinctrl-names = "default"; - - gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH - &qcom_pinmux 0 GPIO_ACTIVE_HIGH>; - - phy0: ethernet-phy0 { - reg = <0>; - reset-gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>; - reset-assert-us = <24000>; - }; - - phy4: ethernet-phy4 { - reg = <4>; - reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - reset-assert-us = <24000>; - }; - }; -}; - -&wifi0 { - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <4>; -}; - -&wifi1 { - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <3>; -}; - -&wifi2 { - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <2>; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; diff --git a/target/linux/ipq806x/patches-5.15/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch b/target/linux/ipq806x/patches-5.15/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch deleted file mode 100644 index 1860cef8003..00000000000 --- a/target/linux/ipq806x/patches-5.15/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch +++ /dev/null @@ -1,62 +0,0 @@ -From fa71139b55e114aa8c3c4823ff8ee7d49ee810d4 Mon Sep 17 00:00:00 2001 -From: Mathieu Olivari -Date: Wed, 29 Apr 2015 15:21:46 -0700 -Subject: [PATCH 60/69] HACK: arch: arm: force ZRELADDR on arch-qcom - -ARCH_QCOM is using the ARCH_MULTIPLATFORM option, as now recommended -on most ARM architectures. This automatically calculate ZRELADDR by -masking PHYS_OFFSET with 0xf8000000. - -However, on IPQ806x, the first ~20MB of RAM is reserved for the hardware -network accelerators, and the bootloader removes this section from the -layout passed from the ATAGS (when used). - -For newer bootloader, when DT is used, this is not a problem, we just -reserve this memory in the device tree. But if the bootloader doesn't -have DT support, then ATAGS have to be used. In this case, the ARM -decompressor will position the kernel in this low mem, which will not be -in the RAM section mapped by the bootloader, which means the kernel will -freeze in the middle of the boot process trying to map the memory. - -As a work around, this patch allows disabling AUTO_ZRELADDR when -ARCH_QCOM is selected. It makes the zImage usage possible on bootloaders -which don't support device-tree, which is the case on certain early -IPQ806x based designs. - -Signed-off-by: Mathieu Olivari ---- - arch/arm/Kconfig | 2 +- - arch/arm/Makefile | 2 ++ - arch/arm/mach-qcom/Makefile.boot | 1 + - 3 files changed, 4 insertions(+), 1 deletion(-) - create mode 100644 arch/arm/mach-qcom/Makefile.boot - ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -317,7 +317,7 @@ config ARCH_MULTIPLATFORM - select ARCH_SELECT_MEMORY_MODEL - select ARM_HAS_SG_CHAIN - select ARM_PATCH_PHYS_VIRT -- select AUTO_ZRELADDR -+ select AUTO_ZRELADDR if !ARCH_QCOM - select TIMER_OF - select COMMON_CLK - select GENERIC_IRQ_MULTI_HANDLER ---- a/arch/arm/Makefile -+++ b/arch/arm/Makefile -@@ -237,9 +237,11 @@ MACHINE := arch/arm/mach-$(word 1,$(mac - else - MACHINE := - endif -+ifeq ($(CONFIG_ARCH_QCOM),) - ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y) - MACHINE := - endif -+endif - - machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) - platdirs := $(patsubst %,arch/arm/plat-%/,$(sort $(plat-y))) ---- /dev/null -+++ b/arch/arm/mach-qcom/Makefile.boot -@@ -0,0 +1 @@ -+zreladdr-y+= 0x42208000 diff --git a/target/linux/ipq806x/patches-5.15/0067-generic-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/ipq806x/patches-5.15/0067-generic-Mangle-bootloader-s-kernel-arguments.patch deleted file mode 100644 index df5d4811a88..00000000000 --- a/target/linux/ipq806x/patches-5.15/0067-generic-Mangle-bootloader-s-kernel-arguments.patch +++ /dev/null @@ -1,280 +0,0 @@ -From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001 -From: Adrian Panella -Date: Thu, 9 Mar 2017 09:37:17 +0100 -Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments - -The command-line arguments provided by the boot loader will be -appended to a new device tree property: bootloader-args. -If there is a property "append-rootblock" in DT under /chosen -and a root= option in bootloaders command line it will be parsed -and added to DT bootargs with the form: XX. -Only command line ATAG will be processed, the rest of the ATAGs -sent by bootloader will be ignored. -This is usefull in dual boot systems, to get the current root partition -without afecting the rest of the system. - -Signed-off-by: Adrian Panella ---- - arch/arm/Kconfig | 11 +++++ - arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++- - init/main.c | 16 ++++++++ - 3 files changed, 98 insertions(+), 1 deletion(-) - ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1727,6 +1727,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN - The command-line arguments provided by the boot loader will be - appended to the the device tree bootargs property. - -+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE -+ bool "Append rootblock parsing bootloader's kernel arguments" -+ help -+ The command-line arguments provided by the boot loader will be -+ appended to a new device tree property: bootloader-args. -+ If there is a property "append-rootblock" in DT under /chosen -+ and a root= option in bootloaders command line it will be parsed -+ and added to DT bootargs with the form: XX. -+ Only command line ATAG will be processed, the rest of the ATAGs -+ sent by bootloader will be ignored. -+ - endchoice - - config CMDLINE ---- a/arch/arm/boot/compressed/atags_to_fdt.c -+++ b/arch/arm/boot/compressed/atags_to_fdt.c -@@ -5,6 +5,8 @@ - - #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) - #define do_extend_cmdline 1 -+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+#define do_extend_cmdline 1 - #else - #define do_extend_cmdline 0 - #endif -@@ -20,6 +22,7 @@ static int node_offset(void *fdt, const - return offset; - } - -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE - static int setprop(void *fdt, const char *node_path, const char *property, - void *val_array, int size) - { -@@ -28,6 +31,7 @@ static int setprop(void *fdt, const char - return offset; - return fdt_setprop(fdt, offset, property, val_array, size); - } -+#endif - - static int setprop_string(void *fdt, const char *node_path, - const char *property, const char *string) -@@ -38,6 +42,7 @@ static int setprop_string(void *fdt, con - return fdt_setprop_string(fdt, offset, property, string); - } - -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE - static int setprop_cell(void *fdt, const char *node_path, - const char *property, uint32_t val) - { -@@ -46,6 +51,7 @@ static int setprop_cell(void *fdt, const - return offset; - return fdt_setprop_cell(fdt, offset, property, val); - } -+#endif - - static const void *getprop(const void *fdt, const char *node_path, - const char *property, int *len) -@@ -58,6 +64,7 @@ static const void *getprop(const void *f - return fdt_getprop(fdt, offset, property, len); - } - -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE - static uint32_t get_cell_size(const void *fdt) - { - int len; -@@ -68,6 +75,81 @@ static uint32_t get_cell_size(const void - cell_size = fdt32_to_cpu(*size_len); - return cell_size; - } -+#endif -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+/** -+ * taken from arch/x86/boot/string.c -+ * local_strstr - Find the first substring in a %NUL terminated string -+ * @s1: The string to be searched -+ * @s2: The string to search for -+ */ -+static char *local_strstr(const char *s1, const char *s2) -+{ -+ size_t l1, l2; -+ -+ l2 = strlen(s2); -+ if (!l2) -+ return (char *)s1; -+ l1 = strlen(s1); -+ while (l1 >= l2) { -+ l1--; -+ if (!memcmp(s1, s2, l2)) -+ return (char *)s1; -+ s1++; -+ } -+ return NULL; -+} -+ -+static char *append_rootblock(char *dest, const char *str, int len, void *fdt) -+{ -+ char *ptr, *end, *tmp; -+ const char *root="root="; -+ const char *find_rootblock; -+ int i, l; -+ const char *rootblock; -+ -+ find_rootblock = getprop(fdt, "/chosen", "find-rootblock", &l); -+ if (!find_rootblock) -+ find_rootblock = root; -+ -+ //ARM doesn't have __HAVE_ARCH_STRSTR, so it was copied from x86 -+ ptr = local_strstr(str, find_rootblock); -+ -+ if(!ptr) -+ return dest; -+ -+ end = strchr(ptr, ' '); -+ end = end ? (end - 1) : (strchr(ptr, 0) - 1); -+ -+ // Some boards ubi.mtd=XX,ZZZZ, so let's check for '," too. -+ tmp = strchr(ptr, ','); -+ -+ if(tmp) -+ end = end < tmp ? end : tmp - 1; -+ -+ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX | ubi.mtd=XX,ZZZZ ) -+ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++); -+ ptr = end + 1; -+ -+ /* if append-rootblock property is set use it to append to command line */ -+ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l); -+ if(rootblock != NULL) { -+ if(*dest != ' ') { -+ *dest = ' '; -+ dest++; -+ len++; -+ } -+ if (len + l + i <= COMMAND_LINE_SIZE) { -+ memcpy(dest, rootblock, l); -+ dest += l - 1; -+ memcpy(dest, ptr, i); -+ dest += i; -+ } -+ } -+ return dest; -+} -+#endif - - static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline) - { -@@ -88,18 +170,28 @@ static void merge_fdt_bootargs(void *fdt - - /* and append the ATAG_CMDLINE */ - if (fdt_cmdline) { -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ //save original bootloader args -+ //and append ubi.mtd with root partition number to current cmdline -+ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline); -+ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt); -+ -+#else - len = strlen(fdt_cmdline); - if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) { - *ptr++ = ' '; - memcpy(ptr, fdt_cmdline, len); - ptr += len; - } -+#endif - } - *ptr = '\0'; - - setprop_string(fdt, "/chosen", "bootargs", cmdline); - } - -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE - static void hex_str(char *out, uint32_t value) - { - uint32_t digit; -@@ -117,6 +209,7 @@ static void hex_str(char *out, uint32_t - } - *out = '\0'; - } -+#endif - - /* - * Convert and fold provided ATAGs into the provided FDT. -@@ -131,9 +224,11 @@ int atags_to_fdt(void *atag_list, void * - struct tag *atag = atag_list; - /* In the case of 64 bits memory size, need to reserve 2 cells for - * address and size for each bank */ -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE - __be32 mem_reg_property[2 * 2 * NR_BANKS]; -- int memcount = 0; -- int ret, memsize; -+ int memsize, memcount = 0; -+#endif -+ int ret; - - /* make sure we've got an aligned pointer */ - if ((u32)atag_list & 0x3) -@@ -168,7 +263,9 @@ int atags_to_fdt(void *atag_list, void * - else - setprop_string(fdt, "/chosen", "bootargs", - atag->u.cmdline.cmdline); -- } else if (atag->hdr.tag == ATAG_MEM) { -+ } -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE -+ else if (atag->hdr.tag == ATAG_MEM) { - if (memcount >= sizeof(mem_reg_property)/4) - continue; - if (!atag->u.mem.size) -@@ -212,6 +309,10 @@ int atags_to_fdt(void *atag_list, void * - setprop(fdt, "/memory", "reg", mem_reg_property, - 4 * memcount * memsize); - } -+#else -+ -+ } -+#endif - - return fdt_pack(fdt); - } ---- a/init/main.c -+++ b/init/main.c -@@ -114,6 +114,10 @@ - - #include - -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+#include -+#endif -+ - static int kernel_init(void *); - - extern void init_IRQ(void); -@@ -993,6 +997,18 @@ asmlinkage __visible void __init __no_sa - pr_notice("Kernel command line: %s\n", saved_command_line); - /* parameters may set static keys */ - jump_label_init(); -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ //Show bootloader's original command line for reference -+ if(of_chosen) { -+ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL); -+ if(prop) -+ pr_notice("Bootloader command line (ignored): %s\n", prop); -+ else -+ pr_notice("Bootloader command line not present\n"); -+ } -+#endif -+ - parse_early_param(); - after_dashes = parse_args("Booting kernel", - static_command_line, __start___param, diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-04-linux-next-clk-qcom-gcc-ipq806x-fix-wrong-naming-for-gcc_pxo_pl.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-04-linux-next-clk-qcom-gcc-ipq806x-fix-wrong-naming-for-gcc_pxo_pl.patch deleted file mode 100644 index f3f3ea30da8..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-04-linux-next-clk-qcom-gcc-ipq806x-fix-wrong-naming-for-gcc_pxo_pl.patch +++ /dev/null @@ -1,109 +0,0 @@ -From e95e825333eda345d812b461301dad50021d5487 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:24 +0100 -Subject: [PATCH 04/14] clk: qcom: gcc-ipq806x: fix wrong naming for - gcc_pxo_pll8_pll0 - -Parent gcc_pxo_pll8_pll0 had the parent definition and parent map -swapped. Fix this naming error. - -Signed-off-by: Ansuel Smith -Reviewed-by: Bjorn Andersson -Reviewed-by: Stephen Boyd -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-5-ansuelsmth@gmail.com ---- - drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++---------- - 1 file changed, 10 insertions(+), 10 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -291,13 +291,13 @@ static const char * const gcc_pxo_pll3[] - "pll3", - }; - --static const struct parent_map gcc_pxo_pll8_pll0[] = { -+static const struct parent_map gcc_pxo_pll8_pll0_map[] = { - { P_PXO, 0 }, - { P_PLL8, 3 }, - { P_PLL0, 2 } - }; - --static const char * const gcc_pxo_pll8_pll0_map[] = { -+static const char * const gcc_pxo_pll8_pll0[] = { - "pxo", - "pll8_vote", - "pll0_vote", -@@ -1993,7 +1993,7 @@ static struct clk_rcg usb30_master_clk_s - }, - .s = { - .src_sel_shift = 0, -- .parent_map = gcc_pxo_pll8_pll0, -+ .parent_map = gcc_pxo_pll8_pll0_map, - }, - .freq_tbl = clk_tbl_usb30_master, - .clkr = { -@@ -2001,7 +2001,7 @@ static struct clk_rcg usb30_master_clk_s - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "usb30_master_ref_src", -- .parent_names = gcc_pxo_pll8_pll0_map, -+ .parent_names = gcc_pxo_pll8_pll0, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -2063,7 +2063,7 @@ static struct clk_rcg usb30_utmi_clk = { - }, - .s = { - .src_sel_shift = 0, -- .parent_map = gcc_pxo_pll8_pll0, -+ .parent_map = gcc_pxo_pll8_pll0_map, - }, - .freq_tbl = clk_tbl_usb30_utmi, - .clkr = { -@@ -2071,7 +2071,7 @@ static struct clk_rcg usb30_utmi_clk = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "usb30_utmi_clk", -- .parent_names = gcc_pxo_pll8_pll0_map, -+ .parent_names = gcc_pxo_pll8_pll0, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -2133,7 +2133,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s - }, - .s = { - .src_sel_shift = 0, -- .parent_map = gcc_pxo_pll8_pll0, -+ .parent_map = gcc_pxo_pll8_pll0_map, - }, - .freq_tbl = clk_tbl_usb, - .clkr = { -@@ -2141,7 +2141,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "usb_hs1_xcvr_src", -- .parent_names = gcc_pxo_pll8_pll0_map, -+ .parent_names = gcc_pxo_pll8_pll0, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -2197,7 +2197,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s - }, - .s = { - .src_sel_shift = 0, -- .parent_map = gcc_pxo_pll8_pll0, -+ .parent_map = gcc_pxo_pll8_pll0_map, - }, - .freq_tbl = clk_tbl_usb, - .clkr = { -@@ -2205,7 +2205,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "usb_fs1_xcvr_src", -- .parent_names = gcc_pxo_pll8_pll0_map, -+ .parent_names = gcc_pxo_pll8_pll0, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-05-linux-next-clk-qcom-gcc-ipq806x-convert-parent_names-to-parent_.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-05-linux-next-clk-qcom-gcc-ipq806x-convert-parent_names-to-parent_.patch deleted file mode 100644 index d99ac9992f3..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-05-linux-next-clk-qcom-gcc-ipq806x-convert-parent_names-to-parent_.patch +++ /dev/null @@ -1,921 +0,0 @@ -From cb02866f9a740fb9fb8ff19698a69290da4057e5 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:25 +0100 -Subject: [PATCH 05/14] clk: qcom: gcc-ipq806x: convert parent_names to - parent_data - -Convert parent_names to parent_data to modernize the driver. -Where possible use parent_hws directly. - -Signed-off-by: Ansuel Smith -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-6-ansuelsmth@gmail.com ---- - drivers/clk/qcom/gcc-ipq806x.c | 286 ++++++++++++++++++++------------- - 1 file changed, 173 insertions(+), 113 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -25,6 +25,10 @@ - #include "clk-hfpll.h" - #include "reset.h" - -+static const struct clk_parent_data gcc_pxo[] = { -+ { .fw_name = "pxo", .name = "pxo" }, -+}; -+ - static struct clk_pll pll0 = { - .l_reg = 0x30c4, - .m_reg = 0x30c8, -@@ -35,7 +39,7 @@ static struct clk_pll pll0 = { - .status_bit = 16, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pll0", -- .parent_names = (const char *[]){ "pxo" }, -+ .parent_data = gcc_pxo, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -@@ -46,7 +50,9 @@ static struct clk_regmap pll0_vote = { - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "pll0_vote", -- .parent_names = (const char *[]){ "pll0" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &pll0.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -@@ -62,7 +68,7 @@ static struct clk_pll pll3 = { - .status_bit = 16, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pll3", -- .parent_names = (const char *[]){ "pxo" }, -+ .parent_data = gcc_pxo, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -@@ -89,7 +95,7 @@ static struct clk_pll pll8 = { - .status_bit = 16, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pll8", -- .parent_names = (const char *[]){ "pxo" }, -+ .parent_data = gcc_pxo, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -@@ -100,7 +106,9 @@ static struct clk_regmap pll8_vote = { - .enable_mask = BIT(8), - .hw.init = &(struct clk_init_data){ - .name = "pll8_vote", -- .parent_names = (const char *[]){ "pll8" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &pll8.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -@@ -123,7 +131,7 @@ static struct hfpll_data hfpll0_data = { - static struct clk_hfpll hfpll0 = { - .d = &hfpll0_data, - .clkr.hw.init = &(struct clk_init_data){ -- .parent_names = (const char *[]){ "pxo" }, -+ .parent_data = gcc_pxo, - .num_parents = 1, - .name = "hfpll0", - .ops = &clk_ops_hfpll, -@@ -149,7 +157,7 @@ static struct hfpll_data hfpll1_data = { - static struct clk_hfpll hfpll1 = { - .d = &hfpll1_data, - .clkr.hw.init = &(struct clk_init_data){ -- .parent_names = (const char *[]){ "pxo" }, -+ .parent_data = gcc_pxo, - .num_parents = 1, - .name = "hfpll1", - .ops = &clk_ops_hfpll, -@@ -175,7 +183,7 @@ static struct hfpll_data hfpll_l2_data = - static struct clk_hfpll hfpll_l2 = { - .d = &hfpll_l2_data, - .clkr.hw.init = &(struct clk_init_data){ -- .parent_names = (const char *[]){ "pxo" }, -+ .parent_data = gcc_pxo, - .num_parents = 1, - .name = "hfpll_l2", - .ops = &clk_ops_hfpll, -@@ -194,7 +202,7 @@ static struct clk_pll pll14 = { - .status_bit = 16, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pll14", -- .parent_names = (const char *[]){ "pxo" }, -+ .parent_data = gcc_pxo, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -@@ -205,7 +213,9 @@ static struct clk_regmap pll14_vote = { - .enable_mask = BIT(14), - .hw.init = &(struct clk_init_data){ - .name = "pll14_vote", -- .parent_names = (const char *[]){ "pll14" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &pll14.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -@@ -238,7 +248,7 @@ static struct clk_pll pll18 = { - .freq_tbl = pll18_freq_tbl, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pll18", -- .parent_names = (const char *[]){ "pxo" }, -+ .parent_data = gcc_pxo, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -@@ -259,9 +269,9 @@ static const struct parent_map gcc_pxo_p - { P_PLL8, 3 } - }; - --static const char * const gcc_pxo_pll8[] = { -- "pxo", -- "pll8_vote", -+static const struct clk_parent_data gcc_pxo_pll8[] = { -+ { .fw_name = "pxo", .name = "pxo" }, -+ { .hw = &pll8_vote.hw }, - }; - - static const struct parent_map gcc_pxo_pll8_cxo_map[] = { -@@ -270,10 +280,10 @@ static const struct parent_map gcc_pxo_p - { P_CXO, 5 } - }; - --static const char * const gcc_pxo_pll8_cxo[] = { -- "pxo", -- "pll8_vote", -- "cxo", -+static const struct clk_parent_data gcc_pxo_pll8_cxo[] = { -+ { .fw_name = "pxo", .name = "pxo" }, -+ { .hw = &pll8_vote.hw }, -+ { .fw_name = "cxo", .name = "cxo" }, - }; - - static const struct parent_map gcc_pxo_pll3_map[] = { -@@ -286,9 +296,9 @@ static const struct parent_map gcc_pxo_p - { P_PLL3, 6 } - }; - --static const char * const gcc_pxo_pll3[] = { -- "pxo", -- "pll3", -+static const struct clk_parent_data gcc_pxo_pll3[] = { -+ { .fw_name = "pxo", .name = "pxo" }, -+ { .hw = &pll3.clkr.hw }, - }; - - static const struct parent_map gcc_pxo_pll8_pll0_map[] = { -@@ -297,10 +307,10 @@ static const struct parent_map gcc_pxo_p - { P_PLL0, 2 } - }; - --static const char * const gcc_pxo_pll8_pll0[] = { -- "pxo", -- "pll8_vote", -- "pll0_vote", -+static const struct clk_parent_data gcc_pxo_pll8_pll0[] = { -+ { .fw_name = "pxo", .name = "pxo" }, -+ { .hw = &pll8_vote.hw }, -+ { .hw = &pll0_vote.hw }, - }; - - static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = { -@@ -311,12 +321,12 @@ static const struct parent_map gcc_pxo_p - { P_PLL18, 1 } - }; - --static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = { -- "pxo", -- "pll8_vote", -- "pll0_vote", -- "pll14", -- "pll18", -+static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = { -+ { .fw_name = "pxo", .name = "pxo" }, -+ { .hw = &pll8_vote.hw }, -+ { .hw = &pll0_vote.hw }, -+ { .hw = &pll14.clkr.hw }, -+ { .hw = &pll18.clkr.hw }, - }; - - static struct freq_tbl clk_tbl_gsbi_uart[] = { -@@ -362,7 +372,7 @@ static struct clk_rcg gsbi1_uart_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi1_uart_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -378,8 +388,8 @@ static struct clk_branch gsbi1_uart_clk - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi1_uart_clk", -- .parent_names = (const char *[]){ -- "gsbi1_uart_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi1_uart_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -413,7 +423,7 @@ static struct clk_rcg gsbi2_uart_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi2_uart_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -429,8 +439,8 @@ static struct clk_branch gsbi2_uart_clk - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi2_uart_clk", -- .parent_names = (const char *[]){ -- "gsbi2_uart_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi2_uart_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -464,7 +474,7 @@ static struct clk_rcg gsbi4_uart_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi4_uart_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -480,8 +490,8 @@ static struct clk_branch gsbi4_uart_clk - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi4_uart_clk", -- .parent_names = (const char *[]){ -- "gsbi4_uart_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi4_uart_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -515,7 +525,7 @@ static struct clk_rcg gsbi5_uart_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi5_uart_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -531,8 +541,8 @@ static struct clk_branch gsbi5_uart_clk - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi5_uart_clk", -- .parent_names = (const char *[]){ -- "gsbi5_uart_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi5_uart_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -566,7 +576,7 @@ static struct clk_rcg gsbi6_uart_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi6_uart_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -582,8 +592,8 @@ static struct clk_branch gsbi6_uart_clk - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi6_uart_clk", -- .parent_names = (const char *[]){ -- "gsbi6_uart_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi6_uart_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -617,7 +627,7 @@ static struct clk_rcg gsbi7_uart_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi7_uart_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -633,8 +643,8 @@ static struct clk_branch gsbi7_uart_clk - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi7_uart_clk", -- .parent_names = (const char *[]){ -- "gsbi7_uart_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi7_uart_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -681,7 +691,7 @@ static struct clk_rcg gsbi1_qup_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi1_qup_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -697,7 +707,9 @@ static struct clk_branch gsbi1_qup_clk = - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi1_qup_clk", -- .parent_names = (const char *[]){ "gsbi1_qup_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi1_qup_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -730,7 +742,7 @@ static struct clk_rcg gsbi2_qup_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi2_qup_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -746,7 +758,9 @@ static struct clk_branch gsbi2_qup_clk = - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi2_qup_clk", -- .parent_names = (const char *[]){ "gsbi2_qup_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi2_qup_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -779,7 +793,7 @@ static struct clk_rcg gsbi4_qup_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi4_qup_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -795,7 +809,9 @@ static struct clk_branch gsbi4_qup_clk = - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi4_qup_clk", -- .parent_names = (const char *[]){ "gsbi4_qup_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi4_qup_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -828,7 +844,7 @@ static struct clk_rcg gsbi5_qup_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi5_qup_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -844,7 +860,9 @@ static struct clk_branch gsbi5_qup_clk = - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi5_qup_clk", -- .parent_names = (const char *[]){ "gsbi5_qup_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi5_qup_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -877,7 +895,7 @@ static struct clk_rcg gsbi6_qup_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi6_qup_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -893,7 +911,9 @@ static struct clk_branch gsbi6_qup_clk = - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi6_qup_clk", -- .parent_names = (const char *[]){ "gsbi6_qup_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi6_qup_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -926,7 +946,7 @@ static struct clk_rcg gsbi7_qup_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gsbi7_qup_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -942,7 +962,9 @@ static struct clk_branch gsbi7_qup_clk = - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gsbi7_qup_clk", -- .parent_names = (const char *[]){ "gsbi7_qup_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &gsbi7_qup_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1076,7 +1098,7 @@ static struct clk_rcg gp0_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gp0_src", -- .parent_names = gcc_pxo_pll8_cxo, -+ .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, -@@ -1092,7 +1114,9 @@ static struct clk_branch gp0_clk = { - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gp0_clk", -- .parent_names = (const char *[]){ "gp0_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &gp0_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1125,7 +1149,7 @@ static struct clk_rcg gp1_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gp1_src", -- .parent_names = gcc_pxo_pll8_cxo, -+ .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -1141,7 +1165,9 @@ static struct clk_branch gp1_clk = { - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gp1_clk", -- .parent_names = (const char *[]){ "gp1_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &gp1_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1174,7 +1200,7 @@ static struct clk_rcg gp2_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gp2_src", -- .parent_names = gcc_pxo_pll8_cxo, -+ .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -1190,7 +1216,9 @@ static struct clk_branch gp2_clk = { - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gp2_clk", -- .parent_names = (const char *[]){ "gp2_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &gp2_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1228,7 +1256,7 @@ static struct clk_rcg prng_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "prng_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - }, -@@ -1244,7 +1272,9 @@ static struct clk_branch prng_clk = { - .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ - .name = "prng_clk", -- .parent_names = (const char *[]){ "prng_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &prng_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - }, -@@ -1290,7 +1320,7 @@ static struct clk_rcg sdc1_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "sdc1_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - }, -@@ -1305,7 +1335,9 @@ static struct clk_branch sdc1_clk = { - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "sdc1_clk", -- .parent_names = (const char *[]){ "sdc1_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &sdc1_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1338,7 +1370,7 @@ static struct clk_rcg sdc3_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "sdc3_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - }, -@@ -1353,7 +1385,9 @@ static struct clk_branch sdc3_clk = { - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "sdc3_clk", -- .parent_names = (const char *[]){ "sdc3_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &sdc3_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1421,7 +1455,7 @@ static struct clk_rcg tsif_ref_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "tsif_ref_src", -- .parent_names = gcc_pxo_pll8, -+ .parent_data = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, - }, -@@ -1436,7 +1470,9 @@ static struct clk_branch tsif_ref_clk = - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "tsif_ref_clk", -- .parent_names = (const char *[]){ "tsif_ref_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &tsif_ref_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1583,7 +1619,7 @@ static struct clk_rcg pcie_ref_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "pcie_ref_src", -- .parent_names = gcc_pxo_pll3, -+ .parent_data = gcc_pxo_pll3, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -1599,7 +1635,9 @@ static struct clk_branch pcie_ref_src_cl - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "pcie_ref_src_clk", -- .parent_names = (const char *[]){ "pcie_ref_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &pcie_ref_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1675,7 +1713,7 @@ static struct clk_rcg pcie1_ref_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "pcie1_ref_src", -- .parent_names = gcc_pxo_pll3, -+ .parent_data = gcc_pxo_pll3, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -1691,7 +1729,9 @@ static struct clk_branch pcie1_ref_src_c - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "pcie1_ref_src_clk", -- .parent_names = (const char *[]){ "pcie1_ref_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &pcie1_ref_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1767,7 +1807,7 @@ static struct clk_rcg pcie2_ref_src = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "pcie2_ref_src", -- .parent_names = gcc_pxo_pll3, -+ .parent_data = gcc_pxo_pll3, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -1783,7 +1823,9 @@ static struct clk_branch pcie2_ref_src_c - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "pcie2_ref_src_clk", -- .parent_names = (const char *[]){ "pcie2_ref_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &pcie2_ref_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1864,7 +1906,7 @@ static struct clk_rcg sata_ref_src = { - .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ - .name = "sata_ref_src", -- .parent_names = gcc_pxo_pll3, -+ .parent_data = gcc_pxo_pll3, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -1880,7 +1922,9 @@ static struct clk_branch sata_rxoob_clk - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "sata_rxoob_clk", -- .parent_names = (const char *[]){ "sata_ref_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &sata_ref_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1896,7 +1940,9 @@ static struct clk_branch sata_pmalive_cl - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "sata_pmalive_clk", -- .parent_names = (const char *[]){ "sata_ref_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &sata_ref_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -1912,7 +1958,7 @@ static struct clk_branch sata_phy_ref_cl - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "sata_phy_ref_clk", -- .parent_names = (const char *[]){ "pxo" }, -+ .parent_data = gcc_pxo, - .num_parents = 1, - .ops = &clk_branch_ops, - }, -@@ -2001,7 +2047,7 @@ static struct clk_rcg usb30_master_clk_s - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "usb30_master_ref_src", -- .parent_names = gcc_pxo_pll8_pll0, -+ .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -2017,7 +2063,9 @@ static struct clk_branch usb30_0_branch_ - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "usb30_0_branch_clk", -- .parent_names = (const char *[]){ "usb30_master_ref_src", }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &usb30_master_clk_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -2033,7 +2081,9 @@ static struct clk_branch usb30_1_branch_ - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "usb30_1_branch_clk", -- .parent_names = (const char *[]){ "usb30_master_ref_src", }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &usb30_master_clk_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -2071,7 +2121,7 @@ static struct clk_rcg usb30_utmi_clk = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "usb30_utmi_clk", -- .parent_names = gcc_pxo_pll8_pll0, -+ .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -2087,7 +2137,9 @@ static struct clk_branch usb30_0_utmi_cl - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "usb30_0_utmi_clk_ctl", -- .parent_names = (const char *[]){ "usb30_utmi_clk", }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &usb30_utmi_clk.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -2103,7 +2155,9 @@ static struct clk_branch usb30_1_utmi_cl - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "usb30_1_utmi_clk_ctl", -- .parent_names = (const char *[]){ "usb30_utmi_clk", }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &usb30_utmi_clk.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -2141,7 +2195,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "usb_hs1_xcvr_src", -- .parent_names = gcc_pxo_pll8_pll0, -+ .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -2157,7 +2211,9 @@ static struct clk_branch usb_hs1_xcvr_cl - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "usb_hs1_xcvr_clk", -- .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &usb_hs1_xcvr_clk_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -2205,7 +2261,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "usb_fs1_xcvr_src", -- .parent_names = gcc_pxo_pll8_pll0, -+ .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, -@@ -2221,7 +2277,9 @@ static struct clk_branch usb_fs1_xcvr_cl - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "usb_fs1_xcvr_clk", -- .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &usb_fs1_xcvr_clk_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -2237,7 +2295,9 @@ static struct clk_branch usb_fs1_sys_clk - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "usb_fs1_sys_clk", -- .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &usb_fs1_xcvr_clk_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -2337,7 +2397,7 @@ static struct clk_dyn_rcg gmac_core1_src - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gmac_core1_src", -- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, -+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, - .ops = &clk_dyn_rcg_ops, - }, -@@ -2354,8 +2414,8 @@ static struct clk_branch gmac_core1_clk - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gmac_core1_clk", -- .parent_names = (const char *[]){ -- "gmac_core1_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &gmac_core1_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -2409,7 +2469,7 @@ static struct clk_dyn_rcg gmac_core2_src - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gmac_core2_src", -- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, -+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, - .ops = &clk_dyn_rcg_ops, - }, -@@ -2426,8 +2486,8 @@ static struct clk_branch gmac_core2_clk - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gmac_core2_clk", -- .parent_names = (const char *[]){ -- "gmac_core2_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &gmac_core2_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -2481,7 +2541,7 @@ static struct clk_dyn_rcg gmac_core3_src - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gmac_core3_src", -- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, -+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, - .ops = &clk_dyn_rcg_ops, - }, -@@ -2498,8 +2558,8 @@ static struct clk_branch gmac_core3_clk - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gmac_core3_clk", -- .parent_names = (const char *[]){ -- "gmac_core3_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &gmac_core3_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -2553,7 +2613,7 @@ static struct clk_dyn_rcg gmac_core4_src - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gmac_core4_src", -- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, -+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, - .ops = &clk_dyn_rcg_ops, - }, -@@ -2570,8 +2630,8 @@ static struct clk_branch gmac_core4_clk - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gmac_core4_clk", -- .parent_names = (const char *[]){ -- "gmac_core4_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &gmac_core4_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -2613,7 +2673,7 @@ static struct clk_dyn_rcg nss_tcm_src = - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "nss_tcm_src", -- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, -+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, - .ops = &clk_dyn_rcg_ops, - }, -@@ -2628,8 +2688,8 @@ static struct clk_branch nss_tcm_clk = { - .enable_mask = BIT(6) | BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "nss_tcm_clk", -- .parent_names = (const char *[]){ -- "nss_tcm_src", -+ .parent_hws = (const struct clk_hw*[]){ -+ &nss_tcm_src.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_branch_ops, -@@ -2691,7 +2751,7 @@ static struct clk_dyn_rcg ubi32_core1_sr - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "ubi32_core1_src_clk", -- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, -+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, - .ops = &clk_dyn_rcg_ops, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, -@@ -2744,7 +2804,7 @@ static struct clk_dyn_rcg ubi32_core2_sr - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "ubi32_core2_src_clk", -- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, -+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, - .ops = &clk_dyn_rcg_ops, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-06-linux-next-clk-qcom-gcc-ipq806x-use-ARRAY_SIZE-for-num_parents.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-06-linux-next-clk-qcom-gcc-ipq806x-use-ARRAY_SIZE-for-num_parents.patch deleted file mode 100644 index 6e6cec7db5c..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-06-linux-next-clk-qcom-gcc-ipq806x-use-ARRAY_SIZE-for-num_parents.patch +++ /dev/null @@ -1,325 +0,0 @@ -From a6aedd6532131bc81d47bbf63385dfcf2a0e9faa Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:26 +0100 -Subject: [PATCH 06/14] clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents - -Use ARRAY_SIZE for num_parents instead of hardcoding the value. - -Signed-off-by: Ansuel Smith -Reviewed-by: Bjorn Andersson -Reviewed-by: Stephen Boyd -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-7-ansuelsmth@gmail.com ---- - drivers/clk/qcom/gcc-ipq806x.c | 68 +++++++++++++++++----------------- - 1 file changed, 34 insertions(+), 34 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -373,7 +373,7 @@ static struct clk_rcg gsbi1_uart_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi1_uart_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -424,7 +424,7 @@ static struct clk_rcg gsbi2_uart_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi2_uart_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -475,7 +475,7 @@ static struct clk_rcg gsbi4_uart_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi4_uart_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -526,7 +526,7 @@ static struct clk_rcg gsbi5_uart_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi5_uart_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -577,7 +577,7 @@ static struct clk_rcg gsbi6_uart_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi6_uart_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -628,7 +628,7 @@ static struct clk_rcg gsbi7_uart_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi7_uart_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -692,7 +692,7 @@ static struct clk_rcg gsbi1_qup_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi1_qup_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -743,7 +743,7 @@ static struct clk_rcg gsbi2_qup_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi2_qup_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -794,7 +794,7 @@ static struct clk_rcg gsbi4_qup_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi4_qup_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -845,7 +845,7 @@ static struct clk_rcg gsbi5_qup_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi5_qup_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -896,7 +896,7 @@ static struct clk_rcg gsbi6_qup_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi6_qup_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -947,7 +947,7 @@ static struct clk_rcg gsbi7_qup_src = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi7_qup_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -1099,7 +1099,7 @@ static struct clk_rcg gp0_src = { - .hw.init = &(struct clk_init_data){ - .name = "gp0_src", - .parent_data = gcc_pxo_pll8_cxo, -- .num_parents = 3, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), - .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, - }, -@@ -1150,7 +1150,7 @@ static struct clk_rcg gp1_src = { - .hw.init = &(struct clk_init_data){ - .name = "gp1_src", - .parent_data = gcc_pxo_pll8_cxo, -- .num_parents = 3, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -1201,7 +1201,7 @@ static struct clk_rcg gp2_src = { - .hw.init = &(struct clk_init_data){ - .name = "gp2_src", - .parent_data = gcc_pxo_pll8_cxo, -- .num_parents = 3, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -1257,7 +1257,7 @@ static struct clk_rcg prng_src = { - .hw.init = &(struct clk_init_data){ - .name = "prng_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - }, - }, -@@ -1321,7 +1321,7 @@ static struct clk_rcg sdc1_src = { - .hw.init = &(struct clk_init_data){ - .name = "sdc1_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - }, - } -@@ -1371,7 +1371,7 @@ static struct clk_rcg sdc3_src = { - .hw.init = &(struct clk_init_data){ - .name = "sdc3_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - }, - } -@@ -1456,7 +1456,7 @@ static struct clk_rcg tsif_ref_src = { - .hw.init = &(struct clk_init_data){ - .name = "tsif_ref_src", - .parent_data = gcc_pxo_pll8, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, - }, - } -@@ -1620,7 +1620,7 @@ static struct clk_rcg pcie_ref_src = { - .hw.init = &(struct clk_init_data){ - .name = "pcie_ref_src", - .parent_data = gcc_pxo_pll3, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -1714,7 +1714,7 @@ static struct clk_rcg pcie1_ref_src = { - .hw.init = &(struct clk_init_data){ - .name = "pcie1_ref_src", - .parent_data = gcc_pxo_pll3, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -1808,7 +1808,7 @@ static struct clk_rcg pcie2_ref_src = { - .hw.init = &(struct clk_init_data){ - .name = "pcie2_ref_src", - .parent_data = gcc_pxo_pll3, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -1907,7 +1907,7 @@ static struct clk_rcg sata_ref_src = { - .hw.init = &(struct clk_init_data){ - .name = "sata_ref_src", - .parent_data = gcc_pxo_pll3, -- .num_parents = 2, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -2048,7 +2048,7 @@ static struct clk_rcg usb30_master_clk_s - .hw.init = &(struct clk_init_data){ - .name = "usb30_master_ref_src", - .parent_data = gcc_pxo_pll8_pll0, -- .num_parents = 3, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -2122,7 +2122,7 @@ static struct clk_rcg usb30_utmi_clk = { - .hw.init = &(struct clk_init_data){ - .name = "usb30_utmi_clk", - .parent_data = gcc_pxo_pll8_pll0, -- .num_parents = 3, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -2196,7 +2196,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s - .hw.init = &(struct clk_init_data){ - .name = "usb_hs1_xcvr_src", - .parent_data = gcc_pxo_pll8_pll0, -- .num_parents = 3, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -2262,7 +2262,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s - .hw.init = &(struct clk_init_data){ - .name = "usb_fs1_xcvr_src", - .parent_data = gcc_pxo_pll8_pll0, -- .num_parents = 3, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -2398,7 +2398,7 @@ static struct clk_dyn_rcg gmac_core1_src - .hw.init = &(struct clk_init_data){ - .name = "gmac_core1_src", - .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, -- .num_parents = 5, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), - .ops = &clk_dyn_rcg_ops, - }, - }, -@@ -2470,7 +2470,7 @@ static struct clk_dyn_rcg gmac_core2_src - .hw.init = &(struct clk_init_data){ - .name = "gmac_core2_src", - .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, -- .num_parents = 5, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), - .ops = &clk_dyn_rcg_ops, - }, - }, -@@ -2542,7 +2542,7 @@ static struct clk_dyn_rcg gmac_core3_src - .hw.init = &(struct clk_init_data){ - .name = "gmac_core3_src", - .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, -- .num_parents = 5, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), - .ops = &clk_dyn_rcg_ops, - }, - }, -@@ -2614,7 +2614,7 @@ static struct clk_dyn_rcg gmac_core4_src - .hw.init = &(struct clk_init_data){ - .name = "gmac_core4_src", - .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, -- .num_parents = 5, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), - .ops = &clk_dyn_rcg_ops, - }, - }, -@@ -2674,7 +2674,7 @@ static struct clk_dyn_rcg nss_tcm_src = - .hw.init = &(struct clk_init_data){ - .name = "nss_tcm_src", - .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, -- .num_parents = 5, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), - .ops = &clk_dyn_rcg_ops, - }, - }, -@@ -2752,7 +2752,7 @@ static struct clk_dyn_rcg ubi32_core1_sr - .hw.init = &(struct clk_init_data){ - .name = "ubi32_core1_src_clk", - .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, -- .num_parents = 5, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), - .ops = &clk_dyn_rcg_ops, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - }, -@@ -2805,7 +2805,7 @@ static struct clk_dyn_rcg ubi32_core2_sr - .hw.init = &(struct clk_init_data){ - .name = "ubi32_core2_src_clk", - .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, -- .num_parents = 5, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), - .ops = &clk_dyn_rcg_ops, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - }, diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-07-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-nss-cores.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-07-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-nss-cores.patch deleted file mode 100644 index b0f09ec34dc..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-07-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-nss-cores.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 512ea2edfe15ffa2cd839b3a31d768145f2edc20 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:27 +0100 -Subject: [PATCH 07/14] clk: qcom: gcc-ipq806x: add additional freq nss cores - -Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be -clocked to 800MHz. Add these missing freq to the gcc driver. -Set the freq_tbl for the ubi32_cores to the correct values based on the -machine compatible. - -Signed-off-by: Ansuel Smith -Reviewed-by: Stephen Boyd -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-8-ansuelsmth@gmail.com ---- - drivers/clk/qcom/gcc-ipq806x.c | 24 +++++++++++++++++++++--- - 1 file changed, 21 insertions(+), 3 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -232,7 +232,9 @@ static struct clk_regmap pll14_vote = { - - static struct pll_freq_tbl pll18_freq_tbl[] = { - NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625), -+ NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625), - NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625), -+ NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625), - }; - - static struct clk_pll pll18 = { -@@ -2698,7 +2700,7 @@ static struct clk_branch nss_tcm_clk = { - }, - }; - --static const struct freq_tbl clk_tbl_nss[] = { -+static const struct freq_tbl clk_tbl_nss_ipq8064[] = { - { 110000000, P_PLL18, 1, 1, 5 }, - { 275000000, P_PLL18, 2, 0, 0 }, - { 550000000, P_PLL18, 1, 0, 0 }, -@@ -2706,6 +2708,14 @@ static const struct freq_tbl clk_tbl_nss - { } - }; - -+static const struct freq_tbl clk_tbl_nss_ipq8065[] = { -+ { 110000000, P_PLL18, 1, 1, 5 }, -+ { 275000000, P_PLL18, 2, 0, 0 }, -+ { 600000000, P_PLL18, 1, 0, 0 }, -+ { 800000000, P_PLL18, 1, 0, 0 }, -+ { } -+}; -+ - static struct clk_dyn_rcg ubi32_core1_src_clk = { - .ns_reg[0] = 0x3d2c, - .ns_reg[1] = 0x3d30, -@@ -2745,7 +2755,7 @@ static struct clk_dyn_rcg ubi32_core1_sr - .pre_div_width = 2, - }, - .mux_sel_bit = 0, -- .freq_tbl = clk_tbl_nss, -+ /* nss freq table is selected based on the SoC compatible */ - .clkr = { - .enable_reg = 0x3d20, - .enable_mask = BIT(1), -@@ -2798,7 +2808,7 @@ static struct clk_dyn_rcg ubi32_core2_sr - .pre_div_width = 2, - }, - .mux_sel_bit = 0, -- .freq_tbl = clk_tbl_nss, -+ /* nss freq table is selected based on the SoC compatible */ - .clkr = { - .enable_reg = 0x3d40, - .enable_mask = BIT(1), -@@ -3131,6 +3141,14 @@ static int gcc_ipq806x_probe(struct plat - if (ret) - return ret; - -+ if (of_machine_is_compatible("qcom,ipq8065")) { -+ ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065; -+ ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065; -+ } else { -+ ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8064; -+ ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8064; -+ } -+ - ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc); - if (ret) - return ret; diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-08-linux-next-clk-qcom-gcc-ipq806x-add-unusued-flag-for-critical-c.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-08-linux-next-clk-qcom-gcc-ipq806x-add-unusued-flag-for-critical-c.patch deleted file mode 100644 index 3d55cb421a1..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-08-linux-next-clk-qcom-gcc-ipq806x-add-unusued-flag-for-critical-c.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 28aa450d38e521de45be951df052d2c49a17fae2 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:28 +0100 -Subject: [PATCH 08/14] clk: qcom: gcc-ipq806x: add unusued flag for critical - clock - -Some clocks are used by other devices present on the SoC. For example -the gsbi4_h_clk is used by RPM and is if disabled cause the RPM to -reject any regulator change command. These clock should never be -disabled. - -Signed-off-by: Ansuel Smith -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-9-ansuelsmth@gmail.com ---- - drivers/clk/qcom/gcc-ipq806x.c | 9 +++++---- - 1 file changed, 5 insertions(+), 4 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -798,7 +798,7 @@ static struct clk_rcg gsbi4_qup_src = { - .parent_data = gcc_pxo_pll8, - .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, -- .flags = CLK_SET_PARENT_GATE, -+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -816,7 +816,7 @@ static struct clk_branch gsbi4_qup_clk = - }, - .num_parents = 1, - .ops = &clk_branch_ops, -- .flags = CLK_SET_RATE_PARENT, -+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -900,7 +900,7 @@ static struct clk_rcg gsbi6_qup_src = { - .parent_data = gcc_pxo_pll8, - .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, -- .flags = CLK_SET_PARENT_GATE, -+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -969,7 +969,7 @@ static struct clk_branch gsbi7_qup_clk = - }, - .num_parents = 1, - .ops = &clk_branch_ops, -- .flags = CLK_SET_RATE_PARENT, -+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -1015,6 +1015,7 @@ static struct clk_branch gsbi4_h_clk = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi4_h_clk", - .ops = &clk_branch_ops, -+ .flags = CLK_IGNORE_UNUSED, - }, - }, - }; diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-09-linux-next-clk-qcom-clk-rcg-add-clk_rcg_floor_ops-ops.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-09-linux-next-clk-qcom-clk-rcg-add-clk_rcg_floor_ops-ops.patch deleted file mode 100644 index 22bd040d1bf..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-09-linux-next-clk-qcom-clk-rcg-add-clk_rcg_floor_ops-ops.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 33958ad3fc02aeb06a4634e59689a9559d968e1f Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:29 +0100 -Subject: [PATCH 09/14] clk: qcom: clk-rcg: add clk_rcg_floor_ops ops - -Add clk_rcg_floor_ops for clock that can't provide a stable freq and -require to use a floor freq to provide the requested frequency. - -Signed-off-by: Ansuel Smith -Reviewed-by: Bjorn Andersson -Reviewed-by: Stephen Boyd -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-10-ansuelsmth@gmail.com ---- - drivers/clk/qcom/clk-rcg.c | 24 ++++++++++++++++++++++++ - drivers/clk/qcom/clk-rcg.h | 1 + - 2 files changed, 25 insertions(+) - ---- a/drivers/clk/qcom/clk-rcg.c -+++ b/drivers/clk/qcom/clk-rcg.c -@@ -526,6 +526,19 @@ static int clk_rcg_set_rate(struct clk_h - return __clk_rcg_set_rate(rcg, f); - } - -+static int clk_rcg_set_floor_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct clk_rcg *rcg = to_clk_rcg(hw); -+ const struct freq_tbl *f; -+ -+ f = qcom_find_freq_floor(rcg->freq_tbl, rate); -+ if (!f) -+ return -EINVAL; -+ -+ return __clk_rcg_set_rate(rcg, f); -+} -+ - static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) - { -@@ -816,6 +829,17 @@ const struct clk_ops clk_rcg_ops = { - }; - EXPORT_SYMBOL_GPL(clk_rcg_ops); - -+const struct clk_ops clk_rcg_floor_ops = { -+ .enable = clk_enable_regmap, -+ .disable = clk_disable_regmap, -+ .get_parent = clk_rcg_get_parent, -+ .set_parent = clk_rcg_set_parent, -+ .recalc_rate = clk_rcg_recalc_rate, -+ .determine_rate = clk_rcg_determine_rate, -+ .set_rate = clk_rcg_set_floor_rate, -+}; -+EXPORT_SYMBOL_GPL(clk_rcg_floor_ops); -+ - const struct clk_ops clk_rcg_bypass_ops = { - .enable = clk_enable_regmap, - .disable = clk_disable_regmap, ---- a/drivers/clk/qcom/clk-rcg.h -+++ b/drivers/clk/qcom/clk-rcg.h -@@ -86,6 +86,7 @@ struct clk_rcg { - }; - - extern const struct clk_ops clk_rcg_ops; -+extern const struct clk_ops clk_rcg_floor_ops; - extern const struct clk_ops clk_rcg_bypass_ops; - extern const struct clk_ops clk_rcg_bypass2_ops; - extern const struct clk_ops clk_rcg_pixel_ops; diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-10-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-for-sdc-tab.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-10-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-for-sdc-tab.patch deleted file mode 100644 index 3bb5e57c87a..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-10-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-for-sdc-tab.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 7e726f34c782b2ca28a29ca9870e34e4319d65bc Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:30 +0100 -Subject: [PATCH 10/14] clk: qcom: gcc-ipq806x: add additional freq for sdc - table - -Add additional freq supported for the sdc table. The ops are changed to -the floor_ops to handle a freq request of 52kHz where we need to provide -a freq of 51.2kHz instead for stability reason. - -Signed-off-by: Ansuel Smith -Reviewed-by: Stephen Boyd -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-11-ansuelsmth@gmail.com ---- - drivers/clk/qcom/gcc-ipq806x.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -1292,6 +1292,7 @@ static const struct freq_tbl clk_tbl_sdc - { 20210000, P_PLL8, 1, 1, 19 }, - { 24000000, P_PLL8, 4, 1, 4 }, - { 48000000, P_PLL8, 4, 1, 2 }, -+ { 51200000, P_PLL8, 1, 2, 15 }, - { 64000000, P_PLL8, 3, 1, 2 }, - { 96000000, P_PLL8, 4, 0, 0 }, - { 192000000, P_PLL8, 2, 0, 0 }, -@@ -1325,7 +1326,7 @@ static struct clk_rcg sdc1_src = { - .name = "sdc1_src", - .parent_data = gcc_pxo_pll8, - .num_parents = ARRAY_SIZE(gcc_pxo_pll8), -- .ops = &clk_rcg_ops, -+ .ops = &clk_rcg_floor_ops, - }, - } - }; diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-11-linux-next-dt-bindings-clock-add-ipq8064-ce5-clk-define.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-11-linux-next-dt-bindings-clock-add-ipq8064-ce5-clk-define.patch deleted file mode 100644 index 858c6f78a52..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-11-linux-next-dt-bindings-clock-add-ipq8064-ce5-clk-define.patch +++ /dev/null @@ -1,39 +0,0 @@ -From b565d66403e3df303a058c0d8d00d0fc6aeb2ddc Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:31 +0100 -Subject: [PATCH 11/14] dt-bindings: clock: add ipq8064 ce5 clk define - -Add ipq8064 ce5 clk define needed for CryptoEngine in gcc driver. -Define CE5_SRC is not used so it's OK to change and we align it to -the QSDK naming. - -Signed-off-by: Ansuel Smith -Acked-by: Rob Herring -Reviewed-by: Stephen Boyd -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-12-ansuelsmth@gmail.com ---- - include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - ---- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h -+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h -@@ -240,7 +240,7 @@ - #define PLL14 232 - #define PLL14_VOTE 233 - #define PLL18 234 --#define CE5_SRC 235 -+#define CE5_A_CLK 235 - #define CE5_H_CLK 236 - #define CE5_CORE_CLK 237 - #define CE3_SLEEP_CLK 238 -@@ -283,5 +283,8 @@ - #define EBI2_AON_CLK 281 - #define NSSTCM_CLK_SRC 282 - #define NSSTCM_CLK 283 -+#define CE5_A_CLK_SRC 285 -+#define CE5_H_CLK_SRC 286 -+#define CE5_CORE_CLK_SRC 287 - - #endif diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-12-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-clocks.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-12-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-clocks.patch deleted file mode 100644 index 3ded707bf0c..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-12-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-clocks.patch +++ /dev/null @@ -1,304 +0,0 @@ -From b293510f3961b90dcab59965f57779be93ceda7c Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:32 +0100 -Subject: [PATCH 12/14] clk: qcom: gcc-ipq806x: add CryptoEngine clocks - -Add missing CryptoEngine clocks and pll11 required clock. - -Signed-off-by: Ansuel Smith -Reviewed-by: Stephen Boyd -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-13-ansuelsmth@gmail.com ---- - drivers/clk/qcom/gcc-ipq806x.c | 244 +++++++++++++++++++++++++++++++++ - 1 file changed, 244 insertions(+) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -256,6 +256,24 @@ static struct clk_pll pll18 = { - }, - }; - -+static struct clk_pll pll11 = { -+ .l_reg = 0x3184, -+ .m_reg = 0x3188, -+ .n_reg = 0x318c, -+ .config_reg = 0x3194, -+ .mode_reg = 0x3180, -+ .status_reg = 0x3198, -+ .status_bit = 16, -+ .clkr.hw.init = &(struct clk_init_data){ -+ .name = "pll11", -+ .parent_data = &(const struct clk_parent_data){ -+ .fw_name = "pxo", -+ }, -+ .num_parents = 1, -+ .ops = &clk_pll_ops, -+ }, -+}; -+ - enum { - P_PXO, - P_PLL8, -@@ -264,6 +282,7 @@ enum { - P_CXO, - P_PLL14, - P_PLL18, -+ P_PLL11, - }; - - static const struct parent_map gcc_pxo_pll8_map[] = { -@@ -331,6 +350,44 @@ static const struct clk_parent_data gcc_ - { .hw = &pll18.clkr.hw }, - }; - -+static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = { -+ { P_PXO, 0 }, -+ { P_PLL8, 4 }, -+ { P_PLL0, 2 }, -+ { P_PLL14, 5 }, -+ { P_PLL18, 1 }, -+ { P_PLL11, 3 }, -+}; -+ -+static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = { -+ { .fw_name = "pxo" }, -+ { .hw = &pll8_vote.hw }, -+ { .hw = &pll0_vote.hw }, -+ { .hw = &pll14.clkr.hw }, -+ { .hw = &pll18.clkr.hw }, -+ { .hw = &pll11.clkr.hw }, -+ -+}; -+ -+static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = { -+ { P_PXO, 0 }, -+ { P_PLL3, 6 }, -+ { P_PLL0, 2 }, -+ { P_PLL14, 5 }, -+ { P_PLL18, 1 }, -+ { P_PLL11, 3 }, -+}; -+ -+static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = { -+ { .fw_name = "pxo" }, -+ { .hw = &pll3.clkr.hw }, -+ { .hw = &pll0_vote.hw }, -+ { .hw = &pll14.clkr.hw }, -+ { .hw = &pll18.clkr.hw }, -+ { .hw = &pll11.clkr.hw }, -+ -+}; -+ - static struct freq_tbl clk_tbl_gsbi_uart[] = { - { 1843200, P_PLL8, 2, 6, 625 }, - { 3686400, P_PLL8, 2, 12, 625 }, -@@ -2824,6 +2881,186 @@ static struct clk_dyn_rcg ubi32_core2_sr - }, - }; - -+static const struct freq_tbl clk_tbl_ce5_core[] = { -+ { 150000000, P_PLL3, 8, 1, 1 }, -+ { 213200000, P_PLL11, 5, 1, 1 }, -+ { } -+}; -+ -+static struct clk_dyn_rcg ce5_core_src = { -+ .ns_reg[0] = 0x36C4, -+ .ns_reg[1] = 0x36C8, -+ .bank_reg = 0x36C0, -+ .s[0] = { -+ .src_sel_shift = 0, -+ .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map, -+ }, -+ .s[1] = { -+ .src_sel_shift = 0, -+ .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map, -+ }, -+ .p[0] = { -+ .pre_div_shift = 3, -+ .pre_div_width = 4, -+ }, -+ .p[1] = { -+ .pre_div_shift = 3, -+ .pre_div_width = 4, -+ }, -+ .mux_sel_bit = 0, -+ .freq_tbl = clk_tbl_ce5_core, -+ .clkr = { -+ .enable_reg = 0x36C0, -+ .enable_mask = BIT(1), -+ .hw.init = &(struct clk_init_data){ -+ .name = "ce5_core_src", -+ .parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3_pll0_pll14_pll18_pll11), -+ .ops = &clk_dyn_rcg_ops, -+ }, -+ }, -+}; -+ -+static struct clk_branch ce5_core_clk = { -+ .halt_reg = 0x2FDC, -+ .halt_bit = 5, -+ .hwcg_reg = 0x36CC, -+ .hwcg_bit = 6, -+ .clkr = { -+ .enable_reg = 0x36CC, -+ .enable_mask = BIT(4), -+ .hw.init = &(struct clk_init_data){ -+ .name = "ce5_core_clk", -+ .parent_hws = (const struct clk_hw*[]){ -+ &ce5_core_src.clkr.hw, -+ }, -+ .num_parents = 1, -+ .ops = &clk_branch_ops, -+ .flags = CLK_SET_RATE_PARENT, -+ }, -+ }, -+}; -+ -+static const struct freq_tbl clk_tbl_ce5_a_clk[] = { -+ { 160000000, P_PLL0, 5, 1, 1 }, -+ { 213200000, P_PLL11, 5, 1, 1 }, -+ { } -+}; -+ -+static struct clk_dyn_rcg ce5_a_clk_src = { -+ .ns_reg[0] = 0x3d84, -+ .ns_reg[1] = 0x3d88, -+ .bank_reg = 0x3d80, -+ .s[0] = { -+ .src_sel_shift = 0, -+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, -+ }, -+ .s[1] = { -+ .src_sel_shift = 0, -+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, -+ }, -+ .p[0] = { -+ .pre_div_shift = 3, -+ .pre_div_width = 4, -+ }, -+ .p[1] = { -+ .pre_div_shift = 3, -+ .pre_div_width = 4, -+ }, -+ .mux_sel_bit = 0, -+ .freq_tbl = clk_tbl_ce5_a_clk, -+ .clkr = { -+ .enable_reg = 0x3d80, -+ .enable_mask = BIT(1), -+ .hw.init = &(struct clk_init_data){ -+ .name = "ce5_a_clk_src", -+ .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11), -+ .ops = &clk_dyn_rcg_ops, -+ }, -+ }, -+}; -+ -+static struct clk_branch ce5_a_clk = { -+ .halt_reg = 0x3c20, -+ .halt_bit = 12, -+ .hwcg_reg = 0x3d8c, -+ .hwcg_bit = 6, -+ .clkr = { -+ .enable_reg = 0x3d8c, -+ .enable_mask = BIT(4), -+ .hw.init = &(struct clk_init_data){ -+ .name = "ce5_a_clk", -+ .parent_hws = (const struct clk_hw*[]){ -+ &ce5_a_clk_src.clkr.hw, -+ }, -+ .num_parents = 1, -+ .ops = &clk_branch_ops, -+ .flags = CLK_SET_RATE_PARENT, -+ }, -+ }, -+}; -+ -+static const struct freq_tbl clk_tbl_ce5_h_clk[] = { -+ { 160000000, P_PLL0, 5, 1, 1 }, -+ { 213200000, P_PLL11, 5, 1, 1 }, -+ { } -+}; -+ -+static struct clk_dyn_rcg ce5_h_clk_src = { -+ .ns_reg[0] = 0x3c64, -+ .ns_reg[1] = 0x3c68, -+ .bank_reg = 0x3c60, -+ .s[0] = { -+ .src_sel_shift = 0, -+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, -+ }, -+ .s[1] = { -+ .src_sel_shift = 0, -+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, -+ }, -+ .p[0] = { -+ .pre_div_shift = 3, -+ .pre_div_width = 4, -+ }, -+ .p[1] = { -+ .pre_div_shift = 3, -+ .pre_div_width = 4, -+ }, -+ .mux_sel_bit = 0, -+ .freq_tbl = clk_tbl_ce5_h_clk, -+ .clkr = { -+ .enable_reg = 0x3c60, -+ .enable_mask = BIT(1), -+ .hw.init = &(struct clk_init_data){ -+ .name = "ce5_h_clk_src", -+ .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11, -+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11), -+ .ops = &clk_dyn_rcg_ops, -+ }, -+ }, -+}; -+ -+static struct clk_branch ce5_h_clk = { -+ .halt_reg = 0x3c20, -+ .halt_bit = 11, -+ .hwcg_reg = 0x3c6c, -+ .hwcg_bit = 6, -+ .clkr = { -+ .enable_reg = 0x3c6c, -+ .enable_mask = BIT(4), -+ .hw.init = &(struct clk_init_data){ -+ .name = "ce5_h_clk", -+ .parent_hws = (const struct clk_hw*[]){ -+ &ce5_h_clk_src.clkr.hw, -+ }, -+ .num_parents = 1, -+ .ops = &clk_branch_ops, -+ .flags = CLK_SET_RATE_PARENT, -+ }, -+ }, -+}; -+ - static struct clk_regmap *gcc_ipq806x_clks[] = { - [PLL0] = &pll0.clkr, - [PLL0_VOTE] = &pll0_vote, -@@ -2831,6 +3068,7 @@ static struct clk_regmap *gcc_ipq806x_cl - [PLL4_VOTE] = &pll4_vote, - [PLL8] = &pll8.clkr, - [PLL8_VOTE] = &pll8_vote, -+ [PLL11] = &pll11.clkr, - [PLL14] = &pll14.clkr, - [PLL14_VOTE] = &pll14_vote, - [PLL18] = &pll18.clkr, -@@ -2945,6 +3183,12 @@ static struct clk_regmap *gcc_ipq806x_cl - [PLL9] = &hfpll0.clkr, - [PLL10] = &hfpll1.clkr, - [PLL12] = &hfpll_l2.clkr, -+ [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr, -+ [CE5_A_CLK] = &ce5_a_clk.clkr, -+ [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr, -+ [CE5_H_CLK] = &ce5_h_clk.clkr, -+ [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr, -+ [CE5_CORE_CLK] = &ce5_core_clk.clkr, - }; - - static const struct qcom_reset_map gcc_ipq806x_resets[] = { diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-13-linux-next-dt-bindings-reset-add-ipq8064-ce5-resets.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-13-linux-next-dt-bindings-reset-add-ipq8064-ce5-resets.patch deleted file mode 100644 index 5d05c2b3af3..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-13-linux-next-dt-bindings-reset-add-ipq8064-ce5-resets.patch +++ /dev/null @@ -1,29 +0,0 @@ -From f4a7e56f4956f0450b9f671ed93d45ffcc15aa62 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 18 Jan 2022 01:22:05 +0100 -Subject: [PATCH v6 13/15] dt-bindings: reset: add ipq8064 ce5 resets - -Add ipq8064 ce5 resets needed for CryptoEngine gcc driver. - -Signed-off-by: Ansuel Smith -Reviewed-by: Bjorn Andersson -Acked-by: Philipp Zabel -Acked-by: Rob Herring -Reviewed-by: Stephen Boyd ---- - include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h -+++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h -@@ -163,5 +163,10 @@ - #define NSS_CAL_PRBS_RST_N_RESET 154 - #define NSS_LCKDT_RST_N_RESET 155 - #define NSS_SRDS_N_RESET 156 -+#define CRYPTO_ENG1_RESET 157 -+#define CRYPTO_ENG2_RESET 158 -+#define CRYPTO_ENG3_RESET 159 -+#define CRYPTO_ENG4_RESET 160 -+#define CRYPTO_AHB_RESET 161 - - #endif diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-14-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-resets.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-14-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-resets.patch deleted file mode 100644 index a26f67e36e0..00000000000 --- a/target/linux/ipq806x/patches-5.15/100-v5.18-14-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-resets.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 4f865bdcb44fb18951de94be5c2ec37a891a8d03 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:34 +0100 -Subject: [PATCH 14/14] clk: qcom: gcc-ipq806x: add CryptoEngine resets - -Add missing CryptoEngine resets. - -Signed-off-by: Ansuel Smith -Reviewed-by: Stephen Boyd -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-15-ansuelsmth@gmail.com ---- - drivers/clk/qcom/gcc-ipq806x.c | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -3320,6 +3320,11 @@ static const struct qcom_reset_map gcc_i - [GMAC_CORE3_RESET] = { 0x3cfc, 0 }, - [GMAC_CORE4_RESET] = { 0x3d1c, 0 }, - [GMAC_AHB_RESET] = { 0x3e24, 0 }, -+ [CRYPTO_ENG1_RESET] = { 0x3e00, 0}, -+ [CRYPTO_ENG2_RESET] = { 0x3e04, 0}, -+ [CRYPTO_ENG3_RESET] = { 0x3e08, 0}, -+ [CRYPTO_ENG4_RESET] = { 0x3e0c, 0}, -+ [CRYPTO_AHB_RESET] = { 0x3e10, 0}, - [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 }, - [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 }, - [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 }, diff --git a/target/linux/ipq806x/patches-5.15/101-v6.0-01-net-ethernet-stmmac-add-missing-sgmii-configure-for-.patch b/target/linux/ipq806x/patches-5.15/101-v6.0-01-net-ethernet-stmmac-add-missing-sgmii-configure-for-.patch deleted file mode 100644 index bd492ca1ecd..00000000000 --- a/target/linux/ipq806x/patches-5.15/101-v6.0-01-net-ethernet-stmmac-add-missing-sgmii-configure-for-.patch +++ /dev/null @@ -1,151 +0,0 @@ -From 9ec092d2feb69045dd289845024301fb91c064ee Mon Sep 17 00:00:00 2001 -From: Christian 'Ansuel' Marangi -Date: Tue, 14 Jun 2022 13:22:27 +0200 -Subject: [PATCH 1/2] net: ethernet: stmmac: add missing sgmii configure for - ipq806x - -The different gmacid require different configuration based on the soc -and on the gmac id. Add these missing configuration taken from the -original driver. - -Signed-off-by: Christian 'Ansuel' Marangi -Link: https://lore.kernel.org/r/20220614112228.1998-1-ansuelsmth@gmail.com -Signed-off-by: Paolo Abeni ---- - drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 + - .../ethernet/stmicro/stmmac/dwmac-ipq806x.c | 93 +++++++++++++++---- - 2 files changed, 78 insertions(+), 16 deletions(-) - ---- a/drivers/net/ethernet/stmicro/stmmac/Kconfig -+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig -@@ -83,6 +83,7 @@ config DWMAC_IPQ806X - default ARCH_QCOM - depends on OF && (ARCH_QCOM || COMPILE_TEST) - select MFD_SYSCON -+ select QCOM_SOCINFO - help - Support for QCA IPQ806X DWMAC Ethernet. - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c -@@ -27,6 +27,8 @@ - #include - #include - #include -+#include -+#include - - #include "stmmac_platform.h" - -@@ -75,11 +77,20 @@ - #define QSGMII_PHY_RX_SIGNAL_DETECT_EN BIT(2) - #define QSGMII_PHY_TX_DRIVER_EN BIT(3) - #define QSGMII_PHY_QSGMII_EN BIT(7) --#define QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET 12 --#define QSGMII_PHY_RX_DC_BIAS_OFFSET 18 --#define QSGMII_PHY_RX_INPUT_EQU_OFFSET 20 --#define QSGMII_PHY_CDR_PI_SLEW_OFFSET 22 --#define QSGMII_PHY_TX_DRV_AMP_OFFSET 28 -+#define QSGMII_PHY_DEEMPHASIS_LVL_MASK GENMASK(11, 10) -+#define QSGMII_PHY_DEEMPHASIS_LVL(x) FIELD_PREP(QSGMII_PHY_DEEMPHASIS_LVL_MASK, (x)) -+#define QSGMII_PHY_PHASE_LOOP_GAIN_MASK GENMASK(14, 12) -+#define QSGMII_PHY_PHASE_LOOP_GAIN(x) FIELD_PREP(QSGMII_PHY_PHASE_LOOP_GAIN_MASK, (x)) -+#define QSGMII_PHY_RX_DC_BIAS_MASK GENMASK(19, 18) -+#define QSGMII_PHY_RX_DC_BIAS(x) FIELD_PREP(QSGMII_PHY_RX_DC_BIAS_MASK, (x)) -+#define QSGMII_PHY_RX_INPUT_EQU_MASK GENMASK(21, 20) -+#define QSGMII_PHY_RX_INPUT_EQU(x) FIELD_PREP(QSGMII_PHY_RX_INPUT_EQU_MASK, (x)) -+#define QSGMII_PHY_CDR_PI_SLEW_MASK GENMASK(23, 22) -+#define QSGMII_PHY_CDR_PI_SLEW(x) FIELD_PREP(QSGMII_PHY_CDR_PI_SLEW_MASK, (x)) -+#define QSGMII_PHY_TX_SLEW_MASK GENMASK(27, 26) -+#define QSGMII_PHY_TX_SLEW(x) FIELD_PREP(QSGMII_PHY_TX_SLEW_MASK, (x)) -+#define QSGMII_PHY_TX_DRV_AMP_MASK GENMASK(31, 28) -+#define QSGMII_PHY_TX_DRV_AMP(x) FIELD_PREP(QSGMII_PHY_TX_DRV_AMP_MASK, (x)) - - struct ipq806x_gmac { - struct platform_device *pdev; -@@ -242,6 +253,64 @@ static void ipq806x_gmac_fix_mac_speed(v - ipq806x_gmac_set_speed(gmac, speed); - } - -+static const struct soc_device_attribute ipq806x_gmac_soc_v1[] = { -+ { -+ .revision = "1.*", -+ }, -+ { -+ /* sentinel */ -+ } -+}; -+ -+static int -+ipq806x_gmac_configure_qsgmii_params(struct ipq806x_gmac *gmac) -+{ -+ struct platform_device *pdev = gmac->pdev; -+ const struct soc_device_attribute *soc; -+ struct device *dev = &pdev->dev; -+ u32 qsgmii_param; -+ -+ switch (gmac->id) { -+ case 1: -+ soc = soc_device_match(ipq806x_gmac_soc_v1); -+ -+ if (soc) -+ qsgmii_param = QSGMII_PHY_TX_DRV_AMP(0xc) | -+ QSGMII_PHY_TX_SLEW(0x2) | -+ QSGMII_PHY_DEEMPHASIS_LVL(0x2); -+ else -+ qsgmii_param = QSGMII_PHY_TX_DRV_AMP(0xd) | -+ QSGMII_PHY_TX_SLEW(0x0) | -+ QSGMII_PHY_DEEMPHASIS_LVL(0x0); -+ -+ qsgmii_param |= QSGMII_PHY_RX_DC_BIAS(0x2); -+ break; -+ case 2: -+ case 3: -+ qsgmii_param = QSGMII_PHY_RX_DC_BIAS(0x3) | -+ QSGMII_PHY_TX_DRV_AMP(0xc); -+ break; -+ default: /* gmac 0 can't be set in SGMII mode */ -+ dev_err(dev, "gmac id %d can't be in SGMII mode", gmac->id); -+ return -EINVAL; -+ } -+ -+ /* Common params across all gmac id */ -+ qsgmii_param |= QSGMII_PHY_CDR_EN | -+ QSGMII_PHY_RX_FRONT_EN | -+ QSGMII_PHY_RX_SIGNAL_DETECT_EN | -+ QSGMII_PHY_TX_DRIVER_EN | -+ QSGMII_PHY_QSGMII_EN | -+ QSGMII_PHY_PHASE_LOOP_GAIN(0x4) | -+ QSGMII_PHY_RX_INPUT_EQU(0x1) | -+ QSGMII_PHY_CDR_PI_SLEW(0x2); -+ -+ regmap_write(gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id), -+ qsgmii_param); -+ -+ return 0; -+} -+ - static int ipq806x_gmac_probe(struct platform_device *pdev) - { - struct plat_stmmacenet_data *plat_dat; -@@ -328,17 +397,9 @@ static int ipq806x_gmac_probe(struct pla - regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val); - - if (gmac->phy_mode == PHY_INTERFACE_MODE_SGMII) { -- regmap_write(gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id), -- QSGMII_PHY_CDR_EN | -- QSGMII_PHY_RX_FRONT_EN | -- QSGMII_PHY_RX_SIGNAL_DETECT_EN | -- QSGMII_PHY_TX_DRIVER_EN | -- QSGMII_PHY_QSGMII_EN | -- 0x4ul << QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET | -- 0x3ul << QSGMII_PHY_RX_DC_BIAS_OFFSET | -- 0x1ul << QSGMII_PHY_RX_INPUT_EQU_OFFSET | -- 0x2ul << QSGMII_PHY_CDR_PI_SLEW_OFFSET | -- 0xCul << QSGMII_PHY_TX_DRV_AMP_OFFSET); -+ err = ipq806x_gmac_configure_qsgmii_params(gmac); -+ if (err) -+ goto err_remove_config_dt; - } - - plat_dat->has_gmac = true; diff --git a/target/linux/ipq806x/patches-5.15/101-v6.0-02-net-ethernet-stmmac-reset-force-speed-bit-for-ipq806.patch b/target/linux/ipq806x/patches-5.15/101-v6.0-02-net-ethernet-stmmac-reset-force-speed-bit-for-ipq806.patch deleted file mode 100644 index d444553452c..00000000000 --- a/target/linux/ipq806x/patches-5.15/101-v6.0-02-net-ethernet-stmmac-reset-force-speed-bit-for-ipq806.patch +++ /dev/null @@ -1,110 +0,0 @@ -From 8bca458990dd8c6d001b2fb52063aa18e8ca7444 Mon Sep 17 00:00:00 2001 -From: Christian 'Ansuel' Marangi -Date: Tue, 14 Jun 2022 13:22:28 +0200 -Subject: [PATCH 2/2] net: ethernet: stmmac: reset force speed bit for ipq806x - -Some bootloader may set the force speed regs even if the actual -interface should use autonegotiation between PCS and PHY. -This cause the complete malfuction of the interface. - -To fix this correctly reset the force speed regs if a fixed-link is not -defined in the DTS. With a fixed-link node correctly configure the -forced speed regs to handle any misconfiguration by the bootloader. - -Reported-by: Mark Mentovai -Co-developed-by: Mark Mentovai -Signed-off-by: Mark Mentovai -Signed-off-by: Christian 'Ansuel' Marangi -Link: https://lore.kernel.org/r/20220614112228.1998-2-ansuelsmth@gmail.com -Signed-off-by: Paolo Abeni ---- - .../ethernet/stmicro/stmmac/dwmac-ipq806x.c | 64 +++++++++++++++++++ - 1 file changed, 64 insertions(+) - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c -@@ -66,6 +66,17 @@ - #define NSS_COMMON_CLK_DIV_SGMII_100 4 - #define NSS_COMMON_CLK_DIV_SGMII_10 49 - -+#define QSGMII_PCS_ALL_CH_CTL 0x80 -+#define QSGMII_PCS_CH_SPEED_FORCE BIT(1) -+#define QSGMII_PCS_CH_SPEED_10 0x0 -+#define QSGMII_PCS_CH_SPEED_100 BIT(2) -+#define QSGMII_PCS_CH_SPEED_1000 BIT(3) -+#define QSGMII_PCS_CH_SPEED_MASK (QSGMII_PCS_CH_SPEED_FORCE | \ -+ QSGMII_PCS_CH_SPEED_10 | \ -+ QSGMII_PCS_CH_SPEED_100 | \ -+ QSGMII_PCS_CH_SPEED_1000) -+#define QSGMII_PCS_CH_SPEED_SHIFT(x) ((x) * 4) -+ - #define QSGMII_PCS_CAL_LCKDT_CTL 0x120 - #define QSGMII_PCS_CAL_LCKDT_CTL_RST BIT(19) - -@@ -253,6 +264,55 @@ static void ipq806x_gmac_fix_mac_speed(v - ipq806x_gmac_set_speed(gmac, speed); - } - -+static int -+ipq806x_gmac_configure_qsgmii_pcs_speed(struct ipq806x_gmac *gmac) -+{ -+ struct platform_device *pdev = gmac->pdev; -+ struct device *dev = &pdev->dev; -+ struct device_node *dn; -+ int link_speed; -+ int val = 0; -+ int ret; -+ -+ /* Some bootloader may apply wrong configuration and cause -+ * not functioning port. If fixed link is not set, -+ * reset the force speed bit. -+ */ -+ if (!of_phy_is_fixed_link(pdev->dev.of_node)) -+ goto write; -+ -+ dn = of_get_child_by_name(pdev->dev.of_node, "fixed-link"); -+ ret = of_property_read_u32(dn, "speed", &link_speed); -+ of_node_put(dn); -+ if (ret) { -+ dev_err(dev, "found fixed-link node with no speed"); -+ return ret; -+ } -+ -+ val = QSGMII_PCS_CH_SPEED_FORCE; -+ -+ switch (link_speed) { -+ case SPEED_1000: -+ val |= QSGMII_PCS_CH_SPEED_1000; -+ break; -+ case SPEED_100: -+ val |= QSGMII_PCS_CH_SPEED_100; -+ break; -+ case SPEED_10: -+ val |= QSGMII_PCS_CH_SPEED_10; -+ break; -+ } -+ -+write: -+ regmap_update_bits(gmac->qsgmii_csr, QSGMII_PCS_ALL_CH_CTL, -+ QSGMII_PCS_CH_SPEED_MASK << -+ QSGMII_PCS_CH_SPEED_SHIFT(gmac->id), -+ val << -+ QSGMII_PCS_CH_SPEED_SHIFT(gmac->id)); -+ -+ return 0; -+} -+ - static const struct soc_device_attribute ipq806x_gmac_soc_v1[] = { - { - .revision = "1.*", -@@ -400,6 +460,10 @@ static int ipq806x_gmac_probe(struct pla - err = ipq806x_gmac_configure_qsgmii_params(gmac); - if (err) - goto err_remove_config_dt; -+ -+ err = ipq806x_gmac_configure_qsgmii_pcs_speed(gmac); -+ if (err) -+ goto err_remove_config_dt; - } - - plat_dat->has_gmac = true; diff --git a/target/linux/ipq806x/patches-5.15/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch b/target/linux/ipq806x/patches-5.15/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch deleted file mode 100644 index e0c195f1ab9..00000000000 --- a/target/linux/ipq806x/patches-5.15/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 5001f2e1a325b68dbf225bd17f69a4d3d975cca5 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 9 Mar 2017 09:31:44 +0100 -Subject: [PATCH 61/69] mtd: "rootfs" conflicts with OpenWrt auto mounting - -Signed-off-by: John Crispin ---- - drivers/mtd/mtdpart.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/mtd/mtdpart.c -+++ b/drivers/mtd/mtdpart.c -@@ -51,7 +51,11 @@ static struct mtd_info *allocate_partiti - - /* allocate the partition structure */ - child = kzalloc(sizeof(*child), GFP_KERNEL); -- name = kstrdup(part->name, GFP_KERNEL); -+ /* "rootfs" conflicts with OpenWrt auto mounting */ -+ if (mtd_type_is_nand(parent) && !strcmp(part->name, "rootfs")) -+ name = "ubi"; -+ else -+ name = kstrdup(part->name, GFP_KERNEL); - if (!name || !child) { - printk(KERN_ERR"memory allocation error while creating partitions for \"%s\"\n", - parent->name); diff --git a/target/linux/ipq806x/patches-5.15/103-v5.19-ARM-dts-qcom-add-syscon-and-cxo-pxo-clock-to-gcc-nod.patch b/target/linux/ipq806x/patches-5.15/103-v5.19-ARM-dts-qcom-add-syscon-and-cxo-pxo-clock-to-gcc-nod.patch deleted file mode 100644 index 2ce526b6ca7..00000000000 --- a/target/linux/ipq806x/patches-5.15/103-v5.19-ARM-dts-qcom-add-syscon-and-cxo-pxo-clock-to-gcc-nod.patch +++ /dev/null @@ -1,48 +0,0 @@ -From a5ba119455c77a07e05f2fe0af446c8bf43d1a00 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 26 Feb 2022 14:52:35 +0100 -Subject: [PATCH] ARM: dts: qcom: add syscon and cxo/pxo clock to gcc node for - ipq8064 - -Add syscon compatible required for tsens driver to correctly probe driver -and access the reg. Also add cxo and pxo tag and declare them as gcc clock -now requires them for the ipq8064 gcc driver that has now been modernized. - -Signed-off-by: Ansuel Smith -Reviewed-by: Bjorn Andersson -Reviewed-by: Stephen Boyd -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220226135235.10051-16-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +++++--- - 1 file changed, 5 insertions(+), 3 deletions(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -298,13 +298,13 @@ - }; - - clocks { -- cxo_board { -+ cxo_board: cxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - -- pxo_board { -+ pxo_board: pxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; -@@ -736,7 +736,9 @@ - }; - - gcc: clock-controller@900000 { -- compatible = "qcom,gcc-ipq8064"; -+ compatible = "qcom,gcc-ipq8064", "syscon"; -+ clocks = <&pxo_board>, <&cxo_board>; -+ clock-names = "pxo", "cxo"; - reg = <0x00900000 0x4000>; - #clock-cells = <1>; - #reset-cells = <1>; diff --git a/target/linux/ipq806x/patches-5.15/103-v6.0-01-ARM-dts-qcom-replace-gcc-PXO-with-pxo_board-fixed-cl.patch b/target/linux/ipq806x/patches-5.15/103-v6.0-01-ARM-dts-qcom-replace-gcc-PXO-with-pxo_board-fixed-cl.patch deleted file mode 100644 index d0bc34c07fa..00000000000 --- a/target/linux/ipq806x/patches-5.15/103-v6.0-01-ARM-dts-qcom-replace-gcc-PXO-with-pxo_board-fixed-cl.patch +++ /dev/null @@ -1,29 +0,0 @@ -From eb9e93937756a05787977875830c0dc482cb57e0 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 30 Apr 2022 07:51:17 +0200 -Subject: [PATCH] ARM: dts: qcom: replace gcc PXO with pxo_board fixed clock - -Replace gcc PXO phandle to pxo_board fixed clock declared in the dts. -gcc driver doesn't provide PXO_SRC as it's a fixed-clock. This cause a -kernel panic if any driver actually try to use it. - -Fixes: 40cf5c884a96 ("ARM: dts: qcom: add L2CC and RPM for IPQ8064") -Signed-off-by: Ansuel Smith -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220430055118.1947-2-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -784,7 +784,7 @@ - l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; - reg = <0x2011000 0x1000>; -- clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; -+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu_l2_aux"; - }; diff --git a/target/linux/ipq806x/patches-5.15/104-v6.0-01-ARM-dts-qcom-ipq8064-add-multiple-missing-pin-defini.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-01-ARM-dts-qcom-ipq8064-add-multiple-missing-pin-defini.patch deleted file mode 100644 index 5dad164e3c2..00000000000 --- a/target/linux/ipq806x/patches-5.15/104-v6.0-01-ARM-dts-qcom-ipq8064-add-multiple-missing-pin-defini.patch +++ /dev/null @@ -1,101 +0,0 @@ -From 4af1defb305798d1a064a5ea0d0c9b30e5eee185 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 03:09:35 +0200 -Subject: [PATCH 1/8] ARM: dts: qcom: ipq8064: add multiple missing pin - definition - -Add missing definition for mdio0 pins used for gpio-bitbang driver,i2c4 -pins and rgmii2 pins for ipq8064. - -Drop i2c4_pins node from ipq8064-ap148 dts as it's now moved to ipq8064 -dtsi. - -Drop mdio0_pins node from ipq8064-rb3011 dts as it's now moved to -ipq8064 dtsi. - -Signed-off-by: Christian Marangi -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220707010943.20857-2-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 6 ----- - arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 9 ------- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 32 +++++++++++++++++++++++ - 3 files changed, 32 insertions(+), 15 deletions(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts -+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts -@@ -305,15 +305,6 @@ - }; - }; - -- mdio0_pins: mdio0_pins { -- mux { -- pins = "gpio0", "gpio1"; -- function = "gpio"; -- drive-strength = <8>; -- bias-disable; -- }; -- }; -- - mdio1_pins: mdio1_pins { - mux { - pins = "gpio10", "gpio11"; ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -382,6 +382,13 @@ - }; - }; - -+ i2c4_pins: i2c4-default { -+ pins = "gpio12", "gpio13"; -+ function = "gsbi4"; -+ drive-strength = <12>; -+ bias-disable; -+ }; -+ - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; -@@ -424,6 +431,8 @@ - - pullups { - pins = "gpio39"; -+ function = "nand"; -+ drive-strength = <10>; - bias-pull-up; - }; - -@@ -431,9 +440,32 @@ - pins = "gpio40", "gpio41", "gpio42", - "gpio43", "gpio44", "gpio45", - "gpio46", "gpio47"; -+ function = "nand"; -+ drive-strength = <10>; - bias-bus-hold; - }; - }; -+ -+ mdio0_pins: mdio0-pins { -+ mux { -+ pins = "gpio0", "gpio1"; -+ function = "mdio"; -+ drive-strength = <8>; -+ bias-disable; -+ }; -+ }; -+ -+ rgmii2_pins: rgmii2-pins { -+ mux { -+ pins = "gpio27", "gpio28", "gpio29", -+ "gpio30", "gpio31", "gpio32", -+ "gpio51", "gpio52", "gpio59", -+ "gpio60", "gpio61", "gpio62"; -+ function = "rgmii2"; -+ drive-strength = <8>; -+ bias-disable; -+ }; -+ }; - }; - - intc: interrupt-controller@2000000 { diff --git a/target/linux/ipq806x/patches-5.15/104-v6.0-02-ARM-dts-qcom-ipq8064-add-gsbi6-missing-definition.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-02-ARM-dts-qcom-ipq8064-add-gsbi6-missing-definition.patch deleted file mode 100644 index 1f4e288fb81..00000000000 --- a/target/linux/ipq806x/patches-5.15/104-v6.0-02-ARM-dts-qcom-ipq8064-add-gsbi6-missing-definition.patch +++ /dev/null @@ -1,67 +0,0 @@ -From d883a12a547b6d42e795ff3b5ac87cfd013b5423 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 03:09:36 +0200 -Subject: [PATCH 2/8] ARM: dts: qcom: ipq8064: add gsbi6 missing definition - -Add gsbi6 missing definition for ipq8064. - -Signed-off-by: Christian Marangi -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220707010943.20857-3-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 43 +++++++++++++++++++++++++++++ - 1 file changed, 43 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -663,6 +663,49 @@ - }; - }; - -+ gsbi6: gsbi@16500000 { -+ compatible = "qcom,gsbi-v1.0.0"; -+ reg = <0x16500000 0x100>; -+ cell-index = <6>; -+ clocks = <&gcc GSBI6_H_CLK>; -+ clock-names = "iface"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ syscon-tcsr = <&tcsr>; -+ -+ status = "disabled"; -+ -+ gsbi6_i2c: i2c@16580000 { -+ compatible = "qcom,i2c-qup-v1.1.1"; -+ reg = <0x16580000 0x1000>; -+ interrupts = ; -+ -+ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; -+ clock-names = "core", "iface"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ status = "disabled"; -+ }; -+ -+ gsbi6_spi: spi@16580000 { -+ compatible = "qcom,spi-qup-v1.1.1"; -+ reg = <0x16580000 0x1000>; -+ interrupts = ; -+ -+ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; -+ clock-names = "core", "iface"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ status = "disabled"; -+ }; -+ }; -+ - gsbi7: gsbi@16600000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; diff --git a/target/linux/ipq806x/patches-5.15/104-v6.0-03-ARM-dts-qcom-ipq8064-add-specific-dtsi-with-smb208-r.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-03-ARM-dts-qcom-ipq8064-add-specific-dtsi-with-smb208-r.patch deleted file mode 100644 index dbba722caaf..00000000000 --- a/target/linux/ipq806x/patches-5.15/104-v6.0-03-ARM-dts-qcom-ipq8064-add-specific-dtsi-with-smb208-r.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 5c47a46d5e942ea6b041c8b7727b201817c1ff76 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 03:09:37 +0200 -Subject: [PATCH 3/8] ARM: dts: qcom: ipq8064: add specific dtsi with smb208 - rpm regulators - -Add specific ipq8064 dtsi with smb208 rpm regulators. - -Qcom advise to use this configuration but it's not mandatory and OEM -can decide to implement their own regulators. -smb208 regulators are used to scale CPU voltage, L2 cache voltage and -Ubi32 cores. - -There regulators are controlled by rpm and to correctly works gsbi4-i2c -require to be NEVER disabled or rpm will reject any regulator change -request. - -Signed-off-by: Christian Marangi -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220707010943.20857-4-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi | 37 ++++++++++++++++++++++ - 1 file changed, 37 insertions(+) - create mode 100644 arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi - ---- /dev/null -+++ b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi -@@ -0,0 +1,37 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#include "qcom-ipq8064.dtsi" -+ -+&rpm { -+ smb208_regulators: regulators { -+ compatible = "qcom,rpm-smb208-regulators"; -+ -+ smb208_s1a: s1a { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s1b: s1b { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2a: s2a { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1250000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2b: s2b { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1250000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ }; -+}; diff --git a/target/linux/ipq806x/patches-5.15/104-v6.0-04-ARM-dts-qcom-ipq8064-add-missing-snps-dwmac-compatib.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-04-ARM-dts-qcom-ipq8064-add-missing-snps-dwmac-compatib.patch deleted file mode 100644 index 1a3185f500d..00000000000 --- a/target/linux/ipq806x/patches-5.15/104-v6.0-04-ARM-dts-qcom-ipq8064-add-missing-snps-dwmac-compatib.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 0ce34e0c13e99c239cce6099f64b0e95697f36b1 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 03:09:38 +0200 -Subject: [PATCH 4/8] ARM: dts: qcom: ipq8064: add missing snps,dwmac - compatible for gmac - -Add missing snps,dwmac compatible for gmac ipq8064 dtsi. - -Signed-off-by: Christian Marangi -Tested-by: Jonathan McDowell -Reviewed-by: Krzysztof Kozlowski -Reviewed-by: Konrad Dybcio -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220707010943.20857-5-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -1042,7 +1042,7 @@ - - gmac0: ethernet@37000000 { - device_type = "network"; -- compatible = "qcom,ipq806x-gmac"; -+ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37000000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; -@@ -1066,7 +1066,7 @@ - - gmac1: ethernet@37200000 { - device_type = "network"; -- compatible = "qcom,ipq806x-gmac"; -+ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37200000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; -@@ -1090,7 +1090,7 @@ - - gmac2: ethernet@37400000 { - device_type = "network"; -- compatible = "qcom,ipq806x-gmac"; -+ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37400000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; -@@ -1114,7 +1114,7 @@ - - gmac3: ethernet@37600000 { - device_type = "network"; -- compatible = "qcom,ipq806x-gmac"; -+ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37600000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; diff --git a/target/linux/ipq806x/patches-5.15/104-v6.0-05-ARM-dts-qcom-ipq8064-disable-usb-phy-by-default.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-05-ARM-dts-qcom-ipq8064-disable-usb-phy-by-default.patch deleted file mode 100644 index 43dac4b7fa2..00000000000 --- a/target/linux/ipq806x/patches-5.15/104-v6.0-05-ARM-dts-qcom-ipq8064-disable-usb-phy-by-default.patch +++ /dev/null @@ -1,37 +0,0 @@ -From d63d3124c0a5cdbe8b91d81b922fe56b2462e1b9 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 03:09:39 +0200 -Subject: [PATCH 5/8] ARM: dts: qcom: ipq8064: disable usb phy by default - -Disable usb phy by default. When the usb phy were pushed, half of them -were flagged as disabled by mistake. -Correctly disable all usb phy and enable them only if a device actually -use them. - -Signed-off-by: Christian Marangi -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220707010943.20857-6-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -1188,6 +1188,8 @@ - clocks = <&gcc USB30_1_UTMI_CLK>; - clock-names = "ref"; - #phy-cells = <0>; -+ -+ status = "disabled"; - }; - - ss_phy_1: phy@110f8830 { -@@ -1196,6 +1198,8 @@ - clocks = <&gcc USB30_1_MASTER_CLK>; - clock-names = "ref"; - #phy-cells = <0>; -+ -+ status = "disabled"; - }; - - usb3_1: usb3@110f8800 { diff --git a/target/linux/ipq806x/patches-5.15/104-v6.0-07-ARM-dts-qcom-ipq8064-fix-and-add-some-missing-gsbi-n.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-07-ARM-dts-qcom-ipq8064-fix-and-add-some-missing-gsbi-n.patch deleted file mode 100644 index ca5e5aa3c4c..00000000000 --- a/target/linux/ipq806x/patches-5.15/104-v6.0-07-ARM-dts-qcom-ipq8064-fix-and-add-some-missing-gsbi-n.patch +++ /dev/null @@ -1,94 +0,0 @@ -From 6c421a9c08286389bb331fe783e2625c9efcc187 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 03:09:41 +0200 -Subject: [PATCH 7/8] ARM: dts: qcom: ipq8064: fix and add some missing gsbi - node - -Add some tag for gsbi to make them usable for ipq8064 SoC. Add missing -gsbi7 i2c node and gsbi1 node. - -Signed-off-by: Christian Marangi -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220707010943.20857-8-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 54 ++++++++++++++++++++++++++++- - 1 file changed, 53 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -539,6 +539,44 @@ - regulator; - }; - -+ gsbi1: gsbi@12440000 { -+ compatible = "qcom,gsbi-v1.0.0"; -+ reg = <0x12440000 0x100>; -+ cell-index = <1>; -+ clocks = <&gcc GSBI1_H_CLK>; -+ clock-names = "iface"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ syscon-tcsr = <&tcsr>; -+ -+ status = "disabled"; -+ -+ gsbi1_serial: serial@12450000 { -+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; -+ reg = <0x12450000 0x100>, -+ <0x12400000 0x03>; -+ interrupts = ; -+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; -+ clock-names = "core", "iface"; -+ -+ status = "disabled"; -+ }; -+ -+ gsbi1_i2c: i2c@12460000 { -+ compatible = "qcom,i2c-qup-v1.1.1"; -+ reg = <0x12460000 0x1000>; -+ interrupts = ; -+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; -+ clock-names = "core", "iface"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ status = "disabled"; -+ }; -+ }; -+ - gsbi2: gsbi@12480000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <2>; -@@ -562,7 +600,7 @@ - status = "disabled"; - }; - -- i2c@124a0000 { -+ gsbi2_i2c: i2c@124a0000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x124a0000 0x1000>; - interrupts = ; -@@ -727,6 +765,20 @@ - clock-names = "core", "iface"; - status = "disabled"; - }; -+ -+ gsbi7_i2c: i2c@16680000 { -+ compatible = "qcom,i2c-qup-v1.1.1"; -+ reg = <0x16680000 0x1000>; -+ interrupts = ; -+ -+ clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; -+ clock-names = "core", "iface"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ status = "disabled"; -+ }; - }; - - rng@1a500000 { diff --git a/target/linux/ipq806x/patches-5.15/104-v6.0-08-ARM-dts-qcom-ipq8064-add-speedbin-efuse-nvmem-node.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-08-ARM-dts-qcom-ipq8064-add-speedbin-efuse-nvmem-node.patch deleted file mode 100644 index 463c3d4a658..00000000000 --- a/target/linux/ipq806x/patches-5.15/104-v6.0-08-ARM-dts-qcom-ipq8064-add-speedbin-efuse-nvmem-node.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 7f5aecdd4ffcc018f73171bc0e028cd4e3361acd Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 03:09:43 +0200 -Subject: [PATCH 8/8] ARM: dts: qcom: ipq8064: add speedbin efuse nvmem node - -Add speedbin efuse nvmem cell needed for the opp table for the CPU -freqs. - -Signed-off-by: Christian Marangi -Tested-by: Jonathan McDowell -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220707010943.20857-10-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -854,6 +854,9 @@ - reg = <0x00700000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; -+ speedbin_efuse: speedbin@c0 { -+ reg = <0xc0 0x4>; -+ }; - tsens_calib: calib@400 { - reg = <0x400 0xb>; - }; diff --git a/target/linux/ipq806x/patches-5.15/105-v6.0-01-hwspinlock-qcom-Add-support-for-mmio-usage-to-sfpb-m.patch b/target/linux/ipq806x/patches-5.15/105-v6.0-01-hwspinlock-qcom-Add-support-for-mmio-usage-to-sfpb-m.patch deleted file mode 100644 index 2c6f6b10c48..00000000000 --- a/target/linux/ipq806x/patches-5.15/105-v6.0-01-hwspinlock-qcom-Add-support-for-mmio-usage-to-sfpb-m.patch +++ /dev/null @@ -1,71 +0,0 @@ -From cdab30b44518513003607ecfc8a22de3dbbb78ed Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 12:20:38 +0200 -Subject: [PATCH 1/1] hwspinlock: qcom: Add support for mmio usage to - sfpb-mutex - -Allow sfpb-mutex to use mmio in addition to syscon. - -Signed-off-by: Christian Marangi -Reviewed-by: Bjorn Andersson -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220707102040.1859-1-ansuelsmth@gmail.com ---- - drivers/hwspinlock/qcom_hwspinlock.c | 28 +++++++++++++++++++++++----- - 1 file changed, 23 insertions(+), 5 deletions(-) - ---- a/drivers/hwspinlock/qcom_hwspinlock.c -+++ b/drivers/hwspinlock/qcom_hwspinlock.c -@@ -19,6 +19,11 @@ - #define QCOM_MUTEX_APPS_PROC_ID 1 - #define QCOM_MUTEX_NUM_LOCKS 32 - -+struct qcom_hwspinlock_of_data { -+ u32 offset; -+ u32 stride; -+}; -+ - static int qcom_hwspinlock_trylock(struct hwspinlock *lock) - { - struct regmap_field *field = lock->priv; -@@ -63,9 +68,20 @@ static const struct hwspinlock_ops qcom_ - .unlock = qcom_hwspinlock_unlock, - }; - -+static const struct qcom_hwspinlock_of_data of_sfpb_mutex = { -+ .offset = 0x4, -+ .stride = 0x4, -+}; -+ -+/* All modern platform has offset 0 and stride of 4k */ -+static const struct qcom_hwspinlock_of_data of_tcsr_mutex = { -+ .offset = 0, -+ .stride = 0x1000, -+}; -+ - static const struct of_device_id qcom_hwspinlock_of_match[] = { -- { .compatible = "qcom,sfpb-mutex" }, -- { .compatible = "qcom,tcsr-mutex" }, -+ { .compatible = "qcom,sfpb-mutex", .data = &of_sfpb_mutex }, -+ { .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex }, - { } - }; - MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match); -@@ -112,12 +128,14 @@ static const struct regmap_config tcsr_m - static struct regmap *qcom_hwspinlock_probe_mmio(struct platform_device *pdev, - u32 *offset, u32 *stride) - { -+ const struct qcom_hwspinlock_of_data *data; - struct device *dev = &pdev->dev; - void __iomem *base; - -- /* All modern platform has offset 0 and stride of 4k */ -- *offset = 0; -- *stride = 0x1000; -+ data = of_device_get_match_data(dev); -+ -+ *offset = data->offset; -+ *stride = data->stride; - - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) diff --git a/target/linux/ipq806x/patches-5.15/105-v6.0-02-ARM-dts-qcom-ipq8064-add-missing-hwlock.patch b/target/linux/ipq806x/patches-5.15/105-v6.0-02-ARM-dts-qcom-ipq8064-add-missing-hwlock.patch deleted file mode 100644 index d8303442f7e..00000000000 --- a/target/linux/ipq806x/patches-5.15/105-v6.0-02-ARM-dts-qcom-ipq8064-add-missing-hwlock.patch +++ /dev/null @@ -1,31 +0,0 @@ -From fbe4be367b2169602f6a5949a20d2917b25714d4 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 12:20:39 +0200 -Subject: [PATCH 1/2] ARM: dts: qcom: ipq8064: add missing hwlock - -Add missing hwlock for ipq8064 dtsi provided by qcom,sfpb-mutex. - -Signed-off-by: Christian Marangi -Acked-by: Krzysztof Kozlowski -[bjorn: Moved the node inside /soc] -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220707102040.1859-2-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -1357,5 +1357,12 @@ - dma-names = "tx", "rx"; - }; - }; -+ -+ sfpb_mutex: hwlock@1200600 { -+ compatible = "qcom,sfpb-mutex"; -+ reg = <0x01200600 0x100>; -+ -+ #hwlock-cells = <1>; -+ }; - }; - }; diff --git a/target/linux/ipq806x/patches-5.15/105-v6.0-03-ARM-dts-qcom-ipq8064-add-missing-smem-compatible.patch b/target/linux/ipq806x/patches-5.15/105-v6.0-03-ARM-dts-qcom-ipq8064-add-missing-smem-compatible.patch deleted file mode 100644 index 8b91eeb5116..00000000000 --- a/target/linux/ipq806x/patches-5.15/105-v6.0-03-ARM-dts-qcom-ipq8064-add-missing-smem-compatible.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 4fefb5434c4b735daf913abaef12431405368031 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 12:20:40 +0200 -Subject: [PATCH 2/2] ARM: dts: qcom: ipq8064: add missing smem compatible - -Add missing smem compatible and hwlocks phandle for ipq8064 dtsi -smem node. - -Signed-off-by: Christian Marangi -Acked-by: Krzysztof Kozlowski -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220707102040.1859-3-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -292,8 +292,11 @@ - }; - - smem: smem@41000000 { -+ compatible = "qcom,smem"; - reg = <0x41000000 0x200000>; - no-map; -+ -+ hwlocks = <&sfpb_mutex 3>; - }; - }; - diff --git a/target/linux/ipq806x/patches-5.15/106-v6.1-01-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch b/target/linux/ipq806x/patches-5.15/106-v6.1-01-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch deleted file mode 100644 index 8b20a550f6f..00000000000 --- a/target/linux/ipq806x/patches-5.15/106-v6.1-01-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch +++ /dev/null @@ -1,129 +0,0 @@ -From 9f7097a8b1948533a6db1b53b5c0480cc75bbd16 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Mon, 18 Jul 2022 18:05:16 +0200 -Subject: [PATCH 1/3] ARM: dts: qcom: ipq8064: add v2 dtsi variant - -Add ipq8064-v2.0 dtsi variant that differ from original ipq8064 SoC for -some additional pcie, sata and usb configuration values, additional -reserved memory and serial output. - -Signed-off-by: Christian Marangi ---- - .../boot/dts/qcom-ipq8064-v2.0-smb208.dtsi | 37 ++++++++++ - arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 69 +++++++++++++++++++ - 2 files changed, 106 insertions(+) - create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi - create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi - ---- /dev/null -+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi -@@ -0,0 +1,37 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#include "qcom-ipq8064-v2.0.dtsi" -+ -+&rpm { -+ smb208_regulators: regulators { -+ compatible = "qcom,rpm-smb208-regulators"; -+ -+ smb208_s1a: s1a { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s1b: s1b { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2a: s2a { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1250000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2b: s2b { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1250000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi -@@ -0,0 +1,69 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#include "qcom-ipq8064.dtsi" -+ -+/ { -+ model = "Qualcomm Technologies, Inc. IPQ8064-v2.0"; -+ -+ aliases { -+ serial0 = &gsbi4_serial; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ reserved-memory { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ rsvd@41200000 { -+ reg = <0x41200000 0x300000>; -+ no-map; -+ }; -+ }; -+}; -+ -+&gsbi4 { -+ qcom,mode = ; -+ status = "okay"; -+ -+ serial@16340000 { -+ status = "okay"; -+ }; -+ /* -+ * The i2c device on gsbi4 should not be enabled. -+ * On ipq806x designs gsbi4 i2c is meant for exclusive -+ * RPM usage. Turning this on in kernel manifests as -+ * i2c failure for the RPM. -+ */ -+}; -+ -+&pcie0 { -+ compatible = "qcom,pcie-ipq8064-v2"; -+}; -+ -+&pcie1 { -+ compatible = "qcom,pcie-ipq8064-v2"; -+}; -+ -+&pcie2 { -+ compatible = "qcom,pcie-ipq8064-v2"; -+}; -+ -+&sata { -+ ports-implemented = <0x1>; -+}; -+ -+&ss_phy_0 { -+ qcom,rx-eq = <2>; -+ qcom,tx-deamp_3_5db = <32>; -+ qcom,mpll = <5>; -+}; -+ -+&ss_phy_1 { -+ qcom,rx-eq = <2>; -+ qcom,tx-deamp_3_5db = <32>; -+ qcom,mpll = <5>; -+}; diff --git a/target/linux/ipq806x/patches-5.15/106-v6.1-02-ARM-dts-qcom-ipq8064-add-ipq8062-variant.patch b/target/linux/ipq806x/patches-5.15/106-v6.1-02-ARM-dts-qcom-ipq8064-add-ipq8062-variant.patch deleted file mode 100644 index fdff292480e..00000000000 --- a/target/linux/ipq806x/patches-5.15/106-v6.1-02-ARM-dts-qcom-ipq8064-add-ipq8062-variant.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 41d9fa8de7845bd92d9c963196fdfd7ea9232bb2 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Mon, 18 Jul 2022 18:07:26 +0200 -Subject: [PATCH 2/3] ARM: dts: qcom: ipq8064: add ipq8062 variant - -ipq8062 SoC is based on ipq8064-v2.0 with lower supported freq, lack of -usb port and a reduced voltage output with the smb208 regulators. - -Signed-off-by: Christian Marangi ---- - arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi | 37 ++++++++++++++++++++++ - arch/arm/boot/dts/qcom-ipq8062.dtsi | 8 +++++ - 2 files changed, 45 insertions(+) - create mode 100644 arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi - create mode 100644 arch/arm/boot/dts/qcom-ipq8062.dtsi - ---- /dev/null -+++ b/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi -@@ -0,0 +1,37 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+ -+#include "qcom-ipq8062.dtsi" -+ -+&rpm { -+ smb208_regulators: regulators { -+ compatible = "qcom,rpm-smb208-regulators"; -+ -+ smb208_s1a: s1a { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s1b: s1b { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2a: s2a { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2b: s2b { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/qcom-ipq8062.dtsi -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+ -+#include "qcom-ipq8064-v2.0.dtsi" -+ -+/ { -+ model = "Qualcomm Technologies, Inc. IPQ8062"; -+ compatible = "qcom,ipq8062", "qcom,ipq8064"; -+}; diff --git a/target/linux/ipq806x/patches-5.15/106-v6.1-03-ARM-dts-qcom-ipq8064-add-ipq8065-variant.patch b/target/linux/ipq806x/patches-5.15/106-v6.1-03-ARM-dts-qcom-ipq8064-add-ipq8065-variant.patch deleted file mode 100644 index bccc577b91c..00000000000 --- a/target/linux/ipq806x/patches-5.15/106-v6.1-03-ARM-dts-qcom-ipq8064-add-ipq8065-variant.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 01e7aa3fe6f76f7960f2382038136235eee9c6cd Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Mon, 18 Jul 2022 18:09:35 +0200 -Subject: [PATCH 3/3] ARM: dts: qcom: ipq8064: add ipq8065 variant - -ipq8065 SoC is based on ipq8064-v2.0 with a more clocked CPU and -an increased voltage output with the smb208 regulators. - -Signed-off-by: Christian Marangi ---- - arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi | 37 ++++++++++++++++++++++ - arch/arm/boot/dts/qcom-ipq8065.dtsi | 8 +++++ - 2 files changed, 45 insertions(+) - create mode 100644 arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi - create mode 100644 arch/arm/boot/dts/qcom-ipq8065.dtsi - ---- /dev/null -+++ b/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi -@@ -0,0 +1,37 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#include "qcom-ipq8065.dtsi" -+ -+&rpm { -+ smb208_regulators: regulators { -+ compatible = "qcom,rpm-smb208-regulators"; -+ -+ smb208_s1a: s1a { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s1b: s1b { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2a: s2a { -+ regulator-min-microvolt = <775000>; -+ regulator-max-microvolt = <1275000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2b: s2b { -+ regulator-min-microvolt = <775000>; -+ regulator-max-microvolt = <1275000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#include "qcom-ipq8064-v2.0.dtsi" -+ -+/ { -+ model = "Qualcomm Technologies, Inc. IPQ8065"; -+ compatible = "qcom,ipq8065", "qcom,ipq8064"; -+}; diff --git a/target/linux/ipq806x/patches-5.15/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch b/target/linux/ipq806x/patches-5.15/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch deleted file mode 100644 index 418d6b26ce7..00000000000 --- a/target/linux/ipq806x/patches-5.15/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch +++ /dev/null @@ -1,95 +0,0 @@ -From bef5018abb7cf94efafdc05087b4c998891ae4ec Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Mon, 17 Jan 2022 23:39:34 +0100 -Subject: [PATCH v3 10/18] ARM: dts: qcom: add saw for l2 cache and kraitcc for - ipq8064 - -Add saw compatible for l2 cache and kraitcc node for ipq8064 dtsi. -Also declare clock-output-names for acc0 and acc1 and qsb fixed clock -for the secondary mux. - -Signed-off-by: Ansuel Smith -Tested-by: Jonathan McDowell ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++-- - 1 file changed, 32 insertions(+), 2 deletions(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -301,6 +301,12 @@ - }; - - clocks { -+ qsb: qsb { -+ compatible = "fixed-clock"; -+ clock-frequency = <225000000>; -+ #clock-cells = <0>; -+ }; -+ - cxo_board: cxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; -@@ -503,11 +509,19 @@ - acc0: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; -+ clock-output-names = "acpu0_aux"; -+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>; -+ clock-names = "pll8_vote", "pxo"; -+ #clock-cells = <0>; - }; - - acc1: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; -+ clock-output-names = "acpu1_aux"; -+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>; -+ clock-names = "pll8_vote", "pxo"; -+ #clock-cells = <0>; - }; - - adm_dma: dma-controller@18300000 { -@@ -531,17 +545,23 @@ - }; - - saw0: regulator@2089000 { -- compatible = "qcom,saw2"; -+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw1: regulator@2099000 { -- compatible = "qcom,saw2"; -+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - -+ saw_l2: regulator@02012000 { -+ compatible = "qcom,saw2", "syscon"; -+ reg = <0x02012000 0x1000>; -+ regulator; -+ }; -+ - gsbi1: gsbi@12440000 { - compatible = "qcom,gsbi-v1.0.0"; - reg = <0x12440000 0x100>; -@@ -920,6 +940,17 @@ - clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu_l2_aux"; -+ #clock-cells = <0>; -+ }; -+ -+ kraitcc: clock-controller { -+ compatible = "qcom,krait-cc-v1"; -+ clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>, -+ <&acc0>, <&acc1>, <&l2cc>, <&qsb>, <&pxo_board>; -+ clock-names = "hfpll0", "hfpll1", "hfpll_l2", -+ "acpu0_aux", "acpu1_aux", "acpu_l2_aux", -+ "qsb", "pxo"; -+ #clock-cells = <1>; - }; - - lcc: clock-controller@28000000 { diff --git a/target/linux/ipq806x/patches-5.15/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch b/target/linux/ipq806x/patches-5.15/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch deleted file mode 100644 index f3c8f18f1de..00000000000 --- a/target/linux/ipq806x/patches-5.15/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch +++ /dev/null @@ -1,268 +0,0 @@ -From 076ebb6e1799c4c7a1d2e07510d88b9e9b57b551 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 18 Jan 2022 00:03:47 +0100 -Subject: [PATCH v3 13/18] ARM: dts: qcom: add opp table for cpu and l2 for - ipq8064 - -Add opp table for cpu and l2 cache. While the current cpufreq is -the generic one that doesn't scale the L2 cache, we add the l2 -cache opp anyway for the sake of completeness. This will be handy in the -future when a dedicated cpufreq driver is introduced for krait cores -that will correctly scale l2 cache with the core freq. - -Opp-level is set based on the logic of -0: idle level -1: normal level -2: turbo level - -Signed-off-by: Ansuel Smith -Tested-by: Jonathan McDowell ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 99 +++++++++++++++++++++++++++++ - 1 file changed, 99 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -48,6 +48,105 @@ - }; - }; - -+ opp_table_l2: opp_table_l2 { -+ compatible = "operating-points-v2"; -+ -+ opp-384000000 { -+ opp-hz = /bits/ 64 <384000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <100000>; -+ opp-level = <0>; -+ }; -+ -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <1150000>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+ }; -+ -+ opp_table0: opp_table0 { -+ compatible = "operating-points-v2-kryo-cpu"; -+ nvmem-cells = <&speedbin_efuse>; -+ -+ /* -+ * Voltage thresholds are -+ */ -+ opp-384000000 { -+ opp-hz = /bits/ 64 <384000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; -+ opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>; -+ opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>; -+ opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <0>; -+ }; -+ -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; -+ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>; -+ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>; -+ opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; -+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; -+ opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>; -+ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>; -+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; -+ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>; -+ opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>; -+ opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>; -+ opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>; -+ opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+ -+ opp-1400000000 { -+ opp-hz = /bits/ 64 <1400000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>; -+ opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>; -+ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>; -+ opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+ }; -+ - thermal-zones { - tsens_tz_sensor0 { - polling-delay-passive = <0>; ---- a/arch/arm/boot/dts/qcom-ipq8065.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi -@@ -6,3 +6,92 @@ - model = "Qualcomm Technologies, Inc. IPQ8065"; - compatible = "qcom,ipq8065", "qcom,ipq8064"; - }; -+ -+&opp_table_l2 { -+ /delete-node/opp-1200000000; -+ -+ opp-1400000000 { -+ opp-hz = /bits/ 64 <1400000000>; -+ opp-microvolt = <1150000>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+}; -+ -+&opp_table0 { -+ /* -+ * On ipq8065 1.2 ghz freq is not present -+ * Remove it to make cpufreq work and not -+ * complain for missing definition -+ */ -+ -+ /delete-node/opp-1200000000; -+ -+ /* -+ * Voltage thresholds are -+ */ -+ opp-384000000 { -+ opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>; -+ opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>; -+ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>; -+ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>; -+ opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>; -+ opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>; -+ opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>; -+ }; -+ -+ opp-600000000 { -+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; -+ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>; -+ opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>; -+ opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>; -+ opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>; -+ opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>; -+ opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>; -+ }; -+ -+ opp-800000000 { -+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; -+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; -+ opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>; -+ opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>; -+ opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>; -+ opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>; -+ opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>; -+ }; -+ -+ opp-1000000000 { -+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; -+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; -+ opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>; -+ opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>; -+ opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>; -+ opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>; -+ opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>; -+ }; -+ -+ opp-1400000000 { -+ opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>; -+ opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>; -+ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>; -+ opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>; -+ opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>; -+ opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>; -+ opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>; -+ opp-level = <1>; -+ }; -+ -+ opp-1725000000 { -+ opp-hz = /bits/ 64 <1725000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>; -+ opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>; -+ opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>; -+ opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>; -+ opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>; -+ opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>; -+ opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+}; ---- a/arch/arm/boot/dts/qcom-ipq8062.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8062.dtsi -@@ -6,3 +6,39 @@ - model = "Qualcomm Technologies, Inc. IPQ8062"; - compatible = "qcom,ipq8062", "qcom,ipq8064"; - }; -+ -+&opp_table0 { -+ /delete-node/opp-1200000000; -+ /delete-node/opp-1400000000; -+ -+ /* -+ * Voltage thresholds are -+ */ -+ opp-384000000 { -+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; -+ opp-microvolt-speed0-pvs1-v0 = < 925000 878750 971250>; -+ opp-microvolt-speed0-pvs2-v0 = < 875000 831250 918750>; -+ opp-microvolt-speed0-pvs3-v0 = < 800000 760000 840000>; -+ }; -+ -+ opp-600000000 { -+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; -+ opp-microvolt-speed0-pvs1-v0 = < 975000 926250 1023750>; -+ opp-microvolt-speed0-pvs2-v0 = < 925000 878750 971250>; -+ opp-microvolt-speed0-pvs3-v0 = < 850000 807500 892500>; -+ }; -+ -+ opp-800000000 { -+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; -+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; -+ opp-microvolt-speed0-pvs2-v0 = < 995000 945250 1044750>; -+ opp-microvolt-speed0-pvs3-v0 = < 900000 855000 945000>; -+ }; -+ -+ opp-1000000000 { -+ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>; -+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; -+ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>; -+ opp-microvolt-speed0-pvs3-v0 = < 950000 902500 997500>; -+ }; -+}; diff --git a/target/linux/ipq806x/patches-5.15/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch b/target/linux/ipq806x/patches-5.15/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch deleted file mode 100644 index cf27aaa08b6..00000000000 --- a/target/linux/ipq806x/patches-5.15/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch +++ /dev/null @@ -1,153 +0,0 @@ -From 211fc0c0a63c99b68663a27182e643316c2d8cbe Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 18 Jan 2022 00:07:57 +0100 -Subject: [PATCH v3 15/18] ARM: dts: qcom: add multiple missing binding for cpu - and l2 for ipq8064 - -Add multiple binding for cpu node, l2 node and add idle-states -definition for ipq8064 dtsi. - -Signed-off-by: Ansuel Smith -Tested-by: Jonathan McDowell ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 36 +++++++++++++++++++++++++++++ - 1 file changed, 36 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -30,6 +30,15 @@ - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; -+ clocks = <&kraitcc 0>, <&kraitcc 4>; -+ clock-names = "cpu", "l2"; -+ clock-latency = <100000>; -+ operating-points-v2 = <&opp_table0>; -+ voltage-tolerance = <5>; -+ cooling-min-state = <0>; -+ cooling-max-state = <10>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_SPC>; - }; - - cpu1: cpu@1 { -@@ -40,11 +49,35 @@ - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; -+ clocks = <&kraitcc 1>, <&kraitcc 4>; -+ clock-names = "cpu", "l2"; -+ clock-latency = <100000>; -+ operating-points-v2 = <&opp_table0>; -+ voltage-tolerance = <5>; -+ cooling-min-state = <0>; -+ cooling-max-state = <10>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_SPC>; -+ }; -+ -+ idle-states { -+ CPU_SPC: spc { -+ compatible = "qcom,idle-state-spc"; -+ status = "disabled"; -+ entry-latency-us = <400>; -+ exit-latency-us = <900>; -+ min-residency-us = <3000>; -+ }; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; -+ qcom,saw = <&saw_l2>; -+ -+ clocks = <&kraitcc 4>; -+ clock-names = "l2"; -+ operating-points-v2 = <&opp_table_l2>; - }; - }; - ---- a/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi -@@ -2,6 +2,18 @@ - - #include "qcom-ipq8064.dtsi" - -+&cpu0 { -+ cpu-supply = <&smb208_s2a>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&smb208_s2b>; -+}; -+ -+&L2 { -+ l2-supply = <&smb208_s1a>; -+}; -+ - &rpm { - smb208_regulators: regulators { - compatible = "qcom,rpm-smb208-regulators"; ---- a/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi -@@ -2,6 +2,18 @@ - - #include "qcom-ipq8064-v2.0.dtsi" - -+&cpu0 { -+ cpu-supply = <&smb208_s2a>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&smb208_s2b>; -+}; -+ -+&L2 { -+ l2-supply = <&smb208_s1a>; -+}; -+ - &rpm { - smb208_regulators: regulators { - compatible = "qcom,rpm-smb208-regulators"; ---- a/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi -@@ -2,6 +2,18 @@ - - #include "qcom-ipq8062.dtsi" - -+&cpu0 { -+ cpu-supply = <&smb208_s2a>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&smb208_s2b>; -+}; -+ -+&L2 { -+ l2-supply = <&smb208_s1a>; -+}; -+ - &rpm { - smb208_regulators: regulators { - compatible = "qcom,rpm-smb208-regulators"; ---- a/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi -@@ -2,6 +2,18 @@ - - #include "qcom-ipq8065.dtsi" - -+&cpu0 { -+ cpu-supply = <&smb208_s2a>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&smb208_s2b>; -+}; -+ -+&L2 { -+ l2-supply = <&smb208_s1a>; -+}; -+ - &rpm { - smb208_regulators: regulators { - compatible = "qcom,rpm-smb208-regulators"; diff --git a/target/linux/ipq806x/patches-5.15/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch b/target/linux/ipq806x/patches-5.15/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch deleted file mode 100644 index d3f821a6a0f..00000000000 --- a/target/linux/ipq806x/patches-5.15/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 6c94e0184e56f9e9f1f5d5f54b20758433e498d2 Mon Sep 17 00:00:00 2001 -From: Christian 'Ansuel' Marangi -Date: Wed, 15 Jun 2022 16:47:09 +0200 -Subject: [PATCH 1/2] ARM: dts: qcom: fix wrong nad_pins definition for ipq806x - -Fix wrong nand_pings definition for bias-disable pins. - -Signed-off-by: Christian 'Ansuel' Marangi ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 7 ++----- - 1 file changed, 2 insertions(+), 5 deletions(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -559,12 +559,9 @@ - }; - - nand_pins: nand_pins { -- mux { -+ disable { - pins = "gpio34", "gpio35", "gpio36", -- "gpio37", "gpio38", "gpio39", -- "gpio40", "gpio41", "gpio42", -- "gpio43", "gpio44", "gpio45", -- "gpio46", "gpio47"; -+ "gpio37", "gpio38"; - function = "nand"; - drive-strength = <10>; - bias-disable; diff --git a/target/linux/ipq806x/patches-5.15/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch b/target/linux/ipq806x/patches-5.15/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch deleted file mode 100644 index 4a57fc0330b..00000000000 --- a/target/linux/ipq806x/patches-5.15/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch +++ /dev/null @@ -1,188 +0,0 @@ -From 504188183408fac0f61b59f5ed8ea1773fe43669 Mon Sep 17 00:00:00 2001 -From: Christian 'Ansuel' Marangi -Date: Wed, 15 Jun 2022 16:59:30 +0200 -Subject: [PATCH 2/2] ARM: dts: qcom: add MDIO dedicated controller node for - ipq806x - -Add MDIO dedicated controller attached to gmac0 and fix rb3011 dts to -correctly use the new tag. - -Signed-off-by: Christian 'Ansuel' Marangi ---- - arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 134 +++++++++++----------- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 14 +++ - 2 files changed, 81 insertions(+), 67 deletions(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts -+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts -@@ -24,73 +24,6 @@ - device_type = "memory"; - }; - -- mdio0: mdio-0 { -- status = "okay"; -- compatible = "virtual,mdio-gpio"; -- gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, -- <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; -- #address-cells = <1>; -- #size-cells = <0>; -- -- pinctrl-0 = <&mdio0_pins>; -- pinctrl-names = "default"; -- -- switch0: switch@10 { -- compatible = "qca,qca8337"; -- #address-cells = <1>; -- #size-cells = <0>; -- -- dsa,member = <0 0>; -- -- pinctrl-0 = <&sw0_reset_pin>; -- pinctrl-names = "default"; -- -- reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; -- reg = <0x10>; -- -- ports { -- #address-cells = <1>; -- #size-cells = <0>; -- -- switch0cpu: port@0 { -- reg = <0>; -- label = "cpu"; -- ethernet = <&gmac0>; -- phy-mode = "rgmii-id"; -- fixed-link { -- speed = <1000>; -- full-duplex; -- }; -- }; -- -- port@1 { -- reg = <1>; -- label = "sw1"; -- }; -- -- port@2 { -- reg = <2>; -- label = "sw2"; -- }; -- -- port@3 { -- reg = <3>; -- label = "sw3"; -- }; -- -- port@4 { -- reg = <4>; -- label = "sw4"; -- }; -- -- port@5 { -- reg = <5>; -- label = "sw5"; -- }; -- }; -- }; -- }; -- - mdio1: mdio-1 { - status = "okay"; - compatible = "virtual,mdio-gpio"; -@@ -220,6 +153,73 @@ - status = "okay"; - }; - -+&mdio0 { -+ status = "okay"; -+ compatible = "virtual,mdio-gpio"; -+ gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, -+ <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pinctrl-0 = <&mdio0_pins>; -+ pinctrl-names = "default"; -+ -+ switch0: switch@10 { -+ compatible = "qca,qca8337"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ dsa,member = <0 0>; -+ -+ pinctrl-0 = <&sw0_reset_pin>; -+ pinctrl-names = "default"; -+ -+ reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; -+ reg = <0x10>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ switch0cpu: port@0 { -+ reg = <0>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ phy-mode = "rgmii-id"; -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "sw1"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "sw2"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "sw3"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "sw4"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "sw5"; -+ }; -+ }; -+ }; -+}; -+ - &gmac0 { - status = "okay"; - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -1446,6 +1446,20 @@ - }; - }; - -+ mdio0: mdio@37000000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ compatible = "qcom,ipq8064-mdio", "syscon"; -+ reg = <0x37000000 0x200000>; -+ resets = <&gcc GMAC_CORE1_RESET>; -+ reset-names = "stmmaceth"; -+ clocks = <&gcc GMAC_CORE1_CLK>; -+ clock-names = "stmmaceth"; -+ -+ status = "disabled"; -+ }; -+ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; diff --git a/target/linux/ipq806x/patches-5.15/109-v6.1-01-dt-bindings-clock-add-pcm-reset-for-ipq806x-lcc.patch b/target/linux/ipq806x/patches-5.15/109-v6.1-01-dt-bindings-clock-add-pcm-reset-for-ipq806x-lcc.patch deleted file mode 100644 index 72e70b613c8..00000000000 --- a/target/linux/ipq806x/patches-5.15/109-v6.1-01-dt-bindings-clock-add-pcm-reset-for-ipq806x-lcc.patch +++ /dev/null @@ -1,29 +0,0 @@ -From fc7dc1d0c10e8e3d72b68ddae8a61c8aa02a62c1 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 15 Jun 2022 17:13:32 +0200 -Subject: [PATCH v4 1/3] dt-bindings: clock: add pcm reset for ipq806x lcc - -Add pcm reset define for ipq806x lcc. - -Signed-off-by: Christian Marangi -Reviewed-by: Dmitry Baryshkov -Acked-by: Rob Herring ---- -v3: - - Added review tag - - Added ack tag -v2: - - Fix Sob tag - - include/dt-bindings/clock/qcom,lcc-ipq806x.h | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/include/dt-bindings/clock/qcom,lcc-ipq806x.h -+++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h -@@ -19,4 +19,6 @@ - #define SPDIF_CLK 10 - #define AHBIX_CLK 11 - -+#define LCC_PCM_RESET 0 -+ - #endif diff --git a/target/linux/ipq806x/patches-5.15/109-v6.1-02-clk-qcom-lcc-ipq806x-add-reset-definition.patch b/target/linux/ipq806x/patches-5.15/109-v6.1-02-clk-qcom-lcc-ipq806x-add-reset-definition.patch deleted file mode 100644 index 23936513064..00000000000 --- a/target/linux/ipq806x/patches-5.15/109-v6.1-02-clk-qcom-lcc-ipq806x-add-reset-definition.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 3587d768bdf4683a53244be1acca5d095044671f Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 15 Jun 2022 17:19:55 +0200 -Subject: [PATCH v4 2/3] clk: qcom: lcc-ipq806x: add reset definition - -Add reset definition for lcc-ipq806x. - -Signed-off-by: Christian Marangi -Reviewed-by: Dmitry Baryshkov ---- -v3: - - Added review tag -v2: - - Fix Sob tag - - drivers/clk/qcom/lcc-ipq806x.c | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/drivers/clk/qcom/lcc-ipq806x.c -+++ b/drivers/clk/qcom/lcc-ipq806x.c -@@ -22,6 +22,7 @@ - #include "clk-branch.h" - #include "clk-regmap-divider.h" - #include "clk-regmap-mux.h" -+#include "reset.h" - - static struct clk_pll pll4 = { - .l_reg = 0x4, -@@ -405,6 +406,10 @@ static struct clk_regmap *lcc_ipq806x_cl - [AHBIX_CLK] = &ahbix_clk.clkr, - }; - -+static const struct qcom_reset_map lcc_ipq806x_resets[] = { -+ [LCC_PCM_RESET] = { 0x54, 13 }, -+}; -+ - static const struct regmap_config lcc_ipq806x_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, -@@ -417,6 +422,8 @@ static const struct qcom_cc_desc lcc_ipq - .config = &lcc_ipq806x_regmap_config, - .clks = lcc_ipq806x_clks, - .num_clks = ARRAY_SIZE(lcc_ipq806x_clks), -+ .resets = lcc_ipq806x_resets, -+ .num_resets = ARRAY_SIZE(lcc_ipq806x_resets), - }; - - static const struct of_device_id lcc_ipq806x_match_table[] = { diff --git a/target/linux/ipq806x/patches-5.15/109-v6.1-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch b/target/linux/ipq806x/patches-5.15/109-v6.1-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch deleted file mode 100644 index 905dc5bf40b..00000000000 --- a/target/linux/ipq806x/patches-5.15/109-v6.1-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch +++ /dev/null @@ -1,217 +0,0 @@ -From 92ef900a4a53b62e0dc32554eb088a422657606c Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 15 Jun 2022 17:35:13 +0200 -Subject: [PATCH v5 3/3] clk: qcom: lcc-ipq806x: convert to parent data - -Convert lcc-ipq806x driver to parent_data API. - -Signed-off-by: Christian Marangi ---- -v5: -- Fix the same compilation error (don't know what the hell happen - to my buildroot) -v4: -- Fix compilation error -v3: - - Inline pxo pll4 parent - - Change .name from pxo to pxo_board - - drivers/clk/qcom/lcc-ipq806x.c | 77 ++++++++++++++++++---------------- - 1 file changed, 42 insertions(+), 35 deletions(-) - ---- a/drivers/clk/qcom/lcc-ipq806x.c -+++ b/drivers/clk/qcom/lcc-ipq806x.c -@@ -34,7 +34,9 @@ static struct clk_pll pll4 = { - .status_bit = 16, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pll4", -- .parent_names = (const char *[]){ "pxo" }, -+ .parent_data = &(const struct clk_parent_data) { -+ .fw_name = "pxo", .name = "pxo_board", -+ }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -@@ -64,9 +66,9 @@ static const struct parent_map lcc_pxo_p - { P_PLL4, 2 } - }; - --static const char * const lcc_pxo_pll4[] = { -- "pxo", -- "pll4_vote", -+static const struct clk_parent_data lcc_pxo_pll4[] = { -+ { .fw_name = "pxo", .name = "pxo" }, -+ { .fw_name = "pll4_vote", .name = "pll4_vote" }, - }; - - static struct freq_tbl clk_tbl_aif_mi2s[] = { -@@ -131,18 +133,14 @@ static struct clk_rcg mi2s_osr_src = { - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "mi2s_osr_src", -- .parent_names = lcc_pxo_pll4, -- .num_parents = 2, -+ .parent_data = lcc_pxo_pll4, -+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, - }, - }; - --static const char * const lcc_mi2s_parents[] = { -- "mi2s_osr_src", --}; -- - static struct clk_branch mi2s_osr_clk = { - .halt_reg = 0x50, - .halt_bit = 1, -@@ -152,7 +150,9 @@ static struct clk_branch mi2s_osr_clk = - .enable_mask = BIT(17), - .hw.init = &(struct clk_init_data){ - .name = "mi2s_osr_clk", -- .parent_names = lcc_mi2s_parents, -+ .parent_hws = (const struct clk_hw*[]){ -+ &mi2s_osr_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -167,7 +167,9 @@ static struct clk_regmap_div mi2s_div_cl - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mi2s_div_clk", -- .parent_names = lcc_mi2s_parents, -+ .parent_hws = (const struct clk_hw*[]){ -+ &mi2s_osr_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_regmap_div_ops, - }, -@@ -183,7 +185,9 @@ static struct clk_branch mi2s_bit_div_cl - .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ - .name = "mi2s_bit_div_clk", -- .parent_names = (const char *[]){ "mi2s_div_clk" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &mi2s_div_clk.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -191,6 +195,10 @@ static struct clk_branch mi2s_bit_div_cl - }, - }; - -+static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = { -+ { .hw = &mi2s_bit_div_clk.clkr.hw, }, -+ { .fw_name = "mi2s_codec_clk", .name = "mi2s_codec_clk" }, -+}; - - static struct clk_regmap_mux mi2s_bit_clk = { - .reg = 0x48, -@@ -199,11 +207,8 @@ static struct clk_regmap_mux mi2s_bit_cl - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mi2s_bit_clk", -- .parent_names = (const char *[]){ -- "mi2s_bit_div_clk", -- "mi2s_codec_clk", -- }, -- .num_parents = 2, -+ .parent_data = lcc_mi2s_bit_div_codec_clk, -+ .num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk), - .ops = &clk_regmap_mux_closest_ops, - .flags = CLK_SET_RATE_PARENT, - }, -@@ -245,8 +250,8 @@ static struct clk_rcg pcm_src = { - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "pcm_src", -- .parent_names = lcc_pxo_pll4, -- .num_parents = 2, -+ .parent_data = lcc_pxo_pll4, -+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, -@@ -262,7 +267,9 @@ static struct clk_branch pcm_clk_out = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "pcm_clk_out", -- .parent_names = (const char *[]){ "pcm_src" }, -+ .parent_hws = (const struct clk_hw*[]){ -+ &pcm_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -270,6 +277,11 @@ static struct clk_branch pcm_clk_out = { - }, - }; - -+static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = { -+ { .hw = &pcm_clk_out.clkr.hw, }, -+ { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" }, -+}; -+ - static struct clk_regmap_mux pcm_clk = { - .reg = 0x54, - .shift = 10, -@@ -277,11 +289,8 @@ static struct clk_regmap_mux pcm_clk = { - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "pcm_clk", -- .parent_names = (const char *[]){ -- "pcm_clk_out", -- "pcm_codec_clk", -- }, -- .num_parents = 2, -+ .parent_data = lcc_pcm_clk_out_codec_clk, -+ .num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk), - .ops = &clk_regmap_mux_closest_ops, - .flags = CLK_SET_RATE_PARENT, - }, -@@ -325,18 +334,14 @@ static struct clk_rcg spdif_src = { - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "spdif_src", -- .parent_names = lcc_pxo_pll4, -- .num_parents = 2, -+ .parent_data = lcc_pxo_pll4, -+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, - }, - }; - --static const char * const lcc_spdif_parents[] = { -- "spdif_src", --}; -- - static struct clk_branch spdif_clk = { - .halt_reg = 0xd4, - .halt_bit = 1, -@@ -346,7 +351,9 @@ static struct clk_branch spdif_clk = { - .enable_mask = BIT(12), - .hw.init = &(struct clk_init_data){ - .name = "spdif_clk", -- .parent_names = lcc_spdif_parents, -+ .parent_hws = (const struct clk_hw*[]){ -+ &spdif_src.clkr.hw, -+ }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, -@@ -384,8 +391,8 @@ static struct clk_rcg ahbix_clk = { - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "ahbix", -- .parent_names = lcc_pxo_pll4, -- .num_parents = 2, -+ .parent_data = lcc_pxo_pll4, -+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), - .ops = &clk_rcg_lcc_ops, - }, - }, diff --git a/target/linux/ipq806x/patches-5.15/110-01-thermal-qcom-tsens-init-debugfs-only-with-successful.patch b/target/linux/ipq806x/patches-5.15/110-01-thermal-qcom-tsens-init-debugfs-only-with-successful.patch deleted file mode 100644 index 4caa2a9560e..00000000000 --- a/target/linux/ipq806x/patches-5.15/110-01-thermal-qcom-tsens-init-debugfs-only-with-successful.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 8f32d48a309246a80bdca505968085a484d54408 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Mon, 19 Apr 2021 03:01:53 +0200 -Subject: [thermal-next PATCH v2 1/2] thermal: qcom: tsens: init debugfs only with - successful probe - -calibrate and tsens_register can fail or PROBE_DEFER. This will cause a -double or a wrong init of the debugfs information. Init debugfs only -with successful probe fixing warning about directory already present. - -Signed-off-by: Ansuel Smith -Acked-by: Thara Gopinath ---- - drivers/thermal/qcom/tsens.c | 9 ++++++--- - 1 file changed, 6 insertions(+), 3 deletions(-) - ---- a/drivers/thermal/qcom/tsens.c -+++ b/drivers/thermal/qcom/tsens.c -@@ -917,8 +917,6 @@ int __init init_common(struct tsens_priv - if (tsens_version(priv) >= VER_0_1) - tsens_enable_irq(priv); - -- tsens_debug_init(op); -- - err_put_device: - put_device(&op->dev); - return ret; -@@ -1163,7 +1161,12 @@ static int tsens_probe(struct platform_d - } - } - -- return tsens_register(priv); -+ ret = tsens_register(priv); -+ -+ if (!ret) -+ tsens_debug_init(pdev); -+ -+ return ret; - } - - static int tsens_remove(struct platform_device *pdev) diff --git a/target/linux/ipq806x/patches-5.15/110-02-thermal-qcom-tsens-simplify-debugfs-init-function.patch b/target/linux/ipq806x/patches-5.15/110-02-thermal-qcom-tsens-simplify-debugfs-init-function.patch deleted file mode 100644 index add2ab45987..00000000000 --- a/target/linux/ipq806x/patches-5.15/110-02-thermal-qcom-tsens-simplify-debugfs-init-function.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 4204f22060f7a5d42c6ccb4d4c25a6a875571099 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Mon, 19 Apr 2021 03:08:37 +0200 -Subject: [thermal-next PATCH v2 2/2] thermal: qcom: tsens: simplify debugfs init - function - -Simplify debugfs init function. -- Add check for existing dev directory. -- Fix wrong version in dbg_version_show (with version 0.0.0, 0.1.0 was - incorrectly reported) - -Signed-off-by: Ansuel Smith -Reviewed-by: Thara Gopinath ---- - drivers/thermal/qcom/tsens.c | 16 +++++++--------- - 1 file changed, 7 insertions(+), 9 deletions(-) - ---- a/drivers/thermal/qcom/tsens.c -+++ b/drivers/thermal/qcom/tsens.c -@@ -691,7 +691,7 @@ static int dbg_version_show(struct seq_f - return ret; - seq_printf(s, "%d.%d.%d\n", maj_ver, min_ver, step_ver); - } else { -- seq_puts(s, "0.1.0\n"); -+ seq_printf(s, "0.%d.0\n", priv->feat->ver_major); - } - - return 0; -@@ -703,21 +703,17 @@ DEFINE_SHOW_ATTRIBUTE(dbg_sensors); - static void tsens_debug_init(struct platform_device *pdev) - { - struct tsens_priv *priv = platform_get_drvdata(pdev); -- struct dentry *root, *file; - -- root = debugfs_lookup("tsens", NULL); -- if (!root) -+ priv->debug_root = debugfs_lookup("tsens", NULL); -+ if (!priv->debug_root) - priv->debug_root = debugfs_create_dir("tsens", NULL); -- else -- priv->debug_root = root; - -- file = debugfs_lookup("version", priv->debug_root); -- if (!file) -+ if (!debugfs_lookup("version", priv->debug_root)) - debugfs_create_file("version", 0444, priv->debug_root, - pdev, &dbg_version_fops); - - /* A directory for each instance of the TSENS IP */ -- priv->debug = debugfs_create_dir(dev_name(&pdev->dev), priv->debug_root); -+ priv->debug = debugfs_lookup(dev_name(&pdev->dev), priv->debug_root); - debugfs_create_file("sensors", 0444, priv->debug, pdev, &dbg_sensors_fops); - } - #else diff --git a/target/linux/ipq806x/patches-5.15/111-v5.19-01-PM-devfreq-Export-devfreq_get_freq_range-symbol-with.patch b/target/linux/ipq806x/patches-5.15/111-v5.19-01-PM-devfreq-Export-devfreq_get_freq_range-symbol-with.patch deleted file mode 100644 index 6b7a68952ea..00000000000 --- a/target/linux/ipq806x/patches-5.15/111-v5.19-01-PM-devfreq-Export-devfreq_get_freq_range-symbol-with.patch +++ /dev/null @@ -1,113 +0,0 @@ -From 713472e53e6e53c985e283782b0fd76b8ecfd47e Mon Sep 17 00:00:00 2001 -From: Chanwoo Choi -Date: Mon, 1 Mar 2021 02:07:29 +0900 -Subject: [PATCH 1/5] PM / devfreq: Export devfreq_get_freq_range symbol within - devfreq - -In order to get frequency range within devfreq governors, -export devfreq_get_freq_range symbol within devfreq. - -Reviewed-by: Matthias Kaehlcke -Tested-by: Chen-Yu Tsai -Tested-by: Johnson Wang -Signed-off-by: Chanwoo Choi ---- - drivers/devfreq/devfreq.c | 20 ++++++++++++-------- - drivers/devfreq/governor.h | 2 ++ - 2 files changed, 14 insertions(+), 8 deletions(-) - ---- a/drivers/devfreq/devfreq.c -+++ b/drivers/devfreq/devfreq.c -@@ -112,16 +112,16 @@ static unsigned long find_available_max_ - } - - /** -- * get_freq_range() - Get the current freq range -+ * devfreq_get_freq_range() - Get the current freq range - * @devfreq: the devfreq instance - * @min_freq: the min frequency - * @max_freq: the max frequency - * - * This takes into consideration all constraints. - */ --static void get_freq_range(struct devfreq *devfreq, -- unsigned long *min_freq, -- unsigned long *max_freq) -+void devfreq_get_freq_range(struct devfreq *devfreq, -+ unsigned long *min_freq, -+ unsigned long *max_freq) - { - unsigned long *freq_table = devfreq->profile->freq_table; - s32 qos_min_freq, qos_max_freq; -@@ -158,6 +158,7 @@ static void get_freq_range(struct devfre - if (*min_freq > *max_freq) - *min_freq = *max_freq; - } -+EXPORT_SYMBOL(devfreq_get_freq_range); - - /** - * devfreq_get_freq_level() - Lookup freq_table for the frequency -@@ -418,7 +419,7 @@ int devfreq_update_target(struct devfreq - err = devfreq->governor->get_target_freq(devfreq, &freq); - if (err) - return err; -- get_freq_range(devfreq, &min_freq, &max_freq); -+ devfreq_get_freq_range(devfreq, &min_freq, &max_freq); - - if (freq < min_freq) { - freq = min_freq; -@@ -784,6 +785,7 @@ struct devfreq *devfreq_add_device(struc - { - struct devfreq *devfreq; - struct devfreq_governor *governor; -+ unsigned long min_freq, max_freq; - int err = 0; - - if (!dev || !profile || !governor_name) { -@@ -848,6 +850,8 @@ struct devfreq *devfreq_add_device(struc - goto err_dev; - } - -+ devfreq_get_freq_range(devfreq, &min_freq, &max_freq); -+ - devfreq->suspend_freq = dev_pm_opp_get_suspend_opp_freq(dev); - devfreq->opp_table = dev_pm_opp_get_opp_table(dev); - if (IS_ERR(devfreq->opp_table)) -@@ -1559,7 +1563,7 @@ static ssize_t min_freq_show(struct devi - unsigned long min_freq, max_freq; - - mutex_lock(&df->lock); -- get_freq_range(df, &min_freq, &max_freq); -+ devfreq_get_freq_range(df, &min_freq, &max_freq); - mutex_unlock(&df->lock); - - return sprintf(buf, "%lu\n", min_freq); -@@ -1613,7 +1617,7 @@ static ssize_t max_freq_show(struct devi - unsigned long min_freq, max_freq; - - mutex_lock(&df->lock); -- get_freq_range(df, &min_freq, &max_freq); -+ devfreq_get_freq_range(df, &min_freq, &max_freq); - mutex_unlock(&df->lock); - - return sprintf(buf, "%lu\n", max_freq); -@@ -1927,7 +1931,7 @@ static int devfreq_summary_show(struct s - - mutex_lock(&devfreq->lock); - cur_freq = devfreq->previous_freq; -- get_freq_range(devfreq, &min_freq, &max_freq); -+ devfreq_get_freq_range(devfreq, &min_freq, &max_freq); - timer = devfreq->profile->timer; - - if (IS_SUPPORTED_ATTR(devfreq->governor->attrs, POLLING_INTERVAL)) ---- a/drivers/devfreq/governor.h -+++ b/drivers/devfreq/governor.h -@@ -86,6 +86,8 @@ int devfreq_remove_governor(struct devfr - - int devfreq_update_status(struct devfreq *devfreq, unsigned long freq); - int devfreq_update_target(struct devfreq *devfreq, unsigned long freq); -+void devfreq_get_freq_range(struct devfreq *devfreq, unsigned long *min_freq, -+ unsigned long *max_freq); - - static inline int devfreq_update_stats(struct devfreq *df) - { diff --git a/target/linux/ipq806x/patches-5.15/111-v5.19-02-PM-devfreq-Add-cpu-based-scaling-support-to-passive-.patch b/target/linux/ipq806x/patches-5.15/111-v5.19-02-PM-devfreq-Add-cpu-based-scaling-support-to-passive-.patch deleted file mode 100644 index 3dd61985b28..00000000000 --- a/target/linux/ipq806x/patches-5.15/111-v5.19-02-PM-devfreq-Add-cpu-based-scaling-support-to-passive-.patch +++ /dev/null @@ -1,461 +0,0 @@ -From a03dacb0316f74400846aaf144d6c73f4217ca08 Mon Sep 17 00:00:00 2001 -From: Saravana Kannan -Date: Tue, 2 Mar 2021 15:58:21 +0900 -Subject: [PATCH 2/5] PM / devfreq: Add cpu based scaling support to passive - governor - -Many CPU architectures have caches that can scale independent of the -CPUs. Frequency scaling of the caches is necessary to make sure that the -cache is not a performance bottleneck that leads to poor performance and -power. The same idea applies for RAM/DDR. - -To achieve this, this patch adds support for cpu based scaling to the -passive governor. This is accomplished by taking the current frequency -of each CPU frequency domain and then adjust the frequency of the cache -(or any devfreq device) based on the frequency of the CPUs. It listens -to CPU frequency transition notifiers to keep itself up to date on the -current CPU frequency. - -To decide the frequency of the device, the governor does one of the -following: -* Derives the optimal devfreq device opp from required-opps property of - the parent cpu opp_table. - -* Scales the device frequency in proportion to the CPU frequency. So, if - the CPUs are running at their max frequency, the device runs at its - max frequency. If the CPUs are running at their min frequency, the - device runs at its min frequency. It is interpolated for frequencies - in between. - -Tested-by: Chen-Yu Tsai -Tested-by: Johnson Wang -Signed-off-by: Saravana Kannan -[Sibi: Integrated cpu-freqmap governor into passive_governor] -Signed-off-by: Sibi Sankar -[Chanwoo: Fix conflict with latest code and cleanup code] -Signed-off-by: Chanwoo Choi ---- - drivers/devfreq/governor.h | 22 +++ - drivers/devfreq/governor_passive.c | 298 +++++++++++++++++++++++++++-- - include/linux/devfreq.h | 17 +- - 3 files changed, 323 insertions(+), 14 deletions(-) - ---- a/drivers/devfreq/governor.h -+++ b/drivers/devfreq/governor.h -@@ -48,6 +48,28 @@ - #define DEVFREQ_GOV_ATTR_TIMER BIT(1) - - /** -+ * struct devfreq_cpu_data - Hold the per-cpu data -+ * @dev: reference to cpu device. -+ * @first_cpu: the cpumask of the first cpu of a policy. -+ * @opp_table: reference to cpu opp table. -+ * @cur_freq: the current frequency of the cpu. -+ * @min_freq: the min frequency of the cpu. -+ * @max_freq: the max frequency of the cpu. -+ * -+ * This structure stores the required cpu_data of a cpu. -+ * This is auto-populated by the governor. -+ */ -+struct devfreq_cpu_data { -+ struct device *dev; -+ unsigned int first_cpu; -+ -+ struct opp_table *opp_table; -+ unsigned int cur_freq; -+ unsigned int min_freq; -+ unsigned int max_freq; -+}; -+ -+/** - * struct devfreq_governor - Devfreq policy governor - * @node: list node - contains registered devfreq governors - * @name: Governor's name ---- a/drivers/devfreq/governor_passive.c -+++ b/drivers/devfreq/governor_passive.c -@@ -8,11 +8,85 @@ - */ - - #include -+#include -+#include -+#include -+#include - #include - #include - #include "governor.h" - --static int devfreq_passive_get_target_freq(struct devfreq *devfreq, -+#define HZ_PER_KHZ 1000 -+ -+static unsigned long get_target_freq_by_required_opp(struct device *p_dev, -+ struct opp_table *p_opp_table, -+ struct opp_table *opp_table, -+ unsigned long *freq) -+{ -+ struct dev_pm_opp *opp = NULL, *p_opp = NULL; -+ unsigned long target_freq; -+ -+ if (!p_dev || !p_opp_table || !opp_table || !freq) -+ return 0; -+ -+ p_opp = devfreq_recommended_opp(p_dev, freq, 0); -+ if (IS_ERR(p_opp)) -+ return 0; -+ -+ opp = dev_pm_opp_xlate_required_opp(p_opp_table, opp_table, p_opp); -+ dev_pm_opp_put(p_opp); -+ -+ if (IS_ERR(opp)) -+ return 0; -+ -+ target_freq = dev_pm_opp_get_freq(opp); -+ dev_pm_opp_put(opp); -+ -+ return target_freq; -+} -+ -+static int get_target_freq_with_cpufreq(struct devfreq *devfreq, -+ unsigned long *target_freq) -+{ -+ struct devfreq_passive_data *p_data = -+ (struct devfreq_passive_data *)devfreq->data; -+ struct devfreq_cpu_data *parent_cpu_data; -+ unsigned long cpu, cpu_cur, cpu_min, cpu_max, cpu_percent; -+ unsigned long dev_min, dev_max; -+ unsigned long freq = 0; -+ -+ for_each_online_cpu(cpu) { -+ parent_cpu_data = p_data->parent_cpu_data[cpu]; -+ if (!parent_cpu_data || parent_cpu_data->first_cpu != cpu) -+ continue; -+ -+ /* Get target freq via required opps */ -+ cpu_cur = parent_cpu_data->cur_freq * HZ_PER_KHZ; -+ freq = get_target_freq_by_required_opp(parent_cpu_data->dev, -+ parent_cpu_data->opp_table, -+ devfreq->opp_table, &cpu_cur); -+ if (freq) { -+ *target_freq = max(freq, *target_freq); -+ continue; -+ } -+ -+ /* Use interpolation if required opps is not available */ -+ devfreq_get_freq_range(devfreq, &dev_min, &dev_max); -+ -+ cpu_min = parent_cpu_data->min_freq; -+ cpu_max = parent_cpu_data->max_freq; -+ cpu_cur = parent_cpu_data->cur_freq; -+ -+ cpu_percent = ((cpu_cur - cpu_min) * 100) / (cpu_max - cpu_min); -+ freq = dev_min + mult_frac(dev_max - dev_min, cpu_percent, 100); -+ -+ *target_freq = max(freq, *target_freq); -+ } -+ -+ return 0; -+} -+ -+static int get_target_freq_with_devfreq(struct devfreq *devfreq, - unsigned long *freq) - { - struct devfreq_passive_data *p_data -@@ -99,6 +173,181 @@ no_required_opp: - return 0; - } - -+static int devfreq_passive_get_target_freq(struct devfreq *devfreq, -+ unsigned long *freq) -+{ -+ struct devfreq_passive_data *p_data = -+ (struct devfreq_passive_data *)devfreq->data; -+ int ret; -+ -+ if (!p_data) -+ return -EINVAL; -+ -+ /* -+ * If the devfreq device with passive governor has the specific method -+ * to determine the next frequency, should use the get_target_freq() -+ * of struct devfreq_passive_data. -+ */ -+ if (p_data->get_target_freq) -+ return p_data->get_target_freq(devfreq, freq); -+ -+ switch (p_data->parent_type) { -+ case DEVFREQ_PARENT_DEV: -+ ret = get_target_freq_with_devfreq(devfreq, freq); -+ break; -+ case CPUFREQ_PARENT_DEV: -+ ret = get_target_freq_with_cpufreq(devfreq, freq); -+ break; -+ default: -+ ret = -EINVAL; -+ dev_err(&devfreq->dev, "Invalid parent type\n"); -+ break; -+ } -+ -+ return ret; -+} -+ -+static int cpufreq_passive_notifier_call(struct notifier_block *nb, -+ unsigned long event, void *ptr) -+{ -+ struct devfreq_passive_data *p_data = -+ container_of(nb, struct devfreq_passive_data, nb); -+ struct devfreq *devfreq = (struct devfreq *)p_data->this; -+ struct devfreq_cpu_data *parent_cpu_data; -+ struct cpufreq_freqs *freqs = ptr; -+ unsigned int cur_freq; -+ int ret; -+ -+ if (event != CPUFREQ_POSTCHANGE || !freqs || -+ !p_data->parent_cpu_data[freqs->policy->cpu]) -+ return 0; -+ -+ parent_cpu_data = p_data->parent_cpu_data[freqs->policy->cpu]; -+ if (parent_cpu_data->cur_freq == freqs->new) -+ return 0; -+ -+ cur_freq = parent_cpu_data->cur_freq; -+ parent_cpu_data->cur_freq = freqs->new; -+ -+ mutex_lock(&devfreq->lock); -+ ret = devfreq_update_target(devfreq, freqs->new); -+ mutex_unlock(&devfreq->lock); -+ if (ret) { -+ parent_cpu_data->cur_freq = cur_freq; -+ dev_err(&devfreq->dev, "failed to update the frequency.\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int cpufreq_passive_unregister_notifier(struct devfreq *devfreq) -+{ -+ struct devfreq_passive_data *p_data -+ = (struct devfreq_passive_data *)devfreq->data; -+ struct devfreq_cpu_data *parent_cpu_data; -+ int cpu, ret; -+ -+ if (p_data->nb.notifier_call) { -+ ret = cpufreq_unregister_notifier(&p_data->nb, -+ CPUFREQ_TRANSITION_NOTIFIER); -+ if (ret < 0) -+ return ret; -+ } -+ -+ for_each_possible_cpu(cpu) { -+ parent_cpu_data = p_data->parent_cpu_data[cpu]; -+ if (!parent_cpu_data) -+ continue; -+ -+ if (parent_cpu_data->opp_table) -+ dev_pm_opp_put_opp_table(parent_cpu_data->opp_table); -+ kfree(parent_cpu_data); -+ } -+ -+ return 0; -+} -+ -+static int cpufreq_passive_register_notifier(struct devfreq *devfreq) -+{ -+ struct devfreq_passive_data *p_data -+ = (struct devfreq_passive_data *)devfreq->data; -+ struct device *dev = devfreq->dev.parent; -+ struct opp_table *opp_table = NULL; -+ struct devfreq_cpu_data *parent_cpu_data; -+ struct cpufreq_policy *policy; -+ struct device *cpu_dev; -+ unsigned int cpu; -+ int ret; -+ -+ p_data->nb.notifier_call = cpufreq_passive_notifier_call; -+ ret = cpufreq_register_notifier(&p_data->nb, CPUFREQ_TRANSITION_NOTIFIER); -+ if (ret) { -+ dev_err(dev, "failed to register cpufreq notifier\n"); -+ p_data->nb.notifier_call = NULL; -+ goto err; -+ } -+ -+ for_each_possible_cpu(cpu) { -+ if (p_data->parent_cpu_data[cpu]) -+ continue; -+ -+ policy = cpufreq_cpu_get(cpu); -+ if (!policy) { -+ ret = -EPROBE_DEFER; -+ goto err; -+ } -+ -+ parent_cpu_data = kzalloc(sizeof(*parent_cpu_data), -+ GFP_KERNEL); -+ if (!parent_cpu_data) { -+ ret = -ENOMEM; -+ goto err_put_policy; -+ } -+ -+ cpu_dev = get_cpu_device(cpu); -+ if (!cpu_dev) { -+ dev_err(dev, "failed to get cpu device\n"); -+ ret = -ENODEV; -+ goto err_free_cpu_data; -+ } -+ -+ opp_table = dev_pm_opp_get_opp_table(cpu_dev); -+ if (IS_ERR(opp_table)) { -+ dev_err(dev, "failed to get opp_table of cpu%d\n", cpu); -+ ret = PTR_ERR(opp_table); -+ goto err_free_cpu_data; -+ } -+ -+ parent_cpu_data->dev = cpu_dev; -+ parent_cpu_data->opp_table = opp_table; -+ parent_cpu_data->first_cpu = cpumask_first(policy->related_cpus); -+ parent_cpu_data->cur_freq = policy->cur; -+ parent_cpu_data->min_freq = policy->cpuinfo.min_freq; -+ parent_cpu_data->max_freq = policy->cpuinfo.max_freq; -+ -+ p_data->parent_cpu_data[cpu] = parent_cpu_data; -+ cpufreq_cpu_put(policy); -+ } -+ -+ mutex_lock(&devfreq->lock); -+ ret = devfreq_update_target(devfreq, 0L); -+ mutex_unlock(&devfreq->lock); -+ if (ret) -+ dev_err(dev, "failed to update the frequency\n"); -+ -+ return ret; -+ -+err_free_cpu_data: -+ kfree(parent_cpu_data); -+err_put_policy: -+ cpufreq_cpu_put(policy); -+err: -+ WARN_ON(cpufreq_passive_unregister_notifier(devfreq)); -+ -+ return ret; -+} -+ - static int devfreq_passive_notifier_call(struct notifier_block *nb, - unsigned long event, void *ptr) - { -@@ -131,30 +380,55 @@ static int devfreq_passive_notifier_call - return NOTIFY_DONE; - } - --static int devfreq_passive_event_handler(struct devfreq *devfreq, -- unsigned int event, void *data) -+static int devfreq_passive_unregister_notifier(struct devfreq *devfreq) -+{ -+ struct devfreq_passive_data *p_data -+ = (struct devfreq_passive_data *)devfreq->data; -+ struct devfreq *parent = (struct devfreq *)p_data->parent; -+ struct notifier_block *nb = &p_data->nb; -+ -+ return devfreq_unregister_notifier(parent, nb, DEVFREQ_TRANSITION_NOTIFIER); -+} -+ -+static int devfreq_passive_register_notifier(struct devfreq *devfreq) - { - struct devfreq_passive_data *p_data - = (struct devfreq_passive_data *)devfreq->data; - struct devfreq *parent = (struct devfreq *)p_data->parent; - struct notifier_block *nb = &p_data->nb; -- int ret = 0; - - if (!parent) - return -EPROBE_DEFER; - -+ nb->notifier_call = devfreq_passive_notifier_call; -+ return devfreq_register_notifier(parent, nb, DEVFREQ_TRANSITION_NOTIFIER); -+} -+ -+static int devfreq_passive_event_handler(struct devfreq *devfreq, -+ unsigned int event, void *data) -+{ -+ struct devfreq_passive_data *p_data -+ = (struct devfreq_passive_data *)devfreq->data; -+ int ret = -EINVAL; -+ -+ if (!p_data) -+ return -EINVAL; -+ -+ if (!p_data->this) -+ p_data->this = devfreq; -+ - switch (event) { - case DEVFREQ_GOV_START: -- if (!p_data->this) -- p_data->this = devfreq; -- -- nb->notifier_call = devfreq_passive_notifier_call; -- ret = devfreq_register_notifier(parent, nb, -- DEVFREQ_TRANSITION_NOTIFIER); -+ if (p_data->parent_type == DEVFREQ_PARENT_DEV) -+ ret = devfreq_passive_register_notifier(devfreq); -+ else if (p_data->parent_type == CPUFREQ_PARENT_DEV) -+ ret = cpufreq_passive_register_notifier(devfreq); - break; - case DEVFREQ_GOV_STOP: -- WARN_ON(devfreq_unregister_notifier(parent, nb, -- DEVFREQ_TRANSITION_NOTIFIER)); -+ if (p_data->parent_type == DEVFREQ_PARENT_DEV) -+ WARN_ON(devfreq_passive_unregister_notifier(devfreq)); -+ else if (p_data->parent_type == CPUFREQ_PARENT_DEV) -+ WARN_ON(cpufreq_passive_unregister_notifier(devfreq)); - break; - default: - break; ---- a/include/linux/devfreq.h -+++ b/include/linux/devfreq.h -@@ -38,6 +38,7 @@ enum devfreq_timer { - - struct devfreq; - struct devfreq_governor; -+struct devfreq_cpu_data; - struct thermal_cooling_device; - - /** -@@ -289,6 +290,11 @@ struct devfreq_simple_ondemand_data { - #endif - - #if IS_ENABLED(CONFIG_DEVFREQ_GOV_PASSIVE) -+enum devfreq_parent_dev_type { -+ DEVFREQ_PARENT_DEV, -+ CPUFREQ_PARENT_DEV, -+}; -+ - /** - * struct devfreq_passive_data - ``void *data`` fed to struct devfreq - * and devfreq_add_device -@@ -300,8 +306,11 @@ struct devfreq_simple_ondemand_data { - * using governors except for passive governor. - * If the devfreq device has the specific method to decide - * the next frequency, should use this callback. -- * @this: the devfreq instance of own device. -- * @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER list -+ * @parent_type: the parent type of the device. -+ * @this: the devfreq instance of own device. -+ * @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER or -+ * CPUFREQ_TRANSITION_NOTIFIER list. -+ * @parent_cpu_data: the state min/max/current frequency of all online cpu's. - * - * The devfreq_passive_data have to set the devfreq instance of parent - * device with governors except for the passive governor. But, don't need to -@@ -315,9 +324,13 @@ struct devfreq_passive_data { - /* Optional callback to decide the next frequency of passvice device */ - int (*get_target_freq)(struct devfreq *this, unsigned long *freq); - -+ /* Should set the type of parent device */ -+ enum devfreq_parent_dev_type parent_type; -+ - /* For passive governor's internal use. Don't need to set them */ - struct devfreq *this; - struct notifier_block nb; -+ struct devfreq_cpu_data *parent_cpu_data[NR_CPUS]; - }; - #endif - diff --git a/target/linux/ipq806x/patches-5.15/111-v5.19-03-PM-devfreq-passive-Reduce-duplicate-code-when-passiv.patch b/target/linux/ipq806x/patches-5.15/111-v5.19-03-PM-devfreq-passive-Reduce-duplicate-code-when-passiv.patch deleted file mode 100644 index cb10bd1b62c..00000000000 --- a/target/linux/ipq806x/patches-5.15/111-v5.19-03-PM-devfreq-passive-Reduce-duplicate-code-when-passiv.patch +++ /dev/null @@ -1,110 +0,0 @@ -From 05723e71234b60a1a47313ea1a889797ec648f1c Mon Sep 17 00:00:00 2001 -From: Chanwoo Choi -Date: Tue, 2 Mar 2021 17:22:50 +0900 -Subject: [PATCH 3/5] PM / devfreq: passive: Reduce duplicate code when - passive_devfreq case - -In order to keep the consistent coding style between passive_devfreq -and passive_cpufreq, use common code for handling required opp property. -Also remove the unneed conditional statement and unify the comment -of both passive_devfreq and passive_cpufreq when getting the target frequency. - -Tested-by: Chen-Yu Tsai -Tested-by: Johnson Wang -Signed-off-by: Chanwoo Choi ---- - drivers/devfreq/governor_passive.c | 66 ++++-------------------------- - 1 file changed, 8 insertions(+), 58 deletions(-) - ---- a/drivers/devfreq/governor_passive.c -+++ b/drivers/devfreq/governor_passive.c -@@ -93,65 +93,16 @@ static int get_target_freq_with_devfreq( - = (struct devfreq_passive_data *)devfreq->data; - struct devfreq *parent_devfreq = (struct devfreq *)p_data->parent; - unsigned long child_freq = ULONG_MAX; -- struct dev_pm_opp *opp, *p_opp; - int i, count; - -- /* -- * If the devfreq device with passive governor has the specific method -- * to determine the next frequency, should use the get_target_freq() -- * of struct devfreq_passive_data. -- */ -- if (p_data->get_target_freq) -- return p_data->get_target_freq(devfreq, freq); -- -- /* -- * If the parent and passive devfreq device uses the OPP table, -- * get the next frequency by using the OPP table. -- */ -- -- /* -- * - parent devfreq device uses the governors except for passive. -- * - passive devfreq device uses the passive governor. -- * -- * Each devfreq has the OPP table. After deciding the new frequency -- * from the governor of parent devfreq device, the passive governor -- * need to get the index of new frequency on OPP table of parent -- * device. And then the index is used for getting the suitable -- * new frequency for passive devfreq device. -- */ -- if (!devfreq->profile || !devfreq->profile->freq_table -- || devfreq->profile->max_state <= 0) -- return -EINVAL; -- -- /* -- * The passive governor have to get the correct frequency from OPP -- * list of parent device. Because in this case, *freq is temporary -- * value which is decided by ondemand governor. -- */ -- if (devfreq->opp_table && parent_devfreq->opp_table) { -- p_opp = devfreq_recommended_opp(parent_devfreq->dev.parent, -- freq, 0); -- if (IS_ERR(p_opp)) -- return PTR_ERR(p_opp); -- -- opp = dev_pm_opp_xlate_required_opp(parent_devfreq->opp_table, -- devfreq->opp_table, p_opp); -- dev_pm_opp_put(p_opp); -- -- if (IS_ERR(opp)) -- goto no_required_opp; -- -- *freq = dev_pm_opp_get_freq(opp); -- dev_pm_opp_put(opp); -- -- return 0; -- } -+ /* Get target freq via required opps */ -+ child_freq = get_target_freq_by_required_opp(parent_devfreq->dev.parent, -+ parent_devfreq->opp_table, -+ devfreq->opp_table, freq); -+ if (child_freq) -+ goto out; - --no_required_opp: -- /* -- * Get the OPP table's index of decided frequency by governor -- * of parent device. -- */ -+ /* Use interpolation if required opps is not available */ - for (i = 0; i < parent_devfreq->profile->max_state; i++) - if (parent_devfreq->profile->freq_table[i] == *freq) - break; -@@ -159,7 +110,6 @@ no_required_opp: - if (i == parent_devfreq->profile->max_state) - return -EINVAL; - -- /* Get the suitable frequency by using index of parent device. */ - if (i < devfreq->profile->max_state) { - child_freq = devfreq->profile->freq_table[i]; - } else { -@@ -167,7 +117,7 @@ no_required_opp: - child_freq = devfreq->profile->freq_table[count - 1]; - } - -- /* Return the suitable frequency for passive device. */ -+out: - *freq = child_freq; - - return 0; diff --git a/target/linux/ipq806x/patches-5.15/111-v5.19-04-PM-devfreq-passive-Keep-cpufreq_policy-for-possible-.patch b/target/linux/ipq806x/patches-5.15/111-v5.19-04-PM-devfreq-passive-Keep-cpufreq_policy-for-possible-.patch deleted file mode 100644 index 9ef02d0ea35..00000000000 --- a/target/linux/ipq806x/patches-5.15/111-v5.19-04-PM-devfreq-passive-Keep-cpufreq_policy-for-possible-.patch +++ /dev/null @@ -1,232 +0,0 @@ -From 26984d9d581e5049bd75091d2e789b9cc3ea12e0 Mon Sep 17 00:00:00 2001 -From: Chanwoo Choi -Date: Wed, 27 Apr 2022 03:49:19 +0900 -Subject: [PATCH 4/5] PM / devfreq: passive: Keep cpufreq_policy for possible - cpus - -The passive governor requires the cpu data to get the next target frequency -of devfreq device if depending on cpu. In order to reduce the unnecessary -memory data, keep cpufreq_policy data for possible cpus instead of NR_CPU. - -Tested-by: Chen-Yu Tsai -Tested-by: Johnson Wang -Signed-off-by: Chanwoo Choi ---- - drivers/devfreq/governor.h | 3 ++ - drivers/devfreq/governor_passive.c | 75 +++++++++++++++++++++++------- - include/linux/devfreq.h | 4 +- - 3 files changed, 64 insertions(+), 18 deletions(-) - ---- a/drivers/devfreq/governor.h -+++ b/drivers/devfreq/governor.h -@@ -49,6 +49,7 @@ - - /** - * struct devfreq_cpu_data - Hold the per-cpu data -+ * @node: list node - * @dev: reference to cpu device. - * @first_cpu: the cpumask of the first cpu of a policy. - * @opp_table: reference to cpu opp table. -@@ -60,6 +61,8 @@ - * This is auto-populated by the governor. - */ - struct devfreq_cpu_data { -+ struct list_head node; -+ - struct device *dev; - unsigned int first_cpu; - ---- a/drivers/devfreq/governor_passive.c -+++ b/drivers/devfreq/governor_passive.c -@@ -1,4 +1,4 @@ --// SPDX-License-Identifier: GPL-2.0-only -+ // SPDX-License-Identifier: GPL-2.0-only - /* - * linux/drivers/devfreq/governor_passive.c - * -@@ -18,6 +18,22 @@ - - #define HZ_PER_KHZ 1000 - -+static struct devfreq_cpu_data * -+get_parent_cpu_data(struct devfreq_passive_data *p_data, -+ struct cpufreq_policy *policy) -+{ -+ struct devfreq_cpu_data *parent_cpu_data; -+ -+ if (!p_data || !policy) -+ return NULL; -+ -+ list_for_each_entry(parent_cpu_data, &p_data->cpu_data_list, node) -+ if (parent_cpu_data->first_cpu == cpumask_first(policy->related_cpus)) -+ return parent_cpu_data; -+ -+ return NULL; -+} -+ - static unsigned long get_target_freq_by_required_opp(struct device *p_dev, - struct opp_table *p_opp_table, - struct opp_table *opp_table, -@@ -51,14 +67,24 @@ static int get_target_freq_with_cpufreq( - struct devfreq_passive_data *p_data = - (struct devfreq_passive_data *)devfreq->data; - struct devfreq_cpu_data *parent_cpu_data; -+ struct cpufreq_policy *policy; - unsigned long cpu, cpu_cur, cpu_min, cpu_max, cpu_percent; - unsigned long dev_min, dev_max; - unsigned long freq = 0; -+ int ret = 0; - - for_each_online_cpu(cpu) { -- parent_cpu_data = p_data->parent_cpu_data[cpu]; -- if (!parent_cpu_data || parent_cpu_data->first_cpu != cpu) -+ policy = cpufreq_cpu_get(cpu); -+ if (!policy) { -+ ret = -EINVAL; -+ continue; -+ } -+ -+ parent_cpu_data = get_parent_cpu_data(p_data, policy); -+ if (!parent_cpu_data) { -+ cpufreq_cpu_put(policy); - continue; -+ } - - /* Get target freq via required opps */ - cpu_cur = parent_cpu_data->cur_freq * HZ_PER_KHZ; -@@ -67,6 +93,7 @@ static int get_target_freq_with_cpufreq( - devfreq->opp_table, &cpu_cur); - if (freq) { - *target_freq = max(freq, *target_freq); -+ cpufreq_cpu_put(policy); - continue; - } - -@@ -81,9 +108,10 @@ static int get_target_freq_with_cpufreq( - freq = dev_min + mult_frac(dev_max - dev_min, cpu_percent, 100); - - *target_freq = max(freq, *target_freq); -+ cpufreq_cpu_put(policy); - } - -- return 0; -+ return ret; - } - - static int get_target_freq_with_devfreq(struct devfreq *devfreq, -@@ -168,12 +196,11 @@ static int cpufreq_passive_notifier_call - unsigned int cur_freq; - int ret; - -- if (event != CPUFREQ_POSTCHANGE || !freqs || -- !p_data->parent_cpu_data[freqs->policy->cpu]) -+ if (event != CPUFREQ_POSTCHANGE || !freqs) - return 0; - -- parent_cpu_data = p_data->parent_cpu_data[freqs->policy->cpu]; -- if (parent_cpu_data->cur_freq == freqs->new) -+ parent_cpu_data = get_parent_cpu_data(p_data, freqs->policy); -+ if (!parent_cpu_data || parent_cpu_data->cur_freq == freqs->new) - return 0; - - cur_freq = parent_cpu_data->cur_freq; -@@ -196,7 +223,7 @@ static int cpufreq_passive_unregister_no - struct devfreq_passive_data *p_data - = (struct devfreq_passive_data *)devfreq->data; - struct devfreq_cpu_data *parent_cpu_data; -- int cpu, ret; -+ int cpu, ret = 0; - - if (p_data->nb.notifier_call) { - ret = cpufreq_unregister_notifier(&p_data->nb, -@@ -206,16 +233,26 @@ static int cpufreq_passive_unregister_no - } - - for_each_possible_cpu(cpu) { -- parent_cpu_data = p_data->parent_cpu_data[cpu]; -- if (!parent_cpu_data) -+ struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); -+ if (!policy) { -+ ret = -EINVAL; -+ continue; -+ } -+ -+ parent_cpu_data = get_parent_cpu_data(p_data, policy); -+ if (!parent_cpu_data) { -+ cpufreq_cpu_put(policy); - continue; -+ } - -+ list_del(&parent_cpu_data->node); - if (parent_cpu_data->opp_table) - dev_pm_opp_put_opp_table(parent_cpu_data->opp_table); - kfree(parent_cpu_data); -+ cpufreq_cpu_put(policy); - } - -- return 0; -+ return ret; - } - - static int cpufreq_passive_register_notifier(struct devfreq *devfreq) -@@ -230,6 +267,9 @@ static int cpufreq_passive_register_noti - unsigned int cpu; - int ret; - -+ p_data->cpu_data_list -+ = (struct list_head)LIST_HEAD_INIT(p_data->cpu_data_list); -+ - p_data->nb.notifier_call = cpufreq_passive_notifier_call; - ret = cpufreq_register_notifier(&p_data->nb, CPUFREQ_TRANSITION_NOTIFIER); - if (ret) { -@@ -239,15 +279,18 @@ static int cpufreq_passive_register_noti - } - - for_each_possible_cpu(cpu) { -- if (p_data->parent_cpu_data[cpu]) -- continue; -- - policy = cpufreq_cpu_get(cpu); - if (!policy) { - ret = -EPROBE_DEFER; - goto err; - } - -+ parent_cpu_data = get_parent_cpu_data(p_data, policy); -+ if (parent_cpu_data) { -+ cpufreq_cpu_put(policy); -+ continue; -+ } -+ - parent_cpu_data = kzalloc(sizeof(*parent_cpu_data), - GFP_KERNEL); - if (!parent_cpu_data) { -@@ -276,7 +319,7 @@ static int cpufreq_passive_register_noti - parent_cpu_data->min_freq = policy->cpuinfo.min_freq; - parent_cpu_data->max_freq = policy->cpuinfo.max_freq; - -- p_data->parent_cpu_data[cpu] = parent_cpu_data; -+ list_add_tail(&parent_cpu_data->node, &p_data->cpu_data_list); - cpufreq_cpu_put(policy); - } - ---- a/include/linux/devfreq.h -+++ b/include/linux/devfreq.h -@@ -310,7 +310,7 @@ enum devfreq_parent_dev_type { - * @this: the devfreq instance of own device. - * @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER or - * CPUFREQ_TRANSITION_NOTIFIER list. -- * @parent_cpu_data: the state min/max/current frequency of all online cpu's. -+ * @cpu_data_list: the list of cpu frequency data for all cpufreq_policy. - * - * The devfreq_passive_data have to set the devfreq instance of parent - * device with governors except for the passive governor. But, don't need to -@@ -330,7 +330,7 @@ struct devfreq_passive_data { - /* For passive governor's internal use. Don't need to set them */ - struct devfreq *this; - struct notifier_block nb; -- struct devfreq_cpu_data *parent_cpu_data[NR_CPUS]; -+ struct list_head cpu_data_list; - }; - #endif - diff --git a/target/linux/ipq806x/patches-5.15/111-v5.19-05-PM-devfreq-passive-Return-non-error-when-not-support.patch b/target/linux/ipq806x/patches-5.15/111-v5.19-05-PM-devfreq-passive-Return-non-error-when-not-support.patch deleted file mode 100644 index 69160fd77a5..00000000000 --- a/target/linux/ipq806x/patches-5.15/111-v5.19-05-PM-devfreq-passive-Return-non-error-when-not-support.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 42d2607d91c4ec37ea1970899c2d614824f3014b Mon Sep 17 00:00:00 2001 -From: Chanwoo Choi -Date: Thu, 19 May 2022 10:07:53 +0900 -Subject: [PATCH 5/5] PM / devfreq: passive: Return non-error when - not-supported event is required - -Each devfreq governor specifies the supported governor event -such as GOV_START and GOV_STOP. When not-supported event is required, -just return non-error. But, commit ce9a0d88d97a ("PM / devfreq: Add -cpu based scaling support to passive governor") returned the error -value. So that return non-error value when not-supported event is required. - -Fixes: ce9a0d88d97a ("PM / devfreq: Add cpu based scaling support to passive governor") -Reported-by: Marek Szyprowski -Signed-off-by: Chanwoo Choi -Signed-off-by: Rafael J. Wysocki ---- - drivers/devfreq/governor_passive.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/devfreq/governor_passive.c -+++ b/drivers/devfreq/governor_passive.c -@@ -402,7 +402,7 @@ static int devfreq_passive_event_handler - { - struct devfreq_passive_data *p_data - = (struct devfreq_passive_data *)devfreq->data; -- int ret = -EINVAL; -+ int ret = 0; - - if (!p_data) - return -EINVAL; diff --git a/target/linux/ipq806x/patches-5.15/112-v5.19-PM-devfreq-Fix-kernel-warning-with-cpufreq-passive-r.patch b/target/linux/ipq806x/patches-5.15/112-v5.19-PM-devfreq-Fix-kernel-warning-with-cpufreq-passive-r.patch deleted file mode 100644 index 3d2bb2de05b..00000000000 --- a/target/linux/ipq806x/patches-5.15/112-v5.19-PM-devfreq-Fix-kernel-warning-with-cpufreq-passive-r.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 82c66d2bbbeda9e493487e7413769087a0b46250 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Mon, 20 Jun 2022 00:29:39 +0200 -Subject: [PATCH 1/1] PM / devfreq: Fix kernel warning with cpufreq passive - register fail - -Remove cpufreq_passive_unregister_notifier from -cpufreq_passive_register_notifier in case of error as devfreq core -already call unregister on GOV_START fail. - -This fix the kernel always printing a WARN on governor PROBE_DEFER as -cpufreq_passive_unregister_notifier is called two times and return -error on the second call as the cpufreq is already unregistered. - -Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor") -Signed-off-by: Christian Marangi -Signed-off-by: Chanwoo Choi ---- - drivers/devfreq/governor_passive.c | 1 - - 1 file changed, 1 deletion(-) - ---- a/drivers/devfreq/governor_passive.c -+++ b/drivers/devfreq/governor_passive.c -@@ -336,7 +336,6 @@ err_free_cpu_data: - err_put_policy: - cpufreq_cpu_put(policy); - err: -- WARN_ON(cpufreq_passive_unregister_notifier(devfreq)); - - return ret; - } diff --git a/target/linux/ipq806x/patches-5.15/113-v5.19-01-PM-devfreq-Fix-cpufreq-passive-unregister-errorin.patch b/target/linux/ipq806x/patches-5.15/113-v5.19-01-PM-devfreq-Fix-cpufreq-passive-unregister-errorin.patch deleted file mode 100644 index 08834245486..00000000000 --- a/target/linux/ipq806x/patches-5.15/113-v5.19-01-PM-devfreq-Fix-cpufreq-passive-unregister-errorin.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 8953603eb5447be52f6fc3d8fcae1b3ce9899189 Mon Sep 17 00:00:00 2001 -From: Christian 'Ansuel' Marangi -Date: Mon, 6 Jun 2022 11:58:49 +0200 -Subject: [PATCH v4 1/4] PM / devfreq: Fix cpufreq passive unregister erroring - on PROBE_DEFER - -With the passive governor, the cpu based scaling can PROBE_DEFER due to -the fact that CPU policy are not ready. -The cpufreq passive unregister notifier is called both from the -GOV_START errors and for the GOV_STOP and assume the notifier is -successfully registred every time. With GOV_START failing it's wrong to -loop over each possible CPU since the register path has failed for -some CPU policy not ready. Change the logic and unregister the notifer -based on the current allocated parent_cpu_data list to correctly handle -errors and the governor unregister path. - -Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor") -Signed-off-by: Christian 'Ansuel' Marangi ---- - drivers/devfreq/governor_passive.c | 39 +++++++++++++----------------- - 1 file changed, 17 insertions(+), 22 deletions(-) - ---- a/drivers/devfreq/governor_passive.c -+++ b/drivers/devfreq/governor_passive.c -@@ -34,6 +34,20 @@ get_parent_cpu_data(struct devfreq_passi - return NULL; - } - -+static void delete_parent_cpu_data(struct devfreq_passive_data *p_data) -+{ -+ struct devfreq_cpu_data *parent_cpu_data, *tmp; -+ -+ list_for_each_entry_safe(parent_cpu_data, tmp, &p_data->cpu_data_list, node) { -+ list_del(&parent_cpu_data->node); -+ -+ if (parent_cpu_data->opp_table) -+ dev_pm_opp_put_opp_table(parent_cpu_data->opp_table); -+ -+ kfree(parent_cpu_data); -+ } -+} -+ - static unsigned long get_target_freq_by_required_opp(struct device *p_dev, - struct opp_table *p_opp_table, - struct opp_table *opp_table, -@@ -222,8 +236,7 @@ static int cpufreq_passive_unregister_no - { - struct devfreq_passive_data *p_data - = (struct devfreq_passive_data *)devfreq->data; -- struct devfreq_cpu_data *parent_cpu_data; -- int cpu, ret = 0; -+ int ret; - - if (p_data->nb.notifier_call) { - ret = cpufreq_unregister_notifier(&p_data->nb, -@@ -232,27 +245,9 @@ static int cpufreq_passive_unregister_no - return ret; - } - -- for_each_possible_cpu(cpu) { -- struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); -- if (!policy) { -- ret = -EINVAL; -- continue; -- } -- -- parent_cpu_data = get_parent_cpu_data(p_data, policy); -- if (!parent_cpu_data) { -- cpufreq_cpu_put(policy); -- continue; -- } -- -- list_del(&parent_cpu_data->node); -- if (parent_cpu_data->opp_table) -- dev_pm_opp_put_opp_table(parent_cpu_data->opp_table); -- kfree(parent_cpu_data); -- cpufreq_cpu_put(policy); -- } -+ delete_parent_cpu_data(p_data); - -- return ret; -+ return 0; - } - - static int cpufreq_passive_register_notifier(struct devfreq *devfreq) diff --git a/target/linux/ipq806x/patches-5.15/113-v5.19-02-PM-devfreq-Fix-kernel-panic-with-cpu-based-scaling-t.patch b/target/linux/ipq806x/patches-5.15/113-v5.19-02-PM-devfreq-Fix-kernel-panic-with-cpu-based-scaling-t.patch deleted file mode 100644 index 867ea83e0c9..00000000000 --- a/target/linux/ipq806x/patches-5.15/113-v5.19-02-PM-devfreq-Fix-kernel-panic-with-cpu-based-scaling-t.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 57e00b40033a376de3f3cf0bb9bf7590d2dd679d Mon Sep 17 00:00:00 2001 -From: Christian 'Ansuel' Marangi -Date: Tue, 14 Jun 2022 13:06:59 +0200 -Subject: [PATCH 1/1] PM / devfreq: Fix kernel panic with cpu based scaling to - passive gov - -The cpufreq passive register notifier can PROBE_DEFER and the devfreq -struct is freed and then reallocaed on probe retry. -The current logic assume that the code can't PROBE_DEFER so the devfreq -struct in the this variable in devfreq_passive_data is assumed to be -(if already set) always correct. -This cause kernel panic as the code try to access the wrong address. -To correctly handle this, update the this variable in -devfreq_passive_data to the devfreq reallocated struct. - -Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor") -Signed-off-by: Christian 'Ansuel' Marangi -Signed-off-by: Chanwoo Choi ---- - drivers/devfreq/governor_passive.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - ---- a/drivers/devfreq/governor_passive.c -+++ b/drivers/devfreq/governor_passive.c -@@ -401,8 +401,7 @@ static int devfreq_passive_event_handler - if (!p_data) - return -EINVAL; - -- if (!p_data->this) -- p_data->this = devfreq; -+ p_data->this = devfreq; - - switch (event) { - case DEVFREQ_GOV_START: diff --git a/target/linux/ipq806x/patches-5.15/113-v5.19-03-PM-devfreq-Rework-freq_table-to-be-local-to-devfr.patch b/target/linux/ipq806x/patches-5.15/113-v5.19-03-PM-devfreq-Rework-freq_table-to-be-local-to-devfr.patch deleted file mode 100644 index 210f57bd7e6..00000000000 --- a/target/linux/ipq806x/patches-5.15/113-v5.19-03-PM-devfreq-Rework-freq_table-to-be-local-to-devfr.patch +++ /dev/null @@ -1,269 +0,0 @@ -From 46d05776a1a5dd8eb479e868f5ff4f4b97d68238 Mon Sep 17 00:00:00 2001 -From: Christian 'Ansuel' Marangi -Date: Mon, 6 Jun 2022 12:39:19 +0200 -Subject: [PATCH v4 3/4] PM / devfreq: Rework freq_table to be local to devfreq - struct - -Currently we reference the freq_table to the profile defined one and we -make changes on it. Devfreq never supported PROBE_DEFER before the cpu -based scaling support to the passive governor and assumed that a devfreq -device could only had error and be done with it. -Now that a device can PROBE_DEFER a rework to the freq_table logic is -required. - -If a device PROBE_DEFER on the GOV_START, the freq_table is already set -in the device profile struct and its init is skipped. This is due to the -fact that it's common for devs to declare this kind of struct static. -This cause the devfreq logic to find a freq table declared (freq_table -not NULL) with random data and poiting to the old addrs freed by devm. - -This problem CAN be solved by devs by clearing the freq_table in their -profile struct on driver exit path but it should not be trusted and it -looks to use a flawed logic. - -A better solution is to move the freq_table and max_state to the -devfreq struct and never change the profile struct. -This permit to correctly handle PROBE_DEFER since the devfreq struct is -reallocated and contains new values. -Also the profile struct should only be used to init the driver and should -not be used by the devfreq to write the freq_table if it's not provided -by the driver. - -Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor") -Signed-off-by: Christian 'Ansuel' Marangi ---- - drivers/devfreq/devfreq.c | 71 ++++++++++++++---------------- - drivers/devfreq/governor_passive.c | 14 +++--- - include/linux/devfreq.h | 4 ++ - 3 files changed, 45 insertions(+), 44 deletions(-) - ---- a/drivers/devfreq/devfreq.c -+++ b/drivers/devfreq/devfreq.c -@@ -123,7 +123,7 @@ void devfreq_get_freq_range(struct devfr - unsigned long *min_freq, - unsigned long *max_freq) - { -- unsigned long *freq_table = devfreq->profile->freq_table; -+ unsigned long *freq_table = devfreq->freq_table; - s32 qos_min_freq, qos_max_freq; - - lockdep_assert_held(&devfreq->lock); -@@ -133,11 +133,11 @@ void devfreq_get_freq_range(struct devfr - * The devfreq drivers can initialize this in either ascending or - * descending order and devfreq core supports both. - */ -- if (freq_table[0] < freq_table[devfreq->profile->max_state - 1]) { -+ if (freq_table[0] < freq_table[devfreq->max_state - 1]) { - *min_freq = freq_table[0]; -- *max_freq = freq_table[devfreq->profile->max_state - 1]; -+ *max_freq = freq_table[devfreq->max_state - 1]; - } else { -- *min_freq = freq_table[devfreq->profile->max_state - 1]; -+ *min_freq = freq_table[devfreq->max_state - 1]; - *max_freq = freq_table[0]; - } - -@@ -169,8 +169,8 @@ static int devfreq_get_freq_level(struct - { - int lev; - -- for (lev = 0; lev < devfreq->profile->max_state; lev++) -- if (freq == devfreq->profile->freq_table[lev]) -+ for (lev = 0; lev < devfreq->max_state; lev++) -+ if (freq == devfreq->freq_table[lev]) - return lev; - - return -EINVAL; -@@ -178,7 +178,6 @@ static int devfreq_get_freq_level(struct - - static int set_freq_table(struct devfreq *devfreq) - { -- struct devfreq_dev_profile *profile = devfreq->profile; - struct dev_pm_opp *opp; - unsigned long freq; - int i, count; -@@ -188,25 +187,22 @@ static int set_freq_table(struct devfreq - if (count <= 0) - return -EINVAL; - -- profile->max_state = count; -- profile->freq_table = devm_kcalloc(devfreq->dev.parent, -- profile->max_state, -- sizeof(*profile->freq_table), -- GFP_KERNEL); -- if (!profile->freq_table) { -- profile->max_state = 0; -+ devfreq->max_state = count; -+ devfreq->freq_table = devm_kcalloc(devfreq->dev.parent, -+ devfreq->max_state, -+ sizeof(*devfreq->freq_table), -+ GFP_KERNEL); -+ if (!devfreq->freq_table) - return -ENOMEM; -- } - -- for (i = 0, freq = 0; i < profile->max_state; i++, freq++) { -+ for (i = 0, freq = 0; i < devfreq->max_state; i++, freq++) { - opp = dev_pm_opp_find_freq_ceil(devfreq->dev.parent, &freq); - if (IS_ERR(opp)) { -- devm_kfree(devfreq->dev.parent, profile->freq_table); -- profile->max_state = 0; -+ devm_kfree(devfreq->dev.parent, devfreq->freq_table); - return PTR_ERR(opp); - } - dev_pm_opp_put(opp); -- profile->freq_table[i] = freq; -+ devfreq->freq_table[i] = freq; - } - - return 0; -@@ -246,7 +242,7 @@ int devfreq_update_status(struct devfreq - - if (lev != prev_lev) { - devfreq->stats.trans_table[ -- (prev_lev * devfreq->profile->max_state) + lev]++; -+ (prev_lev * devfreq->max_state) + lev]++; - devfreq->stats.total_trans++; - } - -@@ -834,6 +830,9 @@ struct devfreq *devfreq_add_device(struc - if (err < 0) - goto err_dev; - mutex_lock(&devfreq->lock); -+ } else { -+ devfreq->freq_table = devfreq->profile->freq_table; -+ devfreq->max_state = devfreq->profile->max_state; - } - - devfreq->scaling_min_freq = find_available_min_freq(devfreq); -@@ -869,8 +868,8 @@ struct devfreq *devfreq_add_device(struc - - devfreq->stats.trans_table = devm_kzalloc(&devfreq->dev, - array3_size(sizeof(unsigned int), -- devfreq->profile->max_state, -- devfreq->profile->max_state), -+ devfreq->max_state, -+ devfreq->max_state), - GFP_KERNEL); - if (!devfreq->stats.trans_table) { - mutex_unlock(&devfreq->lock); -@@ -879,7 +878,7 @@ struct devfreq *devfreq_add_device(struc - } - - devfreq->stats.time_in_state = devm_kcalloc(&devfreq->dev, -- devfreq->profile->max_state, -+ devfreq->max_state, - sizeof(*devfreq->stats.time_in_state), - GFP_KERNEL); - if (!devfreq->stats.time_in_state) { -@@ -1637,9 +1636,9 @@ static ssize_t available_frequencies_sho - - mutex_lock(&df->lock); - -- for (i = 0; i < df->profile->max_state; i++) -+ for (i = 0; i < df->max_state; i++) - count += scnprintf(&buf[count], (PAGE_SIZE - count - 2), -- "%lu ", df->profile->freq_table[i]); -+ "%lu ", df->freq_table[i]); - - mutex_unlock(&df->lock); - /* Truncate the trailing space */ -@@ -1662,7 +1661,7 @@ static ssize_t trans_stat_show(struct de - - if (!df->profile) - return -EINVAL; -- max_state = df->profile->max_state; -+ max_state = df->max_state; - - if (max_state == 0) - return sprintf(buf, "Not Supported.\n"); -@@ -1679,19 +1678,17 @@ static ssize_t trans_stat_show(struct de - len += sprintf(buf + len, " :"); - for (i = 0; i < max_state; i++) - len += sprintf(buf + len, "%10lu", -- df->profile->freq_table[i]); -+ df->freq_table[i]); - - len += sprintf(buf + len, " time(ms)\n"); - - for (i = 0; i < max_state; i++) { -- if (df->profile->freq_table[i] -- == df->previous_freq) { -+ if (df->freq_table[i] == df->previous_freq) - len += sprintf(buf + len, "*"); -- } else { -+ else - len += sprintf(buf + len, " "); -- } -- len += sprintf(buf + len, "%10lu:", -- df->profile->freq_table[i]); -+ -+ len += sprintf(buf + len, "%10lu:", df->freq_table[i]); - for (j = 0; j < max_state; j++) - len += sprintf(buf + len, "%10u", - df->stats.trans_table[(i * max_state) + j]); -@@ -1715,7 +1712,7 @@ static ssize_t trans_stat_store(struct d - if (!df->profile) - return -EINVAL; - -- if (df->profile->max_state == 0) -+ if (df->max_state == 0) - return count; - - err = kstrtoint(buf, 10, &value); -@@ -1723,11 +1720,11 @@ static ssize_t trans_stat_store(struct d - return -EINVAL; - - mutex_lock(&df->lock); -- memset(df->stats.time_in_state, 0, (df->profile->max_state * -+ memset(df->stats.time_in_state, 0, (df->max_state * - sizeof(*df->stats.time_in_state))); - memset(df->stats.trans_table, 0, array3_size(sizeof(unsigned int), -- df->profile->max_state, -- df->profile->max_state)); -+ df->max_state, -+ df->max_state)); - df->stats.total_trans = 0; - df->stats.last_update = get_jiffies_64(); - mutex_unlock(&df->lock); ---- a/drivers/devfreq/governor_passive.c -+++ b/drivers/devfreq/governor_passive.c -@@ -145,18 +145,18 @@ static int get_target_freq_with_devfreq( - goto out; - - /* Use interpolation if required opps is not available */ -- for (i = 0; i < parent_devfreq->profile->max_state; i++) -- if (parent_devfreq->profile->freq_table[i] == *freq) -+ for (i = 0; i < parent_devfreq->max_state; i++) -+ if (parent_devfreq->freq_table[i] == *freq) - break; - -- if (i == parent_devfreq->profile->max_state) -+ if (i == parent_devfreq->max_state) - return -EINVAL; - -- if (i < devfreq->profile->max_state) { -- child_freq = devfreq->profile->freq_table[i]; -+ if (i < devfreq->max_state) { -+ child_freq = devfreq->freq_table[i]; - } else { -- count = devfreq->profile->max_state; -- child_freq = devfreq->profile->freq_table[count - 1]; -+ count = devfreq->max_state; -+ child_freq = devfreq->freq_table[count - 1]; - } - - out: ---- a/include/linux/devfreq.h -+++ b/include/linux/devfreq.h -@@ -185,6 +185,10 @@ struct devfreq { - struct notifier_block nb; - struct delayed_work work; - -+ /* devfreq local freq_table */ -+ unsigned long *freq_table; -+ unsigned int max_state; -+ - unsigned long previous_freq; - struct devfreq_dev_status last_status; - diff --git a/target/linux/ipq806x/patches-5.15/113-v5.19-04-PM-devfreq-Mute-warning-on-governor-PROBE_DEFER.patch b/target/linux/ipq806x/patches-5.15/113-v5.19-04-PM-devfreq-Mute-warning-on-governor-PROBE_DEFER.patch deleted file mode 100644 index 591340c6f22..00000000000 --- a/target/linux/ipq806x/patches-5.15/113-v5.19-04-PM-devfreq-Mute-warning-on-governor-PROBE_DEFER.patch +++ /dev/null @@ -1,28 +0,0 @@ -From eee9f767c41b03a2744d4b0f0c1a144e4ff41e78 Mon Sep 17 00:00:00 2001 -From: Christian 'Ansuel' Marangi -Date: Mon, 6 Jun 2022 13:01:02 +0200 -Subject: [PATCH v4 4/4] PM / devfreq: Mute warning on governor PROBE_DEFER - -Don't print warning when a governor PROBE_DEFER as it's not a real -GOV_START fail. - -Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor") -Signed-off-by: Christian 'Ansuel' Marangi ---- - drivers/devfreq/devfreq.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/drivers/devfreq/devfreq.c -+++ b/drivers/devfreq/devfreq.c -@@ -930,8 +930,9 @@ struct devfreq *devfreq_add_device(struc - err = devfreq->governor->event_handler(devfreq, DEVFREQ_GOV_START, - NULL); - if (err) { -- dev_err(dev, "%s: Unable to start governor for the device\n", -- __func__); -+ dev_err_probe(dev, err, -+ "%s: Unable to start governor for the device\n", -+ __func__); - goto err_init; - } - create_sysfs_files(devfreq, devfreq->governor); diff --git a/target/linux/ipq806x/patches-5.15/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch b/target/linux/ipq806x/patches-5.15/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch deleted file mode 100644 index 85feb89148b..00000000000 --- a/target/linux/ipq806x/patches-5.15/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch +++ /dev/null @@ -1,242 +0,0 @@ -From b044ae89862132a86fb511648e9c52ea3cdf8c30 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 5 Aug 2020 14:19:23 +0200 -Subject: [PATCH 1/4] devfreq: qcom: Add L2 Krait Cache devfreq scaling driver - -Qcom L2 Krait CPUs use the generic cpufreq-dt driver and doesn't actually -scale the Cache frequency when the CPU frequency is changed. This -devfreq driver register with the cpu notifier and scale the Cache -based on the max Freq across all core as the CPU cache is shared across -all of them. If provided this also scale the voltage of the regulator -attached to the CPU cache. The scaling logic is based on the CPU freq -and the 3 scaling interval are set by the device dts. - -Signed-off-by: Christian Marangi ---- - drivers/devfreq/Kconfig | 11 ++ - drivers/devfreq/Makefile | 1 + - drivers/devfreq/krait-cache-devfreq.c | 188 ++++++++++++++++++++++++++ - 3 files changed, 200 insertions(+) - create mode 100644 drivers/devfreq/krait-cache-devfreq.c - ---- a/drivers/devfreq/Kconfig -+++ b/drivers/devfreq/Kconfig -@@ -132,6 +132,17 @@ config ARM_RK3399_DMC_DEVFREQ - It sets the frequency for the memory controller and reads the usage counts - from hardware. - -+config ARM_KRAIT_CACHE_DEVFREQ -+ tristate "Scaling support for Krait CPU Cache Devfreq" -+ depends on ARCH_QCOM || COMPILE_TEST -+ select DEVFREQ_GOV_PASSIVE -+ help -+ This adds the DEVFREQ driver for the Krait CPU L2 Cache shared by all cores. -+ -+ The driver register with the cpufreq notifier and find the right frequency -+ based on the max frequency across all core and the range set in the device -+ dts. If provided this scale also the regulator attached to the l2 cache. -+ - source "drivers/devfreq/event/Kconfig" - - endif # PM_DEVFREQ ---- a/drivers/devfreq/Makefile -+++ b/drivers/devfreq/Makefile -@@ -13,6 +13,7 @@ obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx - obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o - obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o - obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o -+obj-$(CONFIG_ARM_KRAIT_CACHE_DEVFREQ) += krait-cache-devfreq.o - - # DEVFREQ Event Drivers - obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/ ---- /dev/null -+++ b/drivers/devfreq/krait-cache-devfreq.c -@@ -0,0 +1,188 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "governor.h" -+ -+struct krait_cache_data { -+ struct clk *clk; -+ unsigned long idle_freq; -+}; -+ -+static int krait_cache_set_opp(struct dev_pm_set_opp_data *data) -+{ -+ unsigned long old_freq = data->old_opp.rate, freq = data->new_opp.rate; -+ struct dev_pm_opp_supply *supply = &data->new_opp.supplies[0]; -+ struct regulator *reg = data->regulators[0]; -+ struct krait_cache_data *kdata; -+ struct clk *clk = data->clk; -+ unsigned long idle_freq; -+ int ret; -+ -+ kdata = dev_get_drvdata(data->dev); -+ idle_freq = kdata->idle_freq; -+ -+ if (reg) { -+ ret = regulator_set_voltage_triplet(reg, supply->u_volt_min, -+ supply->u_volt, -+ supply->u_volt_max); -+ if (ret) -+ goto exit; -+ } -+ -+ /* -+ * Set to idle bin if switching from normal to high bin -+ * or vice versa. It has been notice that a bug is triggered -+ * in cache scaling when more than one bin is scaled, to fix -+ * this we first need to transition to the base rate and then -+ * to target rate -+ */ -+ if (likely(freq != idle_freq && old_freq != idle_freq)) { -+ ret = clk_set_rate(clk, idle_freq); -+ if (ret) -+ goto exit; -+ } -+ -+ ret = clk_set_rate(clk, freq); -+ if (ret) -+ goto exit; -+ -+exit: -+ return ret; -+}; -+ -+static int krait_cache_get_cur_freq(struct device *dev, unsigned long *freq) -+{ -+ struct krait_cache_data *data = dev_get_drvdata(dev); -+ -+ *freq = clk_get_rate(data->clk); -+ -+ return 0; -+}; -+ -+static int krait_cache_target(struct device *dev, unsigned long *freq, -+ u32 flags) -+{ -+ struct dev_pm_opp *opp; -+ -+ opp = dev_pm_opp_find_freq_ceil(dev, freq); -+ if (unlikely(IS_ERR(opp))) -+ return PTR_ERR(opp); -+ -+ dev_pm_opp_put(opp); -+ -+ return dev_pm_opp_set_rate(dev, *freq); -+}; -+ -+static int krait_cache_get_dev_status(struct device *dev, -+ struct devfreq_dev_status *stat) -+{ -+ struct krait_cache_data *data = dev_get_drvdata(dev); -+ -+ stat->busy_time = 0; -+ stat->total_time = 0; -+ stat->current_frequency = clk_get_rate(data->clk); -+ -+ return 0; -+}; -+ -+static struct devfreq_dev_profile krait_cache_devfreq_profile = { -+ .target = krait_cache_target, -+ .get_dev_status = krait_cache_get_dev_status, -+ .get_cur_freq = krait_cache_get_cur_freq -+}; -+ -+static struct devfreq_passive_data devfreq_gov_data = { -+ .parent_type = CPUFREQ_PARENT_DEV, -+}; -+ -+static int krait_cache_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct krait_cache_data *data; -+ struct opp_table *table; -+ struct devfreq *devfreq; -+ struct dev_pm_opp *opp; -+ struct clk *clk; -+ int ret; -+ -+ krait_cache_devfreq_profile.freq_table = NULL; -+ -+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); -+ if (!data) -+ return -ENOMEM; -+ -+ clk = devm_clk_get(dev, "l2"); -+ if (IS_ERR(clk)) -+ return PTR_ERR(clk); -+ -+ table = dev_pm_opp_set_regulators(dev, (const char *[]){ "l2" }, 1); -+ if (IS_ERR(table)) { -+ ret = PTR_ERR(table); -+ dev_err_probe(dev, -EPROBE_DEFER, "failed to set regulators %d\n", ret); -+ return ret; -+ } -+ -+ ret = PTR_ERR_OR_ZERO( -+ dev_pm_opp_register_set_opp_helper(dev, krait_cache_set_opp)); -+ if (ret) -+ return ret; -+ -+ ret = dev_pm_opp_of_add_table(dev); -+ if (ret) { -+ dev_err(dev, "failed to parse L2 freq thresholds\n"); -+ return ret; -+ } -+ -+ data->clk = clk; -+ opp = dev_pm_opp_find_freq_ceil(dev, &data->idle_freq); -+ dev_pm_opp_put(opp); -+ -+ dev_set_drvdata(dev, data); -+ -+ devfreq = devm_devfreq_add_device(&pdev->dev, &krait_cache_devfreq_profile, -+ DEVFREQ_GOV_PASSIVE, &devfreq_gov_data); -+ if (IS_ERR(devfreq)) { -+ dev_pm_opp_remove_table(dev); -+ dev_pm_opp_put_regulators(table); -+ dev_pm_opp_unregister_set_opp_helper(table); -+ } -+ -+ return PTR_ERR_OR_ZERO(devfreq); -+}; -+ -+static int krait_cache_remove(struct platform_device *pdev) -+{ -+ dev_pm_opp_remove_table(&pdev->dev); -+ -+ return 0; -+}; -+ -+static const struct of_device_id krait_cache_match_table[] = { -+ { .compatible = "qcom,krait-cache" }, -+ {} -+}; -+ -+static struct platform_driver krait_cache_driver = { -+ .probe = krait_cache_probe, -+ .remove = krait_cache_remove, -+ .driver = { -+ .name = "krait-cache-scaling", -+ .of_match_table = krait_cache_match_table, -+ }, -+}; -+module_platform_driver(krait_cache_driver); -+ -+MODULE_DESCRIPTION("Krait CPU Cache Scaling driver"); -+MODULE_AUTHOR("Christian 'Ansuel' Marangi "); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ipq806x/patches-5.15/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch b/target/linux/ipq806x/patches-5.15/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch deleted file mode 100644 index f42729fd509..00000000000 --- a/target/linux/ipq806x/patches-5.15/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch +++ /dev/null @@ -1,50 +0,0 @@ -From ef124ad0ff8abfbf4ebe3fe6d7dcef4541dec13a Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 16 Jun 2022 18:39:21 +0200 -Subject: [PATCH] ARM: dts: qcom: add krait-cache compatible for ipq806x dtsi - -Add qcom,krait-cache compatible to enable cache devfreq driver for -ipq806x SoC and move the L2 node to the soc node to make the devfreq -driver correctly probe. - -Signed-off-by: Christian Marangi ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 22 +++++++++++----------- - 1 file changed, 11 insertions(+), 11 deletions(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -69,16 +69,6 @@ - min-residency-us = <3000>; - }; - }; -- -- L2: l2-cache { -- compatible = "cache"; -- cache-level = <2>; -- qcom,saw = <&saw_l2>; -- -- clocks = <&kraitcc 4>; -- clock-names = "l2"; -- operating-points-v2 = <&opp_table_l2>; -- }; - }; - - opp_table_l2: opp_table_l2 { -@@ -470,6 +460,16 @@ - ranges; - compatible = "simple-bus"; - -+ L2: l2-cache { -+ compatible = "cache", "qcom,krait-cache"; -+ cache-level = <2>; -+ qcom,saw = <&saw_l2>; -+ -+ clocks = <&kraitcc 4>; -+ clock-names = "l2"; -+ operating-points-v2 = <&opp_table_l2>; -+ }; -+ - lpass@28100000 { - compatible = "qcom,lpass-cpu"; - status = "disabled"; diff --git a/target/linux/ipq806x/patches-5.15/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch b/target/linux/ipq806x/patches-5.15/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch deleted file mode 100644 index 340c58a0c18..00000000000 --- a/target/linux/ipq806x/patches-5.15/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch +++ /dev/null @@ -1,203 +0,0 @@ -From 13f075999935bb696dbab63243923179f06fa05e Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 16 Jun 2022 19:56:08 +0200 -Subject: [PATCH 3/4] devfreq: add ipq806x fabric scaling driver - -Add ipq806x fabric scaling driver using the devfreq passive governor. - -Signed-off-by: Christian Marangi ---- - drivers/devfreq/Kconfig | 11 ++ - drivers/devfreq/Makefile | 1 + - drivers/devfreq/ipq806x-fab-devfreq.c | 155 ++++++++++++++++++++++++++ - 3 files changed, 167 insertions(+) - create mode 100644 drivers/devfreq/ipq806x-fab-devfreq.c - ---- a/drivers/devfreq/Kconfig -+++ b/drivers/devfreq/Kconfig -@@ -143,6 +143,17 @@ config ARM_KRAIT_CACHE_DEVFREQ - based on the max frequency across all core and the range set in the device - dts. If provided this scale also the regulator attached to the l2 cache. - -+config ARM_IPQ806X_FAB_DEVFREQ -+ tristate "Scaling support for ipq806x Soc Fabric" -+ depends on ARCH_QCOM || COMPILE_TEST -+ select DEVFREQ_GOV_PASSIVE -+ help -+ This adds the DEVFREQ driver for the ipq806x Soc Fabric. -+ -+ The driver register with the cpufreq notifier and find the right frequency -+ based on the max frequency across all core and the range set in the device -+ dts. -+ - source "drivers/devfreq/event/Kconfig" - - endif # PM_DEVFREQ ---- a/drivers/devfreq/Makefile -+++ b/drivers/devfreq/Makefile -@@ -14,6 +14,7 @@ obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += - obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o - obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o - obj-$(CONFIG_ARM_KRAIT_CACHE_DEVFREQ) += krait-cache-devfreq.o -+obj-$(CONFIG_ARM_IPQ806X_FAB_DEVFREQ) += ipq806x-fab-devfreq.o - - # DEVFREQ Event Drivers - obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/ ---- /dev/null -+++ b/drivers/devfreq/ipq806x-fab-devfreq.c -@@ -0,0 +1,155 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "governor.h" -+ -+struct ipq806x_fab_data { -+ struct clk *fab_clk; -+ struct clk *ddr_clk; -+}; -+ -+static int ipq806x_fab_get_cur_freq(struct device *dev, unsigned long *freq) -+{ -+ struct ipq806x_fab_data *data = dev_get_drvdata(dev); -+ -+ *freq = clk_get_rate(data->fab_clk); -+ -+ return 0; -+}; -+ -+static int ipq806x_fab_target(struct device *dev, unsigned long *freq, -+ u32 flags) -+{ -+ struct ipq806x_fab_data *data = dev_get_drvdata(dev); -+ struct dev_pm_opp *opp; -+ int ret; -+ -+ opp = dev_pm_opp_find_freq_ceil(dev, freq); -+ if (unlikely(IS_ERR(opp))) -+ return PTR_ERR(opp); -+ -+ dev_pm_opp_put(opp); -+ -+ ret = clk_set_rate(data->fab_clk, *freq); -+ if (ret) -+ return ret; -+ -+ return clk_set_rate(data->ddr_clk, *freq); -+}; -+ -+static int ipq806x_fab_get_dev_status(struct device *dev, -+ struct devfreq_dev_status *stat) -+{ -+ struct ipq806x_fab_data *data = dev_get_drvdata(dev); -+ -+ stat->busy_time = 0; -+ stat->total_time = 0; -+ stat->current_frequency = clk_get_rate(data->fab_clk); -+ -+ return 0; -+}; -+ -+static struct devfreq_dev_profile ipq806x_fab_devfreq_profile = { -+ .target = ipq806x_fab_target, -+ .get_dev_status = ipq806x_fab_get_dev_status, -+ .get_cur_freq = ipq806x_fab_get_cur_freq -+}; -+ -+static struct devfreq_passive_data devfreq_gov_data = { -+ .parent_type = CPUFREQ_PARENT_DEV, -+}; -+ -+static int ipq806x_fab_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct ipq806x_fab_data *data; -+ struct devfreq *devfreq; -+ struct clk *clk; -+ int ret; -+ -+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); -+ if (!data) -+ return -ENOMEM; -+ -+ clk = devm_clk_get(dev, "apps-fab-clk"); -+ if (IS_ERR(clk)) { -+ dev_err_probe(dev, PTR_ERR(clk), "failed to get apps fab clk\n"); -+ return PTR_ERR(clk); -+ } -+ -+ clk_prepare_enable(clk); -+ data->fab_clk = clk; -+ -+ clk = devm_clk_get(dev, "ddr-fab-clk"); -+ if (IS_ERR(clk)) { -+ dev_err_probe(dev, PTR_ERR(clk), "failed to get ddr fab clk\n"); -+ goto err_ddr; -+ } -+ -+ clk_prepare_enable(clk); -+ data->ddr_clk = clk; -+ -+ ret = dev_pm_opp_of_add_table(dev); -+ if (ret) { -+ dev_err(dev, "failed to parse fab freq thresholds\n"); -+ return ret; -+ } -+ -+ dev_set_drvdata(dev, data); -+ -+ devfreq = devm_devfreq_add_device(&pdev->dev, &ipq806x_fab_devfreq_profile, -+ DEVFREQ_GOV_PASSIVE, &devfreq_gov_data); -+ if (IS_ERR(devfreq)) -+ dev_pm_opp_remove_table(dev); -+ -+ return PTR_ERR_OR_ZERO(devfreq); -+ -+err_ddr: -+ clk_unprepare(data->fab_clk); -+ clk_put(data->fab_clk); -+ return PTR_ERR(clk); -+}; -+ -+static int ipq806x_fab_remove(struct platform_device *pdev) -+{ -+ struct ipq806x_fab_data *data = dev_get_drvdata(&pdev->dev); -+ -+ clk_unprepare(data->fab_clk); -+ clk_put(data->fab_clk); -+ -+ clk_unprepare(data->ddr_clk); -+ clk_put(data->ddr_clk); -+ -+ dev_pm_opp_remove_table(&pdev->dev); -+ -+ return 0; -+}; -+ -+static const struct of_device_id ipq806x_fab_match_table[] = { -+ { .compatible = "qcom,fab-scaling" }, -+ {} -+}; -+ -+static struct platform_driver ipq806x_fab_driver = { -+ .probe = ipq806x_fab_probe, -+ .remove = ipq806x_fab_remove, -+ .driver = { -+ .name = "ipq806x-fab-scaling", -+ .of_match_table = ipq806x_fab_match_table, -+ }, -+}; -+module_platform_driver(ipq806x_fab_driver); -+ -+MODULE_DESCRIPTION("ipq806x Fab Scaling driver"); -+MODULE_AUTHOR("Christian Marangi "); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ipq806x/patches-5.15/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch b/target/linux/ipq806x/patches-5.15/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch deleted file mode 100644 index f4de1dbb52c..00000000000 --- a/target/linux/ipq806x/patches-5.15/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch +++ /dev/null @@ -1,48 +0,0 @@ -From c3573f0907dadb0a6e9933aae2a46a489abcbd48 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 16 Jun 2022 20:03:05 +0200 -Subject: [PATCH 4/4] ARM: dts: qcom: add fab scaling node for ipq806x - -Add fabric scaling node for ipq806x to correctly scale apps and ddr -fabric clk. - -Signed-off-by: Christian Marangi ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -170,6 +170,18 @@ - }; - }; - -+ opp_table_fab: opp_table_fab { -+ compatible = "operating-points-v2"; -+ -+ opp-533000000 { -+ opp-hz = /bits/ 64 <533000000>; -+ }; -+ -+ opp-400000000 { -+ opp-hz = /bits/ 64 <400000000>; -+ }; -+ }; -+ - thermal-zones { - tsens_tz_sensor0 { - polling-delay-passive = <0>; -@@ -470,6 +482,13 @@ - operating-points-v2 = <&opp_table_l2>; - }; - -+ fab-scaling { -+ compatible = "qcom,fab-scaling"; -+ clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>; -+ clock-names = "apps-fab-clk", "ddr-fab-clk"; -+ operating-points-v2 = <&opp_table_fab>; -+ }; -+ - lpass@28100000 { - compatible = "qcom,lpass-cpu"; - status = "disabled"; diff --git a/target/linux/ipq806x/patches-5.15/116-v6.0-01-mtd-nand-raw-qcom_nandc-reorder-qcom_nand_host-struc.patch b/target/linux/ipq806x/patches-5.15/116-v6.0-01-mtd-nand-raw-qcom_nandc-reorder-qcom_nand_host-struc.patch deleted file mode 100644 index c595b10dd74..00000000000 --- a/target/linux/ipq806x/patches-5.15/116-v6.0-01-mtd-nand-raw-qcom_nandc-reorder-qcom_nand_host-struc.patch +++ /dev/null @@ -1,268 +0,0 @@ -From b360514edb4743cbf86fc377699c75e98b1264c7 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 16 Jun 2022 02:18:33 +0200 -Subject: [PATCH 1/2] mtd: nand: raw: qcom_nandc: reorder qcom_nand_host struct - -Reorder structs in nandc driver to save holes. - -Signed-off-by: Christian Marangi -Reviewed-by: Manivannan Sadhasivam -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20220616001835.24393-2-ansuelsmth@gmail.com ---- - drivers/mtd/nand/raw/qcom_nandc.c | 107 +++++++++++++++++------------- - 1 file changed, 62 insertions(+), 45 deletions(-) - ---- a/drivers/mtd/nand/raw/qcom_nandc.c -+++ b/drivers/mtd/nand/raw/qcom_nandc.c -@@ -237,6 +237,9 @@ nandc_set_reg(chip, reg, \ - * @bam_ce - the array of BAM command elements - * @cmd_sgl - sgl for NAND BAM command pipe - * @data_sgl - sgl for NAND BAM consumer/producer pipe -+ * @last_data_desc - last DMA desc in data channel (tx/rx). -+ * @last_cmd_desc - last DMA desc in command channel. -+ * @txn_done - completion for NAND transfer. - * @bam_ce_pos - the index in bam_ce which is available for next sgl - * @bam_ce_start - the index in bam_ce which marks the start position ce - * for current sgl. It will be used for size calculation -@@ -249,14 +252,14 @@ nandc_set_reg(chip, reg, \ - * @rx_sgl_start - start index in data sgl for rx. - * @wait_second_completion - wait for second DMA desc completion before making - * the NAND transfer completion. -- * @txn_done - completion for NAND transfer. -- * @last_data_desc - last DMA desc in data channel (tx/rx). -- * @last_cmd_desc - last DMA desc in command channel. - */ - struct bam_transaction { - struct bam_cmd_element *bam_ce; - struct scatterlist *cmd_sgl; - struct scatterlist *data_sgl; -+ struct dma_async_tx_descriptor *last_data_desc; -+ struct dma_async_tx_descriptor *last_cmd_desc; -+ struct completion txn_done; - u32 bam_ce_pos; - u32 bam_ce_start; - u32 cmd_sgl_pos; -@@ -266,25 +269,23 @@ struct bam_transaction { - u32 rx_sgl_pos; - u32 rx_sgl_start; - bool wait_second_completion; -- struct completion txn_done; -- struct dma_async_tx_descriptor *last_data_desc; -- struct dma_async_tx_descriptor *last_cmd_desc; - }; - - /* - * This data type corresponds to the nand dma descriptor -+ * @dma_desc - low level DMA engine descriptor - * @list - list for desc_info -- * @dir - DMA transfer direction -+ * - * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by - * ADM - * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM - * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM -- * @dma_desc - low level DMA engine descriptor -+ * @dir - DMA transfer direction - */ - struct desc_info { -+ struct dma_async_tx_descriptor *dma_desc; - struct list_head node; - -- enum dma_data_direction dir; - union { - struct scatterlist adm_sgl; - struct { -@@ -292,7 +293,7 @@ struct desc_info { - int sgl_cnt; - }; - }; -- struct dma_async_tx_descriptor *dma_desc; -+ enum dma_data_direction dir; - }; - - /* -@@ -336,52 +337,64 @@ struct nandc_regs { - /* - * NAND controller data struct - * -- * @controller: base controller structure -- * @host_list: list containing all the chips attached to the -- * controller - * @dev: parent device -+ * - * @base: MMIO base -- * @base_phys: physical base address of controller registers -- * @base_dma: dma base address of controller registers -+ * - * @core_clk: controller clock - * @aon_clk: another controller clock - * -+ * @regs: a contiguous chunk of memory for DMA register -+ * writes. contains the register values to be -+ * written to controller -+ * -+ * @props: properties of current NAND controller, -+ * initialized via DT match data -+ * -+ * @controller: base controller structure -+ * @host_list: list containing all the chips attached to the -+ * controller -+ * - * @chan: dma channel - * @cmd_crci: ADM DMA CRCI for command flow control - * @data_crci: ADM DMA CRCI for data flow control -+ * - * @desc_list: DMA descriptor list (list of desc_infos) - * - * @data_buffer: our local DMA buffer for page read/writes, - * used when we can't use the buffer provided - * by upper layers directly -- * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf -- * functions - * @reg_read_buf: local buffer for reading back registers via DMA -+ * -+ * @base_phys: physical base address of controller registers -+ * @base_dma: dma base address of controller registers - * @reg_read_dma: contains dma address for register read buffer -- * @reg_read_pos: marker for data read in reg_read_buf - * -- * @regs: a contiguous chunk of memory for DMA register -- * writes. contains the register values to be -- * written to controller -- * @cmd1/vld: some fixed controller register values -- * @props: properties of current NAND controller, -- * initialized via DT match data -+ * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf -+ * functions - * @max_cwperpage: maximum QPIC codewords required. calculated - * from all connected NAND devices pagesize -+ * -+ * @reg_read_pos: marker for data read in reg_read_buf -+ * -+ * @cmd1/vld: some fixed controller register values - */ - struct qcom_nand_controller { -- struct nand_controller controller; -- struct list_head host_list; -- - struct device *dev; - - void __iomem *base; -- phys_addr_t base_phys; -- dma_addr_t base_dma; - - struct clk *core_clk; - struct clk *aon_clk; - -+ struct nandc_regs *regs; -+ struct bam_transaction *bam_txn; -+ -+ const struct qcom_nandc_props *props; -+ -+ struct nand_controller controller; -+ struct list_head host_list; -+ - union { - /* will be used only by QPIC for BAM DMA */ - struct { -@@ -399,22 +412,22 @@ struct qcom_nand_controller { - }; - - struct list_head desc_list; -- struct bam_transaction *bam_txn; - - u8 *data_buffer; -+ __le32 *reg_read_buf; -+ -+ phys_addr_t base_phys; -+ dma_addr_t base_dma; -+ dma_addr_t reg_read_dma; -+ - int buf_size; - int buf_count; - int buf_start; - unsigned int max_cwperpage; - -- __le32 *reg_read_buf; -- dma_addr_t reg_read_dma; - int reg_read_pos; - -- struct nandc_regs *regs; -- - u32 cmd1, vld; -- const struct qcom_nandc_props *props; - }; - - /* -@@ -430,19 +443,21 @@ struct qcom_nand_controller { - * and reserved bytes - * @cw_data: the number of bytes within a codeword protected - * by ECC -- * @use_ecc: request the controller to use ECC for the -- * upcoming read/write -- * @bch_enabled: flag to tell whether BCH ECC mode is used - * @ecc_bytes_hw: ECC bytes used by controller hardware for this - * chip -- * @status: value to be returned if NAND_CMD_STATUS command -- * is executed -+ * - * @last_command: keeps track of last command on this chip. used - * for reading correct status - * - * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for - * ecc/non-ecc mode for the current nand flash - * device -+ * -+ * @status: value to be returned if NAND_CMD_STATUS command -+ * is executed -+ * @use_ecc: request the controller to use ECC for the -+ * upcoming read/write -+ * @bch_enabled: flag to tell whether BCH ECC mode is used - */ - struct qcom_nand_host { - struct nand_chip chip; -@@ -451,12 +466,10 @@ struct qcom_nand_host { - int cs; - int cw_size; - int cw_data; -- bool use_ecc; -- bool bch_enabled; - int ecc_bytes_hw; - int spare_bytes; - int bbm_size; -- u8 status; -+ - int last_command; - - u32 cfg0, cfg1; -@@ -465,23 +478,27 @@ struct qcom_nand_host { - u32 ecc_bch_cfg; - u32 clrflashstatus; - u32 clrreadstatus; -+ -+ u8 status; -+ bool use_ecc; -+ bool bch_enabled; - }; - - /* - * This data type corresponds to the NAND controller properties which varies - * among different NAND controllers. - * @ecc_modes - ecc mode for NAND -+ * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset - * @is_bam - whether NAND controller is using BAM - * @is_qpic - whether NAND CTRL is part of qpic IP - * @qpic_v2 - flag to indicate QPIC IP version 2 -- * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset - */ - struct qcom_nandc_props { - u32 ecc_modes; -+ u32 dev_cmd_reg_start; - bool is_bam; - bool is_qpic; - bool qpic_v2; -- u32 dev_cmd_reg_start; - }; - - /* Frees the BAM transaction memory */ diff --git a/target/linux/ipq806x/patches-5.15/116-v6.0-02-mtd-nand-raw-qcom_nandc-add-support-for-unprotected-.patch b/target/linux/ipq806x/patches-5.15/116-v6.0-02-mtd-nand-raw-qcom_nandc-add-support-for-unprotected-.patch deleted file mode 100644 index 2a661953044..00000000000 --- a/target/linux/ipq806x/patches-5.15/116-v6.0-02-mtd-nand-raw-qcom_nandc-add-support-for-unprotected-.patch +++ /dev/null @@ -1,406 +0,0 @@ -From 862bdedd7f4b8aebf00fdb422062e64896e97809 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 16 Jun 2022 02:18:34 +0200 -Subject: [PATCH 2/2] mtd: nand: raw: qcom_nandc: add support for unprotected - spare data pages - -IPQ8064 nand have special pages where a different layout scheme is used. -These special page are used by boot partition and on reading them -lots of warning are reported about wrong ECC data and if written to -results in broken data and not bootable device. - -The layout scheme used by these special page consist in using 512 bytes -as the codeword size (even for the last codeword) while writing to CFG0 -register. This forces the NAND controller to unprotect the 4 bytes of -spare data. - -Since the kernel is unaware of this different layout for these special -page, it does try to protect the spare data too during read/write and -warn about CRC errors. - -Add support for this by permitting the user to declare these special -pages in dts by declaring offset and size of the partition. The driver -internally will convert these value to nand pages. - -On user read/write the page is checked and if it's a boot page the -correct layout is used. - -Signed-off-by: Christian Marangi -Reviewed-by: Manivannan Sadhasivam -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20220616001835.24393-3-ansuelsmth@gmail.com ---- - drivers/mtd/nand/raw/qcom_nandc.c | 199 +++++++++++++++++++++++++++++- - 1 file changed, 194 insertions(+), 5 deletions(-) - ---- a/drivers/mtd/nand/raw/qcom_nandc.c -+++ b/drivers/mtd/nand/raw/qcom_nandc.c -@@ -79,8 +79,10 @@ - #define DISABLE_STATUS_AFTER_WRITE 4 - #define CW_PER_PAGE 6 - #define UD_SIZE_BYTES 9 -+#define UD_SIZE_BYTES_MASK GENMASK(18, 9) - #define ECC_PARITY_SIZE_BYTES_RS 19 - #define SPARE_SIZE_BYTES 23 -+#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23) - #define NUM_ADDR_CYCLES 27 - #define STATUS_BFR_READ 30 - #define SET_RD_MODE_AFTER_STATUS 31 -@@ -101,6 +103,7 @@ - #define ECC_MODE 4 - #define ECC_PARITY_SIZE_BYTES_BCH 8 - #define ECC_NUM_DATA_BYTES 16 -+#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16) - #define ECC_FORCE_CLK_OPEN 30 - - /* NAND_DEV_CMD1 bits */ -@@ -431,12 +434,31 @@ struct qcom_nand_controller { - }; - - /* -+ * NAND special boot partitions -+ * -+ * @page_offset: offset of the partition where spare data is not protected -+ * by ECC (value in pages) -+ * @page_offset: size of the partition where spare data is not protected -+ * by ECC (value in pages) -+ */ -+struct qcom_nand_boot_partition { -+ u32 page_offset; -+ u32 page_size; -+}; -+ -+/* - * NAND chip structure - * -+ * @boot_partitions: array of boot partitions where offset and size of the -+ * boot partitions are stored -+ * - * @chip: base NAND chip structure - * @node: list node to add itself to host_list in - * qcom_nand_controller - * -+ * @nr_boot_partitions: count of the boot partitions where spare data is not -+ * protected by ECC -+ * - * @cs: chip select value for this chip - * @cw_size: the number of bytes in a single step/codeword - * of a page, consisting of all data, ecc, spare -@@ -455,14 +477,20 @@ struct qcom_nand_controller { - * - * @status: value to be returned if NAND_CMD_STATUS command - * is executed -+ * @codeword_fixup: keep track of the current layout used by -+ * the driver for read/write operation. - * @use_ecc: request the controller to use ECC for the - * upcoming read/write - * @bch_enabled: flag to tell whether BCH ECC mode is used - */ - struct qcom_nand_host { -+ struct qcom_nand_boot_partition *boot_partitions; -+ - struct nand_chip chip; - struct list_head node; - -+ int nr_boot_partitions; -+ - int cs; - int cw_size; - int cw_data; -@@ -480,6 +508,7 @@ struct qcom_nand_host { - u32 clrreadstatus; - - u8 status; -+ bool codeword_fixup; - bool use_ecc; - bool bch_enabled; - }; -@@ -492,6 +521,7 @@ struct qcom_nand_host { - * @is_bam - whether NAND controller is using BAM - * @is_qpic - whether NAND CTRL is part of qpic IP - * @qpic_v2 - flag to indicate QPIC IP version 2 -+ * @use_codeword_fixup - whether NAND has different layout for boot partitions - */ - struct qcom_nandc_props { - u32 ecc_modes; -@@ -499,6 +529,7 @@ struct qcom_nandc_props { - bool is_bam; - bool is_qpic; - bool qpic_v2; -+ bool use_codeword_fixup; - }; - - /* Frees the BAM transaction memory */ -@@ -1708,7 +1739,7 @@ qcom_nandc_read_cw_raw(struct mtd_info * - data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); - oob_size1 = host->bbm_size; - -- if (qcom_nandc_is_last_cw(ecc, cw)) { -+ if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) { - data_size2 = ecc->size - data_size1 - - ((ecc->steps - 1) * 4); - oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw + -@@ -1789,7 +1820,7 @@ check_for_erased_page(struct qcom_nand_h - } - - for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) { -- if (qcom_nandc_is_last_cw(ecc, cw)) { -+ if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) { - data_size = ecc->size - ((ecc->steps - 1) * 4); - oob_size = (ecc->steps * 4) + host->ecc_bytes_hw; - } else { -@@ -1947,7 +1978,7 @@ static int read_page_ecc(struct qcom_nan - for (i = 0; i < ecc->steps; i++) { - int data_size, oob_size; - -- if (qcom_nandc_is_last_cw(ecc, i)) { -+ if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { - data_size = ecc->size - ((ecc->steps - 1) << 2); - oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + - host->spare_bytes; -@@ -2044,6 +2075,69 @@ static int copy_last_cw(struct qcom_nand - return ret; - } - -+static bool qcom_nandc_is_boot_partition(struct qcom_nand_host *host, int page) -+{ -+ struct qcom_nand_boot_partition *boot_partition; -+ u32 start, end; -+ int i; -+ -+ /* -+ * Since the frequent access will be to the non-boot partitions like rootfs, -+ * optimize the page check by: -+ * -+ * 1. Checking if the page lies after the last boot partition. -+ * 2. Checking from the boot partition end. -+ */ -+ -+ /* First check the last boot partition */ -+ boot_partition = &host->boot_partitions[host->nr_boot_partitions - 1]; -+ start = boot_partition->page_offset; -+ end = start + boot_partition->page_size; -+ -+ /* Page is after the last boot partition end. This is NOT a boot partition */ -+ if (page > end) -+ return false; -+ -+ /* Actually check if it's a boot partition */ -+ if (page < end && page >= start) -+ return true; -+ -+ /* Check the other boot partitions starting from the second-last partition */ -+ for (i = host->nr_boot_partitions - 2; i >= 0; i--) { -+ boot_partition = &host->boot_partitions[i]; -+ start = boot_partition->page_offset; -+ end = start + boot_partition->page_size; -+ -+ if (page < end && page >= start) -+ return true; -+ } -+ -+ return false; -+} -+ -+static void qcom_nandc_codeword_fixup(struct qcom_nand_host *host, int page) -+{ -+ bool codeword_fixup = qcom_nandc_is_boot_partition(host, page); -+ -+ /* Skip conf write if we are already in the correct mode */ -+ if (codeword_fixup == host->codeword_fixup) -+ return; -+ -+ host->codeword_fixup = codeword_fixup; -+ -+ host->cw_data = codeword_fixup ? 512 : 516; -+ host->spare_bytes = host->cw_size - host->ecc_bytes_hw - -+ host->bbm_size - host->cw_data; -+ -+ host->cfg0 &= ~(SPARE_SIZE_BYTES_MASK | UD_SIZE_BYTES_MASK); -+ host->cfg0 |= host->spare_bytes << SPARE_SIZE_BYTES | -+ host->cw_data << UD_SIZE_BYTES; -+ -+ host->ecc_bch_cfg &= ~ECC_NUM_DATA_BYTES_MASK; -+ host->ecc_bch_cfg |= host->cw_data << ECC_NUM_DATA_BYTES; -+ host->ecc_buf_cfg = (host->cw_data - 1) << NUM_STEPS; -+} -+ - /* implements ecc->read_page() */ - static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf, - int oob_required, int page) -@@ -2052,6 +2146,9 @@ static int qcom_nandc_read_page(struct n - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - u8 *data_buf, *oob_buf = NULL; - -+ if (host->nr_boot_partitions) -+ qcom_nandc_codeword_fixup(host, page); -+ - nand_read_page_op(chip, page, 0, NULL, 0); - data_buf = buf; - oob_buf = oob_required ? chip->oob_poi : NULL; -@@ -2071,6 +2168,9 @@ static int qcom_nandc_read_page_raw(stru - int cw, ret; - u8 *data_buf = buf, *oob_buf = chip->oob_poi; - -+ if (host->nr_boot_partitions) -+ qcom_nandc_codeword_fixup(host, page); -+ - for (cw = 0; cw < ecc->steps; cw++) { - ret = qcom_nandc_read_cw_raw(mtd, chip, data_buf, oob_buf, - page, cw); -@@ -2091,6 +2191,9 @@ static int qcom_nandc_read_oob(struct na - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - struct nand_ecc_ctrl *ecc = &chip->ecc; - -+ if (host->nr_boot_partitions) -+ qcom_nandc_codeword_fixup(host, page); -+ - clear_read_regs(nandc); - clear_bam_transaction(nandc); - -@@ -2111,6 +2214,9 @@ static int qcom_nandc_write_page(struct - u8 *data_buf, *oob_buf; - int i, ret; - -+ if (host->nr_boot_partitions) -+ qcom_nandc_codeword_fixup(host, page); -+ - nand_prog_page_begin_op(chip, page, 0, NULL, 0); - - clear_read_regs(nandc); -@@ -2126,7 +2232,7 @@ static int qcom_nandc_write_page(struct - for (i = 0; i < ecc->steps; i++) { - int data_size, oob_size; - -- if (qcom_nandc_is_last_cw(ecc, i)) { -+ if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { - data_size = ecc->size - ((ecc->steps - 1) << 2); - oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + - host->spare_bytes; -@@ -2183,6 +2289,9 @@ static int qcom_nandc_write_page_raw(str - u8 *data_buf, *oob_buf; - int i, ret; - -+ if (host->nr_boot_partitions) -+ qcom_nandc_codeword_fixup(host, page); -+ - nand_prog_page_begin_op(chip, page, 0, NULL, 0); - clear_read_regs(nandc); - clear_bam_transaction(nandc); -@@ -2201,7 +2310,7 @@ static int qcom_nandc_write_page_raw(str - data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); - oob_size1 = host->bbm_size; - -- if (qcom_nandc_is_last_cw(ecc, i)) { -+ if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { - data_size2 = ecc->size - data_size1 - - ((ecc->steps - 1) << 2); - oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw + -@@ -2261,6 +2370,9 @@ static int qcom_nandc_write_oob(struct n - int data_size, oob_size; - int ret; - -+ if (host->nr_boot_partitions) -+ qcom_nandc_codeword_fixup(host, page); -+ - host->use_ecc = true; - clear_bam_transaction(nandc); - -@@ -2922,6 +3034,74 @@ static int qcom_nandc_setup(struct qcom_ - - static const char * const probes[] = { "cmdlinepart", "ofpart", "qcomsmem", NULL }; - -+static int qcom_nand_host_parse_boot_partitions(struct qcom_nand_controller *nandc, -+ struct qcom_nand_host *host, -+ struct device_node *dn) -+{ -+ struct nand_chip *chip = &host->chip; -+ struct mtd_info *mtd = nand_to_mtd(chip); -+ struct qcom_nand_boot_partition *boot_partition; -+ struct device *dev = nandc->dev; -+ int partitions_count, i, j, ret; -+ -+ if (!of_find_property(dn, "qcom,boot-partitions", NULL)) -+ return 0; -+ -+ partitions_count = of_property_count_u32_elems(dn, "qcom,boot-partitions"); -+ if (partitions_count <= 0) { -+ dev_err(dev, "Error parsing boot partition\n"); -+ return partitions_count ? partitions_count : -EINVAL; -+ } -+ -+ host->nr_boot_partitions = partitions_count / 2; -+ host->boot_partitions = devm_kcalloc(dev, host->nr_boot_partitions, -+ sizeof(*host->boot_partitions), GFP_KERNEL); -+ if (!host->boot_partitions) { -+ host->nr_boot_partitions = 0; -+ return -ENOMEM; -+ } -+ -+ for (i = 0, j = 0; i < host->nr_boot_partitions; i++, j += 2) { -+ boot_partition = &host->boot_partitions[i]; -+ -+ ret = of_property_read_u32_index(dn, "qcom,boot-partitions", j, -+ &boot_partition->page_offset); -+ if (ret) { -+ dev_err(dev, "Error parsing boot partition offset at index %d\n", i); -+ host->nr_boot_partitions = 0; -+ return ret; -+ } -+ -+ if (boot_partition->page_offset % mtd->writesize) { -+ dev_err(dev, "Boot partition offset not multiple of writesize at index %i\n", -+ i); -+ host->nr_boot_partitions = 0; -+ return -EINVAL; -+ } -+ /* Convert offset to nand pages */ -+ boot_partition->page_offset /= mtd->writesize; -+ -+ ret = of_property_read_u32_index(dn, "qcom,boot-partitions", j + 1, -+ &boot_partition->page_size); -+ if (ret) { -+ dev_err(dev, "Error parsing boot partition size at index %d\n", i); -+ host->nr_boot_partitions = 0; -+ return ret; -+ } -+ -+ if (boot_partition->page_size % mtd->writesize) { -+ dev_err(dev, "Boot partition size not multiple of writesize at index %i\n", -+ i); -+ host->nr_boot_partitions = 0; -+ return -EINVAL; -+ } -+ /* Convert size to nand pages */ -+ boot_partition->page_size /= mtd->writesize; -+ } -+ -+ return 0; -+} -+ - static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, - struct qcom_nand_host *host, - struct device_node *dn) -@@ -2979,6 +3159,14 @@ static int qcom_nand_host_init_and_regis - if (ret) - nand_cleanup(chip); - -+ if (nandc->props->use_codeword_fixup) { -+ ret = qcom_nand_host_parse_boot_partitions(nandc, host, dn); -+ if (ret) { -+ nand_cleanup(chip); -+ return ret; -+ } -+ } -+ - return ret; - } - -@@ -3144,6 +3332,7 @@ static int qcom_nandc_remove(struct plat - static const struct qcom_nandc_props ipq806x_nandc_props = { - .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT), - .is_bam = false, -+ .use_codeword_fixup = true, - .dev_cmd_reg_start = 0x0, - }; - diff --git a/target/linux/ipq806x/patches-5.15/117-v6.0-01-clk-qcom-clk-hfpll-use-poll_timeout-macro.patch b/target/linux/ipq806x/patches-5.15/117-v6.0-01-clk-qcom-clk-hfpll-use-poll_timeout-macro.patch deleted file mode 100644 index 3008fff9b7f..00000000000 --- a/target/linux/ipq806x/patches-5.15/117-v6.0-01-clk-qcom-clk-hfpll-use-poll_timeout-macro.patch +++ /dev/null @@ -1,41 +0,0 @@ -From fcfbfe373d41b4728ffec075f8f91b6572a88c27 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 30 Apr 2022 07:44:56 +0200 -Subject: [PATCH 1/3] clk: qcom: clk-hfpll: use poll_timeout macro - -Use regmap_read_poll_timeout macro instead of do-while structure to tidy -things up. Also set a timeout to prevent any sort of system stall. - -Signed-off-by: Ansuel Smith -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220430054458.31321-2-ansuelsmth@gmail.com ---- - drivers/clk/qcom/clk-hfpll.c | 15 +++++++++------ - 1 file changed, 9 insertions(+), 6 deletions(-) - ---- a/drivers/clk/qcom/clk-hfpll.c -+++ b/drivers/clk/qcom/clk-hfpll.c -@@ -72,13 +72,16 @@ static void __clk_hfpll_enable(struct cl - regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); - - /* Wait for PLL to lock. */ -- if (hd->status_reg) { -- do { -- regmap_read(regmap, hd->status_reg, &val); -- } while (!(val & BIT(hd->lock_bit))); -- } else { -+ if (hd->status_reg) -+ /* -+ * Busy wait. Should never timeout, we add a timeout to -+ * prevent any sort of stall. -+ */ -+ regmap_read_poll_timeout(regmap, hd->status_reg, val, -+ !(val & BIT(hd->lock_bit)), 0, -+ 100 * USEC_PER_MSEC); -+ else - udelay(60); -- } - - /* Enable PLL output. */ - regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL); diff --git a/target/linux/ipq806x/patches-5.15/117-v6.0-03-clk-qcom-clk-krait-add-apq-ipq8064-errata-workaround.patch b/target/linux/ipq806x/patches-5.15/117-v6.0-03-clk-qcom-clk-krait-add-apq-ipq8064-errata-workaround.patch deleted file mode 100644 index 4012e16f9bc..00000000000 --- a/target/linux/ipq806x/patches-5.15/117-v6.0-03-clk-qcom-clk-krait-add-apq-ipq8064-errata-workaround.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 898d0d6483a9360f1968e0a900465c1fa152a4a9 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 30 Apr 2022 07:44:58 +0200 -Subject: [PATCH 3/3] clk: qcom: clk-krait: add apq/ipq8064 errata workaround - -Add apq/ipq8064 errata workaround where the sec_src clock gating needs to -be disabled during switching. krait-cc compatible is not enough to -handle this and limit this workaround to apq/ipq8064. We check machine -compatible to handle this. - -Signed-off-by: Ansuel Smith -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220430054458.31321-4-ansuelsmth@gmail.com ---- - drivers/clk/qcom/clk-krait.c | 16 ++++++++++++++++ - drivers/clk/qcom/clk-krait.h | 1 + - drivers/clk/qcom/krait-cc.c | 8 ++++++++ - 3 files changed, 25 insertions(+) - ---- a/drivers/clk/qcom/clk-krait.c -+++ b/drivers/clk/qcom/clk-krait.c -@@ -18,13 +18,23 @@ - static DEFINE_SPINLOCK(krait_clock_reg_lock); - - #define LPL_SHIFT 8 -+#define SECCLKAGD BIT(4) -+ - static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) - { - unsigned long flags; - u32 regval; - - spin_lock_irqsave(&krait_clock_reg_lock, flags); -+ - regval = krait_get_l2_indirect_reg(mux->offset); -+ -+ /* apq/ipq8064 Errata: disable sec_src clock gating during switch. */ -+ if (mux->disable_sec_src_gating) { -+ regval |= SECCLKAGD; -+ krait_set_l2_indirect_reg(mux->offset, regval); -+ } -+ - regval &= ~(mux->mask << mux->shift); - regval |= (sel & mux->mask) << mux->shift; - if (mux->lpl) { -@@ -33,6 +43,12 @@ static void __krait_mux_set_sel(struct k - } - krait_set_l2_indirect_reg(mux->offset, regval); - -+ /* apq/ipq8064 Errata: re-enabled sec_src clock gating. */ -+ if (mux->disable_sec_src_gating) { -+ regval &= ~SECCLKAGD; -+ krait_set_l2_indirect_reg(mux->offset, regval); -+ } -+ - /* Wait for switch to complete. */ - mb(); - udelay(1); ---- a/drivers/clk/qcom/clk-krait.h -+++ b/drivers/clk/qcom/clk-krait.h -@@ -15,6 +15,7 @@ struct krait_mux_clk { - u8 safe_sel; - u8 old_index; - bool reparent; -+ bool disable_sec_src_gating; - - struct clk_hw hw; - struct notifier_block clk_nb; ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -139,6 +139,14 @@ krait_add_sec_mux(struct device *dev, in - mux->hw.init = &init; - mux->safe_sel = 0; - -+ /* Checking for qcom,krait-cc-v1 or qcom,krait-cc-v2 is not -+ * enough to limit this to apq/ipq8064. Directly check machine -+ * compatible to correctly handle this errata. -+ */ -+ if (of_machine_is_compatible("qcom,ipq8064") || -+ of_machine_is_compatible("qcom,apq8064")) -+ mux->disable_sec_src_gating = true; -+ - init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); - if (!init.name) - return -ENOMEM; diff --git a/target/linux/ipq806x/patches-5.15/118-v6.1-03-clk-introduce-devm_-hw_register_mux_parent_data_tabl.patch b/target/linux/ipq806x/patches-5.15/118-v6.1-03-clk-introduce-devm_-hw_register_mux_parent_data_tabl.patch deleted file mode 100644 index 8567d0802bc..00000000000 --- a/target/linux/ipq806x/patches-5.15/118-v6.1-03-clk-introduce-devm_-hw_register_mux_parent_data_tabl.patch +++ /dev/null @@ -1,46 +0,0 @@ -From e4cacac0cae3ce7399b70df3bce92eac03151624 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Tue, 12 Apr 2022 16:48:39 +0200 -Subject: [PATCH 3/4] clk: introduce (devm_)hw_register_mux_parent_data_table - API - -Introduce (devm_)hw_register_mux_parent_data_table new API. We have -basic support for clk_register_mux using parent_data but we lack any API -to provide a custom parent_map. Add these 2 new API to correctly handle -these special configuration instead of using the generic -__(devm_)clk_hw_register_mux API. - -Signed-off-by: Christian Marangi ---- - include/linux/clk-provider.h | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/include/linux/clk-provider.h -+++ b/include/linux/clk-provider.h -@@ -955,12 +955,26 @@ struct clk *clk_register_mux_table(struc - __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ - (parent_data), (flags), (reg), (shift), \ - BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) -+#define clk_hw_register_mux_parent_data_table(dev, name, parent_data, \ -+ num_parents, flags, reg, shift, \ -+ width, clk_mux_flags, table, \ -+ lock) \ -+ __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ -+ (parent_data), (flags), (reg), (shift), \ -+ BIT((width)) - 1, (clk_mux_flags), table, (lock)) - #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ - shift, width, clk_mux_flags, lock) \ - __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \ - (parent_names), NULL, NULL, (flags), (reg), \ - (shift), BIT((width)) - 1, (clk_mux_flags), \ - NULL, (lock)) -+#define devm_clk_hw_register_mux_parent_data_table(dev, name, parent_data, \ -+ num_parents, flags, reg, shift, \ -+ width, clk_mux_flags, table, \ -+ lock) \ -+ __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ -+ NULL, (parent_data), (flags), (reg), (shift), \ -+ BIT((width)) - 1, (clk_mux_flags), table, (lock)) - - int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, - unsigned int val); diff --git a/target/linux/ipq806x/patches-5.15/118-v6.1-04-clk-qcom-kpss-xcc-convert-to-parent-data-API.patch b/target/linux/ipq806x/patches-5.15/118-v6.1-04-clk-qcom-kpss-xcc-convert-to-parent-data-API.patch deleted file mode 100644 index 6c5f5ea96b2..00000000000 --- a/target/linux/ipq806x/patches-5.15/118-v6.1-04-clk-qcom-kpss-xcc-convert-to-parent-data-API.patch +++ /dev/null @@ -1,70 +0,0 @@ -From d08c79b818767f24c3c9cbba585d8a3ec896c1a1 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 17 Feb 2022 22:43:34 +0100 -Subject: [PATCH 4/4] clk: qcom: kpss-xcc: convert to parent data API - -Convert the driver to parent data API. From the Documentation pll8_vote -and pxo should be declared in the DTS so fw_name can be used instead of -parent_names. Name is still used to save regression on old definition. - -Signed-off-by: Christian Marangi ---- - drivers/clk/qcom/kpss-xcc.c | 26 +++++++++----------------- - 1 file changed, 9 insertions(+), 17 deletions(-) - ---- a/drivers/clk/qcom/kpss-xcc.c -+++ b/drivers/clk/qcom/kpss-xcc.c -@@ -12,9 +12,9 @@ - #include - #include - --static const char *aux_parents[] = { -- "pll8_vote", -- "pxo", -+static const struct clk_parent_data aux_parents[] = { -+ { .name = "pll8_vote", .fw_name = "pll8_vote" }, -+ { .name = "pxo", .fw_name = "pxo" }, - }; - - static unsigned int aux_parent_map[] = { -@@ -32,9 +32,9 @@ MODULE_DEVICE_TABLE(of, kpss_xcc_match_t - static int kpss_xcc_driver_probe(struct platform_device *pdev) - { - const struct of_device_id *id; -- struct clk *clk; - struct resource *res; - void __iomem *base; -+ struct clk_hw *hw; - const char *name; - - id = of_match_device(kpss_xcc_match_table, &pdev->dev); -@@ -57,24 +57,16 @@ static int kpss_xcc_driver_probe(struct - base += 0x28; - } - -- clk = clk_register_mux_table(&pdev->dev, name, aux_parents, -- ARRAY_SIZE(aux_parents), 0, base, 0, 0x3, -- 0, aux_parent_map, NULL); -+ hw = devm_clk_hw_register_mux_parent_data_table(&pdev->dev, name, aux_parents, -+ ARRAY_SIZE(aux_parents), 0, -+ base, 0, 0x3, -+ 0, aux_parent_map, NULL); - -- platform_set_drvdata(pdev, clk); -- -- return PTR_ERR_OR_ZERO(clk); --} -- --static int kpss_xcc_driver_remove(struct platform_device *pdev) --{ -- clk_unregister_mux(platform_get_drvdata(pdev)); -- return 0; -+ return PTR_ERR_OR_ZERO(hw); - } - - static struct platform_driver kpss_xcc_driver = { - .probe = kpss_xcc_driver_probe, -- .remove = kpss_xcc_driver_remove, - .driver = { - .name = "kpss-xcc", - .of_match_table = kpss_xcc_match_table, diff --git a/target/linux/ipq806x/patches-5.15/119-v6.0-02-ARM-dts-qcom-add-rpmcc-missing-clocks-for-apq-ipq806.patch b/target/linux/ipq806x/patches-5.15/119-v6.0-02-ARM-dts-qcom-add-rpmcc-missing-clocks-for-apq-ipq806.patch deleted file mode 100644 index f853b5d2f24..00000000000 --- a/target/linux/ipq806x/patches-5.15/119-v6.0-02-ARM-dts-qcom-add-rpmcc-missing-clocks-for-apq-ipq806.patch +++ /dev/null @@ -1,61 +0,0 @@ -From aa7fd3bb6017b343585e97a909f9b7d2fe174018 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 00:53:19 +0200 -Subject: [PATCH] ARM: dts: qcom: add rpmcc missing clocks for apq/ipq8064 and - msm8660 - -Add missing rpmcc pxo and cxo clock for apq8064, ipq8064 and -msm8660 dtsi. - -Signed-off-by: Christian Marangi -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220706225321.26215-3-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-apq8064.dtsi | 2 ++ - arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 ++ - arch/arm/boot/dts/qcom-msm8660.dtsi | 4 +++- - 3 files changed, 7 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/qcom-apq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi -@@ -862,6 +862,8 @@ - rpmcc: clock-controller { - compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; - #clock-cells = <1>; -+ clocks = <&pxo_board>, <&cxo_board>; -+ clock-names = "pxo", "cxo"; - }; - - regulators { ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -1074,6 +1074,8 @@ - rpmcc: clock-controller { - compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; - #clock-cells = <1>; -+ clocks = <&pxo_board>; -+ clock-names = "pxo"; - }; - }; - ---- a/arch/arm/boot/dts/qcom-msm8660.dtsi -+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi -@@ -56,7 +56,7 @@ - clock-frequency = <19200000>; - }; - -- pxo_board { -+ pxo_board: pxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; -@@ -420,6 +420,8 @@ - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; - #clock-cells = <1>; -+ clocks = <&pxo_board>; -+ clock-names = "pxo"; - }; - - pm8901-regulators { diff --git a/target/linux/ipq806x/patches-5.15/119-v6.0-03-clk-qcom-clk-rpm-convert-to-parent_data-API.patch b/target/linux/ipq806x/patches-5.15/119-v6.0-03-clk-qcom-clk-rpm-convert-to-parent_data-API.patch deleted file mode 100644 index 8481b636708..00000000000 --- a/target/linux/ipq806x/patches-5.15/119-v6.0-03-clk-qcom-clk-rpm-convert-to-parent_data-API.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 129d9cd9c25041f8b8681fd6e8584fa47c385f3b Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 7 Jul 2022 00:53:20 +0200 -Subject: [PATCH] clk: qcom: clk-rpm: convert to parent_data API - -Convert clk-rpm driver to parent_data API. -We keep the old pxo/cxo_board parent naming to keep compatibility with -old DT and we use the new pxo/cxo for new implementation where these -clock are defined in DTS. - -Signed-off-by: Christian Marangi -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220706225321.26215-4-ansuelsmth@gmail.com ---- - drivers/clk/qcom/clk-rpm.c | 24 ++++++++++++++++-------- - 1 file changed, 16 insertions(+), 8 deletions(-) - ---- a/drivers/clk/qcom/clk-rpm.c -+++ b/drivers/clk/qcom/clk-rpm.c -@@ -23,6 +23,14 @@ - #define QCOM_RPM_SCALING_ENABLE_ID 0x2 - #define QCOM_RPM_XO_MODE_ON 0x2 - -+static const struct clk_parent_data gcc_pxo[] = { -+ { .fw_name = "pxo", .name = "pxo_board" }, -+}; -+ -+static const struct clk_parent_data gcc_cxo[] = { -+ { .fw_name = "cxo", .name = "cxo_board" }, -+}; -+ - #define DEFINE_CLK_RPM(_platform, _name, _active, r_id) \ - static struct clk_rpm _platform##_##_active; \ - static struct clk_rpm _platform##_##_name = { \ -@@ -32,8 +40,8 @@ - .hw.init = &(struct clk_init_data){ \ - .ops = &clk_rpm_ops, \ - .name = #_name, \ -- .parent_names = (const char *[]){ "pxo_board" }, \ -- .num_parents = 1, \ -+ .parent_data = gcc_pxo, \ -+ .num_parents = ARRAY_SIZE(gcc_pxo), \ - }, \ - }; \ - static struct clk_rpm _platform##_##_active = { \ -@@ -44,8 +52,8 @@ - .hw.init = &(struct clk_init_data){ \ - .ops = &clk_rpm_ops, \ - .name = #_active, \ -- .parent_names = (const char *[]){ "pxo_board" }, \ -- .num_parents = 1, \ -+ .parent_data = gcc_pxo, \ -+ .num_parents = ARRAY_SIZE(gcc_pxo), \ - }, \ - } - -@@ -56,8 +64,8 @@ - .hw.init = &(struct clk_init_data){ \ - .ops = &clk_rpm_xo_ops, \ - .name = #_name, \ -- .parent_names = (const char *[]){ "cxo_board" }, \ -- .num_parents = 1, \ -+ .parent_data = gcc_cxo, \ -+ .num_parents = ARRAY_SIZE(gcc_cxo), \ - }, \ - } - -@@ -68,8 +76,8 @@ - .hw.init = &(struct clk_init_data){ \ - .ops = &clk_rpm_fixed_ops, \ - .name = #_name, \ -- .parent_names = (const char *[]){ "pxo" }, \ -- .num_parents = 1, \ -+ .parent_data = gcc_pxo, \ -+ .num_parents = ARRAY_SIZE(gcc_pxo), \ - }, \ - } - diff --git a/target/linux/ipq806x/patches-5.15/120-v6.2-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch b/target/linux/ipq806x/patches-5.15/120-v6.2-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch deleted file mode 100644 index ace313663d5..00000000000 --- a/target/linux/ipq806x/patches-5.15/120-v6.2-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 09be1a39e685d8c5edd471fd1cac9a8f8280d2de Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Tue, 8 Nov 2022 22:17:34 +0100 -Subject: [PATCH] clk: qcom: kpss-xcc: register it as clk provider - -krait-cc use this driver for the secondary mux. Register it as a clk -provider to correctly use this clk in other drivers. - -Signed-off-by: Christian Marangi -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20221108211734.3707-1-ansuelsmth@gmail.com ---- - drivers/clk/qcom/kpss-xcc.c | 13 +++++++++---- - 1 file changed, 9 insertions(+), 4 deletions(-) - ---- a/drivers/clk/qcom/kpss-xcc.c -+++ b/drivers/clk/qcom/kpss-xcc.c -@@ -31,13 +31,14 @@ MODULE_DEVICE_TABLE(of, kpss_xcc_match_t - - static int kpss_xcc_driver_probe(struct platform_device *pdev) - { -+ struct device *dev = &pdev->dev; - const struct of_device_id *id; - struct resource *res; - void __iomem *base; - struct clk_hw *hw; - const char *name; - -- id = of_match_device(kpss_xcc_match_table, &pdev->dev); -+ id = of_match_device(kpss_xcc_match_table, dev); - if (!id) - return -ENODEV; - -@@ -47,7 +48,7 @@ static int kpss_xcc_driver_probe(struct - return PTR_ERR(base); - - if (id->data) { -- if (of_property_read_string_index(pdev->dev.of_node, -+ if (of_property_read_string_index(dev->of_node, - "clock-output-names", - 0, &name)) - return -ENODEV; -@@ -57,12 +58,16 @@ static int kpss_xcc_driver_probe(struct - base += 0x28; - } - -- hw = devm_clk_hw_register_mux_parent_data_table(&pdev->dev, name, aux_parents, -+ hw = devm_clk_hw_register_mux_parent_data_table(dev, name, aux_parents, - ARRAY_SIZE(aux_parents), 0, - base, 0, 0x3, - 0, aux_parent_map, NULL); -+ if (IS_ERR(hw)) -+ return PTR_ERR(hw); - -- return PTR_ERR_OR_ZERO(hw); -+ of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, hw); -+ -+ return 0; - } - - static struct platform_driver kpss_xcc_driver = { diff --git a/target/linux/ipq806x/patches-5.15/121-v6.2-01-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch b/target/linux/ipq806x/patches-5.15/121-v6.2-01-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch deleted file mode 100644 index 65c1fc17f21..00000000000 --- a/target/linux/ipq806x/patches-5.15/121-v6.2-01-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 3198106a99e73dbc4c02bd5128cec0997c73af82 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Tue, 8 Nov 2022 22:58:27 +0100 -Subject: [PATCH 1/6] clk: qcom: krait-cc: use devm variant for clk notifier - register - -Use devm variant for clk notifier register and correctly handle free -resource on driver remove. - -Signed-off-by: Christian Marangi -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20221108215827.30475-1-ansuelsmth@gmail.com ---- - drivers/clk/qcom/krait-cc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -62,7 +62,7 @@ static int krait_notifier_register(struc - int ret = 0; - - mux->clk_nb.notifier_call = krait_notifier_cb; -- ret = clk_notifier_register(clk, &mux->clk_nb); -+ ret = devm_clk_notifier_register(dev, clk, &mux->clk_nb); - if (ret) - dev_err(dev, "failed to register clock notifier: %d\n", ret); - diff --git a/target/linux/ipq806x/patches-5.15/121-v6.2-02-clk-qcom-krait-cc-fix-wrong-parent-order-for-seconda.patch b/target/linux/ipq806x/patches-5.15/121-v6.2-02-clk-qcom-krait-cc-fix-wrong-parent-order-for-seconda.patch deleted file mode 100644 index 2dcb69399cf..00000000000 --- a/target/linux/ipq806x/patches-5.15/121-v6.2-02-clk-qcom-krait-cc-fix-wrong-parent-order-for-seconda.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 8e456411abcbf899c04740b9dbb3dcefcd61c946 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 9 Nov 2022 01:56:27 +0100 -Subject: [PATCH 2/6] clk: qcom: krait-cc: fix wrong parent order for secondary - mux - -The secondary mux parent order is swapped. -This currently doesn't cause problems as the secondary mux is used for idle -clk and as a safe clk source while reprogramming the hfpll. - -Each mux have 2 or more output but he always have a safe source to -switch while reprogramming the connected pll. We use a clk notifier to -switch to the correct parent before clk core can apply the correct rate. -The parent to switch is hardcoded in the mux struct. - -For the secondary mux the safe source to use is the qsb parent as it's -the only fixed clk as the acpus_aux is a pll that can source from pxo or -from pll8. - -The hardcoded safe parent for the secondary mux is set to index 0 that -in the secondary mux map is set to 2. - -But the index 0 is actually acpu_aux in the parent list. - -Fix the swapped parents to correctly handle idle frequency and output a -sane clk_summary report. - -Signed-off-by: Christian Marangi -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20221109005631.3189-1-ansuelsmth@gmail.com ---- - drivers/clk/qcom/krait-cc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -116,8 +116,8 @@ krait_add_sec_mux(struct device *dev, in - int ret; - struct krait_mux_clk *mux; - static const char *sec_mux_list[] = { -- "acpu_aux", - "qsb", -+ "acpu_aux", - }; - struct clk_init_data init = { - .parent_names = sec_mux_list, diff --git a/target/linux/ipq806x/patches-5.15/121-v6.2-03-clk-qcom-krait-cc-also-enable-secondary-mux-and-div-.patch b/target/linux/ipq806x/patches-5.15/121-v6.2-03-clk-qcom-krait-cc-also-enable-secondary-mux-and-div-.patch deleted file mode 100644 index 6261a940d71..00000000000 --- a/target/linux/ipq806x/patches-5.15/121-v6.2-03-clk-qcom-krait-cc-also-enable-secondary-mux-and-div-.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 18ae57b1e8abee6c453381470f6e18991d2901a8 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 9 Nov 2022 01:56:28 +0100 -Subject: [PATCH 3/6] clk: qcom: krait-cc: also enable secondary mux and div - clk - -clk-krait ignore any rate change if clk is not flagged as enabled. -Correctly enable the secondary mux and div clk to correctly change rate -instead of silently ignoring the request. - -Signed-off-by: Christian Marangi -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20221109005631.3189-2-ansuelsmth@gmail.com ---- - drivers/clk/qcom/krait-cc.c | 21 ++++++++++++++++++++- - 1 file changed, 20 insertions(+), 1 deletion(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -80,6 +80,7 @@ krait_add_div(struct device *dev, int id - }; - const char *p_names[1]; - struct clk *clk; -+ int cpu; - - div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); - if (!div) -@@ -103,6 +104,17 @@ krait_add_div(struct device *dev, int id - } - - clk = devm_clk_register(dev, &div->hw); -+ if (IS_ERR(clk)) -+ goto err; -+ -+ /* clk-krait ignore any rate change if mux is not flagged as enabled */ -+ if (id < 0) -+ for_each_online_cpu(cpu) -+ clk_prepare_enable(div->hw.clk); -+ else -+ clk_prepare_enable(div->hw.clk); -+ -+err: - kfree(p_names[0]); - kfree(init.name); - -@@ -113,7 +125,7 @@ static int - krait_add_sec_mux(struct device *dev, int id, const char *s, - unsigned int offset, bool unique_aux) - { -- int ret; -+ int cpu, ret; - struct krait_mux_clk *mux; - static const char *sec_mux_list[] = { - "qsb", -@@ -165,6 +177,13 @@ krait_add_sec_mux(struct device *dev, in - if (ret) - goto unique_aux; - -+ /* clk-krait ignore any rate change if mux is not flagged as enabled */ -+ if (id < 0) -+ for_each_online_cpu(cpu) -+ clk_prepare_enable(mux->hw.clk); -+ else -+ clk_prepare_enable(mux->hw.clk); -+ - unique_aux: - if (unique_aux) - kfree(sec_mux_list[0]); diff --git a/target/linux/ipq806x/patches-5.15/121-v6.2-04-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch b/target/linux/ipq806x/patches-5.15/121-v6.2-04-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch deleted file mode 100644 index fabb299f427..00000000000 --- a/target/linux/ipq806x/patches-5.15/121-v6.2-04-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch +++ /dev/null @@ -1,48 +0,0 @@ -From e5dc1a4c01510da8438dddfdf4200b79d73990dc Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 9 Nov 2022 01:56:29 +0100 -Subject: [PATCH 4/6] clk: qcom: krait-cc: handle secondary mux sourcing out of - acpu_aux - -Some bootloader may leave the system in an even more undefined state -with the secondary mux of L2 or other cores sourcing out of the acpu_aux -parent. This results in the clk set to the PXO rate or a PLL8 rate. - -The current logic to reset the mux and set them to a defined state only -handle if the mux are configured to source out of QSB. Change this and -force a new and defined state if the current clk is lower than the aux -rate. This way we can handle any wrong configuration where the mux is -sourcing out of QSB (rate 225MHz, currently set to a virtual rate of 1), -PXO rate (rate 25MHz) or PLL8 (needs to be configured to run at 384Mhz). - -Signed-off-by: Christian Marangi -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20221109005631.3189-3-ansuelsmth@gmail.com ---- - drivers/clk/qcom/krait-cc.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -383,8 +383,8 @@ static int krait_cc_probe(struct platfor - */ - cur_rate = clk_get_rate(l2_pri_mux_clk); - aux_rate = 384000000; -- if (cur_rate == 1) { -- pr_info("L2 @ QSB rate. Forcing new rate.\n"); -+ if (cur_rate < aux_rate) { -+ pr_info("L2 @ Undefined rate. Forcing new rate.\n"); - cur_rate = aux_rate; - } - clk_set_rate(l2_pri_mux_clk, aux_rate); -@@ -394,8 +394,8 @@ static int krait_cc_probe(struct platfor - for_each_possible_cpu(cpu) { - clk = clks[cpu]; - cur_rate = clk_get_rate(clk); -- if (cur_rate == 1) { -- pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu); -+ if (cur_rate < aux_rate) { -+ pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu); - cur_rate = aux_rate; - } - diff --git a/target/linux/ipq806x/patches-5.15/121-v6.2-05-clk-qcom-krait-cc-convert-to-devm_clk_hw_register.patch b/target/linux/ipq806x/patches-5.15/121-v6.2-05-clk-qcom-krait-cc-convert-to-devm_clk_hw_register.patch deleted file mode 100644 index 049b1fa49f1..00000000000 --- a/target/linux/ipq806x/patches-5.15/121-v6.2-05-clk-qcom-krait-cc-convert-to-devm_clk_hw_register.patch +++ /dev/null @@ -1,104 +0,0 @@ -From 8ea9fb841a7e528bc8ae79d726ce951dcf7b46e2 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 9 Nov 2022 01:56:30 +0100 -Subject: [PATCH 5/6] clk: qcom: krait-cc: convert to devm_clk_hw_register - -clk_register is now deprecated. Convert the driver to devm_clk_hw_register. - -Signed-off-by: Christian Marangi -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20221109005631.3189-4-ansuelsmth@gmail.com ---- - drivers/clk/qcom/krait-cc.c | 31 +++++++++++++++++++------------ - 1 file changed, 19 insertions(+), 12 deletions(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -79,8 +79,7 @@ krait_add_div(struct device *dev, int id - .flags = CLK_SET_RATE_PARENT, - }; - const char *p_names[1]; -- struct clk *clk; -- int cpu; -+ int cpu, ret; - - div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); - if (!div) -@@ -103,8 +102,8 @@ krait_add_div(struct device *dev, int id - return -ENOMEM; - } - -- clk = devm_clk_register(dev, &div->hw); -- if (IS_ERR(clk)) -+ ret = devm_clk_hw_register(dev, &div->hw); -+ if (ret) - goto err; - - /* clk-krait ignore any rate change if mux is not flagged as enabled */ -@@ -118,7 +117,7 @@ err: - kfree(p_names[0]); - kfree(init.name); - -- return PTR_ERR_OR_ZERO(clk); -+ return ret; - } - - static int -@@ -137,7 +136,6 @@ krait_add_sec_mux(struct device *dev, in - .ops = &krait_mux_clk_ops, - .flags = CLK_SET_RATE_PARENT, - }; -- struct clk *clk; - - mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); - if (!mux) -@@ -166,14 +164,16 @@ krait_add_sec_mux(struct device *dev, in - if (unique_aux) { - sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s); - if (!sec_mux_list[0]) { -- clk = ERR_PTR(-ENOMEM); -+ ret = -ENOMEM; - goto err_aux; - } - } - -- clk = devm_clk_register(dev, &mux->hw); -+ ret = devm_clk_hw_register(dev, &mux->hw); -+ if (ret) -+ goto unique_aux; - -- ret = krait_notifier_register(dev, clk, mux); -+ ret = krait_notifier_register(dev, mux->hw.clk, mux); - if (ret) - goto unique_aux; - -@@ -189,7 +189,7 @@ unique_aux: - kfree(sec_mux_list[0]); - err_aux: - kfree(init.name); -- return PTR_ERR_OR_ZERO(clk); -+ return ret; - } - - static struct clk * -@@ -241,11 +241,18 @@ krait_add_pri_mux(struct device *dev, in - goto err_p2; - } - -- clk = devm_clk_register(dev, &mux->hw); -+ ret = devm_clk_hw_register(dev, &mux->hw); -+ if (ret) { -+ clk = ERR_PTR(ret); -+ goto err_p3; -+ } -+ -+ clk = mux->hw.clk; - - ret = krait_notifier_register(dev, clk, mux); - if (ret) -- goto err_p3; -+ clk = ERR_PTR(ret); -+ - err_p3: - kfree(p_names[2]); - err_p2: diff --git a/target/linux/ipq806x/patches-5.15/121-v6.2-06-clk-qcom-krait-cc-convert-to-parent_data-API.patch b/target/linux/ipq806x/patches-5.15/121-v6.2-06-clk-qcom-krait-cc-convert-to-parent_data-API.patch deleted file mode 100644 index 453a37dfc08..00000000000 --- a/target/linux/ipq806x/patches-5.15/121-v6.2-06-clk-qcom-krait-cc-convert-to-parent_data-API.patch +++ /dev/null @@ -1,414 +0,0 @@ -From 56a655e1c41a86445cf2de656649ad93424b2a63 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 9 Nov 2022 01:56:31 +0100 -Subject: [PATCH 6/6] clk: qcom: krait-cc: convert to parent_data API - -Modernize the krait-cc driver to parent-data API and refactor to drop -any use of parent_names. From Documentation all the required clocks should -be declared in DTS so fw_name can be correctly used to get the parents -for all the muxes. .name is also declared to save compatibility with old -DT. - -While at it also drop some hardcoded index and introduce an enum to make -index values more clear. - -Signed-off-by: Christian Marangi -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20221109005631.3189-5-ansuelsmth@gmail.com ---- - drivers/clk/qcom/krait-cc.c | 202 ++++++++++++++++++++---------------- - 1 file changed, 112 insertions(+), 90 deletions(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -15,6 +15,16 @@ - - #include "clk-krait.h" - -+enum { -+ cpu0_mux = 0, -+ cpu1_mux, -+ cpu2_mux, -+ cpu3_mux, -+ l2_mux, -+ -+ clks_max, -+}; -+ - static unsigned int sec_mux_map[] = { - 2, - 0, -@@ -69,21 +79,23 @@ static int krait_notifier_register(struc - return ret; - } - --static int -+static struct clk_hw * - krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) - { - struct krait_div2_clk *div; -+ static struct clk_parent_data p_data[1]; - struct clk_init_data init = { -- .num_parents = 1, -+ .num_parents = ARRAY_SIZE(p_data), - .ops = &krait_div2_clk_ops, - .flags = CLK_SET_RATE_PARENT, - }; -- const char *p_names[1]; -+ struct clk_hw *clk; -+ char *parent_name; - int cpu, ret; - - div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); - if (!div) -- return -ENOMEM; -+ return ERR_PTR(-ENOMEM); - - div->width = 2; - div->shift = 6; -@@ -93,18 +105,25 @@ krait_add_div(struct device *dev, int id - - init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s); - if (!init.name) -- return -ENOMEM; -+ return ERR_PTR(-ENOMEM); - -- init.parent_names = p_names; -- p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); -- if (!p_names[0]) { -- kfree(init.name); -- return -ENOMEM; -+ init.parent_data = p_data; -+ parent_name = kasprintf(GFP_KERNEL, "hfpll%s", s); -+ if (!parent_name) { -+ clk = ERR_PTR(-ENOMEM); -+ goto err_parent_name; - } - -+ p_data[0].fw_name = parent_name; -+ p_data[0].name = parent_name; -+ - ret = devm_clk_hw_register(dev, &div->hw); -- if (ret) -- goto err; -+ if (ret) { -+ clk = ERR_PTR(ret); -+ goto err_clk; -+ } -+ -+ clk = &div->hw; - - /* clk-krait ignore any rate change if mux is not flagged as enabled */ - if (id < 0) -@@ -113,33 +132,36 @@ krait_add_div(struct device *dev, int id - else - clk_prepare_enable(div->hw.clk); - --err: -- kfree(p_names[0]); -+err_clk: -+ kfree(parent_name); -+err_parent_name: - kfree(init.name); - -- return ret; -+ return clk; - } - --static int -+static struct clk_hw * - krait_add_sec_mux(struct device *dev, int id, const char *s, - unsigned int offset, bool unique_aux) - { - int cpu, ret; - struct krait_mux_clk *mux; -- static const char *sec_mux_list[] = { -- "qsb", -- "acpu_aux", -+ static struct clk_parent_data sec_mux_list[2] = { -+ { .name = "qsb", .fw_name = "qsb" }, -+ {}, - }; - struct clk_init_data init = { -- .parent_names = sec_mux_list, -+ .parent_data = sec_mux_list, - .num_parents = ARRAY_SIZE(sec_mux_list), - .ops = &krait_mux_clk_ops, - .flags = CLK_SET_RATE_PARENT, - }; -+ struct clk_hw *clk; -+ char *parent_name; - - mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); - if (!mux) -- return -ENOMEM; -+ return ERR_PTR(-ENOMEM); - - mux->offset = offset; - mux->lpl = id >= 0; -@@ -159,23 +181,33 @@ krait_add_sec_mux(struct device *dev, in - - init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); - if (!init.name) -- return -ENOMEM; -+ return ERR_PTR(-ENOMEM); - - if (unique_aux) { -- sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s); -- if (!sec_mux_list[0]) { -- ret = -ENOMEM; -+ parent_name = kasprintf(GFP_KERNEL, "acpu%s_aux", s); -+ if (!parent_name) { -+ clk = ERR_PTR(-ENOMEM); - goto err_aux; - } -+ sec_mux_list[1].fw_name = parent_name; -+ sec_mux_list[1].name = parent_name; -+ } else { -+ sec_mux_list[1].name = "apu_aux"; - } - - ret = devm_clk_hw_register(dev, &mux->hw); -- if (ret) -- goto unique_aux; -+ if (ret) { -+ clk = ERR_PTR(ret); -+ goto err_clk; -+ } -+ -+ clk = &mux->hw; - - ret = krait_notifier_register(dev, mux->hw.clk, mux); -- if (ret) -- goto unique_aux; -+ if (ret) { -+ clk = ERR_PTR(ret); -+ goto err_clk; -+ } - - /* clk-krait ignore any rate change if mux is not flagged as enabled */ - if (id < 0) -@@ -184,28 +216,29 @@ krait_add_sec_mux(struct device *dev, in - else - clk_prepare_enable(mux->hw.clk); - --unique_aux: -+err_clk: - if (unique_aux) -- kfree(sec_mux_list[0]); -+ kfree(parent_name); - err_aux: - kfree(init.name); -- return ret; -+ return clk; - } - --static struct clk * --krait_add_pri_mux(struct device *dev, int id, const char *s, -- unsigned int offset) -+static struct clk_hw * -+krait_add_pri_mux(struct device *dev, struct clk_hw *hfpll_div, struct clk_hw *sec_mux, -+ int id, const char *s, unsigned int offset) - { - int ret; - struct krait_mux_clk *mux; -- const char *p_names[3]; -+ static struct clk_parent_data p_data[3]; - struct clk_init_data init = { -- .parent_names = p_names, -- .num_parents = ARRAY_SIZE(p_names), -+ .parent_data = p_data, -+ .num_parents = ARRAY_SIZE(p_data), - .ops = &krait_mux_clk_ops, - .flags = CLK_SET_RATE_PARENT, - }; -- struct clk *clk; -+ struct clk_hw *clk; -+ char *hfpll_name; - - mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); - if (!mux) -@@ -223,55 +256,44 @@ krait_add_pri_mux(struct device *dev, in - if (!init.name) - return ERR_PTR(-ENOMEM); - -- p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); -- if (!p_names[0]) { -+ hfpll_name = kasprintf(GFP_KERNEL, "hfpll%s", s); -+ if (!hfpll_name) { - clk = ERR_PTR(-ENOMEM); -- goto err_p0; -+ goto err_hfpll; - } - -- p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s); -- if (!p_names[1]) { -- clk = ERR_PTR(-ENOMEM); -- goto err_p1; -- } -+ p_data[0].fw_name = hfpll_name; -+ p_data[0].name = hfpll_name; - -- p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); -- if (!p_names[2]) { -- clk = ERR_PTR(-ENOMEM); -- goto err_p2; -- } -+ p_data[1].hw = hfpll_div; -+ p_data[2].hw = sec_mux; - - ret = devm_clk_hw_register(dev, &mux->hw); - if (ret) { - clk = ERR_PTR(ret); -- goto err_p3; -+ goto err_clk; - } - -- clk = mux->hw.clk; -+ clk = &mux->hw; - -- ret = krait_notifier_register(dev, clk, mux); -+ ret = krait_notifier_register(dev, mux->hw.clk, mux); - if (ret) - clk = ERR_PTR(ret); - --err_p3: -- kfree(p_names[2]); --err_p2: -- kfree(p_names[1]); --err_p1: -- kfree(p_names[0]); --err_p0: -+err_clk: -+ kfree(hfpll_name); -+err_hfpll: - kfree(init.name); - return clk; - } - - /* id < 0 for L2, otherwise id == physical CPU number */ --static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) -+static struct clk_hw *krait_add_clks(struct device *dev, int id, bool unique_aux) - { -- int ret; -+ struct clk_hw *hfpll_div, *sec_mux, *pri_mux; - unsigned int offset; - void *p = NULL; - const char *s; -- struct clk *clk; - - if (id >= 0) { - offset = 0x4501 + (0x1000 * id); -@@ -283,22 +305,23 @@ static struct clk *krait_add_clks(struct - s = "_l2"; - } - -- ret = krait_add_div(dev, id, s, offset); -- if (ret) { -- clk = ERR_PTR(ret); -+ hfpll_div = krait_add_div(dev, id, s, offset); -+ if (IS_ERR(hfpll_div)) { -+ pri_mux = hfpll_div; - goto err; - } - -- ret = krait_add_sec_mux(dev, id, s, offset, unique_aux); -- if (ret) { -- clk = ERR_PTR(ret); -+ sec_mux = krait_add_sec_mux(dev, id, s, offset, unique_aux); -+ if (IS_ERR(sec_mux)) { -+ pri_mux = sec_mux; - goto err; - } - -- clk = krait_add_pri_mux(dev, id, s, offset); -+ pri_mux = krait_add_pri_mux(dev, hfpll_div, sec_mux, id, s, offset); -+ - err: - kfree(p); -- return clk; -+ return pri_mux; - } - - static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data) -@@ -306,7 +329,7 @@ static struct clk *krait_of_get(struct o - unsigned int idx = clkspec->args[0]; - struct clk **clks = data; - -- if (idx >= 5) { -+ if (idx >= clks_max) { - pr_err("%s: invalid clock index %d\n", __func__, idx); - return ERR_PTR(-EINVAL); - } -@@ -327,9 +350,8 @@ static int krait_cc_probe(struct platfor - const struct of_device_id *id; - unsigned long cur_rate, aux_rate; - int cpu; -- struct clk *clk; -- struct clk **clks; -- struct clk *l2_pri_mux_clk; -+ struct clk_hw *mux, *l2_pri_mux; -+ struct clk *clk, **clks; - - id = of_match_device(krait_cc_match_table, dev); - if (!id) -@@ -348,21 +370,21 @@ static int krait_cc_probe(struct platfor - } - - /* Krait configurations have at most 4 CPUs and one L2 */ -- clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL); -+ clks = devm_kcalloc(dev, clks_max, sizeof(*clks), GFP_KERNEL); - if (!clks) - return -ENOMEM; - - for_each_possible_cpu(cpu) { -- clk = krait_add_clks(dev, cpu, id->data); -+ mux = krait_add_clks(dev, cpu, id->data); - if (IS_ERR(clk)) - return PTR_ERR(clk); -- clks[cpu] = clk; -+ clks[cpu] = mux->clk; - } - -- l2_pri_mux_clk = krait_add_clks(dev, -1, id->data); -- if (IS_ERR(l2_pri_mux_clk)) -- return PTR_ERR(l2_pri_mux_clk); -- clks[4] = l2_pri_mux_clk; -+ l2_pri_mux = krait_add_clks(dev, -1, id->data); -+ if (IS_ERR(l2_pri_mux)) -+ return PTR_ERR(l2_pri_mux); -+ clks[l2_mux] = l2_pri_mux->clk; - - /* - * We don't want the CPU or L2 clocks to be turned off at late init -@@ -372,7 +394,7 @@ static int krait_cc_probe(struct platfor - * they take over. - */ - for_each_online_cpu(cpu) { -- clk_prepare_enable(l2_pri_mux_clk); -+ clk_prepare_enable(clks[l2_mux]); - WARN(clk_prepare_enable(clks[cpu]), - "Unable to turn on CPU%d clock", cpu); - } -@@ -388,16 +410,16 @@ static int krait_cc_probe(struct platfor - * two different rates to force a HFPLL reinit under all - * circumstances. - */ -- cur_rate = clk_get_rate(l2_pri_mux_clk); -+ cur_rate = clk_get_rate(clks[l2_mux]); - aux_rate = 384000000; - if (cur_rate < aux_rate) { - pr_info("L2 @ Undefined rate. Forcing new rate.\n"); - cur_rate = aux_rate; - } -- clk_set_rate(l2_pri_mux_clk, aux_rate); -- clk_set_rate(l2_pri_mux_clk, 2); -- clk_set_rate(l2_pri_mux_clk, cur_rate); -- pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000); -+ clk_set_rate(clks[l2_mux], aux_rate); -+ clk_set_rate(clks[l2_mux], 2); -+ clk_set_rate(clks[l2_mux], cur_rate); -+ pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000); - for_each_possible_cpu(cpu) { - clk = clks[cpu]; - cur_rate = clk_get_rate(clk); diff --git a/target/linux/ipq806x/patches-5.15/122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch b/target/linux/ipq806x/patches-5.15/122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch deleted file mode 100644 index c30c245d0a5..00000000000 --- a/target/linux/ipq806x/patches-5.15/122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 666c1b745e93ccddde841d5057c33f97b29a316a Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 15 Sep 2022 02:19:28 +0200 -Subject: [PATCH 3/9] clk: qcom: krait-cc: handle qsb clock defined in DTS - -qsb fixed clk may be defined in DTS and correctly passed in the clocks -list. Add related code to handle this and modify the logic to -dynamically read qsb clock frequency. - -Signed-off-by: Christian Marangi ---- - drivers/clk/qcom/krait-cc.c | 14 +++++++++++--- - 1 file changed, 11 insertions(+), 3 deletions(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -348,7 +348,7 @@ static int krait_cc_probe(struct platfor - { - struct device *dev = &pdev->dev; - const struct of_device_id *id; -- unsigned long cur_rate, aux_rate; -+ unsigned long cur_rate, aux_rate, qsb_rate; - int cpu; - struct clk_hw *mux, *l2_pri_mux; - struct clk *clk, **clks; -@@ -357,11 +357,19 @@ static int krait_cc_probe(struct platfor - if (!id) - return -ENODEV; - -- /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */ -- clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); -+ /* -+ * Per Documentation qsb should be provided from DTS. -+ * To address old implementation, register the fixed clock anyway. -+ * Rate is 1 because 0 causes problems for __clk_mux_determine_rate -+ */ -+ clk = clk_get(dev, "qsb"); -+ if (IS_ERR(clk)) -+ clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); - if (IS_ERR(clk)) - return PTR_ERR(clk); - -+ qsb_rate = clk_get_rate(clk); -+ - if (!id->data) { - clk = clk_register_fixed_factor(dev, "acpu_aux", - "gpll0_vote", 0, 1, 2); diff --git a/target/linux/ipq806x/patches-5.15/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch b/target/linux/ipq806x/patches-5.15/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch deleted file mode 100644 index e2f78f79fb1..00000000000 --- a/target/linux/ipq806x/patches-5.15/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch +++ /dev/null @@ -1,36 +0,0 @@ -From fca6f185a9d9ef0892a719bc6da955b22d326ec7 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 15 Sep 2022 02:24:33 +0200 -Subject: [PATCH 4/9] clk: qcom: krait-cc: register REAL qsb fixed clock - -With some tools it was discovered the real frequency of the qsb fixed -clock. While not 100% correct it's still better than using 1 as a dummy -frequency. -Correctly register the qsb fixed clock with the frequency of 225 MHz -instead of 1. - -Signed-off-by: Christian Marangi ---- - drivers/clk/qcom/krait-cc.c | 8 +++++--- - 1 file changed, 5 insertions(+), 3 deletions(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -25,6 +25,8 @@ enum { - clks_max, - }; - -+#define QSB_RATE 2250000000 -+ - static unsigned int sec_mux_map[] = { - 2, - 0, -@@ -364,7 +366,7 @@ static int krait_cc_probe(struct platfor - */ - clk = clk_get(dev, "qsb"); - if (IS_ERR(clk)) -- clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); -+ clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, QSB_RATE); - if (IS_ERR(clk)) - return PTR_ERR(clk); - diff --git a/target/linux/ipq806x/patches-5.15/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch b/target/linux/ipq806x/patches-5.15/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch deleted file mode 100644 index d95a63fc44f..00000000000 --- a/target/linux/ipq806x/patches-5.15/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 2399d181557d94ae9a2686926cd25768f132e4b4 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Fri, 18 Mar 2022 16:12:14 +0100 -Subject: [PATCH 7/9] clk: qcom: krait-cc: drop pr_info and use dev_info - -Replace pr_info() with dev_info() to provide better diagnostics. - -Signed-off-by: Christian Marangi ---- - drivers/clk/qcom/krait-cc.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -423,25 +423,25 @@ static int krait_cc_probe(struct platfor - cur_rate = clk_get_rate(clks[l2_mux]); - aux_rate = 384000000; - if (cur_rate < aux_rate) { -- pr_info("L2 @ Undefined rate. Forcing new rate.\n"); -+ dev_info(dev, "L2 @ Undefined rate. Forcing new rate.\n"); - cur_rate = aux_rate; - } - clk_set_rate(clks[l2_mux], aux_rate); - clk_set_rate(clks[l2_mux], 2); - clk_set_rate(clks[l2_mux], cur_rate); -- pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000); -+ dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000); - for_each_possible_cpu(cpu) { - clk = clks[cpu]; - cur_rate = clk_get_rate(clk); - if (cur_rate < aux_rate) { -- pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu); -+ dev_info(dev, "CPU%d @ Undefined rate. Forcing new rate.\n", cpu); - cur_rate = aux_rate; - } - - clk_set_rate(clk, aux_rate); - clk_set_rate(clk, 2); - clk_set_rate(clk, cur_rate); -- pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); -+ dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); - } - - of_clk_add_provider(dev->of_node, krait_of_get, clks); diff --git a/target/linux/ipq806x/patches-5.15/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch b/target/linux/ipq806x/patches-5.15/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch deleted file mode 100644 index 8f88e069912..00000000000 --- a/target/linux/ipq806x/patches-5.15/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 6a77cf3f5f95ec0058e1b4d1ada018748cb0b83b Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 15 Sep 2022 03:33:13 +0200 -Subject: [PATCH 9/9] clk: qcom: krait-cc: rework mux reset logic and reset - hfpll - -Rework and clean mux reset logic. -Compact it to a for loop to handle both CPU and L2 in one place. -Move hardcoded aux_rate to define and add a new hfpll_rate value to -reset hfpll settings. -Change logic to now reset the hfpll to the lowest value of 600 Mhz and -then restoring the previous frequency. This permits to reset the hfpll if -the primary mux was set to source out of the secondary mux. - -Signed-off-by: Christian Marangi ---- - drivers/clk/qcom/krait-cc.c | 50 +++++++++++++++++-------------------- - 1 file changed, 23 insertions(+), 27 deletions(-) - ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -25,7 +25,9 @@ enum { - clks_max, - }; - --#define QSB_RATE 2250000000 -+#define QSB_RATE 225000000 -+#define AUX_RATE 384000000 -+#define HFPLL_RATE 600000000 - - static unsigned int sec_mux_map[] = { - 2, -@@ -350,7 +352,7 @@ static int krait_cc_probe(struct platfor - { - struct device *dev = &pdev->dev; - const struct of_device_id *id; -- unsigned long cur_rate, aux_rate, qsb_rate; -+ unsigned long cur_rate, qsb_rate; - int cpu; - struct clk_hw *mux, *l2_pri_mux; - struct clk *clk, **clks; -@@ -420,28 +422,29 @@ static int krait_cc_probe(struct platfor - * two different rates to force a HFPLL reinit under all - * circumstances. - */ -- cur_rate = clk_get_rate(clks[l2_mux]); -- aux_rate = 384000000; -- if (cur_rate < aux_rate) { -- dev_info(dev, "L2 @ Undefined rate. Forcing new rate.\n"); -- cur_rate = aux_rate; -- } -- clk_set_rate(clks[l2_mux], aux_rate); -- clk_set_rate(clks[l2_mux], 2); -- clk_set_rate(clks[l2_mux], cur_rate); -- dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000); -- for_each_possible_cpu(cpu) { -+ for (cpu = 0; cpu < 5; cpu++) { -+ const char *l2_s = "L2"; -+ char cpu_s[5]; -+ - clk = clks[cpu]; -+ if (!clk) -+ continue; -+ -+ if (cpu < 4) -+ snprintf(cpu_s, 5, "CPU%d", cpu); -+ - cur_rate = clk_get_rate(clk); -- if (cur_rate < aux_rate) { -- dev_info(dev, "CPU%d @ Undefined rate. Forcing new rate.\n", cpu); -- cur_rate = aux_rate; -+ if (cur_rate < AUX_RATE) { -+ dev_info(dev, "%s @ Undefined rate. Forcing new rate.\n", -+ cpu < 4 ? cpu_s : l2_s); -+ cur_rate = AUX_RATE; - } - -- clk_set_rate(clk, aux_rate); -- clk_set_rate(clk, 2); -+ clk_set_rate(clk, AUX_RATE); -+ clk_set_rate(clk, HFPLL_RATE); - clk_set_rate(clk, cur_rate); -- dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); -+ dev_info(dev, "%s @ %lu KHz\n", cpu < 4 ? cpu_s : l2_s, -+ clk_get_rate(clk) / 1000); - } - - of_clk_add_provider(dev->of_node, krait_of_get, clks); diff --git a/target/linux/ipq806x/patches-5.15/122-05-clk-qcom-clk-krait-generilize-div-functions.patch b/target/linux/ipq806x/patches-5.15/122-05-clk-qcom-clk-krait-generilize-div-functions.patch deleted file mode 100644 index a7c0f046c84..00000000000 --- a/target/linux/ipq806x/patches-5.15/122-05-clk-qcom-clk-krait-generilize-div-functions.patch +++ /dev/null @@ -1,156 +0,0 @@ -From 908c361b3c3a139eb3e6a798cb620a6da7514d5c Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Fri, 23 Sep 2022 19:05:39 +0200 -Subject: [PATCH 2/4] clk: qcom: clk-krait: generilize div functions - -Generilize div functions and remove hardcode to a divisor of 2. -This is just a cleanup and permit to make it more clear the settings of -the devisor when used by the krait-cc driver. - -Signed-off-by: Christian Marangi ---- - drivers/clk/qcom/clk-krait.c | 57 ++++++++++++++++++++---------------- - drivers/clk/qcom/clk-krait.h | 11 ++++--- - drivers/clk/qcom/krait-cc.c | 7 +++-- - 3 files changed, 42 insertions(+), 33 deletions(-) - ---- a/drivers/clk/qcom/clk-krait.c -+++ b/drivers/clk/qcom/clk-krait.c -@@ -97,53 +97,58 @@ const struct clk_ops krait_mux_clk_ops = - EXPORT_SYMBOL_GPL(krait_mux_clk_ops); - - /* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */ --static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate, -+static long krait_div_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) - { -- *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2); -- return DIV_ROUND_UP(*parent_rate, 2); -+ struct krait_div_clk *d = to_krait_div_clk(hw); -+ -+ *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), -+ rate * d->divisor); -+ -+ return DIV_ROUND_UP(*parent_rate, d->divisor); - } - --static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate, -+static int krait_div_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) - { -- struct krait_div2_clk *d = to_krait_div2_clk(hw); -+ struct krait_div_clk *d = to_krait_div_clk(hw); -+ u8 div_val = krait_div_to_val(d->divisor); - unsigned long flags; -- u32 val; -- u32 mask = BIT(d->width) - 1; -- -- if (d->lpl) -- mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift; -- else -- mask <<= d->shift; -+ u32 regval; - - spin_lock_irqsave(&krait_clock_reg_lock, flags); -- val = krait_get_l2_indirect_reg(d->offset); -- val &= ~mask; -- krait_set_l2_indirect_reg(d->offset, val); -+ regval = krait_get_l2_indirect_reg(d->offset); -+ -+ regval &= ~(d->mask << d->shift); -+ regval |= (div_val & d->mask) << d->shift; -+ -+ if (d->lpl) { -+ regval &= ~(d->mask << (d->shift + LPL_SHIFT)); -+ regval |= (div_val & d->mask) << (d->shift + LPL_SHIFT); -+ } -+ -+ krait_set_l2_indirect_reg(d->offset, regval); - spin_unlock_irqrestore(&krait_clock_reg_lock, flags); - - return 0; - } - - static unsigned long --krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) -+krait_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) - { -- struct krait_div2_clk *d = to_krait_div2_clk(hw); -- u32 mask = BIT(d->width) - 1; -+ struct krait_div_clk *d = to_krait_div_clk(hw); - u32 div; - - div = krait_get_l2_indirect_reg(d->offset); - div >>= d->shift; -- div &= mask; -- div = (div + 1) * 2; -+ div &= d->mask; - -- return DIV_ROUND_UP(parent_rate, div); -+ return DIV_ROUND_UP(parent_rate, krait_val_to_div(div)); - } - --const struct clk_ops krait_div2_clk_ops = { -- .round_rate = krait_div2_round_rate, -- .set_rate = krait_div2_set_rate, -- .recalc_rate = krait_div2_recalc_rate, -+const struct clk_ops krait_div_clk_ops = { -+ .round_rate = krait_div_round_rate, -+ .set_rate = krait_div_set_rate, -+ .recalc_rate = krait_div_recalc_rate, - }; --EXPORT_SYMBOL_GPL(krait_div2_clk_ops); -+EXPORT_SYMBOL_GPL(krait_div_clk_ops); ---- a/drivers/clk/qcom/clk-krait.h -+++ b/drivers/clk/qcom/clk-krait.h -@@ -25,17 +25,20 @@ struct krait_mux_clk { - - extern const struct clk_ops krait_mux_clk_ops; - --struct krait_div2_clk { -+struct krait_div_clk { - u32 offset; -- u8 width; -+ u32 mask; -+ u8 divisor; - u32 shift; - bool lpl; - - struct clk_hw hw; - }; - --#define to_krait_div2_clk(_hw) container_of(_hw, struct krait_div2_clk, hw) -+#define to_krait_div_clk(_hw) container_of(_hw, struct krait_div_clk, hw) -+#define krait_div_to_val(_div) ((_div) / 2) - 1 -+#define krait_val_to_div(_val) ((_val) + 1) * 2 - --extern const struct clk_ops krait_div2_clk_ops; -+extern const struct clk_ops krait_div_clk_ops; - - #endif ---- a/drivers/clk/qcom/krait-cc.c -+++ b/drivers/clk/qcom/krait-cc.c -@@ -86,11 +86,11 @@ static int krait_notifier_register(struc - static struct clk_hw * - krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) - { -- struct krait_div2_clk *div; -+ struct krait_div_clk *div; - static struct clk_parent_data p_data[1]; - struct clk_init_data init = { - .num_parents = ARRAY_SIZE(p_data), -- .ops = &krait_div2_clk_ops, -+ .ops = &krait_div_clk_ops, - .flags = CLK_SET_RATE_PARENT, - }; - struct clk_hw *clk; -@@ -101,7 +101,8 @@ krait_add_div(struct device *dev, int id - if (!div) - return ERR_PTR(-ENOMEM); - -- div->width = 2; -+ div->mask = 0x3; -+ div->divisor = 2; - div->shift = 6; - div->lpl = id >= 0; - div->offset = offset; diff --git a/target/linux/ipq806x/patches-5.15/123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch b/target/linux/ipq806x/patches-5.15/123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch deleted file mode 100644 index 20e7440ace8..00000000000 --- a/target/linux/ipq806x/patches-5.15/123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch +++ /dev/null @@ -1,31 +0,0 @@ -From ac84ac819a2e8fd3d87122b452c502a386c54437 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Tue, 5 Jul 2022 18:30:18 +0200 -Subject: [PATCH v2 4/4] clk: qcom: gcc-ipq806x: remove cc_register_board for - pxo and cxo - -Now that these clock are defined as fixed clk in dts, we can drop the -register_board_clk for cxo_board and pxo_board in gcc_ipq806x_probe. - -Signed-off-by: Christian Marangi ---- - drivers/clk/qcom/gcc-ipq806x.c | 8 -------- - 1 file changed, 8 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -3384,14 +3384,6 @@ static int gcc_ipq806x_probe(struct plat - struct regmap *regmap; - int ret; - -- ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000); -- if (ret) -- return ret; -- -- ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000); -- if (ret) -- return ret; -- - if (of_machine_is_compatible("qcom,ipq8065")) { - ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065; - ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065; diff --git a/target/linux/ipq806x/patches-5.15/130-6.1-mtd-rawnand-qcom-handle-ret-from-parse-with-codeword.patch b/target/linux/ipq806x/patches-5.15/130-6.1-mtd-rawnand-qcom-handle-ret-from-parse-with-codeword.patch deleted file mode 100644 index 2e7e6833bb8..00000000000 --- a/target/linux/ipq806x/patches-5.15/130-6.1-mtd-rawnand-qcom-handle-ret-from-parse-with-codeword.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 7df140e84a75c89962feef659d686303d3ce75e5 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Fri, 21 Oct 2022 18:53:04 +0200 -Subject: [PATCH] mtd: rawnand: qcom: handle ret from parse with codeword_fixup - -With use_codeword_fixup enabled, any return from -mtd_device_parse_register gets overwritten. Aside from the clear bug, this -is also problematic as a parser can EPROBE_DEFER and because this is not -correctly handled, the nand is never rescanned later in the bootup -process. - -An example of this problem is when smem requires additional time to be -probed and nandc use qcomsmempart as parser. Parser will return -EPROBE_DEFER but in the current code this ret gets overwritten by -qcom_nand_host_parse_boot_partitions and qcom_nand_host_init_and_register -return 0. - -Correctly handle the return code from mtd_device_parse_register so that -any error from this function is not ignored. - -Fixes: 862bdedd7f4b ("mtd: nand: raw: qcom_nandc: add support for unprotected spare data pages") -Cc: stable@vger.kernel.org # v6.0+ -Signed-off-by: Christian Marangi -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20221021165304.19991-1-ansuelsmth@gmail.com ---- - drivers/mtd/nand/raw/qcom_nandc.c | 12 +++++++----- - 1 file changed, 7 insertions(+), 5 deletions(-) - ---- a/drivers/mtd/nand/raw/qcom_nandc.c -+++ b/drivers/mtd/nand/raw/qcom_nandc.c -@@ -3157,16 +3157,18 @@ static int qcom_nand_host_init_and_regis - - ret = mtd_device_parse_register(mtd, probes, NULL, NULL, 0); - if (ret) -- nand_cleanup(chip); -+ goto err; - - if (nandc->props->use_codeword_fixup) { - ret = qcom_nand_host_parse_boot_partitions(nandc, host, dn); -- if (ret) { -- nand_cleanup(chip); -- return ret; -- } -+ if (ret) -+ goto err; - } - -+ return 0; -+ -+err: -+ nand_cleanup(chip); - return ret; - } - diff --git a/target/linux/ipq806x/patches-5.15/131-6.2-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch b/target/linux/ipq806x/patches-5.15/131-6.2-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch deleted file mode 100644 index 8493f380fe0..00000000000 --- a/target/linux/ipq806x/patches-5.15/131-6.2-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch +++ /dev/null @@ -1,28 +0,0 @@ -From c9713e4ede1e5d044b64fe4d3cbb84223625637f Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Tue, 25 Oct 2022 01:38:17 +0200 -Subject: [PATCH] ARM: dts: qcom: ipq8064: disable mmc-ddr-1_8v for sdcc1 - -It was reported non working mmc with this option enabled. -Both mmc for ipq8064 are supplied by a fixed 3.3v regulator so mmc can't -be run at 1.8v. -Disable it to restore correct functionality of this SoC feature. - -Tested-by: Hendrik Koerner -Signed-off-by: Christian Marangi -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20221024233817.27410-1-ansuelsmth@gmail.com ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 1 - - 1 file changed, 1 deletion(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -1529,7 +1529,6 @@ - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; -- mmc-ddr-1_8v; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; - dma-names = "tx", "rx"; diff --git a/target/linux/ipq806x/patches-5.15/850-soc-add-qualcomm-syscon.patch b/target/linux/ipq806x/patches-5.15/850-soc-add-qualcomm-syscon.patch deleted file mode 100644 index 0d983410ec1..00000000000 --- a/target/linux/ipq806x/patches-5.15/850-soc-add-qualcomm-syscon.patch +++ /dev/null @@ -1,121 +0,0 @@ -From: Christian Lamparter -Subject: SoC: add qualcomm syscon ---- a/drivers/soc/qcom/Makefile -+++ b/drivers/soc/qcom/Makefile -@@ -21,6 +21,7 @@ obj-$(CONFIG_QCOM_SMP2P) += smp2p.o - obj-$(CONFIG_QCOM_SMSM) += smsm.o - obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o - obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o -+obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o - obj-$(CONFIG_QCOM_APR) += apr.o - obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o - obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o ---- a/drivers/soc/qcom/Kconfig -+++ b/drivers/soc/qcom/Kconfig -@@ -192,6 +192,13 @@ config QCOM_SOCINFO - Say yes here to support the Qualcomm socinfo driver, providing - information about the SoC to user space. - -+config QCOM_TCSR -+ tristate "QCOM Top Control and Status Registers" -+ depends on ARCH_QCOM -+ help -+ Say y here to enable TCSR support. The TCSR provides control -+ functions for various peripherals. -+ - config QCOM_WCNSS_CTRL - tristate "Qualcomm WCNSS control driver" - depends on ARCH_QCOM || COMPILE_TEST ---- /dev/null -+++ b/drivers/soc/qcom/qcom_tcsr.c -@@ -0,0 +1,64 @@ -+/* -+ * Copyright (c) 2014, The Linux foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License rev 2 and -+ * only rev 2 as published by the free Software foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define TCSR_USB_PORT_SEL 0xb0 -+ -+static int tcsr_probe(struct platform_device *pdev) -+{ -+ struct resource *res; -+ const struct device_node *node = pdev->dev.of_node; -+ void __iomem *base; -+ u32 val; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) { -+ dev_err(&pdev->dev, "setting usb port select = %d\n", val); -+ writel(val, base + TCSR_USB_PORT_SEL); -+ } -+ -+ return 0; -+} -+ -+static const struct of_device_id tcsr_dt_match[] = { -+ { .compatible = "qcom,tcsr", }, -+ { }, -+}; -+ -+MODULE_DEVICE_TABLE(of, tcsr_dt_match); -+ -+static struct platform_driver tcsr_driver = { -+ .driver = { -+ .name = "tcsr", -+ .owner = THIS_MODULE, -+ .of_match_table = tcsr_dt_match, -+ }, -+ .probe = tcsr_probe, -+}; -+ -+module_platform_driver(tcsr_driver); -+ -+MODULE_AUTHOR("Andy Gross "); -+MODULE_DESCRIPTION("QCOM TCSR driver"); -+MODULE_LICENSE("GPL v2"); ---- /dev/null -+++ b/include/dt-bindings/soc/qcom,tcsr.h -@@ -0,0 +1,23 @@ -+/* Copyright (c) 2014, The Linux Foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 and -+ * only version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+#ifndef __DT_BINDINGS_QCOM_TCSR_H -+#define __DT_BINDINGS_QCOM_TCSR_H -+ -+#define TCSR_USB_SELECT_USB3_P0 0x1 -+#define TCSR_USB_SELECT_USB3_P1 0x2 -+#define TCSR_USB_SELECT_USB3_DUAL 0x3 -+ -+/* TCSR A/B REG */ -+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0 -+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1 -+ -+#endif diff --git a/target/linux/ipq806x/patches-5.15/900-arm-add-cmdline-override.patch b/target/linux/ipq806x/patches-5.15/900-arm-add-cmdline-override.patch deleted file mode 100644 index 23cec10f445..00000000000 --- a/target/linux/ipq806x/patches-5.15/900-arm-add-cmdline-override.patch +++ /dev/null @@ -1,37 +0,0 @@ ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1740,6 +1740,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGL - - endchoice - -+config CMDLINE_OVERRIDE -+ bool "Use alternative cmdline from device tree" -+ help -+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can -+ be used, this is not a good option for kernels that are shared across -+ devices. This setting enables using "chosen/cmdline-override" as the -+ cmdline if it exists in the device tree. -+ - config CMDLINE - string "Default kernel command string" - default "" ---- a/drivers/of/fdt.c -+++ b/drivers/of/fdt.c -@@ -1162,6 +1162,17 @@ int __init early_init_dt_scan_chosen(uns - if (p != NULL && l > 0) - strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE)); - -+ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different -+ * device tree option of chosen/bootargs-override. This is -+ * helpful on boards where u-boot sets bootargs, and is unable -+ * to be modified. -+ */ -+#ifdef CONFIG_CMDLINE_OVERRIDE -+ p = of_get_flat_dt_prop(node, "bootargs-override", &l); -+ if (p != NULL && l > 0) -+ strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); -+#endif -+ - /* - * CONFIG_CMDLINE is meant to be a default in case nothing else - * managed to set the command line, unless CONFIG_CMDLINE_FORCE