mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-19 13:48:06 +00:00
uboot-rockchip: fix swig dependency for ROCK64
Pre build files to fix swig dependency. Signed-off-by: Antonio Flores <antflores627@gmail.com>
This commit is contained in:
Antonio Flores
Hauke Mehrtens
parent
0405e11a71
commit
c0c4efe6f1
@ -0,0 +1,27 @@
|
||||
/*
|
||||
* DO NOT MODIFY
|
||||
*
|
||||
* Declares externs for all device/uclass instances.
|
||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
||||
*/
|
||||
|
||||
#include <dm/device-internal.h>
|
||||
#include <dm/uclass-internal.h>
|
||||
|
||||
/* driver declarations - these allow DM_DRIVER_GET() to be used */
|
||||
extern U_BOOT_DRIVER(rockchip_rk3328_cru);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
|
||||
extern U_BOOT_DRIVER(ns16550_serial);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3328_spi);
|
||||
extern U_BOOT_DRIVER(jedec_spi_nor);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3328_grf);
|
||||
|
||||
/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
|
||||
extern UCLASS_DRIVER(clk);
|
||||
extern UCLASS_DRIVER(mmc);
|
||||
extern UCLASS_DRIVER(ram);
|
||||
extern UCLASS_DRIVER(serial);
|
||||
extern UCLASS_DRIVER(spi_flash);
|
||||
extern UCLASS_DRIVER(syscon);
|
||||
@ -0,0 +1,219 @@
|
||||
/*
|
||||
* DO NOT MODIFY
|
||||
*
|
||||
* Declares the U_BOOT_DRIVER() records and platform data.
|
||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
||||
*/
|
||||
|
||||
/* Allow use of U_BOOT_DRVINFO() in this file */
|
||||
#define DT_PLAT_C
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <dt-structs.h>
|
||||
|
||||
/*
|
||||
* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
|
||||
*
|
||||
* idx driver_info driver
|
||||
* --- -------------------- --------------------
|
||||
* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
|
||||
* 1: dmc rockchip_rk3328_dmc
|
||||
* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
|
||||
* 3: mmc_at_ff520000 rockchip_rk3288_dw_mshc
|
||||
* 4: serial_at_ff130000 ns16550_serial
|
||||
* 5: spi_at_ff190000 rockchip_rk3328_spi
|
||||
* 6: spiflash_at_0 jedec_spi_nor
|
||||
* 7: syscon_at_ff100000 rockchip_rk3328_grf
|
||||
* --- -------------------- --------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* Node /clock-controller@ff440000 index 0
|
||||
* driver rockchip_rk3328_cru parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
|
||||
.reg = {0xff440000, 0x1000},
|
||||
.rockchip_grf = 0x3b,
|
||||
};
|
||||
U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
|
||||
.name = "rockchip_rk3328_cru",
|
||||
.plat = &dtv_clock_controller_at_ff440000,
|
||||
.plat_size = sizeof(dtv_clock_controller_at_ff440000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/*
|
||||
* Node /dmc index 1
|
||||
* driver rockchip_rk3328_dmc parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
|
||||
.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
|
||||
0xff720000, 0x1000, 0xff798000, 0x1000},
|
||||
.rockchip_sdram_params = {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10,
|
||||
0x10, 0x10, 0x0, 0x98899459, 0x0, 0x2e, 0x544, 0x15,
|
||||
0x432, 0xff, 0x320, 0x6, 0x1, 0x0, 0x1, 0x0,
|
||||
0x43041008, 0x64, 0x300054, 0xd0, 0x500002, 0xd4, 0x10000, 0xd8,
|
||||
0xe03, 0xdc, 0x43001a, 0xe0, 0x10000, 0xe4, 0xe0005, 0xf4,
|
||||
0xf011f, 0x100, 0xb141b11, 0x104, 0x3031a, 0x108, 0x3060809, 0x10c,
|
||||
0x606000, 0x110, 0x8020409, 0x114, 0x1010606, 0x118, 0x2020004, 0x120,
|
||||
0x404, 0x138, 0x58, 0x180, 0x900024, 0x184, 0x1400000, 0x190,
|
||||
0x7050002, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, 0xa020b28, 0x244,
|
||||
0x101, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, 0xffffffff, 0xffffffff,
|
||||
0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xb, 0x28, 0xc, 0x2c,
|
||||
0x0, 0x30, 0x6, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
|
||||
0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
|
||||
0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
|
||||
0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
|
||||
0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
|
||||
0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
|
||||
0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
|
||||
0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
|
||||
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
|
||||
0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
|
||||
0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
|
||||
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
|
||||
0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
|
||||
0x77, 0x77, 0x79, 0x9},
|
||||
};
|
||||
U_BOOT_DRVINFO(dmc) = {
|
||||
.name = "rockchip_rk3328_dmc",
|
||||
.plat = &dtv_dmc,
|
||||
.plat_size = sizeof(dtv_dmc),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/*
|
||||
* Node /mmc@ff500000 index 2
|
||||
* driver rockchip_rk3288_dw_mshc parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
|
||||
.bus_width = 0x4,
|
||||
.cap_mmc_highspeed = true,
|
||||
.cap_sd_highspeed = true,
|
||||
.clocks = {
|
||||
{0, {317}},
|
||||
{0, {33}},
|
||||
{0, {74}},
|
||||
{0, {78}},},
|
||||
.disable_wp = true,
|
||||
.fifo_depth = 0x100,
|
||||
.interrupts = {0x0, 0xc, 0x4},
|
||||
.max_frequency = 0x8f0d180,
|
||||
.pinctrl_0 = {0x4a, 0x4b, 0x4c, 0x4d},
|
||||
.pinctrl_names = "default",
|
||||
.reg = {0xff500000, 0x4000},
|
||||
.u_boot_spl_fifo_mode = true,
|
||||
.vmmc_supply = 0x4e,
|
||||
};
|
||||
U_BOOT_DRVINFO(mmc_at_ff500000) = {
|
||||
.name = "rockchip_rk3288_dw_mshc",
|
||||
.plat = &dtv_mmc_at_ff500000,
|
||||
.plat_size = sizeof(dtv_mmc_at_ff500000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/*
|
||||
* Node /mmc@ff520000 index 3
|
||||
* driver rockchip_rk3288_dw_mshc parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff520000 = {
|
||||
.bus_width = 0x8,
|
||||
.cap_mmc_highspeed = true,
|
||||
.clocks = {
|
||||
{0, {319}},
|
||||
{0, {35}},
|
||||
{0, {76}},
|
||||
{0, {80}},},
|
||||
.fifo_depth = 0x100,
|
||||
.interrupts = {0x0, 0xe, 0x4},
|
||||
.max_frequency = 0x8f0d180,
|
||||
.mmc_hs200_1_8v = true,
|
||||
.non_removable = true,
|
||||
.pinctrl_0 = {0x4f, 0x50, 0x51, 0x0},
|
||||
.pinctrl_names = "default",
|
||||
.reg = {0xff520000, 0x4000},
|
||||
.u_boot_spl_fifo_mode = true,
|
||||
.vmmc_supply = 0x1e,
|
||||
.vqmmc_supply = 0x1f,
|
||||
};
|
||||
U_BOOT_DRVINFO(mmc_at_ff520000) = {
|
||||
.name = "rockchip_rk3288_dw_mshc",
|
||||
.plat = &dtv_mmc_at_ff520000,
|
||||
.plat_size = sizeof(dtv_mmc_at_ff520000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/*
|
||||
* Node /serial@ff130000 index 4
|
||||
* driver ns16550_serial parent None
|
||||
*/
|
||||
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
|
||||
.clock_frequency = 0x16e3600,
|
||||
.clocks = {
|
||||
{0, {40}},
|
||||
{0, {212}},},
|
||||
.dma_names = {"tx", "rx"},
|
||||
.dmas = {0x10, 0x6, 0x10, 0x7},
|
||||
.interrupts = {0x0, 0x39, 0x4},
|
||||
.pinctrl_0 = 0x27,
|
||||
.pinctrl_names = "default",
|
||||
.reg = {0xff130000, 0x100},
|
||||
.reg_io_width = 0x4,
|
||||
.reg_shift = 0x2,
|
||||
};
|
||||
U_BOOT_DRVINFO(serial_at_ff130000) = {
|
||||
.name = "ns16550_serial",
|
||||
.plat = &dtv_serial_at_ff130000,
|
||||
.plat_size = sizeof(dtv_serial_at_ff130000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/* Node /spi@ff190000 index 5 */
|
||||
static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = {
|
||||
.clocks = {
|
||||
{0, {32}},
|
||||
{0, {209}},},
|
||||
.dma_names = {"tx", "rx"},
|
||||
.dmas = {0x10, 0x8, 0x10, 0x9},
|
||||
.interrupts = {0x0, 0x31, 0x4},
|
||||
.pinctrl_0 = {0x2f, 0x30, 0x31, 0x32},
|
||||
.pinctrl_names = "default",
|
||||
.reg = {0xff190000, 0x1000},
|
||||
};
|
||||
U_BOOT_DRVINFO(spi_at_ff190000) = {
|
||||
.name = "rockchip_rk3328_spi",
|
||||
.plat = &dtv_spi_at_ff190000,
|
||||
.plat_size = sizeof(dtv_spi_at_ff190000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/*
|
||||
* Node /spi@ff190000/spiflash@0 index 6
|
||||
* driver jedec_spi_nor parent None
|
||||
*/
|
||||
static struct dtd_jedec_spi_nor dtv_spiflash_at_0 = {
|
||||
.reg = {0x0},
|
||||
.spi_max_frequency = 0x2faf080,
|
||||
};
|
||||
U_BOOT_DRVINFO(spiflash_at_0) = {
|
||||
.name = "jedec_spi_nor",
|
||||
.plat = &dtv_spiflash_at_0,
|
||||
.plat_size = sizeof(dtv_spiflash_at_0),
|
||||
.parent_idx = 5,
|
||||
};
|
||||
|
||||
/*
|
||||
* Node /syscon@ff100000 index 7
|
||||
* driver rockchip_rk3328_grf parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
|
||||
.reg = {0xff100000, 0x1000},
|
||||
};
|
||||
U_BOOT_DRVINFO(syscon_at_ff100000) = {
|
||||
.name = "rockchip_rk3328_grf",
|
||||
.plat = &dtv_syscon_at_ff100000,
|
||||
.plat_size = sizeof(dtv_syscon_at_ff100000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
@ -0,0 +1,63 @@
|
||||
/*
|
||||
* DO NOT MODIFY
|
||||
*
|
||||
* Defines the structs used to hold devicetree data.
|
||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <linux/libfdt.h>
|
||||
struct dtd_jedec_spi_nor {
|
||||
fdt32_t reg[1];
|
||||
fdt32_t spi_max_frequency;
|
||||
};
|
||||
struct dtd_ns16550_serial {
|
||||
fdt32_t clock_frequency;
|
||||
struct phandle_1_arg clocks[2];
|
||||
const char * dma_names[2];
|
||||
fdt32_t dmas[4];
|
||||
fdt32_t interrupts[3];
|
||||
fdt32_t pinctrl_0;
|
||||
const char * pinctrl_names;
|
||||
fdt64_t reg[2];
|
||||
fdt32_t reg_io_width;
|
||||
fdt32_t reg_shift;
|
||||
};
|
||||
struct dtd_rockchip_rk3288_dw_mshc {
|
||||
fdt32_t bus_width;
|
||||
bool cap_mmc_highspeed;
|
||||
bool cap_sd_highspeed;
|
||||
struct phandle_1_arg clocks[4];
|
||||
bool disable_wp;
|
||||
fdt32_t fifo_depth;
|
||||
fdt32_t interrupts[3];
|
||||
fdt32_t max_frequency;
|
||||
bool mmc_hs200_1_8v;
|
||||
bool non_removable;
|
||||
fdt32_t pinctrl_0[4];
|
||||
const char * pinctrl_names;
|
||||
fdt64_t reg[2];
|
||||
bool u_boot_spl_fifo_mode;
|
||||
fdt32_t vmmc_supply;
|
||||
fdt32_t vqmmc_supply;
|
||||
};
|
||||
struct dtd_rockchip_rk3328_cru {
|
||||
fdt64_t reg[2];
|
||||
fdt32_t rockchip_grf;
|
||||
};
|
||||
struct dtd_rockchip_rk3328_dmc {
|
||||
fdt64_t reg[12];
|
||||
fdt32_t rockchip_sdram_params[196];
|
||||
};
|
||||
struct dtd_rockchip_rk3328_grf {
|
||||
fdt64_t reg[2];
|
||||
};
|
||||
struct dtd_rockchip_rk3328_spi {
|
||||
struct phandle_1_arg clocks[2];
|
||||
const char * dma_names[2];
|
||||
fdt32_t dmas[4];
|
||||
fdt32_t interrupts[3];
|
||||
fdt32_t pinctrl_0[4];
|
||||
const char * pinctrl_names;
|
||||
fdt64_t reg[2];
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user