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https://github.com/openwrt/openwrt.git
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mediatek: filogic: update MT7988 device tree
* move ethernet to mt7988a.dtsi
* move switch definition to mt7988a.dtsi
* add PHY LEDs
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit 64b99802a6)
This commit is contained in:
Daniel Golle
parent
830bb57f6a
commit
c072069fa7
@ -7,6 +7,7 @@
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/dts-v1/;
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#include "mt7988a-rfb-spim-nand.dtsi"
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#include <dt-bindings/pinctrl/mt65xx.h>
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#include <dt-bindings/leds/common.h>
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/ {
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model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB";
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@ -29,173 +30,105 @@
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pinctrl-0 = <&mdio0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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&gmac0 {
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status = "okay";
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};
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&gmac1 {
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status = "okay";
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phy-mode = "internal";
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phy-connection-type = "internal";
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phy = <&int_2p5g_phy>;
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};
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&gmac2 {
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status = "okay";
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phy-mode = "usxgmii";
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phy-connection-type = "usxgmii";
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phy = <&phy8>;
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};
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&mdio_bus {
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/* external Aquantia AQR113C */
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phy0: ethernet-phy@0 {
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reg = <0>;
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phy-mode = "internal";
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fixed-link {
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speed = <10000>;
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full-duplex;
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pause;
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};
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compatible = "ethernet-phy-ieee802.3-c45";
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reset-gpios = <&pio 72 1>;
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reset-assert-us = <100000>;
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reset-deassert-us = <221000>;
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};
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-mode = "internal";
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phy-connection-type = "internal";
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phy = <&phy15>;
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/* external Aquantia AQR113C */
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phy8: ethernet-phy@8 {
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reg = <8>;
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compatible = "ethernet-phy-ieee802.3-c45";
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reset-gpios = <&pio 71 1>;
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reset-assert-us = <100000>;
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reset-deassert-us = <221000>;
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};
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gmac2: mac@2 {
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compatible = "mediatek,eth-mac";
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reg = <2>;
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phy-mode = "10gbase-kr";
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phy-connection-type = "10gbase-kr";
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phy = <&phy8>;
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/* external Maxlinear GPY211C */
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phy5: ethernet-phy@5 {
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reg = <5>;
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compatible = "ethernet-phy-ieee802.3-c45";
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phy-mode = "2500base-x";
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};
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mdio0: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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/* external Aquantia AQR113C */
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phy0: ethernet-phy@0 {
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reg = <0>;
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compatible = "ethernet-phy-ieee802.3-c45";
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reset-gpios = <&pio 72 1>;
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reset-assert-us = <100000>;
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reset-deassert-us = <221000>;
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};
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/* external Aquantia AQR113C */
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phy8: ethernet-phy@8 {
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reg = <8>;
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compatible = "ethernet-phy-ieee802.3-c45";
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reset-gpios = <&pio 71 1>;
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reset-assert-us = <100000>;
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reset-deassert-us = <221000>;
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};
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/* external Maxlinear GPY211C */
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phy5: ethernet-phy@5 {
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reg = <5>;
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compatible = "ethernet-phy-ieee802.3-c45";
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phy-mode = "2500base-x";
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};
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/* external Maxlinear GPY211C */
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phy13: ethernet-phy@13 {
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reg = <13>;
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compatible = "ethernet-phy-ieee802.3-c45";
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phy-mode = "2500base-x";
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};
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/* internal 2.5G PHY */
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phy15: ethernet-phy@15 {
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reg = <15>;
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pinctrl-names = "i2p5gbe-led";
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pinctrl-0 = <&i2p5gbe_led0_pins>;
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compatible = "ethernet-phy-ieee802.3-c45";
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phy-mode = "internal";
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};
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/* external Maxlinear GPY211C */
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phy13: ethernet-phy@13 {
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reg = <13>;
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compatible = "ethernet-phy-ieee802.3-c45";
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phy-mode = "2500base-x";
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};
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};
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&int_2p5g_phy {
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pinctrl-names = "i2p5gbe-led";
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pinctrl-0 = <&i2p5gbe_led0_pins>;
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};
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&switch {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan0";
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phy-mode = "internal";
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phy-handle = <&gsw_phy0>;
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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phy-mode = "internal";
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phy-handle = <&gsw_phy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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phy-mode = "internal";
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phy-handle = <&gsw_phy2>;
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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phy-mode = "internal";
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phy-handle = <&gsw_phy3>;
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};
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port@6 {
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reg = <6>;
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ethernet = <&gmac0>;
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phy-mode = "internal";
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fixed-link {
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speed = <10000>;
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full-duplex;
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pause;
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};
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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mediatek,pio = <&pio>;
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gsw_phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-id03a2.9481";
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reg = <0>;
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phy-mode = "internal";
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe0_led0_pins>;
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nvmem-cells = <&phy_calibration_p0>;
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nvmem-cell-names = "phy-cal-data";
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};
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gsw_phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-id03a2.9481";
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reg = <1>;
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phy-mode = "internal";
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe1_led0_pins>;
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nvmem-cells = <&phy_calibration_p1>;
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nvmem-cell-names = "phy-cal-data";
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};
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gsw_phy2: ethernet-phy@2 {
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compatible = "ethernet-phy-id03a2.9481";
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reg = <2>;
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phy-mode = "internal";
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe2_led0_pins>;
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nvmem-cells = <&phy_calibration_p2>;
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nvmem-cell-names = "phy-cal-data";
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};
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gsw_phy3: ethernet-phy@3 {
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compatible = "ethernet-phy-id03a2.9481";
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reg = <3>;
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phy-mode = "internal";
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe3_led0_pins>;
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nvmem-cells = <&phy_calibration_p3>;
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nvmem-cell-names = "phy-cal-data";
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};
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};
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};
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&gsw_phy0 {
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe0_led0_pins>;
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};
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&gsw_phy0_led0 {
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status = "okay";
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color = <LED_COLOR_ID_GREEN>;
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};
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&gsw_phy1 {
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe1_led0_pins>;
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};
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&gsw_phy1_led0 {
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status = "okay";
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color = <LED_COLOR_ID_GREEN>;
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};
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&gsw_phy2 {
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe2_led0_pins>;
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};
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&gsw_phy2_led0 {
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status = "okay";
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color = <LED_COLOR_ID_GREEN>;
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};
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&gsw_phy3 {
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe3_led0_pins>;
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};
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&gsw_phy3_led0 {
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status = "okay";
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color = <LED_COLOR_ID_GREEN>;
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};
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@ -4,12 +4,13 @@
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/ti-syscon.h>
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#include <dt-bindings/clock/mediatek,mt7988-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/pinctrl/mt65xx.h>
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#include <dt-bindings/reset/ti-syscon.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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@ -144,9 +145,9 @@
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#size-cells = <2>;
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ranges;
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/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
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/* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
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secmon_reserved: secmon@43000000 {
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reg = <0 0x43000000 0 0x30000>;
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reg = <0 0x43000000 0 0x50000>;
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no-map;
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};
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};
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@ -228,7 +229,7 @@
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"iocfg_lb_base", "iocfg_tl_base", "eint";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pio 0 0 83>;
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gpio-ranges = <&pio 0 0 84>;
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interrupt-controller;
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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@ -260,47 +261,131 @@
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};
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};
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i2c2_pins: i2c2-pins-g0 {
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i2c1_sfp_pins: i2c1-sfp-pins-g0 {
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mux {
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function = "i2c";
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groups = "i2c1_sfp";
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};
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};
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i2c2_pins: i2c2-pins {
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mux {
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function = "i2c";
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groups = "i2c2";
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};
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};
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i2c2_0_pins: i2c2-pins-g0 {
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mux {
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function = "i2c";
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groups = "i2c2_0";
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};
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};
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i2c2_1_pins: i2c2-pins-g1 {
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mux {
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function = "i2c";
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groups = "i2c2_1";
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};
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};
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gbe0_led0_pins: gbe0-pins {
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gbe0_led0_pins: gbe0-led0-pins {
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mux {
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function = "led";
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groups = "gbe0_led0";
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};
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};
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gbe1_led0_pins: gbe1-pins {
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gbe1_led0_pins: gbe1-led0-pins {
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mux {
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function = "led";
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groups = "gbe1_led0";
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};
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};
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gbe2_led0_pins: gbe2-pins {
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gbe2_led0_pins: gbe2-led0-pins {
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mux {
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function = "led";
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groups = "gbe2_led0";
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};
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};
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gbe3_led0_pins: gbe3-pins {
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gbe3_led0_pins: gbe3-led0-pins {
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mux {
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function = "led";
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groups = "gbe3_led0";
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};
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};
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i2p5gbe_led0_pins: 2p5gbe-pins {
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gbe0_led1_pins: gbe0-led1-pins {
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mux {
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function = "led";
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groups = "gbe0_led1";
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};
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};
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gbe1_led1_pins: gbe1-led1-pins {
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mux {
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function = "led";
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groups = "gbe1_led1";
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};
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};
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gbe2_led1_pins: gbe2-led1-pins {
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mux {
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function = "led";
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groups = "gbe2_led1";
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};
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};
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gbe3_led1_pins: gbe3-led1-pins {
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mux {
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function = "led";
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groups = "gbe3_led1";
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};
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};
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i2p5gbe_led0_pins: 2p5gbe-led0-pins {
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mux {
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function = "led";
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groups = "2p5gbe_led0";
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};
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};
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i2p5gbe_led1_pins: 2p5gbe-led1-pins {
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mux {
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function = "led";
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groups = "2p5gbe_led1";
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};
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};
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mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
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mux {
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function = "flash";
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groups = "emmc_45";
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};
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};
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mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
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mux {
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function = "flash";
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groups = "emmc_51";
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};
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};
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mmc0_pins_sdcard: mmc0-pins-sdcard {
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mux {
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function = "flash";
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groups = "sdcard";
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};
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};
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uart0_pins: uart0-pins {
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mux {
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function = "uart";
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groups = "uart0";
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};
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};
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};
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sgmiisys0: syscon@10060000 {
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@ -380,6 +465,8 @@
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<&infracfg CLK_INFRA_MUX_UART0_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
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<&topckgen CLK_TOP_UART_SEL>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "disabled";
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};
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@ -645,6 +732,29 @@
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status = "disabled";
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};
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt7986-mmc",
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"mediatek,mt7981-mmc";
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reg = <0 0x11230000 0 0x1000>,
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<0 0x11D60000 0 0x1000>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_MSDC400>,
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<&infracfg CLK_INFRA_MSDC2_HCK>,
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<&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
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<&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
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assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
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<&topckgen CLK_TOP_EMMC_400M_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
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<&apmixedsys CLK_APMIXED_MSDCPLL>;
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clock-names = "source",
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"hclk",
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"axi_cg",
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"ahb_cg";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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tphy: tphy@11c50000 {
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compatible = "mediatek,mt7988",
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"mediatek,generic-tphy-v2";
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@ -747,6 +857,157 @@
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
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resets = <ðrst 0>;
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ports {
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#address-cells = <1>;
|
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#size-cells = <0>;
|
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|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan0";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&gsw_phy0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan1";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&gsw_phy1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&gsw_phy2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan3";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&gsw_phy3>;
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
ethernet = <&gmac0>;
|
||||
phy-mode = "internal";
|
||||
|
||||
fixed-link {
|
||||
speed = <10000>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mediatek,pio = <&pio>;
|
||||
|
||||
gsw_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id03a2.9481";
|
||||
reg = <0>;
|
||||
phy-mode = "internal";
|
||||
nvmem-cells = <&phy_calibration_p0>;
|
||||
nvmem-cell-names = "phy-cal-data";
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gsw_phy0_led0: gsw-phy0-led0@0 {
|
||||
reg = <0>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gsw_phy0_led1: gsw-phy0-led1@1 {
|
||||
reg = <1>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsw_phy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-id03a2.9481";
|
||||
reg = <1>;
|
||||
phy-mode = "internal";
|
||||
nvmem-cells = <&phy_calibration_p1>;
|
||||
nvmem-cell-names = "phy-cal-data";
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gsw_phy1_led0: gsw-phy1-led0@0 {
|
||||
reg = <0>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gsw_phy1_led1: gsw-phy1-led1@1 {
|
||||
reg = <1>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsw_phy2: ethernet-phy@2 {
|
||||
compatible = "ethernet-phy-id03a2.9481";
|
||||
reg = <2>;
|
||||
phy-mode = "internal";
|
||||
nvmem-cells = <&phy_calibration_p2>;
|
||||
nvmem-cell-names = "phy-cal-data";
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gsw_phy2_led0: gsw-phy2-led0@0 {
|
||||
reg = <0>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gsw_phy2_led1: gsw-phy2-led1@1 {
|
||||
reg = <1>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsw_phy3: ethernet-phy@3 {
|
||||
compatible = "ethernet-phy-id03a2.9481";
|
||||
reg = <3>;
|
||||
phy-mode = "internal";
|
||||
nvmem-cells = <&phy_calibration_p3>;
|
||||
nvmem-cell-names = "phy-cal-data";
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gsw_phy3_led0: gsw-phy3-led0@0 {
|
||||
reg = <0>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gsw_phy3_led1: gsw-phy3-led1@1 {
|
||||
reg = <1>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ethwarp: syscon@15031000 {
|
||||
@ -843,6 +1104,40 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
gmac0: mac@0 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <0>;
|
||||
phy-mode = "internal";
|
||||
|
||||
fixed-link {
|
||||
speed = <10000>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: mac@1 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
gmac2: mac@2 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
mdio_bus: mdio-bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* internal 2.5G PHY */
|
||||
int_2p5g_phy: ethernet-phy@15 {
|
||||
reg = <15>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
phy-mode = "internal";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user