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lantiq: remove stale phy register setup properties from dts files
Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 37544
This commit is contained in:
parent
54b4074074
commit
bfe65eaf7a
@ -205,27 +205,22 @@
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phy0: ethernet-phy@0 {
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phy0: ethernet-phy@0 {
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reg = <0x0>;
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reg = <0x0>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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lantiq,c45-reg-init = <1 0 0 0>;
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};
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};
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phy1: ethernet-phy@1 {
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phy1: ethernet-phy@1 {
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reg = <0x1>;
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reg = <0x1>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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lantiq,c45-reg-init = <1 0 0 0>;
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};
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};
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phy5: ethernet-phy@5 {
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phy5: ethernet-phy@5 {
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reg = <0x5>;
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reg = <0x5>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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lantiq,c45-reg-init = <1 0 0 0>;
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};
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};
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phy11: ethernet-phy@11 {
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phy11: ethernet-phy@11 {
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reg = <0x11>;
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reg = <0x11>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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lantiq,c45-reg-init = <1 0 0 0>;
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};
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};
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phy13: ethernet-phy@13 {
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phy13: ethernet-phy@13 {
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reg = <0x13>;
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reg = <0x13>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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lantiq,c45-reg-init = <1 0 0 0>;
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};
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};
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};
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};
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};
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};
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@ -192,22 +192,18 @@
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phy0: ethernet-phy@0 {
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phy0: ethernet-phy@0 {
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reg = <0x0>;
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reg = <0x0>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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lantiq,c45-reg-init = <1 0 0 0>;
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};
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};
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phy1: ethernet-phy@1 {
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phy1: ethernet-phy@1 {
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reg = <0x1>;
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reg = <0x1>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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lantiq,c45-reg-init = <1 0 0 0>;
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};
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};
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phy11: ethernet-phy@11 {
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phy11: ethernet-phy@11 {
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reg = <0x11>;
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reg = <0x11>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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lantiq,c45-reg-init = <1 0 0 0>;
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};
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};
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phy13: ethernet-phy@13 {
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phy13: ethernet-phy@13 {
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reg = <0x13>;
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reg = <0x13>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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lantiq,c45-reg-init = <1 0 0 0>;
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};
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};
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};
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};
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};
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};
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@ -100,22 +100,18 @@
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phy0: ethernet-phy@0 {
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phy0: ethernet-phy@0 {
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reg = <0x0>;
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reg = <0x0>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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// lantiq,c45-reg-init = <1 0 0 0>;
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};
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};
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phy5: ethernet-phy@5 {
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phy5: ethernet-phy@5 {
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reg = <0x5>;
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reg = <0x5>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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// lantiq,c45-reg-init = <1 0 0 0>;
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};
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};
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phy11: ethernet-phy@11 {
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phy11: ethernet-phy@11 {
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reg = <0x11>;
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reg = <0x11>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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// lantiq,c45-reg-init = <1 0 0 0>;
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};
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};
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phy13: ethernet-phy@13 {
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phy13: ethernet-phy@13 {
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reg = <0x13>;
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reg = <0x13>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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// lantiq,c45-reg-init = <1 0 0 0>;
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};
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};
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};
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};
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};
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};
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@ -126,12 +126,10 @@
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phy11: ethernet-phy@11 {
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phy11: ethernet-phy@11 {
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reg = <0x11>;
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reg = <0x11>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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lantiq,c45-reg-init = <1 0 0 0>;
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};
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};
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phy13: ethernet-phy@13 {
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phy13: ethernet-phy@13 {
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reg = <0x13>;
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reg = <0x13>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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lantiq,c45-reg-init = <1 0 0 0>;
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};
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};
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};
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};
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};
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};
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