ExternalVendorCode/openwrt
1
0
Fork 0
mirror of https://github.com/openwrt/openwrt.git synced 2024-12-25 08:21:14 +00:00
Code Issues Actions 3 Packages Projects Releases Wiki Activity

ar71xx: Clear bits in ath79_setup_qca955x_eth_cfg

Browse Source 
Some u-boot versions for QCA955x set currently not cleared bits depending
on the used link speed. This breaks the rx/tx under OpenWrt. The mach-*.c
file is responsible to select the correct configuration bits and thus the
ath79_setup_qca955x_eth_cfg has to clear the unset.

Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>

SVN-Revision: 49028
This commit is contained in:
John Crispin 2016-03-16 09:27:04 +00:00
parent eff9a4b176
commit be68f34708
1 changed files with 13 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
View File

@ -833,14 +833,24 @@ void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd,
void __init ath79_setup_qca955x_eth_cfg(u32 mask) void __init ath79_setup_qca955x_eth_cfg(u32 mask)
{ {
void __iomem *base; void __iomem *base;
u32 t; u32 t, m;
m = QCA955X_ETH_CFG_RGMII_EN |
QCA955X_ETH_CFG_MII_GE0 |
QCA955X_ETH_CFG_GMII_GE0 |
QCA955X_ETH_CFG_MII_GE0_MASTER |
QCA955X_ETH_CFG_MII_GE0_SLAVE |
QCA955X_ETH_CFG_GE0_ERR_EN |
QCA955X_ETH_CFG_GE0_SGMII |
QCA955X_ETH_CFG_RMII_GE0 |
QCA955X_ETH_CFG_MII_CNTL_SPEED |
QCA955X_ETH_CFG_RMII_GE0_MASTER;
base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG); t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII); t &= ~m;
t |= mask; t |= mask;
__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);