ExternalVendorCode/openwrt
1
0
Fork 0
mirror of https://github.com/openwrt/openwrt.git synced 2025-01-31 08:25:29 +00:00
Code Issues Actions 4 Packages Projects Releases Wiki Activity

mediatek: dts: mt7988: add uart1 and uart2

Browse Source 
Add device tree nodes for uart1 and uart2 of the MT7988 SoC.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
Daniel Golle 2024-02-13 05:32:49 +00:00
parent 430a96ed0d
commit bbd49326c5
1 changed files with 103 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

103
target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
View File

@ -423,6 +423,69 @@
};
};
uart1_0_pins: uart1-0-pins {
mux {
function = "uart";
groups = "uart1_0";
};
};
uart1_1_pins: uart1-1-pins {
mux {
function = "uart";
groups = "uart1_1";
};
};
uart1_2_pins: uart1-2-pins {
mux {
function = "uart";
groups = "uart1_2";
};
};
uart1_2_lite_pins: uart1-2-lite-pins {
mux {
function = "uart";
groups = "uart1_2_lite";
};
};
uart2_pins: uart2-pins {
mux {
function = "uart";
groups = "uart2";
};
};
uart2_0_pins: uart2-0-pins {
mux {
function = "uart";
groups = "uart2_0";
};
};
uart2_1_pins: uart2-1-pins {
mux {
function = "uart";
groups = "uart2_1";
};
};
uart2_2_pins: uart2-2-pins {
mux {
function = "uart";
groups = "uart2_2";
};
};
uart2_3_pins: uart2-3-pins {
mux {
function = "uart";
groups = "uart2_3";
};
};
snfi_pins: snfi-pins {
mux {
function = "flash";
@ -595,6 +658,46 @@
status = "disabled";
};
uart1: serial@11000100 {
compatible = "mediatek,mt7986-uart",
"mediatek,mt6577-uart";
reg = <0 0x11000100 0 0x100>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
/*
* 8250-mtk driver don't control "baud" clock since commit
* e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
* still need to be passed to the driver to prevent probe fail
*/
clocks = <&topckgen CLK_TOP_UART_SEL>,
<&infracfg CLK_INFRA_52M_UART1_CK>;
clock-names = "baud", "bus";
assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
<&infracfg CLK_INFRA_MUX_UART1_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
<&topckgen CLK_TOP_UART_SEL>;
status = "disabled";
};
uart2: serial@11000200 {
compatible = "mediatek,mt7986-uart",
"mediatek,mt6577-uart";
reg = <0 0x11000200 0 0x100>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
/*
* 8250-mtk driver don't control "baud" clock since commit
* e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
* still need to be passed to the driver to prevent probe fail
*/
clocks = <&topckgen CLK_TOP_UART_SEL>,
<&infracfg CLK_INFRA_52M_UART2_CK>;
clock-names = "baud", "bus";
assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
<&infracfg CLK_INFRA_MUX_UART2_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
<&topckgen CLK_TOP_UART_SEL>;
status = "disabled";
};
snand: spi@11001000 {
compatible = "mediatek,mt7986-snand";
reg = <0 0x11001000 0 0x1000>;