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qualcommbe: ipq95xx: add bus clock for NSSCC

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Missing bus clock prevent access to NSSCC registers and thus it is
impossible change clock configuration, when ethernet connection speed
changes.

Signed-off-by: Mantas Pucka <mantas@8devices.com>
Link: https://github.com/openwrt/openwrt/pull/18459
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This commit is contained in:
Mantas Pucka 2025-04-11 17:38:28 +03:00 committed by Christian Marangi
parent 7450f993e8
commit baf7be6705
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1 changed files with 46 additions and 0 deletions

46
target/linux/qualcommbe/patches-6.6/309-clk-qcom-nsscc-ipq9574-enable-bus-clock.patch Normal file

@ -0,0 +1,46 @@
From 145aa2977a42b97d052ed0984fb305a853f55d49 Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Wed, 11 Apr 2025 15:14:19 +0300
Subject: [PATCH] clk: qcom: nsscc-ipq9574: enable bus clock
Enable bus clock, otherwise nsscc registers are unaccessible.
Signed-off-by: Mantas Pucka <mantas@8devices.com>
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 3 +-
drivers/clk/qcom/nsscc-ipq9574.c | 5 +
2 file changed, 7 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -1252,7 +1252,8 @@
<&pcsuniphy2 UNIPHY_NSS_TX_CLK>,
<&gcc GCC_NSSNOC_NSSCC_CLK>,
<&gcc GCC_NSSNOC_SNOC_CLK>,
- <&gcc GCC_NSSNOC_SNOC_1_CLK>;
+ <&gcc GCC_NSSNOC_SNOC_1_CLK>,
+ <&gcc GCC_NSSCC_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
--- a/drivers/clk/qcom/nsscc-ipq9574.c
+++ b/drivers/clk/qcom/nsscc-ipq9574.c
@@ -46,6 +46,7 @@ enum {
DT_GCC_NSSNOC_NSSCC_CLK,
DT_GCC_NSSNOC_SNOC_CLK,
DT_GCC_NSSNOC_SNOC_1_CLK,
+ DT_GCC_NSS_BUS_CLK,
};
enum {
@@ -3075,6 +3076,10 @@ static int nss_cc_ipq9574_probe(struct p
if (ret)
return ret;
+ ret = of_pm_clk_add_clk_index(dev, DT_GCC_NSS_BUS_CLK);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "Fail to add bus clock\n");
+
ret = of_pm_clk_add_clk_index(dev, DT_GCC_NSSNOC_NSSCC_CLK);
if (ret)
return dev_err_probe(dev, ret,"failed to acquire nssnoc clock\n");