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ar71xx: disable PHY_SWAP and PHY_ADDR_SWAP bits on TL-WR703N/MR3020/MR3040/MR11U boards

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The PHY_SWAP and PHY_ADDR_SWAP bits are initialized
differently by different versions of the bootloader.
This leads to broken ethernet connection with OpenWrt
on some boards.

Turn both SWAP bits OFF on these boards to make it
consistent regardless of the bootloader used.

Based on a patch by Michel Stempin <michel.stempin@wanadoo.fr>.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 35037
This commit is contained in:
Gabor Juhos 2013-01-07 14:30:37 +00:00
parent 251e4608b0
commit ba4de984b9
3 changed files with 7 additions and 4 deletions
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4
target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr11u.c
View File

@ -85,7 +85,8 @@ static void __init common_setup(void)
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_setup_ar933x_phy4_switch(false, true);
/* disable PHY_SWAP and PHY_ADDR_SWAP bits */
ath79_setup_ar933x_phy4_switch(false, false);
ath79_register_m25p80(&tl_mr11u_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr11u_leds_gpio),
@ -97,7 +98,6 @@ static void __init common_setup(void)
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_eth0_data.phy_mask = BIT(0);
ath79_register_wmac(ee, mac);
}

4
target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr3020.c
View File

@ -100,7 +100,8 @@ static void __init tl_mr3020_setup(void)
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_setup_ar933x_phy4_switch(false, true);
/* disable PHY_SWAP and PHY_ADDR_SWAP bits */
ath79_setup_ar933x_phy4_switch(false, false);
ath79_register_m25p80(&tl_mr3020_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3020_leds_gpio),
@ -118,7 +119,6 @@ static void __init tl_mr3020_setup(void)
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_eth0_data.phy_mask = BIT(0);
ath79_register_wmac(ee, mac);
}

3
target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr703n.c
View File

@ -62,6 +62,9 @@ static void __init tl_wr703n_setup(void)
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
/* disable PHY_SWAP and PHY_ADDR_SWAP bits */
ath79_setup_ar933x_phy4_switch(false, false);
ath79_register_m25p80(&tl_wr703n_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr703n_leds_gpio),
tl_wr703n_leds_gpio);