From b7aab1958591e62900e0275bc9cd80d10a4f9f53 Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Fri, 30 Sep 2022 08:03:38 +0200 Subject: [PATCH] realtek: SMP handling of R4K timer interrupts Until now there has been no good explanation why we mess with the R4K timer on SMP. After extensive testing and looking at the SDK code it becomes clear what it is all about. When we disable the CEVT_R4K module (we will do with the new timer driver) the R4K timer hardware still fires interrupts on the secondary CPU. To get around this we have two options: - Disable IRQ 7 - Stop the counter completely This patch selects option two because this is the root of evil.. To be on the safe side we will do it only in case the CEVT_R4K module is disabled. Signed-off-by: Markus Stockhausen --- .../realtek/files-5.10/arch/mips/rtl838x/prom.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c b/target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c index 3282a9c38fc..24e4bfc5686 100644 --- a/target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c +++ b/target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c @@ -35,11 +35,17 @@ static struct plat_smp_ops rtl_smp_ops; static void rtl_init_secondary(void) { +#ifndef CONFIG_CEVT_R4K /* - * MIPS timer interrupt might fire like crazy if not used or initialized - * properly. Silence it by setting the maximum possible interval. + * These devices are low on resources. There might be the chance that CEVT_R4K + * is not enabled in kernel build. Nevertheless the timer and interrupt 7 might + * be active by default after startup of secondary VPE. With no registered + * handler that leads to continuous unhandeled interrupts. In this case disable + * counting (DC) in the core and confirm a pending interrupt. */ + write_c0_cause(read_c0_cause() | CAUSE_DC); write_c0_compare(0); +#endif /* CONFIG_CEVT_R4K */ /* * Enable all CPU interrupts, as everything is managed by the external * controller. TODO: Standard vsmp_init_secondary() has special treatment for @@ -50,7 +56,7 @@ static void rtl_init_secondary(void) else set_c0_status(ST0_IM); } -#endif +#endif /* CONFIG_MIPS_MT_SMP */ const char *get_system_type(void) {