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lantiq: xrx200: switch the subtarget to the mainline DSA driver
Enable the XRX200 PMAC, GSWIP DSA tag and GSIP DSA drivers in the 5.4
kernel config. Update the existing vr9_*.dts{,i} to use the new
Ethernet and switch drivers. Drop the swconfig package from the xrx200
target because swconfig doesn't manage DSA based switches.
The new /etc/config/network format for the DSA driver is not compatible
with the old (swconfig) based one. Show a message during sysupgrade
notifying users about this change and asking them to start with a fresh
config (or forcefully update and then migrate the config manually).
Failsafe mode can now automatically bring up the first lan interface
based on board.json including DSA based setups. Drop
05_set_preinit_iface_lantiq from the xRX200 sub-target as this is not
needed anymore. For now we are keeping it for the ase, xway and
xway_legacy until there's some confirmation that it can be dropped from
there as well.
While here, some boards also receive minor fixups:
- Use LAN1 as LAN1 (according to a photo this port can also be
configured as WAN) on the Buffalo WBMR-300HPD. This makes it easier to
read the port mapping because otherwise we would have LAN{2,3,4} and
WAN (which was the case for the non-DSA version previously).
- vr9_avm_fritz3390.dts: move the "gpio" comment from port 0 and 1 to
their corresponding PHYs
- vr9_tplink_vr200.dtsi: move the "gpio" comment from port 0 to PHY 0
- vr9_tplink_tdw89x0.dtsi: move the "gpio" comment from port 0 to PHY 0
Acked-by: Aleksander Jan Bajkowski <A.Bajkowski@stud.elka.pw.edu.pl>
Tested-by: Notupus <notpp46@googlemail.com> # TD-W9980/DM200/FRITZ 7430
Tested-by: Martin Schiller <ms@dev.tdt.de> # tested on TDT VR2020
Tested-by: Martin Schiller <ms@dev.tdt.de> # tested on TP-Link TD-W8980B
Tested-by: Martin Schiller <ms@dev.tdt.de> # tested on ZyXEL P-2812HNU-F1
Tested-by: Daniel Kestrel <kestrel1974@t-online.de> # tested on Fritzbox 7490
Tested-by: Daniel Kestrel <kestrel1974@t-online.de> # tested on Fritzbox 3490
Tested-by: @jospezial <jospezial@gmx.de> # tested on VGV7510KW22 (o2 Box 6431)
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
This commit is contained in:
Martin Blumenstingl
Hauke Mehrtens
parent
dea4bae7c2
commit
b1df48caac
@ -16,6 +16,7 @@ CONFIG_NLS=y
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CONFIG_SGL_ALLOC=y
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CONFIG_SOC_AMAZON_SE=y
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CONFIG_SOC_TYPE_XWAY=y
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CONFIG_SWCONFIG=y
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CONFIG_TARGET_ISA_REV=1
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CONFIG_USB=y
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CONFIG_USB_COMMON=y
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@ -16,6 +16,7 @@ CONFIG_NLS=y
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CONFIG_SGL_ALLOC=y
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CONFIG_SOC_AMAZON_SE=y
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# CONFIG_SOC_XWAY is not set
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CONFIG_SWCONFIG=y
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CONFIG_TARGET_ISA_REV=1
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CONFIG_USB=y
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CONFIG_USB_COMMON=y
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@ -129,7 +129,6 @@ CONFIG_LANTIQ_DT_NONE=y
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# CONFIG_LANTIQ_ETOP is not set
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CONFIG_LANTIQ_WDT=y
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# CONFIG_LANTIQ_XRX200 is not set
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# CONFIG_LANTIQ_XRX200_LEGACY is not set
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CONFIG_LEDS_GPIO=y
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CONFIG_LIBFDT=y
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CONFIG_LLD_VERSION=0
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@ -211,7 +210,6 @@ CONFIG_SPI_MASTER=y
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CONFIG_SPI_MEM=y
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CONFIG_SRCU=y
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CONFIG_SWAP_IO_SPACE=y
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CONFIG_SWCONFIG=y
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CONFIG_SWPHY=y
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CONFIG_SYSCTL_EXCEPTION_TRACE=y
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CONFIG_SYS_HAS_CPU_MIPS32_R1=y
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@ -228,4 +226,3 @@ CONFIG_TICK_CPU_ACCOUNTING=y
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CONFIG_TINY_SRCU=y
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CONFIG_USE_OF=y
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CONFIG_WATCHDOG_CORE=y
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# CONFIG_XRX200_PHY_FW is not set
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@ -130,7 +130,6 @@ CONFIG_LANTIQ_DT_NONE=y
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# CONFIG_LANTIQ_ETOP is not set
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CONFIG_LANTIQ_WDT=y
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# CONFIG_LANTIQ_XRX200 is not set
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# CONFIG_LANTIQ_XRX200_LEGACY is not set
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CONFIG_LEDS_GPIO=y
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CONFIG_LIBFDT=y
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CONFIG_LOCK_DEBUGGING_SUPPORT=y
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@ -207,7 +206,6 @@ CONFIG_SPI_MASTER=y
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CONFIG_SPI_MEM=y
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CONFIG_SRCU=y
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CONFIG_SWAP_IO_SPACE=y
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CONFIG_SWCONFIG=y
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CONFIG_SWPHY=y
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CONFIG_SYSCTL_EXCEPTION_TRACE=y
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CONFIG_SYS_HAS_CPU_MIPS32_R1=y
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@ -224,4 +222,3 @@ CONFIG_TICK_CPU_ACCOUNTING=y
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CONFIG_TINY_SRCU=y
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CONFIG_USE_OF=y
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CONFIG_WATCHDOG_CORE=y
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# CONFIG_XRX200_PHY_FW is not set
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@ -120,22 +120,6 @@
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ranges = <0x0 0x203000 0x100>;
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big-endian;
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gphy0: gphy@20 {
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compatible = "lantiq,xrx200-gphy";
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reg = <0x20 0x4>;
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resets = <&reset0 31 30>, <&reset1 7 7>;
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reset-names = "gphy", "gphy2";
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};
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gphy1: gphy@68 {
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compatible = "lantiq,xrx200-gphy";
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reg = <0x68 0x4>;
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resets = <&reset0 29 28>, <&reset1 6 6>;
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reset-names = "gphy", "gphy2";
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};
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reset0: reset-controller@10 {
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compatible = "lantiq,xrx200-reset";
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reg = <0x10 4>, <0x14 4>;
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@ -446,22 +430,71 @@
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};
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};
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eth0: eth@e108000 {
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gswip: switch@e108000 {
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compatible = "lantiq,xrx200-gswip";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = < 0xe108000 0x3000 /* switch */
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0xe10b100 0x70 /* mdio */
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0xe10b1d8 0x30 /* mii */
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>;
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dsa,member = <0 0>;
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gswip_ports: ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@6 {
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reg = <0x6>;
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label = "cpu";
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ethernet = <ð0>;
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};
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};
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gswip_mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "lantiq,xrx200-mdio";
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};
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gphy-fw {
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compatible = "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw";
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lantiq,rcu = <&rcu0>;
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#address-cells = <1>;
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#size-cells = <0>;
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gphy0: gphy@20 {
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reg = <0x20>;
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resets = <&reset0 31 30>;
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reset-names = "gphy";
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};
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gphy1: gphy@68 {
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reg = <0x68>;
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resets = <&reset0 29 28>;
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reset-names = "gphy";
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};
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};
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};
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eth0: eth@e10b308 {
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compatible = "lantiq,xrx200-net";
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reg = < 0xe108000 0x3000 /* switch */
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0xe10b100 0x70 /* mdio */
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0xe10b1d8 0x30 /* mii */
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0xe10b308 0x30 /* pmac */
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>;
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reg = <0xe10b308 0x30>; /* pmac */
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interrupt-parent = <&icu0>;
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interrupts = <75 73 72>;
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resets = <&reset0 21 16>, <&reset0 8 8>;
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reset-names = "switch", "ppe";
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lantiq,phys = <&gphy0>, <&gphy1>;
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pinctrl-0 = <&mdio_pins>;
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pinctrl-names = "default";
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interrupts = <73>, <72>;
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interrupt-names = "tx", "rx";
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resets = <&reset0 21 16>, <&reset0 8 8>, <&reset0 3 3>;
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reset-names = "switch", "ppe", "ppe_dsp";
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#address-cells = <1>;
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#size-cells = <0>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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mei@e116000 {
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@ -69,46 +69,6 @@
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};
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};
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ð0 {
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interface@0 {
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compatible = "lantiq,xrx200-pdi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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lantiq,switch;
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ethernet@2 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <2>;
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phy-mode = "mii";
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phy-handle = <&phy11>;
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};
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ethernet@3 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <3>;
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phy-mode = "mii";
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phy-handle = <&phy14>;
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "lantiq,xrx200-mdio";
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phy11: ethernet-phy@11 {
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reg = <0x11>;
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compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
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};
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phy14: ethernet-phy@14 {
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reg = <0x14>;
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compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
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};
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};
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};
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&gphy0 {
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lantiq,gphy-mode = <GPHY_MODE_FE>;
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};
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@ -117,6 +77,32 @@
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lantiq,gphy-mode = <GPHY_MODE_FE>;
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};
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&gswip_mdio {
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phy11: ethernet-phy@11 {
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reg = <0x11>;
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};
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phy14: ethernet-phy@14 {
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reg = <0x14>;
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};
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};
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&gswip_ports {
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port@2 {
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reg = <2>;
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label = "lan1";
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phy-mode = "internal";
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phy-handle = <&phy11>;
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};
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port@3 {
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reg = <3>;
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label = "lan2";
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phy-mode = "internal";
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phy-handle = <&phy14>;
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};
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};
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&localbus {
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flash@0 {
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compatible = "lantiq,nor";
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@ -94,72 +94,7 @@
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};
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ð0 {
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interface@0 {
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compatible = "lantiq,xrx200-pdi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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mtd-mac-address = <&boardconfig 0x16>;
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lantiq,switch;
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ethernet@0 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <0>;
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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};
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ethernet@2 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <2>;
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phy-mode = "mii";
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phy-handle = <&phy11>;
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};
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ethernet@3 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <3>;
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phy-mode = "mii";
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phy-handle = <&phy12>;
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};
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ethernet@4 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <4>;
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phy-mode = "mii";
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phy-handle = <&phy13>;
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};
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ethernet@5 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <5>;
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phy-mode = "mii";
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phy-handle = <&phy14>;
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "lantiq,xrx200-mdio";
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phy0: ethernet-phy@0 {
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reg = <0x0>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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};
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phy11: ethernet-phy@11 {
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reg = <0x11>;
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compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
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};
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phy12: ethernet-phy@12 {
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reg = <0x12>;
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compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
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};
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phy13: ethernet-phy@13 {
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reg = <0x13>;
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compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
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};
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phy14: ethernet-phy@14 {
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reg = <0x14>;
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compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
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};
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};
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mtd-mac-address = <&boardconfig 0x16>;
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};
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&gphy0 {
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@ -183,6 +118,62 @@
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};
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};
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&gswip {
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pinctrl-0 = <&mdio_pins>;
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pinctrl-names = "default";
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};
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&gswip_mdio {
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phy0: ethernet-phy@0 {
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reg = <0x0>;
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};
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phy11: ethernet-phy@11 {
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reg = <0x11>;
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};
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phy12: ethernet-phy@12 {
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reg = <0x12>;
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};
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phy13: ethernet-phy@13 {
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reg = <0x13>;
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};
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phy14: ethernet-phy@14 {
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reg = <0x14>;
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};
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};
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&gswip_ports {
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port@0 {
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reg = <0>;
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label = "lan5";
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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phy-mode = "internal";
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phy-handle = <&phy11>;
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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phy-mode = "internal";
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phy-handle = <&phy12>;
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};
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port@4 {
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reg = <4>;
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label = "lan1";
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phy-mode = "internal";
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phy-handle = <&phy13>;
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};
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port@5 {
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reg = <5>;
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label = "lan2";
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phy-mode = "internal";
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phy-handle = <&phy14>;
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};
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};
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&localbus {
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flash@0 {
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compatible = "lantiq,nor";
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@ -54,56 +54,6 @@
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};
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};
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ð0 {
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pinctrl-0 = <&mdio_pins>,
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<&gphy0_led0_pins>, <&gphy0_led1_pins>, <&gphy0_led2_pins>,
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<&gphy1_led0_pins>, <&gphy1_led1_pins>, <&gphy1_led2_pins>;
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interface@0 {
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compatible = "lantiq,xrx200-pdi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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lantiq,switch;
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ethernet@2 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <2>;
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phy-mode = "mii";
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phy-handle = <&phy11>;
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};
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ethernet@4 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <4>;
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phy-mode = "mii";
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phy-handle = <&phy13>;
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "lantiq,xrx200-mdio";
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phy11: ethernet-phy@11 {
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reg = <0x11>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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lantiq,led1h = <0x70>;
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lantiq,led1l = <0x00>;
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lantiq,led2h = <0x00>;
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lantiq,led2l = <0x03>;
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};
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phy13: ethernet-phy@13 {
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reg = <0x13>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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lantiq,led1h = <0x70>;
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lantiq,led1l = <0x00>;
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lantiq,led2h = <0x00>;
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lantiq,led2l = <0x03>;
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};
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};
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};
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&gphy0 {
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lantiq,gphy-mode = <GPHY_MODE_GE>;
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};
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@ -112,6 +62,44 @@
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lantiq,gphy-mode = <GPHY_MODE_GE>;
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};
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&gswip {
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pinctrl-0 = <&gphy0_led0_pins>, <&gphy0_led1_pins>, <&gphy0_led2_pins>,
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<&gphy1_led0_pins>, <&gphy1_led1_pins>, <&gphy1_led2_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&gswip_mdio {
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
lantiq,led1h = <0x70>;
|
||||
lantiq,led1l = <0x00>;
|
||||
lantiq,led2h = <0x00>;
|
||||
lantiq,led2l = <0x03>;
|
||||
};
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
lantiq,led1h = <0x70>;
|
||||
lantiq,led1l = <0x00>;
|
||||
lantiq,led2h = <0x00>;
|
||||
lantiq,led2l = <0x03>;
|
||||
};
|
||||
};
|
||||
|
||||
&gswip_ports {
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan1";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
};
|
||||
|
||||
&localbus {
|
||||
flash@0 {
|
||||
compatible = "lantiq,nor";
|
||||
|
||||
@ -107,78 +107,7 @@
|
||||
};
|
||||
|
||||
ð0 {
|
||||
pinctrl-0 = <&mdio_pins>,
|
||||
<&gphy0_led0_pins>,
|
||||
<&gphy1_led0_pins>, <&gphy1_led1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
interface@0 {
|
||||
compatible = "lantiq,xrx200-pdi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
mtd-mac-address = <&boardconfig 0x16>;
|
||||
lantiq,switch;
|
||||
|
||||
ethernet@0 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <0>;
|
||||
phy-mode = "mii";
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
ethernet@2 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <2>;
|
||||
phy-mode = "mii";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
ethernet@3 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <3>;
|
||||
phy-mode = "mii";
|
||||
phy-handle = <&phy12>;
|
||||
};
|
||||
ethernet@4 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <4>;
|
||||
phy-mode = "mii";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
ethernet@5 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <5>;
|
||||
phy-mode = "mii";
|
||||
phy-handle = <&phy14>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "lantiq,xrx200-mdio";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy12: ethernet-phy@12 {
|
||||
reg = <0x12>;
|
||||
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy14: ethernet-phy@14 {
|
||||
reg = <0x14>;
|
||||
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
mtd-mac-address = <&boardconfig 0x16>;
|
||||
};
|
||||
|
||||
&gphy0 {
|
||||
@ -203,6 +132,64 @@
|
||||
};
|
||||
};
|
||||
|
||||
&gswip {
|
||||
pinctrl-0 = <&mdio_pins>,
|
||||
<&gphy0_led0_pins>,
|
||||
<&gphy1_led0_pins>, <&gphy1_led1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&gswip_mdio {
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
phy12: ethernet-phy@12 {
|
||||
reg = <0x12>;
|
||||
};
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
phy14: ethernet-phy@14 {
|
||||
reg = <0x14>;
|
||||
};
|
||||
};
|
||||
|
||||
&gswip_ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "wan";
|
||||
phy-mode = "mii";
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan1";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy12>;
|
||||
};
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan4";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "lan3";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy14>;
|
||||
};
|
||||
};
|
||||
|
||||
&localbus {
|
||||
flash@0 {
|
||||
compatible = "lantiq,nor";
|
||||
|
||||
@ -127,76 +127,8 @@
|
||||
};
|
||||
|
||||
ð0 {
|
||||
pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
interface@0 {
|
||||
compatible = "lantiq,xrx200-pdi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
mtd-mac-address = <&boardconfig 0x16>;
|
||||
mtd-mac-address-increment = <1>;
|
||||
lantiq,switch;
|
||||
|
||||
ethernet@0 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <0>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
ethernet@1 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <1>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
ethernet@2 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <2>;
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
ethernet@4 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <4>;
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
ethernet@5 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <5>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy5>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "lantiq,xrx200-mdio";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
mtd-mac-address = <&boardconfig 0x16>;
|
||||
mtd-mac-address-increment = <1>;
|
||||
};
|
||||
|
||||
&gphy0 {
|
||||
@ -221,6 +153,62 @@
|
||||
};
|
||||
};
|
||||
|
||||
&gswip {
|
||||
pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&gswip_mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
};
|
||||
|
||||
&gswip_ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan4";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan3";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan1";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "wan";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy5>;
|
||||
};
|
||||
};
|
||||
|
||||
&localbus {
|
||||
flash@0 {
|
||||
compatible = "lantiq,nor";
|
||||
|
||||
@ -114,72 +114,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
ð0 {
|
||||
interface@0 {
|
||||
compatible = "lantiq,xrx200-pdi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
lantiq,switch;
|
||||
|
||||
ethernet@0 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <0>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy0>;
|
||||
gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
ethernet@1 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <1>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy1>;
|
||||
gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
ethernet@2 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <2>;
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
|
||||
ethernet@4 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <4>;
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "lantiq,xrx200-mdio";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gphy0 {
|
||||
lantiq,gphy-mode = <GPHY_MODE_GE>;
|
||||
};
|
||||
@ -208,6 +142,61 @@
|
||||
};
|
||||
};
|
||||
|
||||
&gswip {
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&gswip_mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
};
|
||||
|
||||
&gswip_ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan3";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan4";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan1";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
|
||||
@ -106,72 +106,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
ð0 {
|
||||
interface@0 {
|
||||
compatible = "lantiq,xrx200-pdi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
lantiq,switch;
|
||||
|
||||
ethernet@0 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <0>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy0>;
|
||||
gpios = <&gpio 32 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
ethernet@1 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <1>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy1>;
|
||||
gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
ethernet@2 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <2>;
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
|
||||
ethernet@4 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <4>;
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "lantiq,xrx200-mdio";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gphy0 {
|
||||
lantiq,gphy-mode = <GPHY_MODE_GE>;
|
||||
};
|
||||
@ -207,6 +141,61 @@
|
||||
};
|
||||
};
|
||||
|
||||
&gswip {
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&gswip_mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
gpios = <&gpio 32 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
};
|
||||
|
||||
&gswip_ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan3";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan4";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan1";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi {
|
||||
status = "okay";
|
||||
|
||||
|
||||
@ -81,71 +81,8 @@
|
||||
};
|
||||
|
||||
ð0 {
|
||||
interface@0 {
|
||||
compatible = "lantiq,xrx200-pdi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
mtd-mac-address = <&urlader 0xa91>;
|
||||
mtd-mac-address-increment = <(-2)>;
|
||||
lantiq,switch;
|
||||
|
||||
ethernet@0 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <0>;
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
ethernet@1 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <1>;
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
|
||||
ethernet@2 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <2>;
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
|
||||
ethernet@4 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <4>;
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "lantiq,xrx200-mdio";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x00>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0x01>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
mtd-mac-address = <&urlader 0xa91>;
|
||||
mtd-mac-address-increment = <(-2)>;
|
||||
};
|
||||
|
||||
&gphy0 {
|
||||
@ -171,6 +108,61 @@
|
||||
|
||||
};
|
||||
|
||||
&gswip {
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&gswip_mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x00>;
|
||||
reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0x01>;
|
||||
reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
};
|
||||
|
||||
&gswip_ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan3";
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan4";
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan1";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
|
||||
|
||||
@ -181,33 +181,17 @@
|
||||
lantiq,gphy-mode = <GPHY_MODE_FE>;
|
||||
};
|
||||
|
||||
ð0 {
|
||||
lantiq,phys = <&gphy0>;
|
||||
|
||||
interface@0 {
|
||||
compatible = "lantiq,xrx200-pdi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
mac-address = [ 00 11 22 33 44 55 ];
|
||||
lantiq,switch;
|
||||
|
||||
ethernet@2 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <2>;
|
||||
phy-mode = "mii";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "lantiq,xrx200-mdio";
|
||||
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
&gswip_mdio {
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
};
|
||||
|
||||
&gswip_ports {
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -185,70 +185,6 @@
|
||||
lantiq,gphy-mode = <GPHY_MODE_FE>;
|
||||
};
|
||||
|
||||
ð0 {
|
||||
interface@0 {
|
||||
compatible = "lantiq,xrx200-pdi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
lantiq,switch;
|
||||
|
||||
ethernet@2 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <2>;
|
||||
phy-mode = "mii";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
|
||||
ethernet@3 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <3>;
|
||||
phy-mode = "mii";
|
||||
phy-handle = <&phy12>;
|
||||
};
|
||||
|
||||
ethernet@4 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <4>;
|
||||
phy-mode = "mii";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
|
||||
ethernet@5 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <5>;
|
||||
phy-mode = "mii";
|
||||
phy-handle = <&phy14>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "lantiq,xrx200-mdio";
|
||||
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
|
||||
phy12: ethernet-phy@12 {
|
||||
reg = <0x12>;
|
||||
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
|
||||
phy14: ethernet-phy@14 {
|
||||
reg = <0x14>;
|
||||
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
@ -262,6 +198,48 @@
|
||||
};
|
||||
};
|
||||
|
||||
&gswip_mdio {
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
phy12: ethernet-phy@12 {
|
||||
reg = <0x12>;
|
||||
};
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
phy14: ethernet-phy@14 {
|
||||
reg = <0x14>;
|
||||
};
|
||||
};
|
||||
|
||||
&gswip_ports {
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan3";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan4";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy12>;
|
||||
};
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan1";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "lan2";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy14>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb_phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -114,74 +114,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
ð0 {
|
||||
interface@0 {
|
||||
compatible = "lantiq,xrx200-pdi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
lantiq,switch;
|
||||
|
||||
ethernet@0 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <0>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
ethernet@1 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <1>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
ethernet@2 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <2>;
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
ethernet@4 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <4>;
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
ethernet@5 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <5>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy5>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "lantiq,xrx200-mdio";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gphy0 {
|
||||
lantiq,gphy-mode = <GPHY_MODE_GE>;
|
||||
};
|
||||
@ -215,6 +147,62 @@
|
||||
};
|
||||
};
|
||||
|
||||
&gswip {
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&gswip_mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
};
|
||||
|
||||
&gswip_ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan3";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan4";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan1";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "wan";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy5>;
|
||||
};
|
||||
};
|
||||
|
||||
&localbus {
|
||||
flash@1 {
|
||||
compatible = "lantiq,nand-xway";
|
||||
|
||||
@ -152,64 +152,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
ð0 {
|
||||
interface@0 {
|
||||
compatible = "lantiq,xrx200-pdi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
lantiq,switch;
|
||||
|
||||
ethernet@2 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <2>;
|
||||
phy-mode = "mii";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
ethernet@3 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <3>;
|
||||
phy-mode = "mii";
|
||||
phy-handle = <&phy12>;
|
||||
};
|
||||
ethernet@4 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <4>;
|
||||
phy-mode = "mii";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
ethernet@5 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <5>;
|
||||
phy-mode = "mii";
|
||||
phy-handle = <&phy14>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "lantiq,xrx200-mdio";
|
||||
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy12: ethernet-phy@12 {
|
||||
reg = <0x12>;
|
||||
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy14: ethernet-phy@14 {
|
||||
reg = <0x14>;
|
||||
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gphy0 {
|
||||
lantiq,gphy-mode = <GPHY_MODE_FE>;
|
||||
};
|
||||
@ -237,6 +179,48 @@
|
||||
};
|
||||
};
|
||||
|
||||
&gswip_mdio {
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
phy12: ethernet-phy@12 {
|
||||
reg = <0x12>;
|
||||
};
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
phy14: ethernet-phy@14 {
|
||||
reg = <0x14>;
|
||||
};
|
||||
};
|
||||
|
||||
&gswip_ports {
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan3";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan4";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy12>;
|
||||
};
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan1";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "lan2";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy14>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi {
|
||||
status = "okay";
|
||||
|
||||
|
||||
@ -97,83 +97,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
ð0 {
|
||||
interface@0 {
|
||||
compatible = "lantiq,xrx200-pdi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
lantiq,switch;
|
||||
|
||||
ethernet@0 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <0>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
ethernet@1 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <1>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
ethernet@2 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <2>;
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
ethernet@4 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <4>;
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
};
|
||||
|
||||
interface@1 {
|
||||
compatible = "lantiq,xrx200-pdi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
lantiq,wan;
|
||||
|
||||
ethernet@5 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <5>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy5>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "lantiq,xrx200-mdio";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gphy0 {
|
||||
lantiq,gphy-mode = <GPHY_MODE_GE>;
|
||||
};
|
||||
@ -210,6 +133,62 @@
|
||||
};
|
||||
};
|
||||
|
||||
&gswip {
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&gswip_mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
};
|
||||
|
||||
&gswip_ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan4";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan3";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan1";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "wan";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy5>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi {
|
||||
status = "okay";
|
||||
|
||||
|
||||
@ -83,37 +83,23 @@
|
||||
};
|
||||
};
|
||||
|
||||
ð0 {
|
||||
lantiq,phys = <&gphy1>;
|
||||
&gphy1 {
|
||||
lantiq,gphy-mode = <GPHY_MODE_FE>;
|
||||
};
|
||||
|
||||
interface@0 {
|
||||
compatible = "lantiq,xrx200-pdi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
ethernet@4 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <4>;
|
||||
phy-mode = "mii";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "lantiq,xrx200-mdio";
|
||||
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
&gswip_mdio {
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
};
|
||||
|
||||
&gphy1 {
|
||||
lantiq,gphy-mode = <GPHY_MODE_FE>;
|
||||
&gswip_ports {
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
|
||||
@ -110,66 +110,7 @@
|
||||
};
|
||||
|
||||
ð0 {
|
||||
pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
interface@0 {
|
||||
compatible = "lantiq,xrx200-pdi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
mtd-mac-address = <&ath9k_cal 0xf100>;
|
||||
lantiq,switch;
|
||||
|
||||
ethernet@0 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <0>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy0>;
|
||||
// gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
ethernet@2 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <2>;
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
ethernet@4 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <4>;
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
ethernet@5 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <5>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy5>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "lantiq,xrx200-mdio";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
mtd-mac-address = <&ath9k_cal 0xf100>;
|
||||
};
|
||||
|
||||
&gphy0 {
|
||||
@ -199,6 +140,54 @@
|
||||
};
|
||||
};
|
||||
|
||||
&gswip {
|
||||
pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&gswip_mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
// reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
};
|
||||
|
||||
&gswip_ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan2";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan3";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan4";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "lan1";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy5>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
|
||||
@ -100,66 +100,7 @@
|
||||
};
|
||||
|
||||
ð0 {
|
||||
pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
lan: interface@0 {
|
||||
compatible = "lantiq,xrx200-pdi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
mtd-mac-address = <&romfile 0xf100>;
|
||||
lantiq,switch;
|
||||
|
||||
ethernet@0 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <0>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy0>;
|
||||
// gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
ethernet@2 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <2>;
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
ethernet@4 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <4>;
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
ethernet@5 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <5>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy5>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "lantiq,xrx200-mdio";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
mtd-mac-address = <&romfile 0xf100>;
|
||||
};
|
||||
|
||||
&gphy0 {
|
||||
@ -189,6 +130,54 @@
|
||||
};
|
||||
};
|
||||
|
||||
&gswip {
|
||||
pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&gswip_mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
// reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
};
|
||||
|
||||
&gswip_ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan3";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan1";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "lan4";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy5>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
|
||||
@ -110,80 +110,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
ð0 {
|
||||
pinctrl-0 = <&mdio_pins>,
|
||||
<&gphy0_led1_pins>, <&gphy0_led2_pins>,
|
||||
<&gphy1_led1_pins>, <&gphy1_led2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
interface@0 {
|
||||
compatible = "lantiq,xrx200-pdi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
mac-address = [ 00 11 22 33 44 55 ];
|
||||
lantiq,switch;
|
||||
|
||||
ethernet@0 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <0>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
ethernet@1 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <1>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
ethernet@2 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <2>;
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
ethernet@4 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <4>;
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
ethernet@5 {
|
||||
compatible = "lantiq,xrx200-pdi-port";
|
||||
reg = <5>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy5>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "lantiq,xrx200-mdio";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gphy0 {
|
||||
lantiq,gphy-mode = <GPHY_MODE_GE>;
|
||||
};
|
||||
@ -221,6 +147,64 @@
|
||||
};
|
||||
};
|
||||
|
||||
&gswip {
|
||||
pinctrl-0 = <&mdio_pins>,
|
||||
<&gphy0_led1_pins>, <&gphy0_led2_pins>,
|
||||
<&gphy1_led1_pins>, <&gphy1_led2_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&gswip_mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
};
|
||||
|
||||
&gswip_ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan1";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan2";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan3";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan4";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy13>;
|
||||
};
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "wan";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy5>;
|
||||
};
|
||||
};
|
||||
|
||||
&pci0 {
|
||||
status = "okay";
|
||||
|
||||
|
||||
@ -1,5 +1,10 @@
|
||||
DEVICE_VARS += TPLINK_FLASHLAYOUT TPLINK_HWID TPLINK_HWREV TPLINK_HWREVADD TPLINK_HVERSION
|
||||
|
||||
define Device/dsa-migration
|
||||
DEVICE_COMPAT_VERSION := 1.1
|
||||
DEVICE_COMPAT_MESSAGE := Config cannot be migrated from swconfig to DSA
|
||||
endef
|
||||
|
||||
define Device/lantiqTpLink
|
||||
DEVICE_VENDOR := TP-Link
|
||||
TPLINK_HWREVADD := 0
|
||||
@ -13,6 +18,7 @@ define Device/lantiqTpLink
|
||||
endef
|
||||
|
||||
define Device/tplink_tdw8970
|
||||
$(Device/dsa-migration)
|
||||
$(Device/lantiqTpLink)
|
||||
DEVICE_MODEL := TD-W8970
|
||||
DEVICE_VARIANT := v1
|
||||
@ -26,6 +32,7 @@ endef
|
||||
TARGET_DEVICES += tplink_tdw8970
|
||||
|
||||
define Device/tplink_tdw8980
|
||||
$(Device/dsa-migration)
|
||||
$(Device/lantiqTpLink)
|
||||
DEVICE_MODEL := TD-W8980
|
||||
DEVICE_VARIANT := v1
|
||||
@ -39,6 +46,7 @@ endef
|
||||
TARGET_DEVICES += tplink_tdw8980
|
||||
|
||||
define Device/tplink_vr200
|
||||
$(Device/dsa-migration)
|
||||
$(Device/lantiqTpLink)
|
||||
DEVICE_MODEL := Archer VR200
|
||||
DEVICE_VARIANT := v1
|
||||
@ -52,6 +60,7 @@ endef
|
||||
TARGET_DEVICES += tplink_vr200
|
||||
|
||||
define Device/tplink_vr200v
|
||||
$(Device/dsa-migration)
|
||||
$(Device/lantiqTpLink)
|
||||
DEVICE_MODEL := Archer VR200v
|
||||
DEVICE_VARIANT := v1
|
||||
|
||||
@ -1,6 +1,12 @@
|
||||
DEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_HW_ID
|
||||
|
||||
define Device/dsa-migration
|
||||
DEVICE_COMPAT_VERSION := 1.1
|
||||
DEVICE_COMPAT_MESSAGE := Config cannot be migrated from swconfig to DSA
|
||||
endef
|
||||
|
||||
define Device/alphanetworks_asl56026
|
||||
$(Device/dsa-migration)
|
||||
DEVICE_VENDOR := Alpha
|
||||
DEVICE_MODEL := ASL56026
|
||||
DEVICE_ALT0_VENDOR := BT Openreach
|
||||
@ -10,6 +16,7 @@ endef
|
||||
TARGET_DEVICES += alphanetworks_asl56026
|
||||
|
||||
define Device/arcadyan_arv7519rw22
|
||||
$(Device/dsa-migration)
|
||||
DEVICE_VENDOR := Arcadyan
|
||||
DEVICE_MODEL := ARV7519RW22
|
||||
DEVICE_ALT0_VENDOR := Orange
|
||||
@ -26,6 +33,7 @@ endef
|
||||
TARGET_DEVICES += arcadyan_arv7519rw22
|
||||
|
||||
define Device/arcadyan_vg3503j
|
||||
$(Device/dsa-migration)
|
||||
DEVICE_VENDOR := BT Openreach
|
||||
DEVICE_MODEL := ECI VDSL Modem V-2FUb/R
|
||||
IMAGE_SIZE := 8000k
|
||||
@ -34,6 +42,7 @@ endef
|
||||
TARGET_DEVICES += arcadyan_vg3503j
|
||||
|
||||
define Device/arcadyan_vgv7510kw22-brn
|
||||
$(Device/dsa-migration)
|
||||
$(Device/lantiqBrnImage)
|
||||
DEVICE_VENDOR := Arcadyan
|
||||
DEVICE_MODEL := VGV7510KW22
|
||||
@ -51,6 +60,7 @@ endef
|
||||
TARGET_DEVICES += arcadyan_vgv7510kw22-brn
|
||||
|
||||
define Device/arcadyan_vgv7510kw22-nor
|
||||
$(Device/dsa-migration)
|
||||
DEVICE_VENDOR := Arcadyan
|
||||
DEVICE_MODEL := VGV7510KW22
|
||||
DEVICE_VARIANT := NOR
|
||||
@ -64,6 +74,7 @@ endef
|
||||
TARGET_DEVICES += arcadyan_vgv7510kw22-nor
|
||||
|
||||
define Device/arcadyan_vgv7519-brn
|
||||
$(Device/dsa-migration)
|
||||
$(Device/lantiqBrnImage)
|
||||
DEVICE_VENDOR := Arcadyan
|
||||
DEVICE_MODEL := VGV7519
|
||||
@ -81,6 +92,7 @@ endef
|
||||
TARGET_DEVICES += arcadyan_vgv7519-brn
|
||||
|
||||
define Device/arcadyan_vgv7519-nor
|
||||
$(Device/dsa-migration)
|
||||
DEVICE_VENDOR := Arcadyan
|
||||
DEVICE_MODEL := VGV7519
|
||||
DEVICE_VARIANT := NOR
|
||||
@ -94,6 +106,7 @@ endef
|
||||
TARGET_DEVICES += arcadyan_vgv7519-nor
|
||||
|
||||
define Device/avm_fritz3370
|
||||
$(Device/dsa-migration)
|
||||
$(Device/AVM)
|
||||
$(Device/NAND)
|
||||
DEVICE_MODEL := FRITZ!Box 3370
|
||||
@ -107,6 +120,7 @@ define Device/avm_fritz3370
|
||||
endef
|
||||
|
||||
define Device/avm_fritz3370-rev2-hynix
|
||||
$(Device/dsa-migration)
|
||||
$(Device/avm_fritz3370)
|
||||
DEVICE_MODEL := FRITZ!Box 3370
|
||||
DEVICE_VARIANT := Rev. 2 (Hynix NAND)
|
||||
@ -114,6 +128,7 @@ endef
|
||||
TARGET_DEVICES += avm_fritz3370-rev2-hynix
|
||||
|
||||
define Device/avm_fritz3370-rev2-micron
|
||||
$(Device/dsa-migration)
|
||||
$(Device/avm_fritz3370)
|
||||
DEVICE_MODEL := FRITZ!Box 3370
|
||||
DEVICE_VARIANT := Rev. 2 (Micron NAND)
|
||||
@ -121,6 +136,7 @@ endef
|
||||
TARGET_DEVICES += avm_fritz3370-rev2-micron
|
||||
|
||||
define Device/avm_fritz3390
|
||||
$(Device/dsa-migration)
|
||||
$(Device/AVM)
|
||||
$(Device/NAND)
|
||||
DEVICE_MODEL := FRITZ!Box 3390
|
||||
@ -132,6 +148,7 @@ endef
|
||||
TARGET_DEVICES += avm_fritz3390
|
||||
|
||||
define Device/avm_fritz7360sl
|
||||
$(Device/dsa-migration)
|
||||
$(Device/AVM)
|
||||
DEVICE_MODEL := FRITZ!Box 7360 SL
|
||||
IMAGE_SIZE := 15744k
|
||||
@ -141,6 +158,7 @@ endef
|
||||
TARGET_DEVICES += avm_fritz7360sl
|
||||
|
||||
define Device/avm_fritz7360-v2
|
||||
$(Device/dsa-migration)
|
||||
$(Device/AVM)
|
||||
DEVICE_MODEL := FRITZ!Box 7360
|
||||
DEVICE_VARIANT := v2
|
||||
@ -150,6 +168,7 @@ endef
|
||||
TARGET_DEVICES += avm_fritz7360-v2
|
||||
|
||||
define Device/avm_fritz7362sl
|
||||
$(Device/dsa-migration)
|
||||
$(Device/AVM)
|
||||
$(Device/NAND)
|
||||
DEVICE_MODEL := FRITZ!Box 7362 SL
|
||||
@ -160,6 +179,7 @@ endef
|
||||
TARGET_DEVICES += avm_fritz7362sl
|
||||
|
||||
define Device/avm_fritz7412
|
||||
$(Device/dsa-migration)
|
||||
$(Device/AVM)
|
||||
$(Device/NAND)
|
||||
DEVICE_MODEL := FRITZ!Box 7412
|
||||
@ -171,6 +191,7 @@ endef
|
||||
TARGET_DEVICES += avm_fritz7412
|
||||
|
||||
define Device/avm_fritz7430
|
||||
$(Device/dsa-migration)
|
||||
$(Device/AVM)
|
||||
$(Device/NAND)
|
||||
DEVICE_MODEL := FRITZ!Box 7430
|
||||
@ -181,6 +202,7 @@ endef
|
||||
TARGET_DEVICES += avm_fritz7430
|
||||
|
||||
define Device/bt_homehub-v5a
|
||||
$(Device/dsa-migration)
|
||||
$(Device/NAND)
|
||||
DEVICE_VENDOR := British Telecom
|
||||
DEVICE_MODEL := Home Hub 5
|
||||
@ -193,6 +215,7 @@ endef
|
||||
TARGET_DEVICES += bt_homehub-v5a
|
||||
|
||||
define Device/buffalo_wbmr-300hpd
|
||||
$(Device/dsa-migration)
|
||||
DEVICE_VENDOR := Buffalo
|
||||
DEVICE_MODEL := WBMR-300HPD
|
||||
IMAGE_SIZE := 15616k
|
||||
@ -202,6 +225,7 @@ endef
|
||||
TARGET_DEVICES += buffalo_wbmr-300hpd
|
||||
|
||||
define Device/lantiq_easy80920-nand
|
||||
$(Device/dsa-migration)
|
||||
$(Device/lantiqFullImage)
|
||||
DEVICE_VENDOR := Lantiq
|
||||
DEVICE_MODEL := VR9 EASY80920
|
||||
@ -212,6 +236,7 @@ endef
|
||||
TARGET_DEVICES += lantiq_easy80920-nand
|
||||
|
||||
define Device/lantiq_easy80920-nor
|
||||
$(Device/dsa-migration)
|
||||
DEVICE_VENDOR := Lantiq
|
||||
DEVICE_MODEL := VR9 EASY80920
|
||||
DEVICE_VARIANT := NOR
|
||||
@ -221,6 +246,7 @@ endef
|
||||
TARGET_DEVICES += lantiq_easy80920-nor
|
||||
|
||||
define Device/netgear_dm200
|
||||
$(Device/dsa-migration)
|
||||
DEVICE_VENDOR := NETGEAR
|
||||
DEVICE_MODEL := DM200
|
||||
IMAGES := sysupgrade.bin factory.img
|
||||
@ -236,6 +262,7 @@ endef
|
||||
TARGET_DEVICES += netgear_dm200
|
||||
|
||||
define Device/zyxel_p-2812hnu-f1
|
||||
$(Device/dsa-migration)
|
||||
$(Device/NAND)
|
||||
DEVICE_VENDOR := ZyXEL
|
||||
DEVICE_MODEL := P-2812HNU
|
||||
@ -248,6 +275,7 @@ endef
|
||||
TARGET_DEVICES += zyxel_p-2812hnu-f1
|
||||
|
||||
define Device/zyxel_p-2812hnu-f3
|
||||
$(Device/dsa-migration)
|
||||
$(Device/NAND)
|
||||
DEVICE_VENDOR := ZyXEL
|
||||
DEVICE_MODEL := P-2812HNU
|
||||
|
||||
@ -1,71 +0,0 @@
|
||||
From d0ee51bbb7ce9880749a3d4794ec1fbbcda0f381 Mon Sep 17 00:00:00 2001
|
||||
From: Mathias Kresin <dev@kresin.me>
|
||||
Date: Sun, 7 Jul 2019 21:45:51 +0200
|
||||
Subject: [PATCH] MIPS: lantiq revert DSA switch driver PMU/clock changes
|
||||
|
||||
Switch back to the former used names, to make the legacy switch driver
|
||||
happy.
|
||||
|
||||
Signed-off-by: Mathias Kresin <dev@kresin.me>
|
||||
---
|
||||
arch/mips/lantiq/xway/sysctrl.c | 18 +++++++++---------
|
||||
1 file changed, 9 insertions(+), 9 deletions(-)
|
||||
|
||||
--- a/arch/mips/lantiq/xway/sysctrl.c
|
||||
+++ b/arch/mips/lantiq/xway/sysctrl.c
|
||||
@@ -469,9 +469,9 @@ void __init ltq_soc_init(void)
|
||||
|
||||
if (of_machine_is_compatible("lantiq,grx390") ||
|
||||
of_machine_is_compatible("lantiq,ar10")) {
|
||||
- clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY0);
|
||||
- clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY1);
|
||||
- clkdev_add_pmu("1e108000.switch", "gphy2", 0, 0, PMU_GPHY2);
|
||||
+ clkdev_add_pmu("1f203020.gphy", NULL, 1, 0, PMU_GPHY0);
|
||||
+ clkdev_add_pmu("1f203068.gphy", NULL, 1, 0, PMU_GPHY1);
|
||||
+ clkdev_add_pmu("1f2030ac.gphy", NULL, 1, 0, PMU_GPHY2);
|
||||
clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB0_P);
|
||||
clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB1_P);
|
||||
/* rc 0 */
|
||||
@@ -503,7 +503,7 @@ void __init ltq_soc_init(void)
|
||||
} else if (of_machine_is_compatible("lantiq,grx390")) {
|
||||
clkdev_add_static(ltq_grx390_cpu_hz(), ltq_grx390_fpi_hz(),
|
||||
ltq_grx390_fpi_hz(), ltq_grx390_pp32_hz());
|
||||
- clkdev_add_pmu("1e108000.switch", "gphy3", 0, 0, PMU_GPHY3);
|
||||
+ clkdev_add_pmu("1f203264.gphy", NULL, 1, 0, PMU_GPHY3);
|
||||
clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
|
||||
clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
|
||||
/* rc 2 */
|
||||
@@ -511,7 +511,7 @@ void __init ltq_soc_init(void)
|
||||
clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI);
|
||||
clkdev_add_pmu("1f106a00.pcie", "pdi", 1, 1, PMU1_PCIE2_PDI);
|
||||
clkdev_add_pmu("1a800000.pcie", "ctl", 1, 1, PMU1_PCIE2_CTL);
|
||||
- clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP);
|
||||
+ clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP);
|
||||
clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
|
||||
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
|
||||
} else if (of_machine_is_compatible("lantiq,ar10")) {
|
||||
@@ -519,7 +519,7 @@ void __init ltq_soc_init(void)
|
||||
ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz());
|
||||
clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
|
||||
clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
|
||||
- clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH |
|
||||
+ clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH |
|
||||
PMU_PPE_DP | PMU_PPE_TC);
|
||||
clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
|
||||
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
|
||||
@@ -540,12 +540,12 @@ void __init ltq_soc_init(void)
|
||||
clkdev_add_pmu(NULL, "ahb", 1, 0, PMU_AHBM | PMU_AHBS);
|
||||
|
||||
clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
|
||||
- clkdev_add_pmu("1e10b308.eth", NULL, 0, 0,
|
||||
+ clkdev_add_pmu("1e108000.eth", NULL, 0, 0,
|
||||
PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
|
||||
PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
|
||||
PMU_PPE_QSB | PMU_PPE_TOP);
|
||||
- clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY);
|
||||
- clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY);
|
||||
+ clkdev_add_pmu("1f203020.gphy", NULL, 0, 0, PMU_GPHY);
|
||||
+ clkdev_add_pmu("1f203068.gphy", NULL, 0, 0, PMU_GPHY);
|
||||
clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
|
||||
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
|
||||
clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,352 +0,0 @@
|
||||
From c8eedcadc38a5e6008d3990fbe0a5285b30335fc Mon Sep 17 00:00:00 2001
|
||||
From: Mathias Kresin <dev@kresin.me>
|
||||
Date: Sun, 7 Jul 2019 21:48:56 +0200
|
||||
Subject: [PATCH] MIPS: lantiq: Add GPHY Firmware loader
|
||||
|
||||
Upstream, the GPHY Firmware loader has been merged into the DSA switch
|
||||
driver. But we don't use the driver yet, so bring it back.
|
||||
|
||||
Signed-off-by: Mathias Kresin <dev@kresin.me>
|
||||
---
|
||||
.../bindings/mips/lantiq/rcu-gphy.txt | 36 +++
|
||||
.../devicetree/bindings/mips/lantiq/rcu.txt | 18 ++
|
||||
arch/mips/configs/xway_defconfig | 1 +
|
||||
arch/mips/lantiq/Kconfig | 4 +
|
||||
drivers/soc/lantiq/Makefile | 1 +
|
||||
drivers/soc/lantiq/gphy.c | 224 ++++++++++++++++++
|
||||
6 files changed, 284 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
|
||||
create mode 100644 drivers/soc/lantiq/gphy.c
|
||||
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
|
||||
@@ -0,0 +1,37 @@
|
||||
+Lantiq XWAY SoC GPHY binding
|
||||
+============================
|
||||
+
|
||||
+This binding describes a software-defined ethernet PHY, provided by the RCU
|
||||
+module on newer Lantiq XWAY SoCs (xRX200 and newer).
|
||||
+
|
||||
+-------------------------------------------------------------------------------
|
||||
+Required properties:
|
||||
+- compatible : Should be one of
|
||||
+ "lantiq,xrx200-gphy"
|
||||
+ "lantiq,xrx200a1x-gphy"
|
||||
+ "lantiq,xrx200a2x-gphy"
|
||||
+ "lantiq,xrx300-gphy"
|
||||
+ "lantiq,xrx330-gphy"
|
||||
+- reg : Addrress of the GPHY FW load address register
|
||||
+- resets : Must reference the RCU GPHY reset bit
|
||||
+- reset-names : One entry, value must be "gphy" or optional "gphy2"
|
||||
+- clocks : A reference to the (PMU) GPHY clock gate
|
||||
+
|
||||
+Optional properties:
|
||||
+- lantiq,gphy-mode : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
|
||||
+ <dt-bindings/mips/lantiq_xway_gphy.h>
|
||||
+
|
||||
+
|
||||
+-------------------------------------------------------------------------------
|
||||
+Example for the GPHys on the xRX200 SoCs:
|
||||
+
|
||||
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
|
||||
+ gphy0: gphy@20 {
|
||||
+ compatible = "lantiq,xrx200a2x-gphy";
|
||||
+ reg = <0x20 0x4>;
|
||||
+
|
||||
+ resets = <&reset0 31 30>, <&reset1 7 7>;
|
||||
+ reset-names = "gphy", "gphy2";
|
||||
+ clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
|
||||
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
|
||||
+ };
|
||||
--- a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
|
||||
+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
|
||||
@@ -26,6 +26,24 @@ Example of the RCU bindings on a xRX200
|
||||
ranges = <0x0 0x203000 0x100>;
|
||||
big-endian;
|
||||
|
||||
+ gphy0: gphy@20 {
|
||||
+ compatible = "lantiq,xrx200a2x-gphy";
|
||||
+ reg = <0x20 0x4>;
|
||||
+
|
||||
+ resets = <&reset0 31 30>, <&reset1 7 7>;
|
||||
+ reset-names = "gphy", "gphy2";
|
||||
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
|
||||
+ };
|
||||
+
|
||||
+ gphy1: gphy@68 {
|
||||
+ compatible = "lantiq,xrx200a2x-gphy";
|
||||
+ reg = <0x68 0x4>;
|
||||
+
|
||||
+ resets = <&reset0 29 28>, <&reset1 6 6>;
|
||||
+ reset-names = "gphy", "gphy2";
|
||||
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
|
||||
+ };
|
||||
+
|
||||
reset0: reset-controller@10 {
|
||||
compatible = "lantiq,xrx200-reset";
|
||||
reg = <0x10 4>, <0x14 4>;
|
||||
--- a/arch/mips/configs/xway_defconfig
|
||||
+++ b/arch/mips/configs/xway_defconfig
|
||||
@@ -13,6 +13,7 @@ CONFIG_EMBEDDED=y
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
CONFIG_LANTIQ=y
|
||||
CONFIG_PCI_LANTIQ=y
|
||||
+CONFIG_XRX200_PHY_FW=y
|
||||
CONFIG_CPU_MIPS32_R2=y
|
||||
CONFIG_MIPS_VPE_LOADER=y
|
||||
CONFIG_NR_CPUS=2
|
||||
--- a/arch/mips/lantiq/Kconfig
|
||||
+++ b/arch/mips/lantiq/Kconfig
|
||||
@@ -62,4 +62,8 @@ config PCIE_LANTIQ_MSI
|
||||
depends on PCIE_LANTIQ && PCI_MSI
|
||||
default y
|
||||
|
||||
+config XRX200_PHY_FW
|
||||
+ bool "XRX200 PHY firmware loader"
|
||||
+ depends on SOC_XWAY
|
||||
+
|
||||
endif
|
||||
--- a/drivers/soc/lantiq/Makefile
|
||||
+++ b/drivers/soc/lantiq/Makefile
|
||||
@@ -1,2 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
obj-y += fpi-bus.o
|
||||
+obj-$(CONFIG_XRX200_PHY_FW) += gphy.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/soc/lantiq/gphy.c
|
||||
@@ -0,0 +1,235 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ * Copyright (C) 2012 John Crispin <blogic@phrozen.org>
|
||||
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
|
||||
+ * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/dma-mapping.h>
|
||||
+#include <linux/firmware.h>
|
||||
+#include <linux/mfd/syscon.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/reboot.h>
|
||||
+#include <linux/regmap.h>
|
||||
+#include <linux/reset.h>
|
||||
+#include <linux/of_device.h>
|
||||
+#include <linux/of_platform.h>
|
||||
+#include <linux/property.h>
|
||||
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
|
||||
+
|
||||
+#include <lantiq_soc.h>
|
||||
+
|
||||
+#define XRX200_GPHY_FW_ALIGN (16 * 1024)
|
||||
+
|
||||
+struct xway_gphy_priv {
|
||||
+ struct clk *gphy_clk_gate;
|
||||
+ struct reset_control *gphy_reset;
|
||||
+ struct reset_control *gphy_reset2;
|
||||
+ void __iomem *membase;
|
||||
+ char *fw_name;
|
||||
+};
|
||||
+
|
||||
+struct xway_gphy_match_data {
|
||||
+ char *fe_firmware_name;
|
||||
+ char *ge_firmware_name;
|
||||
+};
|
||||
+
|
||||
+static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
|
||||
+ .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
|
||||
+ .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
|
||||
+};
|
||||
+
|
||||
+static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
|
||||
+ .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
|
||||
+ .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
|
||||
+};
|
||||
+
|
||||
+static const struct xway_gphy_match_data xrx300_gphy_data = {
|
||||
+ .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
|
||||
+ .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id xway_gphy_match[] = {
|
||||
+ { .compatible = "lantiq,xrx200-gphy", .data = NULL },
|
||||
+ { .compatible = "lantiq,xrx200a1x-gphy", .data = &xrx200a1x_gphy_data },
|
||||
+ { .compatible = "lantiq,xrx200a2x-gphy", .data = &xrx200a2x_gphy_data },
|
||||
+ { .compatible = "lantiq,xrx300-gphy", .data = &xrx300_gphy_data },
|
||||
+ { .compatible = "lantiq,xrx330-gphy", .data = &xrx300_gphy_data },
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, xway_gphy_match);
|
||||
+
|
||||
+static int xway_gphy_load(struct device *dev, struct xway_gphy_priv *priv,
|
||||
+ dma_addr_t *dev_addr)
|
||||
+{
|
||||
+ const struct firmware *fw;
|
||||
+ void *fw_addr;
|
||||
+ dma_addr_t dma_addr;
|
||||
+ size_t size;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = request_firmware(&fw, priv->fw_name, dev);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "failed to load firmware: %s, error: %i\n",
|
||||
+ priv->fw_name, ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * GPHY cores need the firmware code in a persistent and contiguous
|
||||
+ * memory area with a 16 kB boundary aligned start address.
|
||||
+ */
|
||||
+ size = fw->size + XRX200_GPHY_FW_ALIGN;
|
||||
+
|
||||
+ fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
|
||||
+ if (fw_addr) {
|
||||
+ fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
|
||||
+ *dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
|
||||
+ memcpy(fw_addr, fw->data, fw->size);
|
||||
+ } else {
|
||||
+ dev_err(dev, "failed to alloc firmware memory\n");
|
||||
+ ret = -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ release_firmware(fw);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int xway_gphy_of_probe(struct platform_device *pdev,
|
||||
+ struct xway_gphy_priv *priv)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ const struct xway_gphy_match_data *gphy_fw_name_cfg;
|
||||
+ u32 gphy_mode;
|
||||
+ int ret;
|
||||
+ struct resource *res_gphy;
|
||||
+
|
||||
+ gphy_fw_name_cfg = of_device_get_match_data(dev);
|
||||
+
|
||||
+ if (of_device_is_compatible(pdev->dev.of_node, "lantiq,xrx200-gphy"))
|
||||
+ switch (ltq_soc_type()) {
|
||||
+ case SOC_TYPE_VR9:
|
||||
+ gphy_fw_name_cfg = &xrx200a1x_gphy_data;
|
||||
+ break;
|
||||
+ case SOC_TYPE_VR9_2:
|
||||
+ gphy_fw_name_cfg = &xrx200a2x_gphy_data;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ priv->gphy_clk_gate = devm_clk_get(dev, NULL);
|
||||
+ if (IS_ERR(priv->gphy_clk_gate)) {
|
||||
+ dev_err(dev, "Failed to lookup gate clock\n");
|
||||
+ return PTR_ERR(priv->gphy_clk_gate);
|
||||
+ }
|
||||
+
|
||||
+ res_gphy = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ priv->membase = devm_ioremap_resource(dev, res_gphy);
|
||||
+ if (IS_ERR(priv->membase))
|
||||
+ return PTR_ERR(priv->membase);
|
||||
+
|
||||
+ priv->gphy_reset = devm_reset_control_get(dev, "gphy");
|
||||
+ if (IS_ERR(priv->gphy_reset)) {
|
||||
+ if (PTR_ERR(priv->gphy_reset) != -EPROBE_DEFER)
|
||||
+ dev_err(dev, "Failed to lookup gphy reset\n");
|
||||
+ return PTR_ERR(priv->gphy_reset);
|
||||
+ }
|
||||
+
|
||||
+ priv->gphy_reset2 = devm_reset_control_get_optional(dev, "gphy2");
|
||||
+ if (IS_ERR(priv->gphy_reset2))
|
||||
+ return PTR_ERR(priv->gphy_reset2);
|
||||
+
|
||||
+ ret = device_property_read_u32(dev, "lantiq,gphy-mode", &gphy_mode);
|
||||
+ /* Default to GE mode */
|
||||
+ if (ret)
|
||||
+ gphy_mode = GPHY_MODE_GE;
|
||||
+
|
||||
+ switch (gphy_mode) {
|
||||
+ case GPHY_MODE_FE:
|
||||
+ priv->fw_name = gphy_fw_name_cfg->fe_firmware_name;
|
||||
+ break;
|
||||
+ case GPHY_MODE_GE:
|
||||
+ priv->fw_name = gphy_fw_name_cfg->ge_firmware_name;
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int xway_gphy_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct xway_gphy_priv *priv;
|
||||
+ dma_addr_t fw_addr = 0;
|
||||
+ int ret;
|
||||
+
|
||||
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
+ if (!priv)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ ret = xway_gphy_of_probe(pdev, priv);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = clk_prepare_enable(priv->gphy_clk_gate);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = xway_gphy_load(dev, priv, &fw_addr);
|
||||
+ if (ret) {
|
||||
+ clk_disable_unprepare(priv->gphy_clk_gate);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ reset_control_assert(priv->gphy_reset);
|
||||
+ reset_control_assert(priv->gphy_reset2);
|
||||
+
|
||||
+ iowrite32be(fw_addr, priv->membase);
|
||||
+
|
||||
+ reset_control_deassert(priv->gphy_reset);
|
||||
+ reset_control_deassert(priv->gphy_reset2);
|
||||
+
|
||||
+ platform_set_drvdata(pdev, priv);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int xway_gphy_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct xway_gphy_priv *priv = platform_get_drvdata(pdev);
|
||||
+
|
||||
+ iowrite32be(0, priv->membase);
|
||||
+
|
||||
+ clk_disable_unprepare(priv->gphy_clk_gate);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver xway_gphy_driver = {
|
||||
+ .probe = xway_gphy_probe,
|
||||
+ .remove = xway_gphy_remove,
|
||||
+ .driver = {
|
||||
+ .name = "xway-rcu-gphy",
|
||||
+ .of_match_table = xway_gphy_match,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(xway_gphy_driver);
|
||||
+
|
||||
+MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
|
||||
+MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
|
||||
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
|
||||
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
|
||||
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
|
||||
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
|
||||
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
|
||||
+MODULE_DESCRIPTION("Lantiq XWAY GPHY Firmware Loader");
|
||||
+MODULE_LICENSE("GPL");
|
||||
@ -1,55 +0,0 @@
|
||||
From d0ee51bbb7ce9880749a3d4794ec1fbbcda0f381 Mon Sep 17 00:00:00 2001
|
||||
From: Mathias Kresin <dev@kresin.me>
|
||||
Date: Sun, 7 Jul 2019 21:45:51 +0200
|
||||
Subject: [PATCH] MIPS: lantiq revert DSA switch driver PMU/clock changes
|
||||
|
||||
Switch back to the former used names, to make the legacy switch driver
|
||||
happy.
|
||||
|
||||
Signed-off-by: Mathias Kresin <dev@kresin.me>
|
||||
---
|
||||
arch/mips/lantiq/xway/sysctrl.c | 14 +++++++-------
|
||||
1 file changed, 7 insertions(+), 7 deletions(-)
|
||||
|
||||
--- a/arch/mips/lantiq/xway/sysctrl.c
|
||||
+++ b/arch/mips/lantiq/xway/sysctrl.c
|
||||
@@ -503,7 +503,7 @@ void __init ltq_soc_init(void)
|
||||
clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI);
|
||||
clkdev_add_pmu("1f106a00.pcie", "pdi", 1, 1, PMU1_PCIE2_PDI);
|
||||
clkdev_add_pmu("1a800000.pcie", "ctl", 1, 1, PMU1_PCIE2_CTL);
|
||||
- clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP);
|
||||
+ clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP);
|
||||
clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
|
||||
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
|
||||
} else if (of_machine_is_compatible("lantiq,ar10")) {
|
||||
@@ -511,11 +511,11 @@ void __init ltq_soc_init(void)
|
||||
ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz());
|
||||
clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
|
||||
clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
|
||||
- clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH |
|
||||
+ clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH |
|
||||
PMU_PPE_DP | PMU_PPE_TC);
|
||||
clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
|
||||
- clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY);
|
||||
- clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY);
|
||||
+ clkdev_add_pmu("1f203020.gphy", NULL, 1, 0, PMU_GPHY);
|
||||
+ clkdev_add_pmu("1f203068.gphy", NULL, 1, 0, PMU_GPHY);
|
||||
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
|
||||
clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE);
|
||||
clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
|
||||
@@ -534,12 +534,12 @@ void __init ltq_soc_init(void)
|
||||
clkdev_add_pmu(NULL, "ahb", 1, 0, PMU_AHBM | PMU_AHBS);
|
||||
|
||||
clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
|
||||
- clkdev_add_pmu("1e10b308.eth", NULL, 0, 0,
|
||||
+ clkdev_add_pmu("1e108000.eth", NULL, 0, 0,
|
||||
PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
|
||||
PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
|
||||
PMU_PPE_QSB | PMU_PPE_TOP);
|
||||
- clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY);
|
||||
- clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY);
|
||||
+ clkdev_add_pmu("1f203020.gphy", NULL, 0, 0, PMU_GPHY);
|
||||
+ clkdev_add_pmu("1f203068.gphy", NULL, 0, 0, PMU_GPHY);
|
||||
clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
|
||||
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
|
||||
clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,352 +0,0 @@
|
||||
From c8eedcadc38a5e6008d3990fbe0a5285b30335fc Mon Sep 17 00:00:00 2001
|
||||
From: Mathias Kresin <dev@kresin.me>
|
||||
Date: Sun, 7 Jul 2019 21:48:56 +0200
|
||||
Subject: [PATCH] MIPS: lantiq: Add GPHY Firmware loader
|
||||
|
||||
Upstream, the GPHY Firmware loader has been merged into the DSA switch
|
||||
driver. But we don't use the driver yet, so bring it back.
|
||||
|
||||
Signed-off-by: Mathias Kresin <dev@kresin.me>
|
||||
---
|
||||
.../bindings/mips/lantiq/rcu-gphy.txt | 36 +++
|
||||
.../devicetree/bindings/mips/lantiq/rcu.txt | 18 ++
|
||||
arch/mips/configs/xway_defconfig | 1 +
|
||||
arch/mips/lantiq/Kconfig | 4 +
|
||||
drivers/soc/lantiq/Makefile | 1 +
|
||||
drivers/soc/lantiq/gphy.c | 224 ++++++++++++++++++
|
||||
6 files changed, 284 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
|
||||
create mode 100644 drivers/soc/lantiq/gphy.c
|
||||
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
|
||||
@@ -0,0 +1,37 @@
|
||||
+Lantiq XWAY SoC GPHY binding
|
||||
+============================
|
||||
+
|
||||
+This binding describes a software-defined ethernet PHY, provided by the RCU
|
||||
+module on newer Lantiq XWAY SoCs (xRX200 and newer).
|
||||
+
|
||||
+-------------------------------------------------------------------------------
|
||||
+Required properties:
|
||||
+- compatible : Should be one of
|
||||
+ "lantiq,xrx200-gphy"
|
||||
+ "lantiq,xrx200a1x-gphy"
|
||||
+ "lantiq,xrx200a2x-gphy"
|
||||
+ "lantiq,xrx300-gphy"
|
||||
+ "lantiq,xrx330-gphy"
|
||||
+- reg : Addrress of the GPHY FW load address register
|
||||
+- resets : Must reference the RCU GPHY reset bit
|
||||
+- reset-names : One entry, value must be "gphy" or optional "gphy2"
|
||||
+- clocks : A reference to the (PMU) GPHY clock gate
|
||||
+
|
||||
+Optional properties:
|
||||
+- lantiq,gphy-mode : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
|
||||
+ <dt-bindings/mips/lantiq_xway_gphy.h>
|
||||
+
|
||||
+
|
||||
+-------------------------------------------------------------------------------
|
||||
+Example for the GPHys on the xRX200 SoCs:
|
||||
+
|
||||
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
|
||||
+ gphy0: gphy@20 {
|
||||
+ compatible = "lantiq,xrx200a2x-gphy";
|
||||
+ reg = <0x20 0x4>;
|
||||
+
|
||||
+ resets = <&reset0 31 30>, <&reset1 7 7>;
|
||||
+ reset-names = "gphy", "gphy2";
|
||||
+ clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
|
||||
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
|
||||
+ };
|
||||
--- a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
|
||||
+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
|
||||
@@ -26,6 +26,24 @@ Example of the RCU bindings on a xRX200
|
||||
ranges = <0x0 0x203000 0x100>;
|
||||
big-endian;
|
||||
|
||||
+ gphy0: gphy@20 {
|
||||
+ compatible = "lantiq,xrx200a2x-gphy";
|
||||
+ reg = <0x20 0x4>;
|
||||
+
|
||||
+ resets = <&reset0 31 30>, <&reset1 7 7>;
|
||||
+ reset-names = "gphy", "gphy2";
|
||||
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
|
||||
+ };
|
||||
+
|
||||
+ gphy1: gphy@68 {
|
||||
+ compatible = "lantiq,xrx200a2x-gphy";
|
||||
+ reg = <0x68 0x4>;
|
||||
+
|
||||
+ resets = <&reset0 29 28>, <&reset1 6 6>;
|
||||
+ reset-names = "gphy", "gphy2";
|
||||
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
|
||||
+ };
|
||||
+
|
||||
reset0: reset-controller@10 {
|
||||
compatible = "lantiq,xrx200-reset";
|
||||
reg = <0x10 4>, <0x14 4>;
|
||||
--- a/arch/mips/configs/xway_defconfig
|
||||
+++ b/arch/mips/configs/xway_defconfig
|
||||
@@ -13,6 +13,7 @@ CONFIG_EMBEDDED=y
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
CONFIG_LANTIQ=y
|
||||
CONFIG_PCI_LANTIQ=y
|
||||
+CONFIG_XRX200_PHY_FW=y
|
||||
CONFIG_CPU_MIPS32_R2=y
|
||||
CONFIG_MIPS_VPE_LOADER=y
|
||||
CONFIG_NR_CPUS=2
|
||||
--- a/arch/mips/lantiq/Kconfig
|
||||
+++ b/arch/mips/lantiq/Kconfig
|
||||
@@ -62,4 +62,8 @@ config PCIE_LANTIQ_MSI
|
||||
depends on PCIE_LANTIQ && PCI_MSI
|
||||
default y
|
||||
|
||||
+config XRX200_PHY_FW
|
||||
+ bool "XRX200 PHY firmware loader"
|
||||
+ depends on SOC_XWAY
|
||||
+
|
||||
endif
|
||||
--- a/drivers/soc/lantiq/Makefile
|
||||
+++ b/drivers/soc/lantiq/Makefile
|
||||
@@ -1,2 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
obj-y += fpi-bus.o
|
||||
+obj-$(CONFIG_XRX200_PHY_FW) += gphy.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/soc/lantiq/gphy.c
|
||||
@@ -0,0 +1,235 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ * Copyright (C) 2012 John Crispin <blogic@phrozen.org>
|
||||
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
|
||||
+ * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/dma-mapping.h>
|
||||
+#include <linux/firmware.h>
|
||||
+#include <linux/mfd/syscon.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/reboot.h>
|
||||
+#include <linux/regmap.h>
|
||||
+#include <linux/reset.h>
|
||||
+#include <linux/of_device.h>
|
||||
+#include <linux/of_platform.h>
|
||||
+#include <linux/property.h>
|
||||
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
|
||||
+
|
||||
+#include <lantiq_soc.h>
|
||||
+
|
||||
+#define XRX200_GPHY_FW_ALIGN (16 * 1024)
|
||||
+
|
||||
+struct xway_gphy_priv {
|
||||
+ struct clk *gphy_clk_gate;
|
||||
+ struct reset_control *gphy_reset;
|
||||
+ struct reset_control *gphy_reset2;
|
||||
+ void __iomem *membase;
|
||||
+ char *fw_name;
|
||||
+};
|
||||
+
|
||||
+struct xway_gphy_match_data {
|
||||
+ char *fe_firmware_name;
|
||||
+ char *ge_firmware_name;
|
||||
+};
|
||||
+
|
||||
+static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
|
||||
+ .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
|
||||
+ .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
|
||||
+};
|
||||
+
|
||||
+static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
|
||||
+ .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
|
||||
+ .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
|
||||
+};
|
||||
+
|
||||
+static const struct xway_gphy_match_data xrx300_gphy_data = {
|
||||
+ .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
|
||||
+ .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id xway_gphy_match[] = {
|
||||
+ { .compatible = "lantiq,xrx200-gphy", .data = NULL },
|
||||
+ { .compatible = "lantiq,xrx200a1x-gphy", .data = &xrx200a1x_gphy_data },
|
||||
+ { .compatible = "lantiq,xrx200a2x-gphy", .data = &xrx200a2x_gphy_data },
|
||||
+ { .compatible = "lantiq,xrx300-gphy", .data = &xrx300_gphy_data },
|
||||
+ { .compatible = "lantiq,xrx330-gphy", .data = &xrx300_gphy_data },
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, xway_gphy_match);
|
||||
+
|
||||
+static int xway_gphy_load(struct device *dev, struct xway_gphy_priv *priv,
|
||||
+ dma_addr_t *dev_addr)
|
||||
+{
|
||||
+ const struct firmware *fw;
|
||||
+ void *fw_addr;
|
||||
+ dma_addr_t dma_addr;
|
||||
+ size_t size;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = request_firmware(&fw, priv->fw_name, dev);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "failed to load firmware: %s, error: %i\n",
|
||||
+ priv->fw_name, ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * GPHY cores need the firmware code in a persistent and contiguous
|
||||
+ * memory area with a 16 kB boundary aligned start address.
|
||||
+ */
|
||||
+ size = fw->size + XRX200_GPHY_FW_ALIGN;
|
||||
+
|
||||
+ fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
|
||||
+ if (fw_addr) {
|
||||
+ fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
|
||||
+ *dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
|
||||
+ memcpy(fw_addr, fw->data, fw->size);
|
||||
+ } else {
|
||||
+ dev_err(dev, "failed to alloc firmware memory\n");
|
||||
+ ret = -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ release_firmware(fw);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int xway_gphy_of_probe(struct platform_device *pdev,
|
||||
+ struct xway_gphy_priv *priv)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ const struct xway_gphy_match_data *gphy_fw_name_cfg;
|
||||
+ u32 gphy_mode;
|
||||
+ int ret;
|
||||
+ struct resource *res_gphy;
|
||||
+
|
||||
+ gphy_fw_name_cfg = of_device_get_match_data(dev);
|
||||
+
|
||||
+ if (of_device_is_compatible(pdev->dev.of_node, "lantiq,xrx200-gphy"))
|
||||
+ switch (ltq_soc_type()) {
|
||||
+ case SOC_TYPE_VR9:
|
||||
+ gphy_fw_name_cfg = &xrx200a1x_gphy_data;
|
||||
+ break;
|
||||
+ case SOC_TYPE_VR9_2:
|
||||
+ gphy_fw_name_cfg = &xrx200a2x_gphy_data;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ priv->gphy_clk_gate = devm_clk_get(dev, NULL);
|
||||
+ if (IS_ERR(priv->gphy_clk_gate)) {
|
||||
+ dev_err(dev, "Failed to lookup gate clock\n");
|
||||
+ return PTR_ERR(priv->gphy_clk_gate);
|
||||
+ }
|
||||
+
|
||||
+ res_gphy = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ priv->membase = devm_ioremap_resource(dev, res_gphy);
|
||||
+ if (IS_ERR(priv->membase))
|
||||
+ return PTR_ERR(priv->membase);
|
||||
+
|
||||
+ priv->gphy_reset = devm_reset_control_get(dev, "gphy");
|
||||
+ if (IS_ERR(priv->gphy_reset)) {
|
||||
+ if (PTR_ERR(priv->gphy_reset) != -EPROBE_DEFER)
|
||||
+ dev_err(dev, "Failed to lookup gphy reset\n");
|
||||
+ return PTR_ERR(priv->gphy_reset);
|
||||
+ }
|
||||
+
|
||||
+ priv->gphy_reset2 = devm_reset_control_get_optional(dev, "gphy2");
|
||||
+ if (IS_ERR(priv->gphy_reset2))
|
||||
+ return PTR_ERR(priv->gphy_reset2);
|
||||
+
|
||||
+ ret = device_property_read_u32(dev, "lantiq,gphy-mode", &gphy_mode);
|
||||
+ /* Default to GE mode */
|
||||
+ if (ret)
|
||||
+ gphy_mode = GPHY_MODE_GE;
|
||||
+
|
||||
+ switch (gphy_mode) {
|
||||
+ case GPHY_MODE_FE:
|
||||
+ priv->fw_name = gphy_fw_name_cfg->fe_firmware_name;
|
||||
+ break;
|
||||
+ case GPHY_MODE_GE:
|
||||
+ priv->fw_name = gphy_fw_name_cfg->ge_firmware_name;
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int xway_gphy_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct xway_gphy_priv *priv;
|
||||
+ dma_addr_t fw_addr = 0;
|
||||
+ int ret;
|
||||
+
|
||||
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
+ if (!priv)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ ret = xway_gphy_of_probe(pdev, priv);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = clk_prepare_enable(priv->gphy_clk_gate);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = xway_gphy_load(dev, priv, &fw_addr);
|
||||
+ if (ret) {
|
||||
+ clk_disable_unprepare(priv->gphy_clk_gate);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ reset_control_assert(priv->gphy_reset);
|
||||
+ reset_control_assert(priv->gphy_reset2);
|
||||
+
|
||||
+ iowrite32be(fw_addr, priv->membase);
|
||||
+
|
||||
+ reset_control_deassert(priv->gphy_reset);
|
||||
+ reset_control_deassert(priv->gphy_reset2);
|
||||
+
|
||||
+ platform_set_drvdata(pdev, priv);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int xway_gphy_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct xway_gphy_priv *priv = platform_get_drvdata(pdev);
|
||||
+
|
||||
+ iowrite32be(0, priv->membase);
|
||||
+
|
||||
+ clk_disable_unprepare(priv->gphy_clk_gate);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver xway_gphy_driver = {
|
||||
+ .probe = xway_gphy_probe,
|
||||
+ .remove = xway_gphy_remove,
|
||||
+ .driver = {
|
||||
+ .name = "xway-rcu-gphy",
|
||||
+ .of_match_table = xway_gphy_match,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(xway_gphy_driver);
|
||||
+
|
||||
+MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
|
||||
+MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
|
||||
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
|
||||
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
|
||||
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
|
||||
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
|
||||
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
|
||||
+MODULE_DESCRIPTION("Lantiq XWAY GPHY Firmware Loader");
|
||||
+MODULE_LICENSE("GPL");
|
||||
@ -11,65 +11,41 @@ lantiq_setup_interfaces()
|
||||
local board="$1"
|
||||
|
||||
case "$board" in
|
||||
alphanetworks,asl56026)
|
||||
ucidef_add_switch "switch0" \
|
||||
"2:lan" "3:lan" "6t@eth0"
|
||||
alphanetworks,asl56026|\
|
||||
arcadyan,vg3503j)
|
||||
ucidef_set_interface_lan "lan1 lan2"
|
||||
;;
|
||||
arcadyan,arv7519rw22)
|
||||
ucidef_add_switch "switch0" \
|
||||
"0:lan:5" "2:lan:3" "3:lan:4" "4:lan:1" "5:lan:2" "6t@eth0"
|
||||
;;
|
||||
arcadyan,vg3503j)
|
||||
ucidef_add_switch "switch0" \
|
||||
"2:lan:2" "4:lan:1" "6t@eth0"
|
||||
ucidef_set_interface_lan "lan1 lan2 lan3 lan4 lan5"
|
||||
;;
|
||||
arcadyan,vgv7510kw22-brn|\
|
||||
arcadyan,vgv7510kw22-nor)
|
||||
ucidef_add_switch "switch0" \
|
||||
"2:lan:2" "3:lan:1" "4:lan:4" "5:lan:3" "0:wan:5" "6t@eth0"
|
||||
;;
|
||||
arcadyan,vgv7510kw22-nor|\
|
||||
arcadyan,vgv7519-brn|\
|
||||
arcadyan,vgv7519-nor|\
|
||||
bt,homehub-v5a|\
|
||||
lantiq,easy80920-nand|\
|
||||
lantiq,easy80920-nor)
|
||||
ucidef_add_switch "switch0" \
|
||||
"0:lan:4" "1:lan:3" "2:lan:2" "4:lan:1" "5:wan:5" "6t@eth0"
|
||||
lantiq,easy80920-nor|\
|
||||
zyxel,p-2812hnu-f1|\
|
||||
zyxel,p-2812hnu-f3)
|
||||
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
|
||||
;;
|
||||
avm,fritz3370-rev2-hynix|\
|
||||
avm,fritz3370-rev2-micron|\
|
||||
avm,fritz3390|\
|
||||
avm,fritz7360sl|\
|
||||
avm,fritz7360-v2|\
|
||||
avm,fritz7362sl)
|
||||
ucidef_add_switch "switch0" \
|
||||
"0:lan:3" "1:lan:4" "2:lan:2" "4:lan:1" "6t@eth0"
|
||||
;;
|
||||
avm,fritz7430)
|
||||
ucidef_add_switch "switch0" \
|
||||
"2:lan:3" "3:lan:4" "4:lan:1" "5:lan:2" "6t@eth0"
|
||||
;;
|
||||
bt,homehub-v5a)
|
||||
ucidef_add_switch "switch0" \
|
||||
"0:lan:3" "1:lan:4" "2:lan:2" "4:lan:1" "5:wan:5" "6t@eth0"
|
||||
;;
|
||||
buffalo,wbmr-300hpd)
|
||||
ucidef_add_switch "switch0" \
|
||||
"5:lan:2" "2:lan:3" "3:lan:4" "4:wan:1" "6t@eth0"
|
||||
;;
|
||||
avm,fritz7362sl|\
|
||||
avm,fritz7430|\
|
||||
buffalo,wbmr-300hpd|\
|
||||
tplink,tdw8970|\
|
||||
tplink,tdw8980)
|
||||
ucidef_add_switch "switch0" \
|
||||
"0:lan:2" "2:lan:3" "4:lan:4" "5:lan:1" "6t@eth0"
|
||||
;;
|
||||
tplink,tdw8980|\
|
||||
tplink,vr200|\
|
||||
tplink,vr200v)
|
||||
ucidef_add_switch "switch0" \
|
||||
"0:lan" "2:lan" "4:lan" "5:lan" "6t@eth0"
|
||||
ucidef_set_interface_lan "lan1 lan2 lan3 lan4"
|
||||
;;
|
||||
zyxel,p-2812hnu-f1|\
|
||||
zyxel,p-2812hnu-f3)
|
||||
ucidef_add_switch "switch0" \
|
||||
"0:lan" "1:lan" "2:lan" "4:lan" "5:wan" "6t@eth0"
|
||||
avm,fritz7412|\
|
||||
netgear,dm200)
|
||||
ucidef_set_interface_lan "lan"
|
||||
;;
|
||||
*)
|
||||
ucidef_set_interface_lan 'eth0'
|
||||
|
||||
@ -0,0 +1,18 @@
|
||||
#
|
||||
# Copyright (C) 2020 OpenWrt.org
|
||||
#
|
||||
|
||||
. /lib/functions.sh
|
||||
. /lib/functions/uci-defaults.sh
|
||||
|
||||
board_config_update
|
||||
|
||||
case "$(board_name)" in
|
||||
*)
|
||||
ucidef_set_compat_version "1.1"
|
||||
;;
|
||||
esac
|
||||
|
||||
board_config_flush
|
||||
|
||||
exit 0
|
||||
@ -18,6 +18,7 @@ CONFIG_CRYPTO_ZSTD=y
|
||||
CONFIG_EXTRA_FIRMWARE="lantiq/xrx200_phy11g_a14.bin lantiq/xrx200_phy11g_a22.bin lantiq/xrx200_phy22f_a14.bin lantiq/xrx200_phy22f_a22.bin"
|
||||
CONFIG_EXTRA_FIRMWARE_DIR="firmware"
|
||||
CONFIG_GENERIC_ALLOCATOR=y
|
||||
CONFIG_GRO_CELLS=y
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_ICPLUS_PHY=y
|
||||
@ -27,7 +28,7 @@ CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_POLLDEV=y
|
||||
CONFIG_INTEL_XWAY_PHY=y
|
||||
# CONFIG_ISDN is not set
|
||||
CONFIG_LANTIQ_XRX200_LEGACY=y
|
||||
CONFIG_LANTIQ_XRX200=y
|
||||
CONFIG_LZO_COMPRESS=y
|
||||
CONFIG_LZO_DECOMPRESS=y
|
||||
CONFIG_MIPS_MT=y
|
||||
@ -50,7 +51,12 @@ CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_BEB_LIMIT=20
|
||||
CONFIG_MTD_UBI_BLOCK=y
|
||||
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
||||
CONFIG_NET_DEVLINK=y
|
||||
CONFIG_NET_DSA=y
|
||||
CONFIG_NET_DSA_LANTIQ_GSWIP=y
|
||||
CONFIG_NET_DSA_TAG_GSWIP=y
|
||||
CONFIG_NET_FLOW_LIMIT=y
|
||||
CONFIG_NET_SWITCHDEV=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NR_CPUS=2
|
||||
CONFIG_PADATA=y
|
||||
@ -77,7 +83,6 @@ CONFIG_SMP=y
|
||||
CONFIG_SMP_UP=y
|
||||
CONFIG_SOC_TYPE_XWAY=y
|
||||
CONFIG_SOC_XWAY=y
|
||||
CONFIG_SWCONFIG_LEDS=y
|
||||
CONFIG_SYNC_R4K=y
|
||||
CONFIG_SYS_SUPPORTS_SCHED_SMT=y
|
||||
CONFIG_SYS_SUPPORTS_SMP=y
|
||||
@ -88,7 +93,6 @@ CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XRX200_PHY_FW=y
|
||||
CONFIG_XXHASH=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
|
||||
@ -17,6 +17,7 @@ CONFIG_CRYPTO_ZSTD=y
|
||||
CONFIG_EXTRA_FIRMWARE="lantiq/xrx200_phy11g_a14.bin lantiq/xrx200_phy11g_a22.bin lantiq/xrx200_phy22f_a14.bin lantiq/xrx200_phy22f_a22.bin"
|
||||
CONFIG_EXTRA_FIRMWARE_DIR="firmware"
|
||||
CONFIG_GENERIC_ALLOCATOR=y
|
||||
CONFIG_GRO_CELLS=y
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_ICPLUS_PHY=y
|
||||
CONFIG_IFX_VPE_EXT=y
|
||||
@ -25,7 +26,7 @@ CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_POLLDEV=y
|
||||
CONFIG_INTEL_XWAY_PHY=y
|
||||
# CONFIG_ISDN is not set
|
||||
CONFIG_LANTIQ_XRX200_LEGACY=y
|
||||
CONFIG_LANTIQ_XRX200=y
|
||||
CONFIG_LZO_COMPRESS=y
|
||||
CONFIG_LZO_DECOMPRESS=y
|
||||
CONFIG_MIPS_MT=y
|
||||
@ -47,7 +48,12 @@ CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_BEB_LIMIT=20
|
||||
CONFIG_MTD_UBI_BLOCK=y
|
||||
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
||||
CONFIG_NET_DEVLINK=y
|
||||
CONFIG_NET_DSA=y
|
||||
CONFIG_NET_DSA_LANTIQ_GSWIP=y
|
||||
CONFIG_NET_DSA_TAG_GSWIP=y
|
||||
CONFIG_NET_FLOW_LIMIT=y
|
||||
CONFIG_NET_SWITCHDEV=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NR_CPUS=2
|
||||
CONFIG_PADATA=y
|
||||
@ -56,6 +62,7 @@ CONFIG_PCIEPORTBUS=y
|
||||
CONFIG_PCIE_LANTIQ=y
|
||||
CONFIG_PCI_DOMAINS=y
|
||||
CONFIG_PCI_LANTIQ=y
|
||||
CONFIG_PHYLINK=y
|
||||
CONFIG_PHY_LANTIQ_VRX200_PCIE=y
|
||||
CONFIG_POWER_RESET_GPIO=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
@ -72,7 +79,6 @@ CONFIG_SENSORS_LTQ_CPUTEMP=y
|
||||
CONFIG_SGL_ALLOC=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SMP_UP=y
|
||||
CONFIG_SWCONFIG_LEDS=y
|
||||
CONFIG_SYNC_R4K=y
|
||||
CONFIG_SYS_SUPPORTS_SCHED_SMT=y
|
||||
CONFIG_SYS_SUPPORTS_SMP=y
|
||||
@ -83,7 +89,6 @@ CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XRX200_PHY_FW=y
|
||||
CONFIG_XXHASH=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
|
||||
@ -15,8 +15,7 @@ DEFAULT_PACKAGES+=kmod-leds-gpio \
|
||||
ltq-vdsl-app \
|
||||
dsl-vrx200-firmware-xdsl-a \
|
||||
dsl-vrx200-firmware-xdsl-b-patch \
|
||||
ppp-mod-pppoa \
|
||||
swconfig
|
||||
ppp-mod-pppoa
|
||||
|
||||
define Target/Description
|
||||
Lantiq XRX200
|
||||
|
||||
@ -0,0 +1,5 @@
|
||||
set_preinit_iface() {
|
||||
ifname=eth0
|
||||
}
|
||||
|
||||
boot_hook_add preinit_main set_preinit_iface
|
||||
@ -41,6 +41,7 @@ CONFIG_RTL8367_PHY=y
|
||||
CONFIG_SGL_ALLOC=y
|
||||
CONFIG_SOC_TYPE_XWAY=y
|
||||
CONFIG_SOC_XWAY=y
|
||||
CONFIG_SWCONFIG=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
|
||||
@ -37,6 +37,7 @@ CONFIG_RTL8366_SMI=y
|
||||
CONFIG_RTL8367B_PHY=y
|
||||
CONFIG_RTL8367_PHY=y
|
||||
CONFIG_SGL_ALLOC=y
|
||||
CONFIG_SWCONFIG=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
|
||||
@ -0,0 +1,5 @@
|
||||
set_preinit_iface() {
|
||||
ifname=eth0
|
||||
}
|
||||
|
||||
boot_hook_add preinit_main set_preinit_iface
|
||||
@ -32,6 +32,7 @@ CONFIG_RTL8367_PHY=y
|
||||
CONFIG_SGL_ALLOC=y
|
||||
CONFIG_SOC_TYPE_XWAY=y
|
||||
CONFIG_SOC_XWAY=y
|
||||
CONFIG_SWCONFIG=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
|
||||
@ -30,6 +30,7 @@ CONFIG_RTL8366_SMI=y
|
||||
CONFIG_RTL8367B_PHY=y
|
||||
CONFIG_RTL8367_PHY=y
|
||||
CONFIG_SGL_ALLOC=y
|
||||
CONFIG_SWCONFIG=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user