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qualcommax: backport sdhci patches for ipq60xx
Refresh device tree, remove the useless sdhc2 aliases. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://github.com/openwrt/openwrt/pull/14950 Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Chukun Pan
Robert Marko
parent
eb9e0f2cff
commit
af6cf5d8c0
@ -270,12 +270,12 @@
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};
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};
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&sdhc_1 {
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&sdhc {
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pinctrl-0 = <&sd_pins>;
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pinctrl-names = "default";
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status = "okay";
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vqmmc-supply = <&ipq6018_l2>;
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bus-width = <4>;
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cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
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};
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@ -16,7 +16,6 @@
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aliases {
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serial0 = &blsp1_uart3;
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sdhc2 = &sdhc_1;
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ethernet0 = &dp5;
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ethernet1 = &dp4;
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label-mac-device = &dp5;
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@ -172,7 +171,7 @@
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};
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};
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&sdhc_1 {
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&sdhc {
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pinctrl-0 = <&sd_pins>;
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pinctrl-names = "default";
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status = "okay";
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@ -0,0 +1,26 @@
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From f2743ae3ff84579981ac513f512b9df945d109c0 Mon Sep 17 00:00:00 2001
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From: Chukun Pan <amadeus@jmu.edu.cn>
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Date: Thu, 20 Jun 2024 23:01:21 +0800
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Subject: [PATCH] clk: qcom: gcc-ipq6018: update sdcc max clock frequency
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The mmc controller of the IPQ6018 does not support HS400 mode.
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So adjust the maximum clock frequency of sdcc to 200 MHz (HS200).
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Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
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Link: https://lore.kernel.org/r/20240620150122.1406631-2-amadeus@jmu.edu.cn
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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drivers/clk/qcom/gcc-ipq6018.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/clk/qcom/gcc-ipq6018.c
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+++ b/drivers/clk/qcom/gcc-ipq6018.c
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@@ -1617,7 +1617,7 @@ static const struct freq_tbl ftbl_sdcc_a
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F(96000000, P_GPLL2, 12, 0, 0),
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F(177777778, P_GPLL0, 4.5, 0, 0),
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F(192000000, P_GPLL2, 6, 0, 0),
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- F(384000000, P_GPLL2, 3, 0, 0),
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+ F(200000000, P_GPLL0, 4, 0, 0),
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{ }
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};
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@ -0,0 +1,47 @@
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From 5db216f6e1f85394e79dca74ceceb83b2f8566b5 Mon Sep 17 00:00:00 2001
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From: Chukun Pan <amadeus@jmu.edu.cn>
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Date: Thu, 20 Jun 2024 23:01:22 +0800
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Subject: [PATCH] arm64: dts: qcom: ipq6018: add sdhci node
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Add node to support mmc controller inside of IPQ6018.
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This controller supports both eMMC and SD cards.
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Tested with:
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eMMC (HS200)
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SD Card (SDR50/SDR104)
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Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
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Link: https://lore.kernel.org/r/20240620150122.1406631-3-amadeus@jmu.edu.cn
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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arch/arm64/boot/dts/qcom/ipq6018.dtsi | 19 +++++++++++++++++++
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1 file changed, 19 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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@@ -470,6 +470,25 @@
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};
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};
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+ sdhc: mmc@7804000 {
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+ compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";
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+ reg = <0x0 0x07804000 0x0 0x1000>,
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+ <0x0 0x07805000 0x0 0x1000>;
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+ reg-names = "hc", "cqhci";
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+
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+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "hc_irq", "pwr_irq";
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+
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+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
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+ <&gcc GCC_SDCC1_APPS_CLK>,
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+ <&xo>;
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+ clock-names = "iface", "core", "xo";
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+ resets = <&gcc GCC_SDCC1_BCR>;
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+ max-frequency = <192000000>;
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+ status = "disabled";
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+ };
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+
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blsp_dma: dma-controller@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x0 0x07884000 0x0 0x2b000>;
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@ -182,7 +182,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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@@ -974,10 +974,10 @@
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@@ -993,10 +993,10 @@
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cooling-maps {
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map0 {
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trip = <&cpu_alert>;
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@ -1,45 +0,0 @@
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From e4d7544ce092807e8c5aeb618cec30e2eb9b40c2 Mon Sep 17 00:00:00 2001
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From: Mantas Pucka <mantas@8devices.com>
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Date: Mon, 24 Apr 2023 15:13:32 +0300
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Subject: [PATCH 3/3] arm64: dts: qcom: ipq6018: add SDHCI node
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IPQ6018 has one SD/eMMC controller, add node for it.
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Signed-off-by: Mantas Pucka <mantas@8devices.com>
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Tested-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq6018.dtsi | 23 +++++++++++++++++++++++
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1 file changed, 23 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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@@ -475,6 +475,29 @@
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};
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};
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+ sdhc_1: mmc@7804000 {
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+ compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";
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+ reg = <0x0 0x07804000 0x0 0x1000>,
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+ <0x0 0x07805000 0x0 0x1000>,
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+ <0x0 0x07808000 0x0 0x2000>;
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+ reg-names = "hc", "cqhci", "ice";
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+
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+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "hc_irq", "pwr_irq";
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+
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+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
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+ <&gcc GCC_SDCC1_APPS_CLK>,
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+ <&xo>,
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+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
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+ clock-names = "iface", "core", "xo", "ice";
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+
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+ resets = <&gcc GCC_SDCC1_BCR>;
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+ supports-cqe;
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+ bus-width = <8>;
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+ status = "disabled";
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+ };
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+
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blsp_dma: dma-controller@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x0 0x07884000 0x0 0x2b000>;
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@ -15,7 +15,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
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--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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@@ -827,6 +827,102 @@
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@@ -823,6 +823,102 @@
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};
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};
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@ -15,7 +15,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
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--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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@@ -1175,6 +1175,7 @@
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@@ -1171,6 +1171,7 @@
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wcss_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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@ -13,7 +13,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
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--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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@@ -948,8 +948,8 @@
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@@ -944,8 +944,8 @@
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"wcss_reset",
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"wcss_q6_reset";
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