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ipq95xx: Enable spi-qpic driver for QCOM SPI NAND flash Interface
This driver implements support for the SPI-NAND mode of QCOM NAND Flash Interface as a SPI-MEM controller with pipelined ECC capability. Signed-off-by: Ram Chandra Jangir <quic_rjangir@quicinc.com>
This commit is contained in:
parent
06dd9eb7fa
commit
abb4c91601
target/linux/qualcommax/patches-6.6
0401-spi-dt-bindings-Introduce-qcom-spi-qpic-snand.patch0402-mtd-rawnand-qcom-cleanup-qcom_nandc-driver.patch0403-mtd-rawnand-qcom-Add-qcom-prefix-to-common-api.patch0404-mtd-nand-Add-qpic_common-API-file.patch0405-mtd-rawnand-qcom-use-FIELD_PREP-and-GENMASK.patch0406-spi-spi-qpic-add-driver-for-QCOM-SPI-NAND-flash-Inte.patch0407-arm64-dts-qcom-ipq9574-Add-SPI-nand-support.patch0408-arm64-dts-qcom-ipq9574-Disable-eMMC-node.patch0409-Squashfs-Accept-mtd-names-for-mounting.patch0411-fix-build-errors.patch
@ -0,0 +1,166 @@
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From 852b56e4a92ea9deb703e87a01a03e5934ea0646 Mon Sep 17 00:00:00 2001
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From: Md Sadre Alam <quic_mdalam@quicinc.com>
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Date: Thu, 15 Feb 2024 12:08:23 +0530
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Subject: [PATCH v10 1/8] spi: dt-bindings: Introduce qcom,spi-qpic-snand
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Document the QPIC-SPI-NAND flash controller present in the IPQ SoCs.
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It can work both in serial and parallel mode and supports typical
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SPI-NAND page cache operations.
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
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---
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Change in [v10]
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* No change
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Change in [v9]
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* No change
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Change in [v8]
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* No change
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Change in [v7]
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* No change
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Change in [v6]
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* No change
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Change in [v5]
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* No change
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Change in [v4]
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* Fix spelling mistake in HW description
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* Added commit message
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* Removed '|' from description
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* Removed minItems in clock
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* Added blank line
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* Removed co-developed by
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Change in [v3]
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* Updated commit message, removed "dt-bindings" from commit
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message
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* Updated compatible name as file name
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* Added hardware description
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* Documented clock-name
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* Moved dma-names property to top
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* Droped unused label "qpic_nand"
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* Fixed indentation in example dt node
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Change in [v2]
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* Added initial support for dt-bindings
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Change in [v1]
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* This patch was not included in [v1]
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.../bindings/spi/qcom,spi-qpic-snand.yaml | 83 +++++++++++++++++++
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1 file changed, 83 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
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@@ -0,0 +1,83 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Qualcomm QPIC NAND controller
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+
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+maintainers:
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+ - Md sadre Alam <quic_mdalam@quicinc.com>
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+
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+description:
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+ The QCOM QPIC-SPI-NAND flash controller is an extended version of
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+ the QCOM QPIC NAND flash controller. It can work both in serial
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+ and parallel mode. It supports typical SPI-NAND page cache
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+ operations in single, dual or quad IO mode with pipelined ECC
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+ encoding/decoding using the QPIC ECC HW engine.
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+
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+allOf:
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+ - $ref: /schemas/spi/spi-controller.yaml#
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+
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+properties:
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+ compatible:
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+ enum:
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+ - qcom,spi-qpic-snand
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+
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+ reg:
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+ maxItems: 1
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+
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+ clocks:
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+ maxItems: 3
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+
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+ clock-names:
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+ items:
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+ - const: core
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+ - const: aon
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+ - const: iom
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+
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+ dmas:
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+ items:
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+ - description: tx DMA channel
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+ - description: rx DMA channel
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+ - description: cmd DMA channel
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+
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+ dma-names:
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+ items:
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+ - const: tx
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+ - const: rx
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+ - const: cmd
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - clock-names
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+
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+unevaluatedProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
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+ spi@79b0000 {
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+ compatible = "qcom,spi-qpic-snand";
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+ reg = <0x1ac00000 0x800>;
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+
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+ clocks = <&gcc GCC_QPIC_CLK>,
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+ <&gcc GCC_QPIC_AHB_CLK>,
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+ <&gcc GCC_QPIC_IO_MACRO_CLK>;
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+ clock-names = "core", "aon", "iom";
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ flash@0 {
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+ compatible = "spi-nand";
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+ reg = <0>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ nand-ecc-engine = <&qpic_nand>;
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+ nand-ecc-strength = <4>;
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+ nand-ecc-step-size = <512>;
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+ };
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+ };
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,919 @@
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From dde50ed4a7bdb79b4bb408781d3e4846d4c49f0a Mon Sep 17 00:00:00 2001
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From: Md Sadre Alam <quic_mdalam@quicinc.com>
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Date: Wed, 11 Sep 2024 11:13:42 +0530
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Subject: [PATCH v10 3/8] mtd: rawnand: qcom: Add qcom prefix to common api
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Add qcom prefix to all the api which will be commonly
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used by spi nand driver and raw nand driver.
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Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
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---
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Change in [v10]
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* No change
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Change in [v9]
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* No change
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Change in [v8]
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* No change
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Change in [v7]
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* No change
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Change in [v6]
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* No change
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Change in [v5]
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* Add qcom_ prefix to all common API.
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Change in [v4]
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* This patch was not included in [v4]
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Change in [v3]
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* This patch was not included in [v3]
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Change in [v2]
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* This patch was not included in [v2]
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Change in [v1]
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* This patch was not included in [v1]
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drivers/mtd/nand/raw/qcom_nandc.c | 320 +++++++++++++++---------------
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1 file changed, 160 insertions(+), 160 deletions(-)
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--- a/drivers/mtd/nand/raw/qcom_nandc.c
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+++ b/drivers/mtd/nand/raw/qcom_nandc.c
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@@ -53,7 +53,7 @@
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#define NAND_READ_LOCATION_LAST_CW_2 0xf48
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#define NAND_READ_LOCATION_LAST_CW_3 0xf4c
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-/* dummy register offsets, used by write_reg_dma */
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+/* dummy register offsets, used by qcom_write_reg_dma */
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#define NAND_DEV_CMD1_RESTORE 0xdead
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#define NAND_DEV_CMD_VLD_RESTORE 0xbeef
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@@ -211,7 +211,7 @@
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/*
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* Flags used in DMA descriptor preparation helper functions
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- * (i.e. read_reg_dma/write_reg_dma/read_data_dma/write_data_dma)
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+ * (i.e. qcom_read_reg_dma/qcom_write_reg_dma/qcom_read_data_dma/qcom_write_data_dma)
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*/
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/* Don't set the EOT in current tx BAM sgl */
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#define NAND_BAM_NO_EOT BIT(0)
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@@ -550,7 +550,7 @@ struct qcom_nandc_props {
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};
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/* Frees the BAM transaction memory */
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-static void free_bam_transaction(struct qcom_nand_controller *nandc)
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+static void qcom_free_bam_transaction(struct qcom_nand_controller *nandc)
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{
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struct bam_transaction *bam_txn = nandc->bam_txn;
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@@ -559,7 +559,7 @@ static void free_bam_transaction(struct
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/* Allocates and Initializes the BAM transaction */
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static struct bam_transaction *
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-alloc_bam_transaction(struct qcom_nand_controller *nandc)
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+qcom_alloc_bam_transaction(struct qcom_nand_controller *nandc)
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{
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struct bam_transaction *bam_txn;
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size_t bam_txn_size;
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@@ -595,7 +595,7 @@ alloc_bam_transaction(struct qcom_nand_c
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}
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/* Clears the BAM transaction indexes */
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-static void clear_bam_transaction(struct qcom_nand_controller *nandc)
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+static void qcom_clear_bam_transaction(struct qcom_nand_controller *nandc)
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{
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struct bam_transaction *bam_txn = nandc->bam_txn;
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@@ -614,7 +614,7 @@ static void clear_bam_transaction(struct
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}
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/* Callback for DMA descriptor completion */
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-static void qpic_bam_dma_done(void *data)
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+static void qcom_qpic_bam_dma_done(void *data)
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{
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struct bam_transaction *bam_txn = data;
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@@ -644,7 +644,7 @@ static inline void nandc_write(struct qc
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iowrite32(val, nandc->base + offset);
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}
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-static inline void nandc_dev_to_mem(struct qcom_nand_controller *nandc, bool is_cpu)
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+static inline void qcom_nandc_dev_to_mem(struct qcom_nand_controller *nandc, bool is_cpu)
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{
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if (!nandc->props->supports_bam)
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return;
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@@ -824,9 +824,9 @@ static void update_rw_regs(struct qcom_n
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* for BAM. This descriptor will be added in the NAND DMA descriptor queue
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* which will be submitted to DMA engine.
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*/
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-static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
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- struct dma_chan *chan,
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- unsigned long flags)
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+static int qcom_prepare_bam_async_desc(struct qcom_nand_controller *nandc,
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+ struct dma_chan *chan,
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+ unsigned long flags)
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{
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struct desc_info *desc;
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struct scatterlist *sgl;
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@@ -903,9 +903,9 @@ static int prepare_bam_async_desc(struct
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* NAND_BAM_NEXT_SGL will be used for starting the separate SGL
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* after the current command element.
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*/
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-static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
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- int reg_off, const void *vaddr,
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- int size, unsigned int flags)
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+static int qcom_prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
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+ int reg_off, const void *vaddr,
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+ int size, unsigned int flags)
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{
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int bam_ce_size;
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int i, ret;
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@@ -943,9 +943,9 @@ static int prep_bam_dma_desc_cmd(struct
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bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
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if (flags & NAND_BAM_NWD) {
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- ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
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- DMA_PREP_FENCE |
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- DMA_PREP_CMD);
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+ ret = qcom_prepare_bam_async_desc(nandc, nandc->cmd_chan,
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+ DMA_PREP_FENCE |
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+ DMA_PREP_CMD);
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if (ret)
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return ret;
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}
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@@ -958,9 +958,8 @@ static int prep_bam_dma_desc_cmd(struct
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* Prepares the data descriptor for BAM DMA which will be used for NAND
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* data reads and writes.
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*/
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-static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
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- const void *vaddr,
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- int size, unsigned int flags)
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+static int qcom_prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
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+ const void *vaddr, int size, unsigned int flags)
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{
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int ret;
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struct bam_transaction *bam_txn = nandc->bam_txn;
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@@ -979,8 +978,8 @@ static int prep_bam_dma_desc_data(struct
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* is not set, form the DMA descriptor
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*/
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if (!(flags & NAND_BAM_NO_EOT)) {
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- ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
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- DMA_PREP_INTERRUPT);
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+ ret = qcom_prepare_bam_async_desc(nandc, nandc->tx_chan,
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+ DMA_PREP_INTERRUPT);
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if (ret)
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return ret;
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}
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@@ -989,9 +988,9 @@ static int prep_bam_dma_desc_data(struct
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return 0;
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}
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-static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
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- int reg_off, const void *vaddr, int size,
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- bool flow_control)
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+static int qcom_prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
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+ int reg_off, const void *vaddr, int size,
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+ bool flow_control)
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{
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struct desc_info *desc;
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struct dma_async_tx_descriptor *dma_desc;
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@@ -1069,15 +1068,15 @@ err:
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}
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/*
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- * read_reg_dma: prepares a descriptor to read a given number of
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+ * qcom_read_reg_dma: prepares a descriptor to read a given number of
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* contiguous registers to the reg_read_buf pointer
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*
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* @first: offset of the first register in the contiguous block
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* @num_regs: number of registers to read
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* @flags: flags to control DMA descriptor preparation
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*/
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-static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
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- int num_regs, unsigned int flags)
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+static int qcom_read_reg_dma(struct qcom_nand_controller *nandc, int first,
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+ int num_regs, unsigned int flags)
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{
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bool flow_control = false;
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void *vaddr;
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@@ -1089,18 +1088,18 @@ static int read_reg_dma(struct qcom_nand
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first = dev_cmd_reg_addr(nandc, first);
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if (nandc->props->supports_bam)
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- return prep_bam_dma_desc_cmd(nandc, true, first, vaddr,
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+ return qcom_prep_bam_dma_desc_cmd(nandc, true, first, vaddr,
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num_regs, flags);
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if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
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flow_control = true;
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- return prep_adm_dma_desc(nandc, true, first, vaddr,
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+ return qcom_prep_adm_dma_desc(nandc, true, first, vaddr,
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num_regs * sizeof(u32), flow_control);
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}
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/*
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- * write_reg_dma: prepares a descriptor to write a given number of
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+ * qcom_write_reg_dma: prepares a descriptor to write a given number of
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* contiguous registers
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*
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* @vaddr: contnigeous memory from where register value will
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@@ -1109,8 +1108,8 @@ static int read_reg_dma(struct qcom_nand
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* @num_regs: number of registers to write
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* @flags: flags to control DMA descriptor preparation
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*/
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-static int write_reg_dma(struct qcom_nand_controller *nandc, __le32 *vaddr,
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- int first, int num_regs, unsigned int flags)
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+static int qcom_write_reg_dma(struct qcom_nand_controller *nandc, __le32 *vaddr,
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+ int first, int num_regs, unsigned int flags)
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{
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bool flow_control = false;
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@@ -1124,18 +1123,18 @@ static int write_reg_dma(struct qcom_nan
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first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD);
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if (nandc->props->supports_bam)
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- return prep_bam_dma_desc_cmd(nandc, false, first, vaddr,
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+ return qcom_prep_bam_dma_desc_cmd(nandc, false, first, vaddr,
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num_regs, flags);
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if (first == NAND_FLASH_CMD)
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flow_control = true;
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- return prep_adm_dma_desc(nandc, false, first, vaddr,
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+ return qcom_prep_adm_dma_desc(nandc, false, first, vaddr,
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num_regs * sizeof(u32), flow_control);
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}
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/*
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- * read_data_dma: prepares a DMA descriptor to transfer data from the
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+ * qcom_read_data_dma: prepares a DMA descriptor to transfer data from the
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* controller's internal buffer to the buffer 'vaddr'
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*
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* @reg_off: offset within the controller's data buffer
|
||||
@@ -1143,17 +1142,17 @@ static int write_reg_dma(struct qcom_nan
|
||||
* @size: DMA transaction size in bytes
|
||||
* @flags: flags to control DMA descriptor preparation
|
||||
*/
|
||||
-static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
|
||||
- const u8 *vaddr, int size, unsigned int flags)
|
||||
+static int qcom_read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
|
||||
+ const u8 *vaddr, int size, unsigned int flags)
|
||||
{
|
||||
if (nandc->props->supports_bam)
|
||||
- return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags);
|
||||
+ return qcom_prep_bam_dma_desc_data(nandc, true, vaddr, size, flags);
|
||||
|
||||
- return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
|
||||
+ return qcom_prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
|
||||
}
|
||||
|
||||
/*
|
||||
- * write_data_dma: prepares a DMA descriptor to transfer data from
|
||||
+ * qcom_write_data_dma: prepares a DMA descriptor to transfer data from
|
||||
* 'vaddr' to the controller's internal buffer
|
||||
*
|
||||
* @reg_off: offset within the controller's data buffer
|
||||
@@ -1161,13 +1160,13 @@ static int read_data_dma(struct qcom_nan
|
||||
* @size: DMA transaction size in bytes
|
||||
* @flags: flags to control DMA descriptor preparation
|
||||
*/
|
||||
-static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
|
||||
- const u8 *vaddr, int size, unsigned int flags)
|
||||
+static int qcom_write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
|
||||
+ const u8 *vaddr, int size, unsigned int flags)
|
||||
{
|
||||
if (nandc->props->supports_bam)
|
||||
- return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags);
|
||||
+ return qcom_prep_bam_dma_desc_data(nandc, false, vaddr, size, flags);
|
||||
|
||||
- return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
|
||||
+ return qcom_prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -1178,14 +1177,14 @@ static void config_nand_page_read(struct
|
||||
{
|
||||
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
|
||||
|
||||
- write_reg_dma(nandc, &nandc->regs->addr0, NAND_ADDR0, 2, 0);
|
||||
- write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->addr0, NAND_ADDR0, 2, 0);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
|
||||
if (!nandc->props->qpic_version2)
|
||||
- write_reg_dma(nandc, &nandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, 0);
|
||||
- write_reg_dma(nandc, &nandc->regs->erased_cw_detect_cfg_clr,
|
||||
- NAND_ERASED_CW_DETECT_CFG, 1, 0);
|
||||
- write_reg_dma(nandc, &nandc->regs->erased_cw_detect_cfg_set,
|
||||
- NAND_ERASED_CW_DETECT_CFG, 1, NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, 0);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->erased_cw_detect_cfg_clr,
|
||||
+ NAND_ERASED_CW_DETECT_CFG, 1, 0);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->erased_cw_detect_cfg_set,
|
||||
+ NAND_ERASED_CW_DETECT_CFG, 1, NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -1204,17 +1203,17 @@ config_nand_cw_read(struct nand_chip *ch
|
||||
reg = &nandc->regs->read_location_last0;
|
||||
|
||||
if (nandc->props->supports_bam)
|
||||
- write_reg_dma(nandc, reg, NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SGL);
|
||||
+ qcom_write_reg_dma(nandc, reg, NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SGL);
|
||||
|
||||
- write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
|
||||
- write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
|
||||
|
||||
if (use_ecc) {
|
||||
- read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
|
||||
- read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
|
||||
- NAND_BAM_NEXT_SGL);
|
||||
+ qcom_read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
|
||||
+ qcom_read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
|
||||
+ NAND_BAM_NEXT_SGL);
|
||||
} else {
|
||||
- read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
|
||||
+ qcom_read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1238,11 +1237,11 @@ static void config_nand_page_write(struc
|
||||
{
|
||||
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
|
||||
|
||||
- write_reg_dma(nandc, &nandc->regs->addr0, NAND_ADDR0, 2, 0);
|
||||
- write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->addr0, NAND_ADDR0, 2, 0);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
|
||||
if (!nandc->props->qpic_version2)
|
||||
- write_reg_dma(nandc, &nandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1,
|
||||
- NAND_BAM_NEXT_SGL);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1,
|
||||
+ NAND_BAM_NEXT_SGL);
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -1253,17 +1252,18 @@ static void config_nand_cw_write(struct
|
||||
{
|
||||
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
|
||||
|
||||
- write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
|
||||
- write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
|
||||
|
||||
- read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
|
||||
+ qcom_read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
|
||||
|
||||
- write_reg_dma(nandc, &nandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, 0);
|
||||
- write_reg_dma(nandc, &nandc->regs->clrreadstatus, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, 0);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->clrreadstatus, NAND_READ_STATUS, 1,
|
||||
+ NAND_BAM_NEXT_SGL);
|
||||
}
|
||||
|
||||
/* helpers to submit/free our list of dma descriptors */
|
||||
-static int submit_descs(struct qcom_nand_controller *nandc)
|
||||
+static int qcom_submit_descs(struct qcom_nand_controller *nandc)
|
||||
{
|
||||
struct desc_info *desc, *n;
|
||||
dma_cookie_t cookie = 0;
|
||||
@@ -1272,21 +1272,21 @@ static int submit_descs(struct qcom_nand
|
||||
|
||||
if (nandc->props->supports_bam) {
|
||||
if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) {
|
||||
- ret = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
|
||||
+ ret = qcom_prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
|
||||
if (ret)
|
||||
goto err_unmap_free_desc;
|
||||
}
|
||||
|
||||
if (bam_txn->tx_sgl_pos > bam_txn->tx_sgl_start) {
|
||||
- ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
|
||||
- DMA_PREP_INTERRUPT);
|
||||
+ ret = qcom_prepare_bam_async_desc(nandc, nandc->tx_chan,
|
||||
+ DMA_PREP_INTERRUPT);
|
||||
if (ret)
|
||||
goto err_unmap_free_desc;
|
||||
}
|
||||
|
||||
if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) {
|
||||
- ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
|
||||
- DMA_PREP_CMD);
|
||||
+ ret = qcom_prepare_bam_async_desc(nandc, nandc->cmd_chan,
|
||||
+ DMA_PREP_CMD);
|
||||
if (ret)
|
||||
goto err_unmap_free_desc;
|
||||
}
|
||||
@@ -1296,7 +1296,7 @@ static int submit_descs(struct qcom_nand
|
||||
cookie = dmaengine_submit(desc->dma_desc);
|
||||
|
||||
if (nandc->props->supports_bam) {
|
||||
- bam_txn->last_cmd_desc->callback = qpic_bam_dma_done;
|
||||
+ bam_txn->last_cmd_desc->callback = qcom_qpic_bam_dma_done;
|
||||
bam_txn->last_cmd_desc->callback_param = bam_txn;
|
||||
|
||||
dma_async_issue_pending(nandc->tx_chan);
|
||||
@@ -1314,7 +1314,7 @@ static int submit_descs(struct qcom_nand
|
||||
err_unmap_free_desc:
|
||||
/*
|
||||
* Unmap the dma sg_list and free the desc allocated by both
|
||||
- * prepare_bam_async_desc() and prep_adm_dma_desc() functions.
|
||||
+ * qcom_prepare_bam_async_desc() and qcom_prep_adm_dma_desc() functions.
|
||||
*/
|
||||
list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
|
||||
list_del(&desc->node);
|
||||
@@ -1333,10 +1333,10 @@ err_unmap_free_desc:
|
||||
}
|
||||
|
||||
/* reset the register read buffer for next NAND operation */
|
||||
-static void clear_read_regs(struct qcom_nand_controller *nandc)
|
||||
+static void qcom_clear_read_regs(struct qcom_nand_controller *nandc)
|
||||
{
|
||||
nandc->reg_read_pos = 0;
|
||||
- nandc_dev_to_mem(nandc, false);
|
||||
+ qcom_nandc_dev_to_mem(nandc, false);
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -1400,7 +1400,7 @@ static int check_flash_errors(struct qco
|
||||
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
|
||||
int i;
|
||||
|
||||
- nandc_dev_to_mem(nandc, true);
|
||||
+ qcom_nandc_dev_to_mem(nandc, true);
|
||||
|
||||
for (i = 0; i < cw_cnt; i++) {
|
||||
u32 flash = le32_to_cpu(nandc->reg_read_buf[i]);
|
||||
@@ -1427,13 +1427,13 @@ qcom_nandc_read_cw_raw(struct mtd_info *
|
||||
nand_read_page_op(chip, page, 0, NULL, 0);
|
||||
nandc->buf_count = 0;
|
||||
nandc->buf_start = 0;
|
||||
- clear_read_regs(nandc);
|
||||
+ qcom_clear_read_regs(nandc);
|
||||
host->use_ecc = false;
|
||||
|
||||
if (nandc->props->qpic_version2)
|
||||
raw_cw = ecc->steps - 1;
|
||||
|
||||
- clear_bam_transaction(nandc);
|
||||
+ qcom_clear_bam_transaction(nandc);
|
||||
set_address(host, host->cw_size * cw, page);
|
||||
update_rw_regs(host, 1, true, raw_cw);
|
||||
config_nand_page_read(chip);
|
||||
@@ -1466,18 +1466,18 @@ qcom_nandc_read_cw_raw(struct mtd_info *
|
||||
|
||||
config_nand_cw_read(chip, false, raw_cw);
|
||||
|
||||
- read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
|
||||
+ qcom_read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
|
||||
reg_off += data_size1;
|
||||
|
||||
- read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
|
||||
+ qcom_read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
|
||||
reg_off += oob_size1;
|
||||
|
||||
- read_data_dma(nandc, reg_off, data_buf + data_size1, data_size2, 0);
|
||||
+ qcom_read_data_dma(nandc, reg_off, data_buf + data_size1, data_size2, 0);
|
||||
reg_off += data_size2;
|
||||
|
||||
- read_data_dma(nandc, reg_off, oob_buf + oob_size1, oob_size2, 0);
|
||||
+ qcom_read_data_dma(nandc, reg_off, oob_buf + oob_size1, oob_size2, 0);
|
||||
|
||||
- ret = submit_descs(nandc);
|
||||
+ ret = qcom_submit_descs(nandc);
|
||||
if (ret) {
|
||||
dev_err(nandc->dev, "failure to read raw cw %d\n", cw);
|
||||
return ret;
|
||||
@@ -1575,7 +1575,7 @@ static int parse_read_errors(struct qcom
|
||||
u8 *data_buf_start = data_buf, *oob_buf_start = oob_buf;
|
||||
|
||||
buf = (struct read_stats *)nandc->reg_read_buf;
|
||||
- nandc_dev_to_mem(nandc, true);
|
||||
+ qcom_nandc_dev_to_mem(nandc, true);
|
||||
|
||||
for (i = 0; i < ecc->steps; i++, buf++) {
|
||||
u32 flash, buffer, erased_cw;
|
||||
@@ -1704,8 +1704,8 @@ static int read_page_ecc(struct qcom_nan
|
||||
config_nand_cw_read(chip, true, i);
|
||||
|
||||
if (data_buf)
|
||||
- read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
|
||||
- data_size, 0);
|
||||
+ qcom_read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
|
||||
+ data_size, 0);
|
||||
|
||||
/*
|
||||
* when ecc is enabled, the controller doesn't read the real
|
||||
@@ -1720,8 +1720,8 @@ static int read_page_ecc(struct qcom_nan
|
||||
for (j = 0; j < host->bbm_size; j++)
|
||||
*oob_buf++ = 0xff;
|
||||
|
||||
- read_data_dma(nandc, FLASH_BUF_ACC + data_size,
|
||||
- oob_buf, oob_size, 0);
|
||||
+ qcom_read_data_dma(nandc, FLASH_BUF_ACC + data_size,
|
||||
+ oob_buf, oob_size, 0);
|
||||
}
|
||||
|
||||
if (data_buf)
|
||||
@@ -1730,7 +1730,7 @@ static int read_page_ecc(struct qcom_nan
|
||||
oob_buf += oob_size;
|
||||
}
|
||||
|
||||
- ret = submit_descs(nandc);
|
||||
+ ret = qcom_submit_descs(nandc);
|
||||
if (ret) {
|
||||
dev_err(nandc->dev, "failure to read page/oob\n");
|
||||
return ret;
|
||||
@@ -1751,7 +1751,7 @@ static int copy_last_cw(struct qcom_nand
|
||||
int size;
|
||||
int ret;
|
||||
|
||||
- clear_read_regs(nandc);
|
||||
+ qcom_clear_read_regs(nandc);
|
||||
|
||||
size = host->use_ecc ? host->cw_data : host->cw_size;
|
||||
|
||||
@@ -1763,9 +1763,9 @@ static int copy_last_cw(struct qcom_nand
|
||||
|
||||
config_nand_single_cw_page_read(chip, host->use_ecc, ecc->steps - 1);
|
||||
|
||||
- read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
|
||||
+ qcom_read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
|
||||
|
||||
- ret = submit_descs(nandc);
|
||||
+ ret = qcom_submit_descs(nandc);
|
||||
if (ret)
|
||||
dev_err(nandc->dev, "failed to copy last codeword\n");
|
||||
|
||||
@@ -1851,14 +1851,14 @@ static int qcom_nandc_read_page(struct n
|
||||
nandc->buf_count = 0;
|
||||
nandc->buf_start = 0;
|
||||
host->use_ecc = true;
|
||||
- clear_read_regs(nandc);
|
||||
+ qcom_clear_read_regs(nandc);
|
||||
set_address(host, 0, page);
|
||||
update_rw_regs(host, ecc->steps, true, 0);
|
||||
|
||||
data_buf = buf;
|
||||
oob_buf = oob_required ? chip->oob_poi : NULL;
|
||||
|
||||
- clear_bam_transaction(nandc);
|
||||
+ qcom_clear_bam_transaction(nandc);
|
||||
|
||||
return read_page_ecc(host, data_buf, oob_buf, page);
|
||||
}
|
||||
@@ -1899,8 +1899,8 @@ static int qcom_nandc_read_oob(struct na
|
||||
if (host->nr_boot_partitions)
|
||||
qcom_nandc_codeword_fixup(host, page);
|
||||
|
||||
- clear_read_regs(nandc);
|
||||
- clear_bam_transaction(nandc);
|
||||
+ qcom_clear_read_regs(nandc);
|
||||
+ qcom_clear_bam_transaction(nandc);
|
||||
|
||||
host->use_ecc = true;
|
||||
set_address(host, 0, page);
|
||||
@@ -1927,8 +1927,8 @@ static int qcom_nandc_write_page(struct
|
||||
set_address(host, 0, page);
|
||||
nandc->buf_count = 0;
|
||||
nandc->buf_start = 0;
|
||||
- clear_read_regs(nandc);
|
||||
- clear_bam_transaction(nandc);
|
||||
+ qcom_clear_read_regs(nandc);
|
||||
+ qcom_clear_bam_transaction(nandc);
|
||||
|
||||
data_buf = (u8 *)buf;
|
||||
oob_buf = chip->oob_poi;
|
||||
@@ -1949,8 +1949,8 @@ static int qcom_nandc_write_page(struct
|
||||
oob_size = ecc->bytes;
|
||||
}
|
||||
|
||||
- write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size,
|
||||
- i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0);
|
||||
+ qcom_write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size,
|
||||
+ i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0);
|
||||
|
||||
/*
|
||||
* when ECC is enabled, we don't really need to write anything
|
||||
@@ -1962,8 +1962,8 @@ static int qcom_nandc_write_page(struct
|
||||
if (qcom_nandc_is_last_cw(ecc, i)) {
|
||||
oob_buf += host->bbm_size;
|
||||
|
||||
- write_data_dma(nandc, FLASH_BUF_ACC + data_size,
|
||||
- oob_buf, oob_size, 0);
|
||||
+ qcom_write_data_dma(nandc, FLASH_BUF_ACC + data_size,
|
||||
+ oob_buf, oob_size, 0);
|
||||
}
|
||||
|
||||
config_nand_cw_write(chip);
|
||||
@@ -1972,7 +1972,7 @@ static int qcom_nandc_write_page(struct
|
||||
oob_buf += oob_size;
|
||||
}
|
||||
|
||||
- ret = submit_descs(nandc);
|
||||
+ ret = qcom_submit_descs(nandc);
|
||||
if (ret) {
|
||||
dev_err(nandc->dev, "failure to write page\n");
|
||||
return ret;
|
||||
@@ -1997,8 +1997,8 @@ static int qcom_nandc_write_page_raw(str
|
||||
qcom_nandc_codeword_fixup(host, page);
|
||||
|
||||
nand_prog_page_begin_op(chip, page, 0, NULL, 0);
|
||||
- clear_read_regs(nandc);
|
||||
- clear_bam_transaction(nandc);
|
||||
+ qcom_clear_read_regs(nandc);
|
||||
+ qcom_clear_bam_transaction(nandc);
|
||||
|
||||
data_buf = (u8 *)buf;
|
||||
oob_buf = chip->oob_poi;
|
||||
@@ -2024,28 +2024,28 @@ static int qcom_nandc_write_page_raw(str
|
||||
oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
|
||||
}
|
||||
|
||||
- write_data_dma(nandc, reg_off, data_buf, data_size1,
|
||||
- NAND_BAM_NO_EOT);
|
||||
+ qcom_write_data_dma(nandc, reg_off, data_buf, data_size1,
|
||||
+ NAND_BAM_NO_EOT);
|
||||
reg_off += data_size1;
|
||||
data_buf += data_size1;
|
||||
|
||||
- write_data_dma(nandc, reg_off, oob_buf, oob_size1,
|
||||
- NAND_BAM_NO_EOT);
|
||||
+ qcom_write_data_dma(nandc, reg_off, oob_buf, oob_size1,
|
||||
+ NAND_BAM_NO_EOT);
|
||||
reg_off += oob_size1;
|
||||
oob_buf += oob_size1;
|
||||
|
||||
- write_data_dma(nandc, reg_off, data_buf, data_size2,
|
||||
- NAND_BAM_NO_EOT);
|
||||
+ qcom_write_data_dma(nandc, reg_off, data_buf, data_size2,
|
||||
+ NAND_BAM_NO_EOT);
|
||||
reg_off += data_size2;
|
||||
data_buf += data_size2;
|
||||
|
||||
- write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
|
||||
+ qcom_write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
|
||||
oob_buf += oob_size2;
|
||||
|
||||
config_nand_cw_write(chip);
|
||||
}
|
||||
|
||||
- ret = submit_descs(nandc);
|
||||
+ ret = qcom_submit_descs(nandc);
|
||||
if (ret) {
|
||||
dev_err(nandc->dev, "failure to write raw page\n");
|
||||
return ret;
|
||||
@@ -2075,7 +2075,7 @@ static int qcom_nandc_write_oob(struct n
|
||||
qcom_nandc_codeword_fixup(host, page);
|
||||
|
||||
host->use_ecc = true;
|
||||
- clear_bam_transaction(nandc);
|
||||
+ qcom_clear_bam_transaction(nandc);
|
||||
|
||||
/* calculate the data and oob size for the last codeword/step */
|
||||
data_size = ecc->size - ((ecc->steps - 1) << 2);
|
||||
@@ -2090,11 +2090,11 @@ static int qcom_nandc_write_oob(struct n
|
||||
update_rw_regs(host, 1, false, 0);
|
||||
|
||||
config_nand_page_write(chip);
|
||||
- write_data_dma(nandc, FLASH_BUF_ACC,
|
||||
- nandc->data_buffer, data_size + oob_size, 0);
|
||||
+ qcom_write_data_dma(nandc, FLASH_BUF_ACC,
|
||||
+ nandc->data_buffer, data_size + oob_size, 0);
|
||||
config_nand_cw_write(chip);
|
||||
|
||||
- ret = submit_descs(nandc);
|
||||
+ ret = qcom_submit_descs(nandc);
|
||||
if (ret) {
|
||||
dev_err(nandc->dev, "failure to write oob\n");
|
||||
return ret;
|
||||
@@ -2121,7 +2121,7 @@ static int qcom_nandc_block_bad(struct n
|
||||
*/
|
||||
host->use_ecc = false;
|
||||
|
||||
- clear_bam_transaction(nandc);
|
||||
+ qcom_clear_bam_transaction(nandc);
|
||||
ret = copy_last_cw(host, page);
|
||||
if (ret)
|
||||
goto err;
|
||||
@@ -2148,8 +2148,8 @@ static int qcom_nandc_block_markbad(stru
|
||||
struct nand_ecc_ctrl *ecc = &chip->ecc;
|
||||
int page, ret;
|
||||
|
||||
- clear_read_regs(nandc);
|
||||
- clear_bam_transaction(nandc);
|
||||
+ qcom_clear_read_regs(nandc);
|
||||
+ qcom_clear_bam_transaction(nandc);
|
||||
|
||||
/*
|
||||
* to mark the BBM as bad, we flash the entire last codeword with 0s.
|
||||
@@ -2166,11 +2166,11 @@ static int qcom_nandc_block_markbad(stru
|
||||
update_rw_regs(host, 1, false, ecc->steps - 1);
|
||||
|
||||
config_nand_page_write(chip);
|
||||
- write_data_dma(nandc, FLASH_BUF_ACC,
|
||||
- nandc->data_buffer, host->cw_size, 0);
|
||||
+ qcom_write_data_dma(nandc, FLASH_BUF_ACC,
|
||||
+ nandc->data_buffer, host->cw_size, 0);
|
||||
config_nand_cw_write(chip);
|
||||
|
||||
- ret = submit_descs(nandc);
|
||||
+ ret = qcom_submit_descs(nandc);
|
||||
if (ret) {
|
||||
dev_err(nandc->dev, "failure to update BBM\n");
|
||||
return ret;
|
||||
@@ -2410,14 +2410,14 @@ static int qcom_nand_attach_chip(struct
|
||||
mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops);
|
||||
/* Free the initially allocated BAM transaction for reading the ONFI params */
|
||||
if (nandc->props->supports_bam)
|
||||
- free_bam_transaction(nandc);
|
||||
+ qcom_free_bam_transaction(nandc);
|
||||
|
||||
nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage,
|
||||
cwperpage);
|
||||
|
||||
/* Now allocate the BAM transaction based on updated max_cwperpage */
|
||||
if (nandc->props->supports_bam) {
|
||||
- nandc->bam_txn = alloc_bam_transaction(nandc);
|
||||
+ nandc->bam_txn = qcom_alloc_bam_transaction(nandc);
|
||||
if (!nandc->bam_txn) {
|
||||
dev_err(nandc->dev,
|
||||
"failed to allocate bam transaction\n");
|
||||
@@ -2617,7 +2617,7 @@ static int qcom_wait_rdy_poll(struct nan
|
||||
unsigned long start = jiffies + msecs_to_jiffies(time_ms);
|
||||
u32 flash;
|
||||
|
||||
- nandc_dev_to_mem(nandc, true);
|
||||
+ qcom_nandc_dev_to_mem(nandc, true);
|
||||
|
||||
do {
|
||||
flash = le32_to_cpu(nandc->reg_read_buf[0]);
|
||||
@@ -2657,23 +2657,23 @@ static int qcom_read_status_exec(struct
|
||||
nandc->buf_start = 0;
|
||||
host->use_ecc = false;
|
||||
|
||||
- clear_read_regs(nandc);
|
||||
- clear_bam_transaction(nandc);
|
||||
+ qcom_clear_read_regs(nandc);
|
||||
+ qcom_clear_bam_transaction(nandc);
|
||||
|
||||
nandc->regs->cmd = q_op.cmd_reg;
|
||||
nandc->regs->exec = cpu_to_le32(1);
|
||||
|
||||
- write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
|
||||
- write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
|
||||
- read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
|
||||
+ qcom_read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
|
||||
|
||||
- ret = submit_descs(nandc);
|
||||
+ ret = qcom_submit_descs(nandc);
|
||||
if (ret) {
|
||||
dev_err(nandc->dev, "failure in submitting status descriptor\n");
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
- nandc_dev_to_mem(nandc, true);
|
||||
+ qcom_nandc_dev_to_mem(nandc, true);
|
||||
|
||||
for (i = 0; i < num_cw; i++) {
|
||||
flash_status = le32_to_cpu(nandc->reg_read_buf[i]);
|
||||
@@ -2714,8 +2714,8 @@ static int qcom_read_id_type_exec(struct
|
||||
nandc->buf_start = 0;
|
||||
host->use_ecc = false;
|
||||
|
||||
- clear_read_regs(nandc);
|
||||
- clear_bam_transaction(nandc);
|
||||
+ qcom_clear_read_regs(nandc);
|
||||
+ qcom_clear_bam_transaction(nandc);
|
||||
|
||||
nandc->regs->cmd = q_op.cmd_reg;
|
||||
nandc->regs->addr0 = q_op.addr1_reg;
|
||||
@@ -2723,12 +2723,12 @@ static int qcom_read_id_type_exec(struct
|
||||
nandc->regs->chip_sel = cpu_to_le32(nandc->props->supports_bam ? 0 : DM_EN);
|
||||
nandc->regs->exec = cpu_to_le32(1);
|
||||
|
||||
- write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
|
||||
- write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
|
||||
|
||||
- read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
|
||||
+ qcom_read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
|
||||
|
||||
- ret = submit_descs(nandc);
|
||||
+ ret = qcom_submit_descs(nandc);
|
||||
if (ret) {
|
||||
dev_err(nandc->dev, "failure in submitting read id descriptor\n");
|
||||
goto err_out;
|
||||
@@ -2738,7 +2738,7 @@ static int qcom_read_id_type_exec(struct
|
||||
op_id = q_op.data_instr_idx;
|
||||
len = nand_subop_get_data_len(subop, op_id);
|
||||
|
||||
- nandc_dev_to_mem(nandc, true);
|
||||
+ qcom_nandc_dev_to_mem(nandc, true);
|
||||
memcpy(instr->ctx.data.buf.in, nandc->reg_read_buf, len);
|
||||
|
||||
err_out:
|
||||
@@ -2774,20 +2774,20 @@ static int qcom_misc_cmd_type_exec(struc
|
||||
nandc->buf_start = 0;
|
||||
host->use_ecc = false;
|
||||
|
||||
- clear_read_regs(nandc);
|
||||
- clear_bam_transaction(nandc);
|
||||
+ qcom_clear_read_regs(nandc);
|
||||
+ qcom_clear_bam_transaction(nandc);
|
||||
|
||||
nandc->regs->cmd = q_op.cmd_reg;
|
||||
nandc->regs->exec = cpu_to_le32(1);
|
||||
|
||||
- write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, instrs, NAND_BAM_NEXT_SGL);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, instrs, NAND_BAM_NEXT_SGL);
|
||||
if (q_op.cmd_reg == cpu_to_le32(OP_BLOCK_ERASE))
|
||||
- write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
|
||||
|
||||
- write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
|
||||
- read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
|
||||
+ qcom_read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
|
||||
|
||||
- ret = submit_descs(nandc);
|
||||
+ ret = qcom_submit_descs(nandc);
|
||||
if (ret) {
|
||||
dev_err(nandc->dev, "failure in submitting misc descriptor\n");
|
||||
goto err_out;
|
||||
@@ -2820,8 +2820,8 @@ static int qcom_param_page_type_exec(str
|
||||
nandc->buf_count = 0;
|
||||
nandc->buf_start = 0;
|
||||
host->use_ecc = false;
|
||||
- clear_read_regs(nandc);
|
||||
- clear_bam_transaction(nandc);
|
||||
+ qcom_clear_read_regs(nandc);
|
||||
+ qcom_clear_bam_transaction(nandc);
|
||||
|
||||
nandc->regs->cmd = q_op.cmd_reg;
|
||||
nandc->regs->addr0 = 0;
|
||||
@@ -2864,8 +2864,8 @@ static int qcom_param_page_type_exec(str
|
||||
nandc_set_read_loc(chip, 0, 0, 0, len, 1);
|
||||
|
||||
if (!nandc->props->qpic_version2) {
|
||||
- write_reg_dma(nandc, &nandc->regs->vld, NAND_DEV_CMD_VLD, 1, 0);
|
||||
- write_reg_dma(nandc, &nandc->regs->cmd1, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->vld, NAND_DEV_CMD_VLD, 1, 0);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->cmd1, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL);
|
||||
}
|
||||
|
||||
nandc->buf_count = len;
|
||||
@@ -2873,17 +2873,17 @@ static int qcom_param_page_type_exec(str
|
||||
|
||||
config_nand_single_cw_page_read(chip, false, 0);
|
||||
|
||||
- read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
|
||||
- nandc->buf_count, 0);
|
||||
+ qcom_read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
|
||||
+ nandc->buf_count, 0);
|
||||
|
||||
/* restore CMD1 and VLD regs */
|
||||
if (!nandc->props->qpic_version2) {
|
||||
- write_reg_dma(nandc, &nandc->regs->orig_cmd1, NAND_DEV_CMD1_RESTORE, 1, 0);
|
||||
- write_reg_dma(nandc, &nandc->regs->orig_vld, NAND_DEV_CMD_VLD_RESTORE, 1,
|
||||
- NAND_BAM_NEXT_SGL);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->orig_cmd1, NAND_DEV_CMD1_RESTORE, 1, 0);
|
||||
+ qcom_write_reg_dma(nandc, &nandc->regs->orig_vld, NAND_DEV_CMD_VLD_RESTORE, 1,
|
||||
+ NAND_BAM_NEXT_SGL);
|
||||
}
|
||||
|
||||
- ret = submit_descs(nandc);
|
||||
+ ret = qcom_submit_descs(nandc);
|
||||
if (ret) {
|
||||
dev_err(nandc->dev, "failure in submitting param page descriptor\n");
|
||||
goto err_out;
|
||||
@@ -3067,7 +3067,7 @@ static int qcom_nandc_alloc(struct qcom_
|
||||
* maximum codeword size
|
||||
*/
|
||||
nandc->max_cwperpage = 1;
|
||||
- nandc->bam_txn = alloc_bam_transaction(nandc);
|
||||
+ nandc->bam_txn = qcom_alloc_bam_transaction(nandc);
|
||||
if (!nandc->bam_txn) {
|
||||
dev_err(nandc->dev,
|
||||
"failed to allocate bam transaction\n");
|
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,240 @@
|
||||
From 9c5b6453db27706f090ab06987394aabaaf24e1b Mon Sep 17 00:00:00 2001
|
||||
From: Md Sadre Alam <quic_mdalam@quicinc.com>
|
||||
Date: Wed, 11 Sep 2024 12:50:42 +0530
|
||||
Subject: [PATCH v10 5/8] mtd: rawnand: qcom: use FIELD_PREP and GENMASK
|
||||
|
||||
Use the bitfield macro FIELD_PREP, and GENMASK to
|
||||
do the shift and mask in one go. This makes the code
|
||||
more readable.
|
||||
|
||||
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
|
||||
---
|
||||
|
||||
Change in [v10]
|
||||
|
||||
* No change
|
||||
|
||||
Change in [v9]
|
||||
|
||||
* In update_rw_regs() api added cpu_to_le32() macro to fix compilation
|
||||
issue reported by kernel test bot
|
||||
* In qcom_param_page_type_exec() api added cpu_to_le32() macro to fix
|
||||
compilation issue reported by kernel test bot
|
||||
|
||||
Change in [v8]
|
||||
|
||||
* No change
|
||||
|
||||
Change in [v7]
|
||||
|
||||
* No change
|
||||
|
||||
Change in [v6]
|
||||
|
||||
* Added FIELD_PREP() and GENMASK() macro
|
||||
|
||||
Change in [v5]
|
||||
|
||||
* This patch was not included in [v1]
|
||||
|
||||
Change in [v4]
|
||||
|
||||
* This patch was not included in [v4]
|
||||
|
||||
Change in [v3]
|
||||
|
||||
* This patch was not included in [v3]
|
||||
|
||||
Change in [v2]
|
||||
|
||||
* This patch was not included in [v2]
|
||||
|
||||
Change in [v1]
|
||||
|
||||
* This patch was not included in [v1]
|
||||
|
||||
drivers/mtd/nand/raw/qcom_nandc.c | 97 ++++++++++++++--------------
|
||||
include/linux/mtd/nand-qpic-common.h | 31 +++++----
|
||||
2 files changed, 67 insertions(+), 61 deletions(-)
|
||||
|
||||
--- a/drivers/mtd/nand/raw/qcom_nandc.c
|
||||
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
|
||||
@@ -281,7 +281,7 @@ static void update_rw_regs(struct qcom_n
|
||||
(num_cw - 1) << CW_PER_PAGE);
|
||||
|
||||
cfg1 = cpu_to_le32(host->cfg1_raw);
|
||||
- ecc_bch_cfg = cpu_to_le32(1 << ECC_CFG_ECC_DISABLE);
|
||||
+ ecc_bch_cfg = cpu_to_le32(ECC_CFG_ECC_DISABLE);
|
||||
}
|
||||
|
||||
nandc->regs->cmd = cmd;
|
||||
@@ -1494,42 +1494,41 @@ static int qcom_nand_attach_chip(struct
|
||||
host->cw_size = host->cw_data + ecc->bytes;
|
||||
bad_block_byte = mtd->writesize - host->cw_size * (cwperpage - 1) + 1;
|
||||
|
||||
- host->cfg0 = (cwperpage - 1) << CW_PER_PAGE
|
||||
- | host->cw_data << UD_SIZE_BYTES
|
||||
- | 0 << DISABLE_STATUS_AFTER_WRITE
|
||||
- | 5 << NUM_ADDR_CYCLES
|
||||
- | host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_RS
|
||||
- | 0 << STATUS_BFR_READ
|
||||
- | 1 << SET_RD_MODE_AFTER_STATUS
|
||||
- | host->spare_bytes << SPARE_SIZE_BYTES;
|
||||
-
|
||||
- host->cfg1 = 7 << NAND_RECOVERY_CYCLES
|
||||
- | 0 << CS_ACTIVE_BSY
|
||||
- | bad_block_byte << BAD_BLOCK_BYTE_NUM
|
||||
- | 0 << BAD_BLOCK_IN_SPARE_AREA
|
||||
- | 2 << WR_RD_BSY_GAP
|
||||
- | wide_bus << WIDE_FLASH
|
||||
- | host->bch_enabled << ENABLE_BCH_ECC;
|
||||
-
|
||||
- host->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE
|
||||
- | host->cw_size << UD_SIZE_BYTES
|
||||
- | 5 << NUM_ADDR_CYCLES
|
||||
- | 0 << SPARE_SIZE_BYTES;
|
||||
-
|
||||
- host->cfg1_raw = 7 << NAND_RECOVERY_CYCLES
|
||||
- | 0 << CS_ACTIVE_BSY
|
||||
- | 17 << BAD_BLOCK_BYTE_NUM
|
||||
- | 1 << BAD_BLOCK_IN_SPARE_AREA
|
||||
- | 2 << WR_RD_BSY_GAP
|
||||
- | wide_bus << WIDE_FLASH
|
||||
- | 1 << DEV0_CFG1_ECC_DISABLE;
|
||||
-
|
||||
- host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE
|
||||
- | 0 << ECC_SW_RESET
|
||||
- | host->cw_data << ECC_NUM_DATA_BYTES
|
||||
- | 1 << ECC_FORCE_CLK_OPEN
|
||||
- | ecc_mode << ECC_MODE
|
||||
- | host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;
|
||||
+ host->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
|
||||
+ FIELD_PREP(UD_SIZE_BYTES_MASK, host->cw_data) |
|
||||
+ FIELD_PREP(DISABLE_STATUS_AFTER_WRITE, 0) |
|
||||
+ FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) |
|
||||
+ FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, host->ecc_bytes_hw) |
|
||||
+ FIELD_PREP(STATUS_BFR_READ, 0) |
|
||||
+ FIELD_PREP(SET_RD_MODE_AFTER_STATUS, 1) |
|
||||
+ FIELD_PREP(SPARE_SIZE_BYTES_MASK, host->spare_bytes);
|
||||
+
|
||||
+ host->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) |
|
||||
+ FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, bad_block_byte) |
|
||||
+ FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 0) |
|
||||
+ FIELD_PREP(WR_RD_BSY_GAP_MASK, 2) |
|
||||
+ FIELD_PREP(WIDE_FLASH, wide_bus) |
|
||||
+ FIELD_PREP(ENABLE_BCH_ECC, host->bch_enabled);
|
||||
+
|
||||
+ host->cfg0_raw = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
|
||||
+ FIELD_PREP(UD_SIZE_BYTES_MASK, host->cw_size) |
|
||||
+ FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) |
|
||||
+ FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
|
||||
+
|
||||
+ host->cfg1_raw = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) |
|
||||
+ FIELD_PREP(CS_ACTIVE_BSY, 0) |
|
||||
+ FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
|
||||
+ FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
|
||||
+ FIELD_PREP(WR_RD_BSY_GAP_MASK, 2) |
|
||||
+ FIELD_PREP(WIDE_FLASH, wide_bus) |
|
||||
+ FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
|
||||
+
|
||||
+ host->ecc_bch_cfg = FIELD_PREP(ECC_CFG_ECC_DISABLE, !host->bch_enabled) |
|
||||
+ FIELD_PREP(ECC_SW_RESET, 0) |
|
||||
+ FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, host->cw_data) |
|
||||
+ FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) |
|
||||
+ FIELD_PREP(ECC_MODE_MASK, ecc_mode) |
|
||||
+ FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, host->ecc_bytes_hw);
|
||||
|
||||
if (!nandc->props->qpic_version2)
|
||||
host->ecc_buf_cfg = 0x203 << NUM_STEPS;
|
||||
@@ -1882,21 +1881,21 @@ static int qcom_param_page_type_exec(str
|
||||
nandc->regs->addr0 = 0;
|
||||
nandc->regs->addr1 = 0;
|
||||
|
||||
- nandc->regs->cfg0 = cpu_to_le32(0 << CW_PER_PAGE
|
||||
- | 512 << UD_SIZE_BYTES
|
||||
- | 5 << NUM_ADDR_CYCLES
|
||||
- | 0 << SPARE_SIZE_BYTES);
|
||||
-
|
||||
- nandc->regs->cfg1 = cpu_to_le32(7 << NAND_RECOVERY_CYCLES
|
||||
- | 0 << CS_ACTIVE_BSY
|
||||
- | 17 << BAD_BLOCK_BYTE_NUM
|
||||
- | 1 << BAD_BLOCK_IN_SPARE_AREA
|
||||
- | 2 << WR_RD_BSY_GAP
|
||||
- | 0 << WIDE_FLASH
|
||||
- | 1 << DEV0_CFG1_ECC_DISABLE);
|
||||
+ host->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, 0) |
|
||||
+ FIELD_PREP(UD_SIZE_BYTES_MASK, 512) |
|
||||
+ FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) |
|
||||
+ FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
|
||||
+
|
||||
+ host->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) |
|
||||
+ FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
|
||||
+ FIELD_PREP(CS_ACTIVE_BSY, 0) |
|
||||
+ FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
|
||||
+ FIELD_PREP(WR_RD_BSY_GAP_MASK, 2) |
|
||||
+ FIELD_PREP(WIDE_FLASH, 0) |
|
||||
+ FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
|
||||
|
||||
if (!nandc->props->qpic_version2)
|
||||
- nandc->regs->ecc_buf_cfg = cpu_to_le32(1 << ECC_CFG_ECC_DISABLE);
|
||||
+ nandc->regs->ecc_buf_cfg = cpu_to_le32(ECC_CFG_ECC_DISABLE);
|
||||
|
||||
/* configure CMD1 and VLD for ONFI param probing in QPIC v1 */
|
||||
if (!nandc->props->qpic_version2) {
|
||||
--- a/include/linux/mtd/nand-qpic-common.h
|
||||
+++ b/include/linux/mtd/nand-qpic-common.h
|
||||
@@ -70,35 +70,42 @@
|
||||
#define BS_CORRECTABLE_ERR_MSK 0x1f
|
||||
|
||||
/* NAND_DEVn_CFG0 bits */
|
||||
-#define DISABLE_STATUS_AFTER_WRITE 4
|
||||
+#define DISABLE_STATUS_AFTER_WRITE BIT(4)
|
||||
#define CW_PER_PAGE 6
|
||||
+#define CW_PER_PAGE_MASK GENMASK(8, 6)
|
||||
#define UD_SIZE_BYTES 9
|
||||
#define UD_SIZE_BYTES_MASK GENMASK(18, 9)
|
||||
-#define ECC_PARITY_SIZE_BYTES_RS 19
|
||||
+#define ECC_PARITY_SIZE_BYTES_RS GENMASK(22, 19)
|
||||
#define SPARE_SIZE_BYTES 23
|
||||
#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23)
|
||||
#define NUM_ADDR_CYCLES 27
|
||||
-#define STATUS_BFR_READ 30
|
||||
-#define SET_RD_MODE_AFTER_STATUS 31
|
||||
+#define NUM_ADDR_CYCLES_MASK GENMASK(29, 27)
|
||||
+#define STATUS_BFR_READ BIT(30)
|
||||
+#define SET_RD_MODE_AFTER_STATUS BIT(31)
|
||||
|
||||
/* NAND_DEVn_CFG0 bits */
|
||||
-#define DEV0_CFG1_ECC_DISABLE 0
|
||||
-#define WIDE_FLASH 1
|
||||
+#define DEV0_CFG1_ECC_DISABLE BIT(0)
|
||||
+#define WIDE_FLASH BIT(1)
|
||||
#define NAND_RECOVERY_CYCLES 2
|
||||
-#define CS_ACTIVE_BSY 5
|
||||
+#define NAND_RECOVERY_CYCLES_MASK GENMASK(4, 2)
|
||||
+#define CS_ACTIVE_BSY BIT(5)
|
||||
#define BAD_BLOCK_BYTE_NUM 6
|
||||
-#define BAD_BLOCK_IN_SPARE_AREA 16
|
||||
+#define BAD_BLOCK_BYTE_NUM_MASK GENMASK(15, 6)
|
||||
+#define BAD_BLOCK_IN_SPARE_AREA BIT(16)
|
||||
#define WR_RD_BSY_GAP 17
|
||||
-#define ENABLE_BCH_ECC 27
|
||||
+#define WR_RD_BSY_GAP_MASK GENMASK(22, 17)
|
||||
+#define ENABLE_BCH_ECC BIT(27)
|
||||
|
||||
/* NAND_DEV0_ECC_CFG bits */
|
||||
-#define ECC_CFG_ECC_DISABLE 0
|
||||
-#define ECC_SW_RESET 1
|
||||
+#define ECC_CFG_ECC_DISABLE BIT(0)
|
||||
+#define ECC_SW_RESET BIT(1)
|
||||
#define ECC_MODE 4
|
||||
+#define ECC_MODE_MASK GENMASK(5, 4)
|
||||
#define ECC_PARITY_SIZE_BYTES_BCH 8
|
||||
+#define ECC_PARITY_SIZE_BYTES_BCH_MASK GENMASK(12, 8)
|
||||
#define ECC_NUM_DATA_BYTES 16
|
||||
#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16)
|
||||
-#define ECC_FORCE_CLK_OPEN 30
|
||||
+#define ECC_FORCE_CLK_OPEN BIT(30)
|
||||
|
||||
/* NAND_DEV_CMD1 bits */
|
||||
#define READ_ADDR 0
|
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,144 @@
|
||||
From 968c5e8220209eb2185654f01748c349515a3b8e Mon Sep 17 00:00:00 2001
|
||||
From: Md Sadre Alam <quic_mdalam@quicinc.com>
|
||||
Date: Thu, 15 Feb 2024 12:26:40 +0530
|
||||
Subject: [PATCH v10 7/8] arm64: dts: qcom: ipq9574: Add SPI nand support
|
||||
|
||||
Add SPI NAND support for ipq9574 SoC.
|
||||
|
||||
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
|
||||
---
|
||||
|
||||
Change in [v10]
|
||||
|
||||
* No change
|
||||
|
||||
Change in [v9]
|
||||
|
||||
* No change
|
||||
|
||||
Change in [v8]
|
||||
|
||||
* No change
|
||||
|
||||
Change in [v7]
|
||||
|
||||
* No change
|
||||
|
||||
Change in [v6]
|
||||
|
||||
* No change
|
||||
|
||||
Change in [v5]
|
||||
|
||||
* No change
|
||||
|
||||
Change in [v4]
|
||||
|
||||
* No change
|
||||
|
||||
Change in [v3]
|
||||
|
||||
* Updated gpio number as per pin control driver
|
||||
|
||||
* Fixed alignment issue
|
||||
|
||||
Change in [v2]
|
||||
|
||||
* Added initial enablement for spi-nand
|
||||
|
||||
Change in [v1]
|
||||
|
||||
* Posted as RFC patch for design review
|
||||
|
||||
.../boot/dts/qcom/ipq9574-rdp-common.dtsi | 43 +++++++++++++++++++
|
||||
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 27 ++++++++++++
|
||||
2 files changed, 70 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
|
||||
@@ -121,6 +121,49 @@
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ qpic_snand_default_state: qpic-snand-default-state {
|
||||
+ clock-pins {
|
||||
+ pins = "gpio5";
|
||||
+ function = "qspi_clk";
|
||||
+ drive-strength = <8>;
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ cs-pins {
|
||||
+ pins = "gpio4";
|
||||
+ function = "qspi_cs";
|
||||
+ drive-strength = <8>;
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ data-pins {
|
||||
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
|
||||
+ function = "qspi_data";
|
||||
+ drive-strength = <8>;
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&qpic_bam {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&qpic_nand {
|
||||
+ pinctrl-0 = <&qpic_snand_default_state>;
|
||||
+ pinctrl-names = "default";
|
||||
+ status = "okay";
|
||||
+
|
||||
+ flash@0 {
|
||||
+ compatible = "spi-nand";
|
||||
+ reg = <0>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ nand-ecc-engine = <&qpic_nand>;
|
||||
+ nand-ecc-strength = <4>;
|
||||
+ nand-ecc-step-size = <512>;
|
||||
+ };
|
||||
};
|
||||
|
||||
&usb_0_dwc3 {
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
|
||||
@@ -300,6 +300,33 @@
|
||||
reg = <0x01937000 0x21000>;
|
||||
};
|
||||
|
||||
+ qpic_bam: dma-controller@7984000 {
|
||||
+ compatible = "qcom,bam-v1.7.0";
|
||||
+ reg = <0x7984000 0x1c000>;
|
||||
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&gcc GCC_QPIC_AHB_CLK>;
|
||||
+ clock-names = "bam_clk";
|
||||
+ #dma-cells = <1>;
|
||||
+ qcom,ee = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ qpic_nand: spi@79b0000 {
|
||||
+ compatible = "qcom,spi-qpic-snand", "qcom,ipq9574-nand";
|
||||
+ reg = <0x79b0000 0x10000>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ clocks = <&gcc GCC_QPIC_CLK>,
|
||||
+ <&gcc GCC_QPIC_AHB_CLK>,
|
||||
+ <&gcc GCC_QPIC_IO_MACRO_CLK>;
|
||||
+ clock-names = "core", "aon", "iom";
|
||||
+ dmas = <&qpic_bam 0>,
|
||||
+ <&qpic_bam 1>,
|
||||
+ <&qpic_bam 2>;
|
||||
+ dma-names = "tx", "rx", "cmd";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
sdhc_1: mmc@7804000 {
|
||||
compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
|
||||
reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
|
@ -0,0 +1,65 @@
|
||||
From a28a71e2a4728ec4f1f4a6b28595b664a1a49e4b Mon Sep 17 00:00:00 2001
|
||||
From: Md Sadre Alam <quic_mdalam@quicinc.com>
|
||||
Date: Wed, 7 Feb 2024 16:05:27 +0530
|
||||
Subject: [PATCH v10 8/8] arm64: dts: qcom: ipq9574: Disable eMMC node
|
||||
|
||||
Disable eMMC node for rdp433, since rdp433
|
||||
default boot mode is norplusnand
|
||||
|
||||
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
|
||||
---
|
||||
|
||||
Change in [v10]
|
||||
|
||||
* No change
|
||||
|
||||
Change in [v9]
|
||||
|
||||
* No change
|
||||
|
||||
Change in [v8]
|
||||
|
||||
* No change
|
||||
|
||||
Change in [v7]
|
||||
|
||||
* No Change
|
||||
|
||||
Change in [v6]
|
||||
|
||||
* Updated commit message
|
||||
|
||||
Change in [v5]
|
||||
|
||||
* No Change
|
||||
|
||||
Change in [v4]
|
||||
|
||||
* No change
|
||||
|
||||
Change in [v3]
|
||||
|
||||
* Removed co-developed by
|
||||
|
||||
Change in [v2]
|
||||
|
||||
* Posted as initial eMMC disable patch
|
||||
|
||||
Change in [v1]
|
||||
|
||||
* This patch was not included in v1
|
||||
|
||||
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
|
||||
@@ -82,7 +82,7 @@
|
||||
mmc-hs400-enhanced-strobe;
|
||||
max-frequency = <384000000>;
|
||||
bus-width = <8>;
|
||||
- status = "okay";
|
||||
+ status = "disabled";
|
||||
};
|
||||
|
||||
&sleep_clk {
|
@ -0,0 +1,79 @@
|
||||
From c2622fd4e03d3f79ce341c3b417992831c9d785d Mon Sep 17 00:00:00 2001
|
||||
From: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
Date: Fri, 3 Jan 2014 13:05:56 +0530
|
||||
Subject: [PATCH] Squashfs: Accept mtd names for mounting
|
||||
|
||||
Enable SquashFS to mount using MTD partition names
|
||||
instead of device number.
|
||||
|
||||
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
(cherry picked from commit 4e9850b2e9ce7cdaaca70fc78a426f366f33655c)
|
||||
|
||||
Change-Id: I49093c5139caa8d9e7a80fa8cce91b24f53f47e9
|
||||
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
|
||||
(cherry picked from commit 247c68acccbd646522dcf5b5d823f216806cace6)
|
||||
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
|
||||
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
|
||||
Signed-off-by: Saravanan Jaganathan <quic_sjaganat@quicinc.com>
|
||||
---
|
||||
fs/squashfs/super.c | 40 ++++++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 40 insertions(+)
|
||||
|
||||
--- a/fs/squashfs/super.c
|
||||
+++ b/fs/squashfs/super.c
|
||||
@@ -29,6 +29,10 @@
|
||||
#include <linux/module.h>
|
||||
#include <linux/magic.h>
|
||||
#include <linux/xattr.h>
|
||||
+#include <linux/root_dev.h>
|
||||
+#include <linux/syscalls.h>
|
||||
+#include <linux/mtd/mtd.h>
|
||||
+#include <linux/init_syscalls.h>
|
||||
|
||||
#include "squashfs_fs.h"
|
||||
#include "squashfs_fs_sb.h"
|
||||
@@ -480,8 +484,44 @@ failed_mount:
|
||||
return err;
|
||||
}
|
||||
|
||||
+/* copy from init/do_mounts.h */
|
||||
+static inline int create_dev(char *name, dev_t dev)
|
||||
+{
|
||||
+ init_unlink(name);
|
||||
+ return init_mknod(name, S_IFBLK|0600, new_encode_dev(dev));
|
||||
+}
|
||||
+
|
||||
+static void squashfs_mount(struct fs_context *fc)
|
||||
+{
|
||||
+ if (!strncmp(fc->source, "mtd:", 4) || !strncmp(fc->source, "ubi:", 4)) {
|
||||
+ struct mtd_info *mtd = get_mtd_device_nm("ubi_rootfs");
|
||||
+
|
||||
+ if (!IS_ERR(mtd)) {
|
||||
+ void *bdev;
|
||||
+ char *dev;
|
||||
+ dev = kmalloc(32, GFP_KERNEL);
|
||||
+
|
||||
+ scnprintf(dev, 32, "/dev/mtdblock%d", mtd->index);
|
||||
+ bdev = blkdev_get_by_path(dev, FMODE_READ, fc->fs_type, NULL);
|
||||
+
|
||||
+ if (!IS_ERR(bdev)) {
|
||||
+ kfree(fc->source);
|
||||
+ fc->source = dev;
|
||||
+ } else if (PTR_ERR(bdev) == -ENOENT) {
|
||||
+ create_dev(dev,
|
||||
+ MKDEV(MTD_BLOCK_MAJOR, mtd->index));
|
||||
+ kfree(fc->source);
|
||||
+ fc->source = dev;
|
||||
+ } else
|
||||
+ kfree(dev);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+}
|
||||
+
|
||||
static int squashfs_get_tree(struct fs_context *fc)
|
||||
{
|
||||
+ squashfs_mount(fc);
|
||||
return get_tree_bdev(fc, squashfs_fill_super);
|
||||
}
|
||||
|
@ -0,0 +1,58 @@
|
||||
--- a/drivers/mtd/nand/qpic_common.c
|
||||
+++ b/drivers/mtd/nand/qpic_common.c
|
||||
@@ -82,7 +82,15 @@ void qcom_clear_bam_transaction(struct q
|
||||
if (!nandc->props->supports_bam)
|
||||
return;
|
||||
|
||||
- memset(&bam_txn->bam_ce_pos, 0, sizeof(u32) * 8);
|
||||
+ //memset(&bam_txn->bam_ce_pos, 0, sizeof(u32) * 8);
|
||||
+ bam_txn->bam_ce_pos = 0x0;
|
||||
+ bam_txn->bam_ce_start = 0x0;
|
||||
+ bam_txn->cmd_sgl_pos = 0x0;
|
||||
+ bam_txn->cmd_sgl_start = 0x0;
|
||||
+ bam_txn->tx_sgl_pos = 0x0;
|
||||
+ bam_txn->tx_sgl_start = 0x0;
|
||||
+ bam_txn->rx_sgl_pos = 0x0;
|
||||
+ bam_txn->rx_sgl_start = 0x0;
|
||||
bam_txn->last_data_desc = NULL;
|
||||
|
||||
sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
|
||||
--- a/drivers/spi/spi-qpic-snand.c
|
||||
+++ b/drivers/spi/spi-qpic-snand.c
|
||||
@@ -1586,7 +1586,7 @@ err_dis_core_clk:
|
||||
return ret;
|
||||
}
|
||||
|
||||
-static void qcom_spi_remove(struct platform_device *pdev)
|
||||
+static int qcom_spi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_controller *ctlr = platform_get_drvdata(pdev);
|
||||
struct qcom_nand_controller *snandc = spi_controller_get_devdata(ctlr);
|
||||
@@ -1602,6 +1602,7 @@ static void qcom_spi_remove(struct platf
|
||||
|
||||
dma_unmap_resource(&pdev->dev, snandc->base_dma, resource_size(res),
|
||||
DMA_BIDIRECTIONAL, 0);
|
||||
+ return 0;
|
||||
}
|
||||
|
||||
static const struct qcom_nandc_props ipq9574_snandc_props = {
|
||||
--- a/drivers/mtd/mtd_blkdevs.c
|
||||
+++ b/drivers/mtd/mtd_blkdevs.c
|
||||
@@ -481,7 +481,7 @@ static void blktrans_notify_add(struct m
|
||||
{
|
||||
struct mtd_blktrans_ops *tr;
|
||||
|
||||
- if (mtd->type == MTD_ABSENT || mtd->type == MTD_UBIVOLUME)
|
||||
+ if (mtd->type == MTD_ABSENT)
|
||||
return;
|
||||
|
||||
list_for_each_entry(tr, &blktrans_majors, list)
|
||||
@@ -521,7 +521,7 @@ int register_mtd_blktrans(struct mtd_blk
|
||||
mutex_lock(&mtd_table_mutex);
|
||||
list_add(&tr->list, &blktrans_majors);
|
||||
mtd_for_each_device(mtd)
|
||||
- if (mtd->type != MTD_ABSENT && mtd->type != MTD_UBIVOLUME)
|
||||
+ if (mtd->type != MTD_ABSENT)
|
||||
tr->add_mtd(tr, mtd);
|
||||
mutex_unlock(&mtd_table_mutex);
|
||||
return 0;
|
Loading…
Reference in New Issue
Block a user