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realtek: Packet Inspection Engine support for RTL930x SoCs
Adds the RTL930x-specific PIE support routines. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This commit is contained in:
Birger Koblitz
John Crispin
parent
2d8d81fe28
commit
a96b73a890
@ -6,6 +6,98 @@
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extern struct mutex smi_lock;
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extern struct rtl83xx_soc_info soc_info;
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/* Definition of the RTL930X-specific template field IDs as used in the PIE */
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enum template_field_id {
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TEMPLATE_FIELD_SPM0 = 0, // Source portmask ports 0-15
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TEMPLATE_FIELD_SPM1 = 1, // Source portmask ports 16-31
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TEMPLATE_FIELD_DMAC0 = 2, // Destination MAC [15:0]
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TEMPLATE_FIELD_DMAC1 = 3, // Destination MAC [31:16]
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TEMPLATE_FIELD_DMAC2 = 4, // Destination MAC [47:32]
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TEMPLATE_FIELD_SMAC0 = 5, // Source MAC [15:0]
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TEMPLATE_FIELD_SMAC1 = 6, // Source MAC [31:16]
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TEMPLATE_FIELD_SMAC2 = 7, // Source MAC [47:32]
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TEMPLATE_FIELD_ETHERTYPE = 8, // Ethernet frame type field
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TEMPLATE_FIELD_OTAG = 9,
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TEMPLATE_FIELD_ITAG = 10,
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TEMPLATE_FIELD_SIP0 = 11,
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TEMPLATE_FIELD_SIP1 = 12,
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TEMPLATE_FIELD_DIP0 = 13,
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TEMPLATE_FIELD_DIP1 = 14,
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TEMPLATE_FIELD_IP_TOS_PROTO = 15,
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TEMPLATE_FIELD_L4_SPORT = 16,
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TEMPLATE_FIELD_L4_DPORT = 17,
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TEMPLATE_FIELD_L34_HEADER = 18,
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TEMPLATE_FIELD_TCP_INFO = 19,
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TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 20,
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TEMPLATE_FIELD_FIELD_SELECTOR_0 = 21,
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TEMPLATE_FIELD_FIELD_SELECTOR_1 = 22,
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TEMPLATE_FIELD_FIELD_SELECTOR_2 = 23,
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TEMPLATE_FIELD_FIELD_SELECTOR_3 = 24,
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TEMPLATE_FIELD_FIELD_SELECTOR_4 = 25,
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TEMPLATE_FIELD_FIELD_SELECTOR_5 = 26,
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TEMPLATE_FIELD_SIP2 = 27,
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TEMPLATE_FIELD_SIP3 = 28,
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TEMPLATE_FIELD_SIP4 = 29,
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TEMPLATE_FIELD_SIP5 = 30,
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TEMPLATE_FIELD_SIP6 = 31,
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TEMPLATE_FIELD_SIP7 = 32,
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TEMPLATE_FIELD_DIP2 = 33,
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TEMPLATE_FIELD_DIP3 = 34,
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TEMPLATE_FIELD_DIP4 = 35,
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TEMPLATE_FIELD_DIP5 = 36,
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TEMPLATE_FIELD_DIP6 = 37,
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TEMPLATE_FIELD_DIP7 = 38,
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TEMPLATE_FIELD_PKT_INFO = 39,
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TEMPLATE_FIELD_FLOW_LABEL = 40,
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TEMPLATE_FIELD_DSAP_SSAP = 41,
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TEMPLATE_FIELD_SNAP_OUI = 42,
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TEMPLATE_FIELD_FWD_VID = 43,
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TEMPLATE_FIELD_RANGE_CHK = 44,
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TEMPLATE_FIELD_VLAN_GMSK = 45, // VLAN Group Mask/IP range check
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TEMPLATE_FIELD_DLP = 46,
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TEMPLATE_FIELD_META_DATA = 47,
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TEMPLATE_FIELD_SRC_FWD_VID = 48,
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TEMPLATE_FIELD_SLP = 49,
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};
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/* The meaning of TEMPLATE_FIELD_VLAN depends on phase and the configuration in
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* RTL930X_PIE_CTRL. We use always the same definition and map to the inner VLAN tag:
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*/
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#define TEMPLATE_FIELD_VLAN TEMPLATE_FIELD_ITAG
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// Number of fixed templates predefined in the RTL9300 SoC
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#define N_FIXED_TEMPLATES 5
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// RTL9300 specific predefined templates
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static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
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{
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{
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TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
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TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
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TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_DSAP_SSAP,
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TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
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}, {
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TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
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TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_TCP_INFO,
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TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_VLAN,
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TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
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}, {
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TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
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TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,
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TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
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TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT
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}, {
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TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,
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TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,
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TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_IP_TOS_PROTO,
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TEMPLATE_FIELD_TCP_INFO, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT
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}, {
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TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,
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TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,
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TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_VLAN,
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TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM1
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},
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};
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void rtl930x_print_matrix(void)
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{
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int i;
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@ -975,6 +1067,586 @@ static void rtl930x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
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priv->eee_enabled = enable;
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}
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static void rtl930x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)
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{
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int block = index / PIE_BLOCK_SIZE;
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sw_w32_mask(0, BIT(block), RTL930X_PIE_BLK_LOOKUP_CTRL);
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}
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/*
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* Reads the intermediate representation of the templated match-fields of the
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* PIE rule in the pie_rule structure and fills in the raw data fields in the
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* raw register space r[].
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* The register space configuration size is identical for the RTL8380/90 and RTL9300,
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* however the RTL9310 has 2 more registers / fields and the physical field-ids are different
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* on all SoCs
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* On the RTL9300 the mask fields are not word-aligend!
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*/
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static void rtl930x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
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{
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int i;
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enum template_field_id field_type;
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u16 data, data_m;
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for (i = 0; i < N_FIXED_FIELDS; i++) {
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field_type = t[i];
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data = data_m = 0;
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switch (field_type) {
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case TEMPLATE_FIELD_SPM0:
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data = pr->spm;
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data_m = pr->spm_m;
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break;
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case TEMPLATE_FIELD_SPM1:
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data = pr->spm >> 16;
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data_m = pr->spm_m >> 16;
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break;
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case TEMPLATE_FIELD_OTAG:
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data = pr->otag;
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data_m = pr->otag_m;
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break;
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case TEMPLATE_FIELD_SMAC0:
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data = pr->smac[4];
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data = (data << 8) | pr->smac[5];
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data_m = pr->smac_m[4];
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data_m = (data_m << 8) | pr->smac_m[5];
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break;
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case TEMPLATE_FIELD_SMAC1:
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data = pr->smac[2];
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data = (data << 8) | pr->smac[3];
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data_m = pr->smac_m[2];
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data_m = (data_m << 8) | pr->smac_m[3];
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break;
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case TEMPLATE_FIELD_SMAC2:
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data = pr->smac[0];
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data = (data << 8) | pr->smac[1];
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data_m = pr->smac_m[0];
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data_m = (data_m << 8) | pr->smac_m[1];
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break;
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case TEMPLATE_FIELD_DMAC0:
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data = pr->dmac[4];
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data = (data << 8) | pr->dmac[5];
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data_m = pr->dmac_m[4];
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data_m = (data_m << 8) | pr->dmac_m[5];
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break;
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case TEMPLATE_FIELD_DMAC1:
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data = pr->dmac[2];
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data = (data << 8) | pr->dmac[3];
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data_m = pr->dmac_m[2];
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data_m = (data_m << 8) | pr->dmac_m[3];
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break;
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case TEMPLATE_FIELD_DMAC2:
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data = pr->dmac[0];
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data = (data << 8) | pr->dmac[1];
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data_m = pr->dmac_m[0];
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data_m = (data_m << 8) | pr->dmac_m[1];
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break;
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case TEMPLATE_FIELD_ETHERTYPE:
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data = pr->ethertype;
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data_m = pr->ethertype_m;
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break;
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case TEMPLATE_FIELD_ITAG:
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data = pr->itag;
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data_m = pr->itag_m;
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break;
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case TEMPLATE_FIELD_SIP0:
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if (pr->is_ipv6) {
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data = pr->sip6.s6_addr16[7];
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data_m = pr->sip6_m.s6_addr16[7];
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} else {
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data = pr->sip;
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data_m = pr->sip_m;
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}
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break;
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case TEMPLATE_FIELD_SIP1:
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if (pr->is_ipv6) {
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data = pr->sip6.s6_addr16[6];
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data_m = pr->sip6_m.s6_addr16[6];
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} else {
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data = pr->sip >> 16;
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data_m = pr->sip_m >> 16;
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}
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break;
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case TEMPLATE_FIELD_SIP2:
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case TEMPLATE_FIELD_SIP3:
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case TEMPLATE_FIELD_SIP4:
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case TEMPLATE_FIELD_SIP5:
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case TEMPLATE_FIELD_SIP6:
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case TEMPLATE_FIELD_SIP7:
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data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
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data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
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break;
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case TEMPLATE_FIELD_DIP0:
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if (pr->is_ipv6) {
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data = pr->dip6.s6_addr16[7];
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data_m = pr->dip6_m.s6_addr16[7];
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} else {
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data = pr->dip;
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data_m = pr->dip_m;
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}
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break;
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case TEMPLATE_FIELD_DIP1:
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if (pr->is_ipv6) {
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data = pr->dip6.s6_addr16[6];
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data_m = pr->dip6_m.s6_addr16[6];
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} else {
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data = pr->dip >> 16;
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data_m = pr->dip_m >> 16;
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}
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break;
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case TEMPLATE_FIELD_DIP2:
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case TEMPLATE_FIELD_DIP3:
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case TEMPLATE_FIELD_DIP4:
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case TEMPLATE_FIELD_DIP5:
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case TEMPLATE_FIELD_DIP6:
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case TEMPLATE_FIELD_DIP7:
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data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
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data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
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break;
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case TEMPLATE_FIELD_IP_TOS_PROTO:
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data = pr->tos_proto;
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data_m = pr->tos_proto_m;
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break;
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case TEMPLATE_FIELD_L4_SPORT:
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data = pr->sport;
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data_m = pr->sport_m;
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break;
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case TEMPLATE_FIELD_L4_DPORT:
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data = pr->dport;
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data_m = pr->dport_m;
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break;
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case TEMPLATE_FIELD_DSAP_SSAP:
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data = pr->dsap_ssap;
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data_m = pr->dsap_ssap_m;
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break;
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case TEMPLATE_FIELD_TCP_INFO:
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data = pr->tcp_info;
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data_m = pr->tcp_info_m;
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break;
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case TEMPLATE_FIELD_RANGE_CHK:
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pr_warn("Warning: TEMPLATE_FIELD_RANGE_CHK: not configured\n");
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break;
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default:
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pr_info("%s: unknown field %d\n", __func__, field_type);
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}
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// On the RTL9300, the mask fields are not word aligned!
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if (!(i % 2)) {
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r[5 - i / 2] = data;
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r[12 - i / 2] |= ((u32)data_m << 8);
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} else {
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r[5 - i / 2] |= ((u32)data) << 16;
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r[12 - i / 2] |= ((u32)data_m) << 24;
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r[11 - i / 2] |= ((u32)data_m) >> 8;
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}
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}
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}
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static void rtl930x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
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{
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pr->stacking_port = r[6] & BIT(31);
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pr->spn = (r[6] >> 24) & 0x7f;
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pr->mgnt_vlan = r[6] & BIT(23);
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if (pr->phase == PHASE_IACL)
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pr->dmac_hit_sw = r[6] & BIT(22);
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else
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pr->content_too_deep = r[6] & BIT(22);
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pr->not_first_frag = r[6] & BIT(21);
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pr->frame_type_l4 = (r[6] >> 18) & 7;
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pr->frame_type = (r[6] >> 16) & 3;
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pr->otag_fmt = (r[6] >> 15) & 1;
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pr->itag_fmt = (r[6] >> 14) & 1;
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pr->otag_exist = (r[6] >> 13) & 1;
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pr->itag_exist = (r[6] >> 12) & 1;
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pr->frame_type_l2 = (r[6] >> 10) & 3;
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pr->igr_normal_port = (r[6] >> 9) & 1;
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pr->tid = (r[6] >> 8) & 1;
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pr->stacking_port_m = r[12] & BIT(7);
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pr->spn_m = r[12] & 0x7f;
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pr->mgnt_vlan_m = r[13] & BIT(31);
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if (pr->phase == PHASE_IACL)
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pr->dmac_hit_sw_m = r[13] & BIT(30);
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else
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pr->content_too_deep_m = r[13] & BIT(30);
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pr->not_first_frag_m = r[13] & BIT(29);
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pr->frame_type_l4_m = (r[13] >> 26) & 7;
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pr->frame_type_m = (r[13] >> 24) & 3;
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pr->otag_fmt_m = r[13] & BIT(23);
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pr->itag_fmt_m = r[13] & BIT(22);
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pr->otag_exist_m = r[13] & BIT(21);
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pr->itag_exist_m = r[13] & BIT (20);
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pr->frame_type_l2_m = (r[13] >> 18) & 3;
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pr->igr_normal_port_m = r[13] & BIT(17);
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pr->tid_m = (r[13] >> 16) & 1;
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pr->valid = r[13] & BIT(15);
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pr->cond_not = r[13] & BIT(14);
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pr->cond_and1 = r[13] & BIT(13);
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pr->cond_and2 = r[13] & BIT(12);
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}
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static void rtl930x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr)
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{
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r[6] = pr->stacking_port ? BIT(31) : 0;
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r[6] |= ((u32) (pr->spn & 0x7f)) << 24;
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r[6] |= pr->mgnt_vlan ? BIT(23) : 0;
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if (pr->phase == PHASE_IACL)
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r[6] |= pr->dmac_hit_sw ? BIT(22) : 0;
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else
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r[6] |= pr->content_too_deep ? BIT(22) : 0;
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r[6] |= pr->not_first_frag ? BIT(21) : 0;
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r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 18;
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r[6] |= ((u32) (pr->frame_type & 0x3)) << 16;
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r[6] |= pr->otag_fmt ? BIT(15) : 0;
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r[6] |= pr->itag_fmt ? BIT(14) : 0;
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r[6] |= pr->otag_exist ? BIT(13) : 0;
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r[6] |= pr->itag_exist ? BIT(12) : 0;
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r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 10;
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r[6] |= pr->igr_normal_port ? BIT(9) : 0;
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r[6] |= ((u32) (pr->tid & 0x1)) << 8;
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r[12] |= pr->stacking_port_m ? BIT(7) : 0;
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r[12] |= (u32) (pr->spn_m & 0x7f);
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r[13] |= pr->mgnt_vlan_m ? BIT(31) : 0;
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if (pr->phase == PHASE_IACL)
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r[13] |= pr->dmac_hit_sw_m ? BIT(30) : 0;
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else
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r[13] |= pr->content_too_deep_m ? BIT(30) : 0;
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r[13] |= pr->not_first_frag_m ? BIT(29) : 0;
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r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 26;
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r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 24;
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r[13] |= pr->otag_fmt_m ? BIT(23) : 0;
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r[13] |= pr->itag_fmt_m ? BIT(22) : 0;
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r[13] |= pr->otag_exist_m ? BIT(21) : 0;
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r[13] |= pr->itag_exist_m ? BIT(20) : 0;
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r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 18;
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r[13] |= pr->igr_normal_port_m ? BIT(17) : 0;
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r[13] |= ((u32) (pr->tid_m & 0x1)) << 16;
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||||
|
||||
r[13] |= pr->valid ? BIT(15) : 0;
|
||||
r[13] |= pr->cond_not ? BIT(14) : 0;
|
||||
r[13] |= pr->cond_and1 ? BIT(13) : 0;
|
||||
r[13] |= pr->cond_and2 ? BIT(12) : 0;
|
||||
}
|
||||
|
||||
static void rtl930x_write_pie_action(u32 r[], struct pie_rule *pr)
|
||||
{
|
||||
// Either drop or forward
|
||||
if (pr->drop) {
|
||||
r[14] |= BIT(24) | BIT(25) | BIT(26); // Do Green, Yellow and Red drops
|
||||
// Actually DROP, not PERMIT in Green / Yellow / Red
|
||||
r[14] |= BIT(23) | BIT(22) | BIT(20);
|
||||
} else {
|
||||
r[14] |= pr->fwd_sel ? BIT(27) : 0;
|
||||
r[14] |= pr->fwd_act << 18;
|
||||
r[14] |= BIT(14); // We overwrite any drop
|
||||
}
|
||||
if (pr->phase == PHASE_VACL)
|
||||
r[14] |= pr->fwd_sa_lrn ? BIT(15) : 0;
|
||||
r[13] |= pr->bypass_sel ? BIT(5) : 0;
|
||||
r[13] |= pr->nopri_sel ? BIT(4) : 0;
|
||||
r[13] |= pr->tagst_sel ? BIT(3) : 0;
|
||||
r[13] |= pr->ovid_sel ? BIT(1) : 0;
|
||||
r[14] |= pr->ivid_sel ? BIT(31) : 0;
|
||||
r[14] |= pr->meter_sel ? BIT(30) : 0;
|
||||
r[14] |= pr->mir_sel ? BIT(29) : 0;
|
||||
r[14] |= pr->log_sel ? BIT(28) : 0;
|
||||
|
||||
r[14] |= ((u32)(pr->fwd_data & 0x3fff)) << 3;
|
||||
r[15] |= pr->log_octets ? BIT(31) : 0;
|
||||
r[15] |= (u32)(pr->meter_data) << 23;
|
||||
|
||||
r[15] |= ((u32)(pr->ivid_act) << 21) & 0x3;
|
||||
r[15] |= ((u32)(pr->ivid_data) << 9) & 0xfff;
|
||||
r[16] |= ((u32)(pr->ovid_act) << 30) & 0x3;
|
||||
r[16] |= ((u32)(pr->ovid_data) & 0xfff) << 16;
|
||||
r[16] |= (pr->mir_data & 0x3) << 6;
|
||||
r[17] |= ((u32)(pr->tagst_data) & 0xf) << 28;
|
||||
r[17] |= ((u32)(pr->nopri_data) & 0x7) << 25;
|
||||
r[17] |= pr->bypass_ibc_sc ? BIT(16) : 0;
|
||||
}
|
||||
|
||||
void rtl930x_pie_rule_dump_raw(u32 r[])
|
||||
{
|
||||
pr_info("Raw IACL table entry:\n");
|
||||
pr_info("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n",
|
||||
r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);
|
||||
pr_info("r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\n",
|
||||
r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);
|
||||
pr_info("r 16 - 18: %08x %08x %08x\n", r[16], r[17], r[18]);
|
||||
pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
|
||||
pr_info("Fixed : %06x\n", r[6] >> 8);
|
||||
pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
|
||||
(r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
|
||||
(r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
|
||||
(r[11] << 24) | (r[12] >> 8));
|
||||
pr_info("R[13]: %08x\n", r[13]);
|
||||
pr_info("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
|
||||
pr_info("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
|
||||
pr_info("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]);
|
||||
}
|
||||
|
||||
static int rtl930x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
|
||||
{
|
||||
// Access IACL table (2) via register 0
|
||||
struct table_reg *q = rtl_table_get(RTL9300_TBL_0, 2);
|
||||
u32 r[19];
|
||||
int i;
|
||||
int block = idx / PIE_BLOCK_SIZE;
|
||||
u32 t_select = sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block));
|
||||
|
||||
pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select);
|
||||
|
||||
for (i = 0; i < 19; i++)
|
||||
r[i] = 0;
|
||||
|
||||
if (!pr->valid) {
|
||||
rtl_table_write(q, idx);
|
||||
rtl_table_release(q);
|
||||
return 0;
|
||||
}
|
||||
rtl930x_write_pie_fixed_fields(r, pr);
|
||||
|
||||
pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 4)) & 0xf);
|
||||
rtl930x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 4)) & 0xf]);
|
||||
|
||||
rtl930x_write_pie_action(r, pr);
|
||||
|
||||
// rtl930x_pie_rule_dump_raw(r);
|
||||
|
||||
for (i = 0; i < 19; i++)
|
||||
sw_w32(r[i], rtl_table_data(q, i));
|
||||
|
||||
rtl_table_write(q, idx);
|
||||
rtl_table_release(q);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool rtl930x_pie_templ_has(int t, enum template_field_id field_type)
|
||||
{
|
||||
int i;
|
||||
enum template_field_id ft;
|
||||
|
||||
for (i = 0; i < N_FIXED_FIELDS; i++) {
|
||||
ft = fixed_templates[t][i];
|
||||
if (field_type == ft)
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/*
|
||||
* Verify that the rule pr is compatible with a given template t in block block
|
||||
* Note that this function is SoC specific since the values of e.g. TEMPLATE_FIELD_SIP0
|
||||
* depend on the SoC
|
||||
*/
|
||||
static int rtl930x_pie_verify_template(struct rtl838x_switch_priv *priv,
|
||||
struct pie_rule *pr, int t, int block)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (!pr->is_ipv6 && pr->sip_m && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))
|
||||
return -1;
|
||||
|
||||
if (!pr->is_ipv6 && pr->dip_m && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))
|
||||
return -1;
|
||||
|
||||
if (pr->is_ipv6) {
|
||||
if ((pr->sip6_m.s6_addr32[0] || pr->sip6_m.s6_addr32[1]
|
||||
|| pr->sip6_m.s6_addr32[2] || pr->sip6_m.s6_addr32[3])
|
||||
&& !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))
|
||||
return -1;
|
||||
if ((pr->dip6_m.s6_addr32[0] || pr->dip6_m.s6_addr32[1]
|
||||
|| pr->dip6_m.s6_addr32[2] || pr->dip6_m.s6_addr32[3])
|
||||
&& !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (ether_addr_to_u64(pr->smac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))
|
||||
return -1;
|
||||
|
||||
if (ether_addr_to_u64(pr->dmac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))
|
||||
return -1;
|
||||
|
||||
// TODO: Check more
|
||||
|
||||
i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);
|
||||
|
||||
if (i >= PIE_BLOCK_SIZE)
|
||||
return -1;
|
||||
|
||||
return i + PIE_BLOCK_SIZE * block;
|
||||
}
|
||||
|
||||
static int rtl930x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
|
||||
{
|
||||
int idx, block, j, t;
|
||||
int min_block = 0;
|
||||
int max_block = priv->n_pie_blocks / 2;
|
||||
|
||||
if (pr->is_egress) {
|
||||
min_block = max_block;
|
||||
max_block = priv->n_pie_blocks;
|
||||
}
|
||||
pr_debug("In %s\n", __func__);
|
||||
|
||||
mutex_lock(&priv->pie_mutex);
|
||||
|
||||
for (block = min_block; block < max_block; block++) {
|
||||
for (j = 0; j < 2; j++) {
|
||||
t = (sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)) >> (j * 4)) & 0xf;
|
||||
pr_debug("Testing block %d, template %d, template id %d\n", block, j, t);
|
||||
pr_debug("%s: %08x\n",
|
||||
__func__, sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)));
|
||||
idx = rtl930x_pie_verify_template(priv, pr, t, block);
|
||||
if (idx >= 0)
|
||||
break;
|
||||
}
|
||||
if (j < 2)
|
||||
break;
|
||||
}
|
||||
|
||||
if (block >= priv->n_pie_blocks) {
|
||||
mutex_unlock(&priv->pie_mutex);
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
pr_debug("Using block: %d, index %d, template-id %d\n", block, idx, j);
|
||||
set_bit(idx, priv->pie_use_bm);
|
||||
|
||||
pr->valid = true;
|
||||
pr->tid = j; // Mapped to template number
|
||||
pr->tid_m = 0x1;
|
||||
pr->id = idx;
|
||||
|
||||
rtl930x_pie_lookup_enable(priv, idx);
|
||||
rtl930x_pie_rule_write(priv, idx, pr);
|
||||
|
||||
mutex_unlock(&priv->pie_mutex);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Delete a range of Packet Inspection Engine rules
|
||||
*/
|
||||
static int rtl930x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
|
||||
{
|
||||
u32 v = (index_from << 1)| (index_to << 12 ) | BIT(0);
|
||||
|
||||
pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
|
||||
mutex_lock(&priv->reg_mutex);
|
||||
|
||||
// Write from-to and execute bit into control register
|
||||
sw_w32(v, RTL930X_PIE_CLR_CTRL);
|
||||
|
||||
// Wait until command has completed
|
||||
do {
|
||||
} while (sw_r32(RTL930X_PIE_CLR_CTRL) & BIT(0));
|
||||
|
||||
mutex_unlock(&priv->reg_mutex);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rtl930x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
|
||||
{
|
||||
int idx = pr->id;
|
||||
|
||||
rtl930x_pie_rule_del(priv, idx, idx);
|
||||
clear_bit(idx, priv->pie_use_bm);
|
||||
}
|
||||
|
||||
static void rtl930x_pie_init(struct rtl838x_switch_priv *priv)
|
||||
{
|
||||
int i;
|
||||
u32 template_selectors;
|
||||
|
||||
mutex_init(&priv->pie_mutex);
|
||||
|
||||
pr_info("%s\n", __func__);
|
||||
// Enable ACL lookup on all ports, including CPU_PORT
|
||||
for (i = 0; i <= priv->cpu_port; i++)
|
||||
sw_w32(1, RTL930X_ACL_PORT_LOOKUP_CTRL(i));
|
||||
|
||||
// Include IPG in metering
|
||||
sw_w32_mask(0, 1, RTL930X_METER_GLB_CTRL);
|
||||
|
||||
// Delete all present rules, block size is 128 on all SoC families
|
||||
rtl930x_pie_rule_del(priv, 0, priv->n_pie_blocks * 128 - 1);
|
||||
|
||||
// Assign blocks 0-7 to VACL phase (bit = 0), blocks 8-15 to IACL (bit = 1)
|
||||
sw_w32(0xff00, RTL930X_PIE_BLK_PHASE_CTRL);
|
||||
|
||||
// Enable predefined templates 0, 1 for first quarter of all blocks
|
||||
template_selectors = 0 | (1 << 4);
|
||||
for (i = 0; i < priv->n_pie_blocks / 4; i++)
|
||||
sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
|
||||
|
||||
// Enable predefined templates 2, 3 for second quarter of all blocks
|
||||
template_selectors = 2 | (3 << 4);
|
||||
for (i = priv->n_pie_blocks / 4; i < priv->n_pie_blocks / 2; i++)
|
||||
sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
|
||||
|
||||
// Enable predefined templates 0, 1 for third half of all blocks
|
||||
template_selectors = 0 | (1 << 4);
|
||||
for (i = priv->n_pie_blocks / 2; i < priv->n_pie_blocks * 3 / 4; i++)
|
||||
sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
|
||||
|
||||
// Enable predefined templates 2, 3 for fourth quater of all blocks
|
||||
template_selectors = 2 | (3 << 4);
|
||||
for (i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++)
|
||||
sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
|
||||
|
||||
}
|
||||
|
||||
static u32 rtl930x_packet_cntr_read(int counter)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
// Read LOG table (3) via register RTL9300_TBL_0
|
||||
struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3);
|
||||
|
||||
pr_debug("In %s, id %d\n", __func__, counter);
|
||||
rtl_table_read(r, counter / 2);
|
||||
|
||||
pr_debug("Registers: %08x %08x\n",
|
||||
sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)));
|
||||
// The table has a size of 2 registers
|
||||
if (counter % 2)
|
||||
v = sw_r32(rtl_table_data(r, 0));
|
||||
else
|
||||
v = sw_r32(rtl_table_data(r, 1));
|
||||
|
||||
rtl_table_release(r);
|
||||
|
||||
return v;
|
||||
}
|
||||
|
||||
static void rtl930x_packet_cntr_clear(int counter)
|
||||
{
|
||||
// Access LOG table (3) via register RTL9300_TBL_0
|
||||
struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3);
|
||||
|
||||
pr_info("In %s, id %d\n", __func__, counter);
|
||||
// The table has a size of 2 registers
|
||||
if (counter % 2)
|
||||
sw_w32(0, rtl_table_data(r, 0));
|
||||
else
|
||||
sw_w32(0, rtl_table_data(r, 1));
|
||||
|
||||
rtl_table_write(r, counter / 2);
|
||||
|
||||
rtl_table_release(r);
|
||||
}
|
||||
|
||||
const struct rtl838x_reg rtl930x_reg = {
|
||||
.mask_port_reg_be = rtl838x_mask_port_reg,
|
||||
.set_port_reg_be = rtl838x_set_port_reg,
|
||||
@ -1036,4 +1708,10 @@ const struct rtl838x_reg rtl930x_reg = {
|
||||
.eee_port_ability = rtl930x_eee_port_ability,
|
||||
.read_mcast_pmask = rtl930x_read_mcast_pmask,
|
||||
.write_mcast_pmask = rtl930x_write_mcast_pmask,
|
||||
.pie_init = rtl930x_pie_init,
|
||||
.pie_rule_write = rtl930x_pie_rule_write,
|
||||
.pie_rule_add = rtl930x_pie_rule_add,
|
||||
.pie_rule_rm = rtl930x_pie_rule_rm,
|
||||
.packet_cntr_read = rtl930x_packet_cntr_read,
|
||||
.packet_cntr_clear = rtl930x_packet_cntr_clear,
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user