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layerscape: update linux 4.9 patches to LSDK-18.06

Browse Source 
This patch is to update linux 4.9 patches to LSDK-18.06
release and to adjust config-4.9 accordingly.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
This commit is contained in:
Yangbo Lu 2018-08-15 16:08:53 +08:00 committed by Hauke Mehrtens
parent ad1dbc0ca3
commit a83eae385a
23 changed files with 24234 additions and 12743 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
target/linux/layerscape/armv8_32b/config-4.9
View File

@ -145,6 +145,8 @@ CONFIG_CAN_RAW=y
# CONFIG_CAN_SJA1000 is not set
# CONFIG_CAN_SOFTING is not set
# CONFIG_CAN_TI_HECC is not set
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_CFS_BANDWIDTH is not set
CONFIG_CGROUPS=y
CONFIG_CGROUP_CPUACCT=y
@ -464,6 +466,7 @@ CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IO=y
CONFIG_GENERIC_IRQ_CHIP=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_MSI_IRQ=y

11
target/linux/layerscape/armv8_64b/config-4.9
View File

@ -98,6 +98,7 @@ CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_FSL_MC=y
# CONFIG_ARM_PL172_MPMC is not set
CONFIG_ARM_PMU=y
CONFIG_ARM_PSCI_FW=y
@ -157,6 +158,8 @@ CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23144=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_CEPH_LIB=y
# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
@ -165,7 +168,7 @@ CONFIG_CFQ_GROUP_IOSCHED=y
CONFIG_CGROUPS=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_DEVICE=y
# CONFIG_CGROUP_FREEZER is not set
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_HUGETLB=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_PIDS=y
@ -417,6 +420,8 @@ CONFIG_FSL_BMAN_DEBUGFS=y
CONFIG_FSL_DPAA2=y
CONFIG_FSL_DPAA2_ETH=y
CONFIG_FSL_DPAA2_ETHSW=y
# CONFIG_FSL_DPAA2_ETH_CEETM is not set
# CONFIG_FSL_DPAA2_ETH_DEBUGFS is not set
# CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE is not set
CONFIG_FSL_DPAA2_EVB=y
CONFIG_FSL_DPAA2_MAC=y
@ -499,6 +504,7 @@ CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IO=y
CONFIG_GENERIC_IRQ_CHIP=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
@ -845,6 +851,7 @@ CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_IP_TUNNEL=y
CONFIG_NET_NS=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NET_SWITCHDEV=y
CONFIG_NLS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
@ -957,6 +964,7 @@ CONFIG_QCOM_QDF2400_ERRATUM_0065=y
# CONFIG_QFMT_V2 is not set
CONFIG_QMAN_CEETM_UPDATE_PERIOD=1000
CONFIG_QORIQ_CPUFREQ=y
CONFIG_QORIQ_THERMAL=y
# CONFIG_QUICC_ENGINE is not set
CONFIG_QUOTA=y
CONFIG_QUOTACTL=y
@ -1233,4 +1241,3 @@ CONFIG_XZ_DEC_SPARC=y
CONFIG_XZ_DEC_X86=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_QORIQ_THERMAL=y

65
target/linux/layerscape/patches-4.9/201-config-support-layerscape.patch
View File

@ -1,7 +1,7 @@
From e43dec70614b55ba1ce24dfcdf8f51e36d800af2 Mon Sep 17 00:00:00 2001
From 0774b97305507af18f8c43efb69aa00e6c57ae90 Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Wed, 17 Jan 2018 15:26:46 +0800
Subject: [PATCH 01/30] config: support layerscape
Date: Fri, 6 Jul 2018 15:31:14 +0800
Subject: [PATCH] config: support layerscape
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
@ -19,22 +19,22 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
arch/arm/mach-imx/Kconfig | 1 +
drivers/base/Kconfig | 1 +
drivers/crypto/Makefile | 2 +-
drivers/net/ethernet/freescale/Kconfig | 4 ++-
drivers/net/ethernet/freescale/Makefile | 2 ++
drivers/ptp/Kconfig | 29 +++++++++++++++++++
drivers/rtc/Kconfig | 8 ++++++
drivers/net/ethernet/freescale/Kconfig | 4 +-
drivers/net/ethernet/freescale/Makefile | 2 +
drivers/ptp/Kconfig | 29 +++++++++++
drivers/rtc/Kconfig | 8 +++
drivers/rtc/Makefile | 1 +
drivers/soc/Kconfig | 3 +-
drivers/soc/fsl/Kconfig | 22 ++++++++++++++
drivers/soc/fsl/Kconfig.arm | 16 +++++++++++
drivers/soc/fsl/Makefile | 4 +++
drivers/soc/fsl/layerscape/Kconfig | 10 +++++++
drivers/soc/fsl/Kconfig | 30 ++++++++++++
drivers/soc/fsl/Kconfig.arm | 16 ++++++
drivers/soc/fsl/Makefile | 5 ++
drivers/soc/fsl/layerscape/Kconfig | 10 ++++
drivers/soc/fsl/layerscape/Makefile | 1 +
drivers/staging/Kconfig | 6 ++++
drivers/staging/Kconfig | 6 +++
drivers/staging/Makefile | 3 ++
drivers/staging/fsl-dpaa2/Kconfig | 51 +++++++++++++++++++++++++++++++++
drivers/staging/fsl-dpaa2/Makefile | 9 ++++++
18 files changed, 169 insertions(+), 4 deletions(-)
drivers/staging/fsl-dpaa2/Kconfig | 65 +++++++++++++++++++++++++
drivers/staging/fsl-dpaa2/Makefile | 9 ++++
18 files changed, 192 insertions(+), 4 deletions(-)
create mode 100644 drivers/soc/fsl/Kconfig
create mode 100644 drivers/soc/fsl/Kconfig.arm
create mode 100644 drivers/soc/fsl/layerscape/Kconfig
@ -179,7 +179,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
source "drivers/soc/rockchip/Kconfig"
--- /dev/null
+++ b/drivers/soc/fsl/Kconfig
@@ -0,0 +1,22 @@
@@ -0,0 +1,30 @@
+#
+# Freescale SOC drivers
+#
@ -199,6 +199,14 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ Initially only reading SVR and registering soc device are supported.
+ Other guts accesses, such as reading RCW, should eventually be moved
+ into this driver as well.
+
+config FSL_SLEEP_FSM
+ bool
+ help
+ This driver configures a hardware FSM (Finite State Machine) for deep sleep.
+ The FSM is used to finish clean-ups at the last stage of system entering deep
+ sleep, and also wakes up system when a wake up event happens.
+
+if ARM || ARM64
+source "drivers/soc/fsl/Kconfig.arm"
+endif
@ -223,7 +231,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+endif
--- a/drivers/soc/fsl/Makefile
+++ b/drivers/soc/fsl/Makefile
@@ -5,3 +5,7 @@
@@ -5,3 +5,8 @@
obj-$(CONFIG_FSL_DPAA) += qbman/
obj-$(CONFIG_QUICC_ENGINE) += qe/
obj-$(CONFIG_CPM) += qe/
@ -231,6 +239,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+obj-$(CONFIG_FSL_LS2_CONSOLE) += ls2-console/
+obj-$(CONFIG_SUSPEND) += rcpm.o
+obj-$(CONFIG_LS_SOC_DRIVERS) += layerscape/
+obj-$(CONFIG_FSL_SLEEP_FSM) += sleep_fsm.o
--- /dev/null
+++ b/drivers/soc/fsl/layerscape/Kconfig
@@ -0,0 +1,10 @@
@ -285,7 +294,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+obj-$(CONFIG_FSL_PPFE) += fsl_ppfe/
--- /dev/null
+++ b/drivers/staging/fsl-dpaa2/Kconfig
@@ -0,0 +1,51 @@
@@ -0,0 +1,65 @@
+#
+# Freescale DataPath Acceleration Architecture Gen2 (DPAA2) drivers
+#
@ -317,7 +326,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+
+# QBMAN_DEBUG requires some additional DPIO APIs
+config FSL_DPAA2_ETH_DEBUGFS
+ depends on DEBUG_FS && FSL_QBMAN_DEBUG
+ depends on DEBUG_FS
+ bool "Enable debugfs support"
+ default n
+ ---help---
@ -332,11 +341,25 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ (PFC) in the driver.
+
+ If unsure, say N.
+
+config FSL_DPAA2_ETH_CEETM
+ depends on NET_SCHED
+ bool "DPAA2 Ethernet CEETM QoS"
+ default n
+ ---help---
+ Enable QoS offloading support through the CEETM hardware block.
+endif
+
+source "drivers/staging/fsl-dpaa2/mac/Kconfig"
+source "drivers/staging/fsl-dpaa2/evb/Kconfig"
+source "drivers/staging/fsl-dpaa2/ethsw/Kconfig"
+
+config FSL_DPAA2_ETHSW
+ tristate "Freescale DPAA2 Ethernet Switch"
+ depends on FSL_DPAA2
+ depends on NET_SWITCHDEV
+ ---help---
+ Driver for Freescale DPAA2 Ethernet Switch. Select
+ BRIDGE to have support for bridge tools.
--- /dev/null
+++ b/drivers/staging/fsl-dpaa2/Makefile
@@ -0,0 +1,9 @@
@ -347,5 +370,5 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+obj-$(CONFIG_FSL_DPAA2_ETH) += ethernet/
+obj-$(CONFIG_FSL_DPAA2_MAC) += mac/
+obj-$(CONFIG_FSL_DPAA2_EVB) += evb/
+obj-$(CONFIG_FSL_DPAA2_ETHSW) += ethsw/
+obj-$(CONFIG_PTP_1588_CLOCK_DPAA2) += rtc/
+obj-$(CONFIG_FSL_DPAA2_ETHSW) += ethsw/

982
target/linux/layerscape/patches-4.9/202-core-linux-support-layerscape.patch
View File

File diff suppressed because it is too large Load Diff

94
target/linux/layerscape/patches-4.9/301-arch-support-layerscape.patch
View File

@ -1,7 +1,7 @@
From 45e934873f9147f692dddbb61abc088f4c8059d7 Mon Sep 17 00:00:00 2001
From 2f2a0ab9e4b3186be981f7151a4f4f794d4b6caa Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Wed, 17 Jan 2018 14:51:29 +0800
Subject: [PATCH 03/30] arch: support layerscape
Date: Thu, 5 Jul 2018 16:18:37 +0800
Subject: [PATCH 03/32] arch: support layerscape
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
@ -20,22 +20,25 @@ Signed-off-by: Jianhua Xie <jianhua.xie@nxp.com>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
arch/arm/include/asm/delay.h | 16 +++++++++
arch/arm/include/asm/io.h | 31 ++++++++++++++++++
arch/arm/include/asm/mach/map.h | 4 +--
arch/arm/include/asm/pgtable.h | 7 ++++
arch/arm/kernel/bios32.c | 43 ++++++++++++++++++++++++
arch/arm/mm/dma-mapping.c | 1 +
arch/arm/mm/ioremap.c | 7 ++++
arch/arm/mm/mmu.c | 9 +++++
arch/arm64/include/asm/cache.h | 2 +-
arch/arm64/include/asm/io.h | 30 +++++++++++++++++
arch/arm64/include/asm/pci.h | 4 +++
arch/arm64/include/asm/pgtable-prot.h | 1 +
arch/arm64/include/asm/pgtable.h | 5 +++
arch/arm64/kernel/pci.c | 62 +++++++++++++++++++++++++++++++++++
arch/arm64/mm/dma-mapping.c | 6 ++++
15 files changed, 225 insertions(+), 3 deletions(-)
arch/arm/include/asm/delay.h | 16 +++++++
arch/arm/include/asm/dma-mapping.h | 6 ---
arch/arm/include/asm/io.h | 31 +++++++++++++
arch/arm/include/asm/mach/map.h | 4 +-
arch/arm/include/asm/pgtable.h | 7 +++
arch/arm/kernel/bios32.c | 43 ++++++++++++++++++
arch/arm/mm/dma-mapping.c | 1 +
arch/arm/mm/ioremap.c | 7 +++
arch/arm/mm/mmu.c | 9 ++++
arch/arm64/include/asm/cache.h | 2 +-
arch/arm64/include/asm/io.h | 30 +++++++++++++
arch/arm64/include/asm/pci.h | 4 ++
arch/arm64/include/asm/pgtable-prot.h | 2 +
arch/arm64/include/asm/pgtable.h | 5 +++
arch/arm64/kernel/pci.c | 62 ++++++++++++++++++++++++++
arch/arm64/mm/dma-mapping.c | 6 +++
arch/powerpc/include/asm/dma-mapping.h | 5 ---
arch/tile/include/asm/dma-mapping.h | 5 ---
18 files changed, 226 insertions(+), 19 deletions(-)
--- a/arch/arm/include/asm/delay.h
+++ b/arch/arm/include/asm/delay.h
@ -62,6 +65,21 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
/* Loop-based definitions for assembly code. */
extern void __loop_delay(unsigned long loops);
extern void __loop_udelay(unsigned long usecs);
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -31,12 +31,6 @@ static inline struct dma_map_ops *get_dm
return __generic_dma_ops(dev);
}
-static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops)
-{
- BUG_ON(!dev);
- dev->archdata.dma_ops = ops;
-}
-
#define HAVE_ARCH_DMA_SUPPORTED 1
extern int dma_supported(struct device *dev, u64 mask);
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -129,6 +129,7 @@ static inline u32 __raw_readl(const vola
@ -343,6 +361,14 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
#define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
#define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
@@ -68,6 +69,7 @@
#define PAGE_HYP_DEVICE __pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
#define PAGE_S2 __pgprot(_PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
+#define PAGE_S2_NS __pgprot(PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDWR | PTE_TYPE_PAGE | PTE_AF)
#define PAGE_S2_DEVICE __pgprot(_PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN)
#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_NG | PTE_PXN | PTE_UXN)
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -370,6 +370,11 @@ static inline int pmd_protnone(pmd_t pmd
@ -441,7 +467,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
#include <linux/swiotlb.h>
#include <asm/cacheflush.h>
+#include <../../../drivers/staging/fsl-mc/include/mc-bus.h>
+#include <linux/fsl/mc.h>
static int swiotlb __ro_after_init;
@ -461,3 +487,31 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
__iommu_setup_dma_ops(dev, dma_base, size, iommu);
}
+EXPORT_SYMBOL(arch_setup_dma_ops);
--- a/arch/powerpc/include/asm/dma-mapping.h
+++ b/arch/powerpc/include/asm/dma-mapping.h
@@ -91,11 +91,6 @@ static inline struct dma_map_ops *get_dm
return dev->archdata.dma_ops;
}
-static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops)
-{
- dev->archdata.dma_ops = ops;
-}
-
/*
* get_dma_offset()
*
--- a/arch/tile/include/asm/dma-mapping.h
+++ b/arch/tile/include/asm/dma-mapping.h
@@ -59,11 +59,6 @@ static inline phys_addr_t dma_to_phys(st
static inline void dma_mark_clean(void *addr, size_t size) {}
-static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops)
-{
- dev->archdata.dma_ops = ops;
-}
-
static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
{
if (!dev->dma_mask)

2054
target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch
View File

File diff suppressed because it is too large Load Diff

2
target/linux/layerscape/patches-4.9/304-dts-layerscape-add-traverse-ls1043.patch → target/linux/layerscape/patches-4.9/303-dts-layerscape-add-traverse-ls1043.patch
View File

@ -11,7 +11,7 @@ Signed-off-by: Mathew McBride <matt@traverse.com.au>
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -20,7 +20,10 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2
@@ -21,7 +21,10 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb

35
target/linux/layerscape/patches-4.9/401-mtd-spi-nor-support-layerscape.patch
View File

@ -1,7 +1,7 @@
From 825d57369b196b64387348922b47adc5b651622c Mon Sep 17 00:00:00 2001
From c03c545e064a81515fe109ddcc4ecb3895528e58 Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Wed, 17 Jan 2018 14:55:47 +0800
Subject: [PATCH 05/30] mtd: spi-nor: support layerscape
Date: Fri, 6 Jul 2018 15:32:05 +0800
Subject: [PATCH] mtd: spi-nor: support layerscape
This is an integrated patch for layerscape qspi support.
@ -17,11 +17,12 @@ Signed-off-by: L. D. Pinney <ldpinney@gmail.com>
Signed-off-by: Ash Benz <ash.benz@bk.ru>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
drivers/mtd/devices/m25p80.c | 3 +-
drivers/mtd/mtdchar.c | 2 +-
drivers/mtd/spi-nor/fsl-quadspi.c | 327 +++++++++++++++++++++++++++++++-------
drivers/mtd/spi-nor/spi-nor.c | 136 ++++++++++++++--
drivers/mtd/spi-nor/fsl-quadspi.c | 327 ++++++++++++++++++++++++------
drivers/mtd/spi-nor/spi-nor.c | 141 ++++++++++++-
include/linux/mtd/spi-nor.h | 14 +-
4 files changed, 409 insertions(+), 70 deletions(-)
5 files changed, 416 insertions(+), 71 deletions(-)
--- a/drivers/mtd/mtdchar.c
+++ b/drivers/mtd/mtdchar.c
@ -758,9 +759,15 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
{ "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
@@ -1131,6 +1152,9 @@ static const struct flash_info spi_nor_i
@@ -1130,7 +1151,15 @@ static const struct flash_info spi_nor_i
{ "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
{ "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
{ "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
+ {
+ "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
{ "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
+ { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
+ { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
@ -768,7 +775,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
{ "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
{
"w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
@@ -1197,6 +1221,53 @@ static const struct flash_info *spi_nor_
@@ -1197,6 +1226,53 @@ static const struct flash_info *spi_nor_
id[0], id[1], id[2]);
return ERR_PTR(-ENODEV);
}
@ -822,7 +829,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
size_t *retlen, u_char *buf)
@@ -1416,7 +1487,7 @@ static int macronix_quad_enable(struct s
@@ -1416,7 +1492,7 @@ static int macronix_quad_enable(struct s
* Write status Register and configuration register with 2 bytes
* The first byte will be written to the status register, while the
* second byte will be written to the configuration register.
@ -831,7 +838,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
*/
static int write_sr_cr(struct spi_nor *nor, u16 val)
{
@@ -1464,6 +1535,24 @@ static int spansion_quad_enable(struct s
@@ -1464,6 +1540,24 @@ static int spansion_quad_enable(struct s
return 0;
}
@ -856,7 +863,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
{
int status;
@@ -1610,9 +1699,25 @@ int spi_nor_scan(struct spi_nor *nor, co
@@ -1610,9 +1704,25 @@ int spi_nor_scan(struct spi_nor *nor, co
write_sr(nor, 0);
spi_nor_wait_till_ready(nor);
}
@ -882,7 +889,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
mtd->priv = nor;
mtd->type = MTD_NORFLASH;
mtd->writesize = 1;
@@ -1646,6 +1751,8 @@ int spi_nor_scan(struct spi_nor *nor, co
@@ -1646,6 +1756,8 @@ int spi_nor_scan(struct spi_nor *nor, co
nor->flags |= SNOR_F_USE_FSR;
if (info->flags & SPI_NOR_HAS_TB)
nor->flags |= SNOR_F_HAS_SR_TB;
@ -891,7 +898,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
#ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
/* prefer "small sector" erase if possible */
@@ -1685,9 +1792,15 @@ int spi_nor_scan(struct spi_nor *nor, co
@@ -1685,9 +1797,15 @@ int spi_nor_scan(struct spi_nor *nor, co
/* Some devices cannot do fast-read, no matter what DT tells us */
if (info->flags & SPI_NOR_NO_FR)
nor->flash_read = SPI_NOR_NORMAL;
@ -910,7 +917,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
ret = set_quad_mode(nor, info);
if (ret) {
dev_err(dev, "quad mode not supported\n");
@@ -1700,6 +1813,9 @@ int spi_nor_scan(struct spi_nor *nor, co
@@ -1700,6 +1818,9 @@ int spi_nor_scan(struct spi_nor *nor, co
/* Default commands */
switch (nor->flash_read) {

935
target/linux/layerscape/patches-4.9/701-sdk_dpaa-support-layerscape.patch
View File

File diff suppressed because it is too large Load Diff

36
target/linux/layerscape/patches-4.9/702-pci-support-layerscape.patch
View File

@ -1,7 +1,7 @@
From 5fcb42fbd224e1103bacbae4785745842cfd6304 Mon Sep 17 00:00:00 2001
From b2ee6e29bad31facbbf5ac1ce98235ac163d9fa9 Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Wed, 17 Jan 2018 15:00:43 +0800
Subject: [PATCH 08/30] pci: support layerscape
Date: Thu, 5 Jul 2018 16:26:47 +0800
Subject: [PATCH 08/32] pci: support layerscape
This is an integrated patch for layerscape pcie support.
@ -15,19 +15,19 @@ Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
drivers/irqchip/irq-ls-scfg-msi.c | 257 +++++++--
drivers/irqchip/irq-ls-scfg-msi.c | 257 ++++++-
drivers/pci/host/Makefile | 2 +-
drivers/pci/host/pci-layerscape-ep-debugfs.c | 758 +++++++++++++++++++++++++++
drivers/pci/host/pci-layerscape-ep.c | 309 +++++++++++
drivers/pci/host/pci-layerscape-ep.h | 115 ++++
drivers/pci/host/pci-layerscape-ep-debugfs.c | 758 +++++++++++++++++++
drivers/pci/host/pci-layerscape-ep.c | 309 ++++++++
drivers/pci/host/pci-layerscape-ep.h | 115 +++
drivers/pci/host/pci-layerscape.c | 48 +-
drivers/pci/host/pcie-designware.c | 6 +
drivers/pci/host/pcie-designware.h | 1 +
drivers/pci/pci.c | 2 +-
drivers/pci/pcie/portdrv_core.c | 181 +++----
drivers/pci/quirks.c | 8 +
drivers/pci/pcie/portdrv_core.c | 181 ++---
drivers/pci/quirks.c | 15 +
include/linux/pci.h | 1 +
12 files changed, 1539 insertions(+), 149 deletions(-)
12 files changed, 1546 insertions(+), 149 deletions(-)
create mode 100644 drivers/pci/host/pci-layerscape-ep-debugfs.c
create mode 100644 drivers/pci/host/pci-layerscape-ep.c
create mode 100644 drivers/pci/host/pci-layerscape-ep.h
@ -2060,7 +2060,21 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
}
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -4679,3 +4679,11 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IN
@@ -3329,6 +3329,13 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_A
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
+/*
+ * NXP (Freescale Vendor ID) LS1088 chips do not behave correctly after
+ * bus reset. Link state of device does not comes UP and so config space
+ * never accessible again.
+ */
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x80c0, quirk_no_bus_reset);
+
static void quirk_no_pm_reset(struct pci_dev *dev)
{
/*
@@ -4679,3 +4686,11 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IN
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2031, quirk_no_aersid);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2032, quirk_no_aersid);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2033, quirk_no_aersid);

18730
target/linux/layerscape/patches-4.9/704-fsl-mc-layerscape-support.patch
View File

File diff suppressed because it is too large Load Diff

10747
target/linux/layerscape/patches-4.9/705-dpaa2-support-layerscape.patch
View File

File diff suppressed because it is too large Load Diff

136
target/linux/layerscape/patches-4.9/706-fsl_ppfe-support-layercape.patch
View File

@ -1,48 +1,48 @@
From 79fb41b6040d00d3bdfca9eb70a7848441eb7447 Mon Sep 17 00:00:00 2001
From 50fb2f2e93aeae0baed156eb4794a2f358376b77 Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Wed, 17 Jan 2018 15:14:12 +0800
Subject: [PATCH] fsl_ppfe: support layercape
Date: Thu, 5 Jul 2018 17:19:20 +0800
Subject: [PATCH 12/32] fsl_ppfe: support layercape
This is an integrated patch for layerscape pfe support.
Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
drivers/staging/fsl_ppfe/Kconfig | 20 +
drivers/staging/fsl_ppfe/Makefile | 19 +
drivers/staging/fsl_ppfe/TODO | 2 +
drivers/staging/fsl_ppfe/include/pfe/cbus.h | 78 +
drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h | 55 +
.../staging/fsl_ppfe/include/pfe/cbus/class_csr.h | 289 +++
.../staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h | 242 ++
drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h | 86 +
drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h | 100 +
.../staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h | 50 +
.../staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h | 168 ++
.../staging/fsl_ppfe/include/pfe/cbus/util_csr.h | 61 +
drivers/staging/fsl_ppfe/include/pfe/pfe.h | 372 +++
drivers/staging/fsl_ppfe/pfe_ctrl.c | 238 ++
drivers/staging/fsl_ppfe/pfe_ctrl.h | 112 +
drivers/staging/fsl_ppfe/pfe_debugfs.c | 111 +
drivers/staging/fsl_ppfe/pfe_debugfs.h | 25 +
drivers/staging/fsl_ppfe/pfe_eth.c | 2474 ++++++++++++++++++++
drivers/staging/fsl_ppfe/pfe_eth.h | 184 ++
drivers/staging/fsl_ppfe/pfe_firmware.c | 314 +++
drivers/staging/fsl_ppfe/pfe_firmware.h | 32 +
drivers/staging/fsl_ppfe/pfe_hal.c | 1516 ++++++++++++
drivers/staging/fsl_ppfe/pfe_hif.c | 1072 +++++++++
drivers/staging/fsl_ppfe/pfe_hif.h | 211 ++
drivers/staging/fsl_ppfe/pfe_hif_lib.c | 637 +++++
drivers/staging/fsl_ppfe/pfe_hif_lib.h | 240 ++
drivers/staging/fsl_ppfe/pfe_hw.c | 176 ++
drivers/staging/fsl_ppfe/pfe_hw.h | 27 +
drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c | 385 +++
drivers/staging/fsl_ppfe/pfe_mod.c | 141 ++
drivers/staging/fsl_ppfe/pfe_mod.h | 112 +
drivers/staging/fsl_ppfe/pfe_perfmon.h | 38 +
drivers/staging/fsl_ppfe/pfe_sysfs.c | 818 +++++++
drivers/staging/fsl_ppfe/pfe_sysfs.h | 29 +
34 files changed, 10434 insertions(+)
drivers/staging/fsl_ppfe/Kconfig | 20 +
drivers/staging/fsl_ppfe/Makefile | 19 +
drivers/staging/fsl_ppfe/TODO | 2 +
drivers/staging/fsl_ppfe/include/pfe/cbus.h | 78 +
.../staging/fsl_ppfe/include/pfe/cbus/bmu.h | 55 +
.../fsl_ppfe/include/pfe/cbus/class_csr.h | 289 ++
.../fsl_ppfe/include/pfe/cbus/emac_mtip.h | 242 ++
.../staging/fsl_ppfe/include/pfe/cbus/gpi.h | 86 +
.../staging/fsl_ppfe/include/pfe/cbus/hif.h | 100 +
.../fsl_ppfe/include/pfe/cbus/hif_nocpy.h | 50 +
.../fsl_ppfe/include/pfe/cbus/tmu_csr.h | 168 ++
.../fsl_ppfe/include/pfe/cbus/util_csr.h | 61 +
drivers/staging/fsl_ppfe/include/pfe/pfe.h | 372 +++
drivers/staging/fsl_ppfe/pfe_ctrl.c | 238 ++
drivers/staging/fsl_ppfe/pfe_ctrl.h | 112 +
drivers/staging/fsl_ppfe/pfe_debugfs.c | 111 +
drivers/staging/fsl_ppfe/pfe_debugfs.h | 25 +
drivers/staging/fsl_ppfe/pfe_eth.c | 2491 +++++++++++++++++
drivers/staging/fsl_ppfe/pfe_eth.h | 184 ++
drivers/staging/fsl_ppfe/pfe_firmware.c | 314 +++
drivers/staging/fsl_ppfe/pfe_firmware.h | 32 +
drivers/staging/fsl_ppfe/pfe_hal.c | 1516 ++++++++++
drivers/staging/fsl_ppfe/pfe_hif.c | 1072 +++++++
drivers/staging/fsl_ppfe/pfe_hif.h | 211 ++
drivers/staging/fsl_ppfe/pfe_hif_lib.c | 640 +++++
drivers/staging/fsl_ppfe/pfe_hif_lib.h | 241 ++
drivers/staging/fsl_ppfe/pfe_hw.c | 176 ++
drivers/staging/fsl_ppfe/pfe_hw.h | 27 +
.../staging/fsl_ppfe/pfe_ls1012a_platform.c | 385 +++
drivers/staging/fsl_ppfe/pfe_mod.c | 156 ++
drivers/staging/fsl_ppfe/pfe_mod.h | 114 +
drivers/staging/fsl_ppfe/pfe_perfmon.h | 38 +
drivers/staging/fsl_ppfe/pfe_sysfs.c | 818 ++++++
drivers/staging/fsl_ppfe/pfe_sysfs.h | 29 +
34 files changed, 10472 insertions(+)
create mode 100644 drivers/staging/fsl_ppfe/Kconfig
create mode 100644 drivers/staging/fsl_ppfe/Makefile
create mode 100644 drivers/staging/fsl_ppfe/TODO
@ -2159,7 +2159,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+#endif /* _PFE_DEBUGFS_H_ */
--- /dev/null
+++ b/drivers/staging/fsl_ppfe/pfe_eth.c
@@ -0,0 +1,2474 @@
@@ -0,0 +1,2491 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
@ -4457,6 +4457,8 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ goto err0;
+ }
+
+ if (us)
+ emac_txq_cnt = EMAC_TXQ_CNT;
+ /* Create an ethernet device instance */
+ ndev = alloc_etherdev_mq(sizeof(*priv), emac_txq_cnt);
+
@ -4503,6 +4505,9 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ }
+ }
+
+ if (us)
+ goto phy_init;
+
+ ndev->mtu = 1500;
+
+ /* Set MTU limits */
@ -4542,6 +4547,8 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ netdev_err(ndev, "register_netdev() failed\n");
+ goto err3;
+ }
+
+phy_init:
+ device_init_wakeup(&ndev->dev, WAKE_MAGIC);
+
+ if (!(priv->einfo->phy_flags & GEMAC_NO_PHY)) {
@ -4553,6 +4560,12 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ }
+ }
+
+ if (us) {
+ if (priv->phydev)
+ phy_start(priv->phydev);
+ return 0;
+ }
+
+ netif_carrier_on(ndev);
+
+ /* Create all the sysfs files */
@ -4564,6 +4577,8 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+
+ return 0;
+err4:
+ if (us)
+ goto err3;
+ unregister_netdev(ndev);
+err3:
+ pfe_eth_mdio_exit(priv->mii_bus);
@ -4610,13 +4625,15 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+{
+ netif_info(priv, probe, priv->ndev, "%s\n", __func__);
+
+ pfe_eth_sysfs_exit(priv->ndev);
+
+ unregister_netdev(priv->ndev);
+ if (!us)
+ pfe_eth_sysfs_exit(priv->ndev);
+
+ if (!(priv->einfo->phy_flags & GEMAC_NO_PHY))
+ pfe_phy_exit(priv->ndev);
+
+ if (!us)
+ unregister_netdev(priv->ndev);
+
+ if (priv->mii_bus)
+ pfe_eth_mdio_exit(priv->mii_bus);
+
@ -7983,7 +8000,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+#endif /* _PFE_HIF_H_ */
--- /dev/null
+++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.c
@@ -0,0 +1,637 @@
@@ -0,0 +1,640 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
@ -8421,6 +8438,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ u16 size = *rx_ctrl >> HIF_CTRL_RX_OFFSET_OFST;
+
+ if (size) {
+ size += PFE_PARSE_INFO_SIZE;
+ *len = CL_DESC_BUF_LEN(desc->ctrl) -
+ PFE_PKT_HEADER_SZ - size;
+ *ofst = pfe_pkt_headroom + PFE_PKT_HEADER_SZ
@ -8428,8 +8446,10 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ *priv_data = desc->data + PFE_PKT_HEADER_SZ;
+ } else {
+ *len = CL_DESC_BUF_LEN(desc->ctrl) -
+ PFE_PKT_HEADER_SZ;
+ *ofst = pfe_pkt_headroom + PFE_PKT_HEADER_SZ;
+ PFE_PKT_HEADER_SZ - PFE_PARSE_INFO_SIZE;
+ *ofst = pfe_pkt_headroom
+ + PFE_PKT_HEADER_SZ
+ + PFE_PARSE_INFO_SIZE;
+ *priv_data = NULL;
+ }
+
@ -8623,7 +8643,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+}
--- /dev/null
+++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.h
@@ -0,0 +1,240 @@
@@ -0,0 +1,241 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
@ -8649,6 +8669,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+
+#define HIF_CL_REQ_TIMEOUT 10
+#define GFP_DMA_PFE 0
+#define PFE_PARSE_INFO_SIZE 16
+
+enum {
+ REQUEST_CL_REGISTER = 0,
@ -8772,7 +8793,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+#define PFE_BUF_SIZE 2048
+#define PFE_PKT_HEADROOM 128
+
+#define SKB_SHARED_INFO_SIZE (sizeof(struct skb_shared_info))
+#define SKB_SHARED_INFO_SIZE SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
+#define PFE_PKT_SIZE (PFE_BUF_SIZE - PFE_PKT_HEADROOM \
+ - SKB_SHARED_INFO_SIZE)
+#define MAX_L2_HDR_SIZE 14 /* Not correct for VLAN/PPPoE */
@ -9463,7 +9484,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+MODULE_AUTHOR("NXP DNCPE");
--- /dev/null
+++ b/drivers/staging/fsl_ppfe/pfe_mod.c
@@ -0,0 +1,141 @@
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
@ -9485,6 +9506,10 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+#include <linux/dma-mapping.h>
+#include "pfe_mod.h"
+
+unsigned int us;
+module_param(us, uint, 0444);
+MODULE_PARM_DESC(us, "0: module enabled for kernel networking (DEFAULT)\n"
+ "1: module enabled for userspace networking\n");
+struct pfe *pfe;
+
+/*
@ -9522,6 +9547,9 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ if (rc < 0)
+ goto err_hw;
+
+ if (us)
+ goto firmware_init;
+
+ rc = pfe_hif_lib_init(pfe);
+ if (rc < 0)
+ goto err_hif_lib;
@ -9530,6 +9558,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ if (rc < 0)
+ goto err_hif;
+
+firmware_init:
+ rc = pfe_firmware_init(pfe);
+ if (rc < 0)
+ goto err_firmware;
@ -9565,6 +9594,9 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ pfe_firmware_exit(pfe);
+
+err_firmware:
+ if (us)
+ goto err_hif_lib;
+
+ pfe_hif_exit(pfe);
+
+err_hif:
@ -9597,17 +9629,21 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+#endif
+ pfe_firmware_exit(pfe);
+
+ if (us)
+ goto hw_exit;
+
+ pfe_hif_exit(pfe);
+
+ pfe_hif_lib_exit(pfe);
+
+hw_exit:
+ pfe_hw_exit(pfe);
+
+ return 0;
+}
--- /dev/null
+++ b/drivers/staging/fsl_ppfe/pfe_mod.h
@@ -0,0 +1,112 @@
@@ -0,0 +1,114 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
@ -9632,6 +9668,8 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+#include <linux/device.h>
+#include <linux/elf.h>
+
+extern unsigned int us;
+
+struct pfe;
+
+#include "pfe_hw.h"

522
target/linux/layerscape/patches-4.9/803-cpufreq-support-layerscape.patch
View File

@ -1,20 +1,111 @@
From b018e44a68dc2f4df819ae194e39e07313841dad Mon Sep 17 00:00:00 2001
From d78d78ccbaded757e8bea0d13c4120518bdd4660 Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Wed, 17 Jan 2018 15:27:58 +0800
Subject: [PATCH 15/30] cpufreq: support layerscape
Date: Thu, 5 Jul 2018 17:21:38 +0800
Subject: [PATCH 15/32] cpufreq: support layerscape
This is an integrated patch for layerscape pm support.
Signed-off-by: Tang Yuantian <Yuantian.Tang@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
drivers/cpufreq/Kconfig | 2 +-
drivers/cpufreq/qoriq-cpufreq.c | 176 +++++++++++++++-------------------------
drivers/firmware/psci.c | 12 ++-
drivers/soc/fsl/rcpm.c | 158 ++++++++++++++++++++++++++++++++++++
4 files changed, 235 insertions(+), 113 deletions(-)
.../devicetree/bindings/powerpc/fsl/pmc.txt | 59 ++--
drivers/cpufreq/Kconfig | 2 +-
drivers/cpufreq/qoriq-cpufreq.c | 176 +++++------
drivers/firmware/psci.c | 12 +-
drivers/soc/fsl/rcpm.c | 158 ++++++++++
drivers/soc/fsl/sleep_fsm.c | 279 ++++++++++++++++++
drivers/soc/fsl/sleep_fsm.h | 130 ++++++++
7 files changed, 678 insertions(+), 138 deletions(-)
create mode 100644 drivers/soc/fsl/rcpm.c
create mode 100644 drivers/soc/fsl/sleep_fsm.c
create mode 100644 drivers/soc/fsl/sleep_fsm.h
--- a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
@@ -9,15 +9,20 @@ Properties:
"fsl,mpc8548-pmc" should be listed for any chip whose PMC is
compatible. "fsl,mpc8536-pmc" should also be listed for any chip
- whose PMC is compatible, and implies deep-sleep capability.
+ whose PMC is compatible, and implies deep-sleep capability and
+ wake on user defined packet(wakeup on ARP).
+
+ "fsl,p1022-pmc" should be listed for any chip whose PMC is
+ compatible, and implies lossless Ethernet capability during sleep.
"fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
compatible; all statements below that apply to "fsl,mpc8548-pmc" also
apply to "fsl,mpc8641d-pmc".
Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these
- bit assignments are indicated via the sleep specifier in each device's
- sleep property.
+ bit assignments are indicated via the clock nodes. Device which has a
+ controllable clock source should have a "fsl,pmc-handle" property pointing
+ to the clock node.
- reg: For devices compatible with "fsl,mpc8349-pmc", the first resource
is the PMC block, and the second resource is the Clock Configuration
@@ -33,31 +38,35 @@ Properties:
this is a phandle to an "fsl,gtm" node on which timer 4 can be used as
a wakeup source from deep sleep.
-Sleep specifiers:
-
- fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit
- that is set in the cell, the corresponding bit in SCCR will be saved
- and cleared on suspend, and restored on resume. This sleep controller
- supports disabling and resuming devices at any time.
-
- fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of
- which will be ORed into PMCDR upon suspend, and cleared from PMCDR
- upon resume. The first two cells are as described for fsl,mpc8578-pmc.
- This sleep controller only supports disabling devices during system
- sleep, or permanently.
-
- fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the
- first of which will be ORed into DEVDISR (and the second into
- DEVDISR2, if present -- this cell should be zero or absent if the
- hardware does not have DEVDISR2) upon a request for permanent device
- disabling. This sleep controller does not support configuring devices
- to disable during system sleep (unless supported by another compatible
- match), or dynamically.
+Clock nodes:
+The clock nodes are to describe the masks in PM controller registers for each
+soc clock.
+- fsl,pmcdr-mask: For "fsl,mpc8548-pmc"-compatible devices, the mask will be
+ ORed into PMCDR before suspend if the device using this clock is the wake-up
+ source and need to be running during low power mode; clear the mask if
+ otherwise.
+
+- fsl,sccr-mask: For "fsl,mpc8349-pmc"-compatible devices, the corresponding
+ bit specified by the mask in SCCR will be saved and cleared on suspend, and
+ restored on resume.
+
+- fsl,devdisr-mask: Contain one or two cells, depending on the availability of
+ DEVDISR2 register. For compatible devices, the mask will be ORed into DEVDISR
+ or DEVDISR2 when the clock should be permenently disabled.
Example:
- power@b00 {
- compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
- reg = <0xb00 0x100 0xa00 0x100>;
- interrupts = <80 8>;
+ power@e0070 {
+ compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
+ reg = <0xe0070 0x20>;
+
+ etsec1_clk: soc-clk@24 {
+ fsl,pmcdr-mask = <0x00000080>;
+ };
+ etsec2_clk: soc-clk@25 {
+ fsl,pmcdr-mask = <0x00000040>;
+ };
+ etsec3_clk: soc-clk@26 {
+ fsl,pmcdr-mask = <0x00000020>;
+ };
};
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -334,7 +334,7 @@ endif
@ -522,3 +613,418 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+}
+
+subsys_initcall(layerscape_rcpm_init);
--- /dev/null
+++ b/drivers/soc/fsl/sleep_fsm.c
@@ -0,0 +1,279 @@
+/*
+ * deep sleep FSM (finite-state machine) configuration
+ *
+ * Copyright 2018 NXP
+ *
+ * Author: Hongbo Zhang <hongbo.zhang@freescale.com>
+ * Chenhui Zhao <chenhui.zhao@freescale.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/types.h>
+
+#include "sleep_fsm.h"
+/*
+ * These values are from chip's reference manual. For example,
+ * the values for T1040 can be found in "8.4.3.8 Programming
+ * supporting deep sleep mode" of Chapter 8 "Run Control and
+ * Power Management (RCPM)".
+ * The default value can be applied to T104x, LS1021.
+ */
+struct fsm_reg_vals epu_default_val[] = {
+ /* EPGCR (Event Processor Global Control Register) */
+ {EPGCR, 0},
+ /* EPECR (Event Processor Event Control Registers) */
+ {EPECR0 + EPECR_STRIDE * 0, 0},
+ {EPECR0 + EPECR_STRIDE * 1, 0},
+ {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
+ {EPECR0 + EPECR_STRIDE * 3, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 4, 0x20000084},
+ {EPECR0 + EPECR_STRIDE * 5, 0x08000004},
+ {EPECR0 + EPECR_STRIDE * 6, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 7, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 8, 0x60000084},
+ {EPECR0 + EPECR_STRIDE * 9, 0x08000084},
+ {EPECR0 + EPECR_STRIDE * 10, 0x42000084},
+ {EPECR0 + EPECR_STRIDE * 11, 0x90000084},
+ {EPECR0 + EPECR_STRIDE * 12, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 13, 0x08000084},
+ {EPECR0 + EPECR_STRIDE * 14, 0x02000084},
+ {EPECR0 + EPECR_STRIDE * 15, 0x00000004},
+ /*
+ * EPEVTCR (Event Processor EVT Pin Control Registers)
+ * SCU8 triger EVT2, and SCU11 triger EVT9
+ */
+ {EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
+ /* EPCMPR (Event Processor Counter Compare Registers) */
+ {EPCMPR0 + EPCMPR_STRIDE * 0, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 1, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 3, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
+ {EPCMPR0 + EPCMPR_STRIDE * 6, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 7, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 13, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
+ /* EPCCR (Event Processor Counter Control Registers) */
+ {EPCCR0 + EPCCR_STRIDE * 0, 0},
+ {EPCCR0 + EPCCR_STRIDE * 1, 0},
+ {EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 3, 0},
+ {EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 6, 0},
+ {EPCCR0 + EPCCR_STRIDE * 7, 0},
+ {EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 13, 0},
+ {EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
+ /* EPSMCR (Event Processor SCU Mux Control Registers) */
+ {EPSMCR0 + EPSMCR_STRIDE * 0, 0},
+ {EPSMCR0 + EPSMCR_STRIDE * 1, 0},
+ {EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
+ {EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
+ {EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
+ {EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
+ {EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
+ {EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
+ {EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
+ {EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
+ {EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
+ {EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
+ /* EPACR (Event Processor Action Control Registers) */
+ {EPACR0 + EPACR_STRIDE * 0, 0},
+ {EPACR0 + EPACR_STRIDE * 1, 0},
+ {EPACR0 + EPACR_STRIDE * 2, 0},
+ {EPACR0 + EPACR_STRIDE * 3, 0x00000080},
+ {EPACR0 + EPACR_STRIDE * 4, 0},
+ {EPACR0 + EPACR_STRIDE * 5, 0x00000040},
+ {EPACR0 + EPACR_STRIDE * 6, 0},
+ {EPACR0 + EPACR_STRIDE * 7, 0},
+ {EPACR0 + EPACR_STRIDE * 8, 0},
+ {EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
+ {EPACR0 + EPACR_STRIDE * 10, 0x00000020},
+ {EPACR0 + EPACR_STRIDE * 11, 0},
+ {EPACR0 + EPACR_STRIDE * 12, 0x00000003},
+ {EPACR0 + EPACR_STRIDE * 13, 0x06000000},
+ {EPACR0 + EPACR_STRIDE * 14, 0x04000000},
+ {EPACR0 + EPACR_STRIDE * 15, 0x02000000},
+ /* EPIMCR (Event Processor Input Mux Control Registers) */
+ {EPIMCR0 + EPIMCR_STRIDE * 0, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 1, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 2, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 3, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 6, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 7, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 8, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 9, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 10, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 11, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 13, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 14, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 15, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 17, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 18, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 19, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 21, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 23, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 24, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 25, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 26, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 27, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 29, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 30, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
+ /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
+ {EPXTRIGCR, 0x0000FFDF},
+ /* end */
+ {FSM_END_FLAG, 0},
+};
+
+struct fsm_reg_vals npc_default_val[] = {
+ /* NPC triggered Memory-Mapped Access Registers */
+ {NCR, 0x80000000},
+ {MCCR1, 0},
+ {MCSR1, 0},
+ {MMAR1LO, 0},
+ {MMAR1HI, 0},
+ {MMDR1, 0},
+ {MCSR2, 0},
+ {MMAR2LO, 0},
+ {MMAR2HI, 0},
+ {MMDR2, 0},
+ {MCSR3, 0x80000000},
+ {MMAR3LO, 0x000E2130},
+ {MMAR3HI, 0x00030000},
+ {MMDR3, 0x00020000},
+ /* end */
+ {FSM_END_FLAG, 0},
+};
+
+/**
+ * fsl_fsm_setup - Configure EPU's FSM registers
+ * @base: the base address of registers
+ * @val: Pointer to address-value pairs for FSM registers
+ */
+void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val)
+{
+ struct fsm_reg_vals *data = val;
+
+ WARN_ON(!base || !data);
+ while (data->offset != FSM_END_FLAG) {
+ iowrite32be(data->value, base + data->offset);
+ data++;
+ }
+}
+
+void fsl_epu_setup_default(void __iomem *epu_base)
+{
+ fsl_fsm_setup(epu_base, epu_default_val);
+}
+
+void fsl_npc_setup_default(void __iomem *npc_base)
+{
+ fsl_fsm_setup(npc_base, npc_default_val);
+}
+
+void fsl_epu_clean_default(void __iomem *epu_base)
+{
+ u32 offset;
+
+ /* follow the exact sequence to clear the registers */
+ /* Clear EPACRn */
+ for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPEVTCRn */
+ for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPGCR */
+ iowrite32be(0, epu_base + EPGCR);
+
+ /* Clear EPSMCRn */
+ for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPCCRn */
+ for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPCMPRn */
+ for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPCTRn */
+ for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPIMCRn */
+ for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+
+ /* Clear EPXTRIGCRn */
+ iowrite32be(0, epu_base + EPXTRIGCR);
+
+ /* Clear EPECRn */
+ for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
+ iowrite32be(0, epu_base + offset);
+}
--- /dev/null
+++ b/drivers/soc/fsl/sleep_fsm.h
@@ -0,0 +1,130 @@
+/*
+ * deep sleep FSM (finite-state machine) configuration
+ *
+ * Copyright 2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_SLEEP_FSM_H
+#define _FSL_SLEEP_FSM_H
+
+#define FSL_STRIDE_4B 4
+#define FSL_STRIDE_8B 8
+
+/* End flag */
+#define FSM_END_FLAG 0xFFFFFFFFUL
+
+/* Block offsets */
+#define RCPM_BLOCK_OFFSET 0x00022000
+#define EPU_BLOCK_OFFSET 0x00000000
+#define NPC_BLOCK_OFFSET 0x00001000
+
+/* EPGCR (Event Processor Global Control Register) */
+#define EPGCR 0x000
+
+/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
+#define EPEVTCR0 0x050
+#define EPEVTCR9 0x074
+#define EPEVTCR_STRIDE FSL_STRIDE_4B
+
+/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
+#define EPXTRIGCR 0x090
+
+/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
+#define EPIMCR0 0x100
+#define EPIMCR31 0x17C
+#define EPIMCR_STRIDE FSL_STRIDE_4B
+
+/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
+#define EPSMCR0 0x200
+#define EPSMCR15 0x278
+#define EPSMCR_STRIDE FSL_STRIDE_8B
+
+/* EPECR0-15 (Event Processor Event Control Registers) */
+#define EPECR0 0x300
+#define EPECR15 0x33C
+#define EPECR_STRIDE FSL_STRIDE_4B
+
+/* EPACR0-15 (Event Processor Action Control Registers) */
+#define EPACR0 0x400
+#define EPACR15 0x43C
+#define EPACR_STRIDE FSL_STRIDE_4B
+
+/* EPCCRi0-15 (Event Processor Counter Control Registers) */
+#define EPCCR0 0x800
+#define EPCCR15 0x83C
+#define EPCCR31 0x87C
+#define EPCCR_STRIDE FSL_STRIDE_4B
+
+/* EPCMPR0-15 (Event Processor Counter Compare Registers) */
+#define EPCMPR0 0x900
+#define EPCMPR15 0x93C
+#define EPCMPR31 0x97C
+#define EPCMPR_STRIDE FSL_STRIDE_4B
+
+/* EPCTR0-31 (Event Processor Counter Register) */
+#define EPCTR0 0xA00
+#define EPCTR31 0xA7C
+#define EPCTR_STRIDE FSL_STRIDE_4B
+
+/* NPC triggered Memory-Mapped Access Registers */
+#define NCR 0x000
+#define MCCR1 0x0CC
+#define MCSR1 0x0D0
+#define MMAR1LO 0x0D4
+#define MMAR1HI 0x0D8
+#define MMDR1 0x0DC
+#define MCSR2 0x0E0
+#define MMAR2LO 0x0E4
+#define MMAR2HI 0x0E8
+#define MMDR2 0x0EC
+#define MCSR3 0x0F0
+#define MMAR3LO 0x0F4
+#define MMAR3HI 0x0F8
+#define MMDR3 0x0FC
+
+/* RCPM Core State Action Control Register 0 */
+#define CSTTACR0 0xB00
+
+/* RCPM Core Group 1 Configuration Register 0 */
+#define CG1CR0 0x31C
+
+struct fsm_reg_vals {
+ u32 offset;
+ u32 value;
+};
+
+void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val);
+void fsl_epu_setup_default(void __iomem *epu_base);
+void fsl_npc_setup_default(void __iomem *npc_base);
+void fsl_epu_clean_default(void __iomem *epu_base);
+
+#endif /* _FSL_SLEEP_FSM_H */

1247
target/linux/layerscape/patches-4.9/804-crypto-support-layerscape.patch
View File

File diff suppressed because it is too large Load Diff

320
target/linux/layerscape/patches-4.9/805-dma-support-layerscape.patch
View File

@ -1,7 +1,7 @@
From 515d590e3d5313110faa4f2c86f7784d9b070fa9 Mon Sep 17 00:00:00 2001
From d3d537ebe9884e7d945ab74bb02312d0c2c9b08d Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Wed, 17 Jan 2018 15:30:59 +0800
Subject: [PATCH 17/30] dma: support layerscape
Date: Thu, 5 Jul 2018 17:32:53 +0800
Subject: [PATCH 17/32] dma: support layerscape
This is an integrated patch for layerscape dma support.
@ -10,16 +10,16 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
drivers/dma/Kconfig | 31 +
drivers/dma/Makefile | 3 +
drivers/dma/caam_dma.c | 563 ++++++++++++++
drivers/dma/caam_dma.c | 563 ++++++++++
drivers/dma/dpaa2-qdma/Kconfig | 8 +
drivers/dma/dpaa2-qdma/Makefile | 8 +
drivers/dma/dpaa2-qdma/dpaa2-qdma.c | 986 ++++++++++++++++++++++++
drivers/dma/dpaa2-qdma/dpaa2-qdma.h | 262 +++++++
drivers/dma/dpaa2-qdma/dpdmai.c | 454 +++++++++++
drivers/dma/dpaa2-qdma/fsl_dpdmai.h | 521 +++++++++++++
drivers/dma/dpaa2-qdma/fsl_dpdmai_cmd.h | 222 ++++++
drivers/dma/fsl-qdma.c | 1243 +++++++++++++++++++++++++++++++
11 files changed, 4301 insertions(+)
drivers/dma/dpaa2-qdma/dpaa2-qdma.c | 940 +++++++++++++++++
drivers/dma/dpaa2-qdma/dpaa2-qdma.h | 227 +++++
drivers/dma/dpaa2-qdma/dpdmai.c | 515 ++++++++++
drivers/dma/dpaa2-qdma/fsl_dpdmai.h | 521 ++++++++++
drivers/dma/dpaa2-qdma/fsl_dpdmai_cmd.h | 222 ++++
drivers/dma/fsl-qdma.c | 1243 +++++++++++++++++++++++
11 files changed, 4281 insertions(+)
create mode 100644 drivers/dma/caam_dma.c
create mode 100644 drivers/dma/dpaa2-qdma/Kconfig
create mode 100644 drivers/dma/dpaa2-qdma/Makefile
@ -686,7 +686,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+fsl-dpaa2-qdma-objs := dpaa2-qdma.o dpdmai.o
--- /dev/null
+++ b/drivers/dma/dpaa2-qdma/dpaa2-qdma.c
@@ -0,0 +1,986 @@
@@ -0,0 +1,940 @@
+/*
+ * drivers/dma/dpaa2-qdma/dpaa2-qdma.c
+ *
@ -723,7 +723,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+
+#include "../virt-dma.h"
+
+#include "../../../drivers/staging/fsl-mc/include/mc.h"
+#include <linux/fsl/mc.h>
+#include "../../../drivers/staging/fsl-mc/include/dpaa2-io.h"
+#include "../../../drivers/staging/fsl-mc/include/dpaa2-fd.h"
+#include "fsl_dpdmai_cmd.h"
@ -786,10 +786,10 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ comp_temp->fl_bus_addr = comp_temp->fd_bus_addr +
+ sizeof(struct dpaa2_fd);
+ comp_temp->desc_virt_addr =
+ (void *)((struct dpaa2_frame_list *)
+ (void *)((struct dpaa2_fl_entry *)
+ comp_temp->fl_virt_addr + 3);
+ comp_temp->desc_bus_addr = comp_temp->fl_bus_addr +
+ sizeof(struct dpaa2_frame_list) * 3;
+ sizeof(struct dpaa2_fl_entry) * 3;
+
+ comp_temp->qchan = dpaa2_chan;
+ comp_temp->sg_blk_num = 0;
@ -816,19 +816,19 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ memset(fd, 0, sizeof(struct dpaa2_fd));
+
+ /* fd populated */
+ fd->simple.addr = dpaa2_comp->fl_bus_addr;
+ dpaa2_fd_set_addr(fd, dpaa2_comp->fl_bus_addr);
+ /* Bypass memory translation, Frame list format, short length disable */
+ /* we need to disable BMT if fsl-mc use iova addr */
+ if (smmu_disable)
+ fd->simple.bpid = QMAN_FD_BMT_ENABLE;
+ fd->simple.format_offset = QMAN_FD_FMT_ENABLE | QMAN_FD_SL_DISABLE;
+ dpaa2_fd_set_bpid(fd, QMAN_FD_BMT_ENABLE);
+ dpaa2_fd_set_format(fd, QMAN_FD_FMT_ENABLE | QMAN_FD_SL_DISABLE);
+
+ fd->simple.frc = format | QDMA_SER_CTX;
+ dpaa2_fd_set_frc(fd, format | QDMA_SER_CTX);
+}
+
+/* first frame list for descriptor buffer */
+static void dpaa2_qdma_populate_first_framel(
+ struct dpaa2_frame_list *f_list,
+ struct dpaa2_fl_entry *f_list,
+ struct dpaa2_qdma_comp *dpaa2_comp)
+{
+ struct dpaa2_qdma_sd_d *sdd;
@ -836,48 +836,45 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ sdd = (struct dpaa2_qdma_sd_d *)dpaa2_comp->desc_virt_addr;
+ memset(sdd, 0, 2 * (sizeof(*sdd)));
+ /* source and destination descriptor */
+ sdd->cmd = QDMA_SD_CMD_RDTTYPE_COHERENT; /* source descriptor CMD */
+ sdd->cmd = cpu_to_le32(QDMA_SD_CMD_RDTTYPE_COHERENT); /* source descriptor CMD */
+ sdd++;
+ sdd->cmd = QDMA_DD_CMD_WRTTYPE_COHERENT; /* dest descriptor CMD */
+ sdd->cmd = cpu_to_le32(QDMA_DD_CMD_WRTTYPE_COHERENT); /* dest descriptor CMD */
+
+ memset(f_list, 0, sizeof(struct dpaa2_frame_list));
+ memset(f_list, 0, sizeof(struct dpaa2_fl_entry));
+ /* first frame list to source descriptor */
+ f_list->addr_lo = dpaa2_comp->desc_bus_addr;
+ f_list->addr_hi = (dpaa2_comp->desc_bus_addr >> 32);
+ f_list->data_len.data_len_sl0 = 0x20; /* source/destination desc len */
+ f_list->fmt = QDMA_FL_FMT_SBF; /* single buffer frame */
+
+ dpaa2_fl_set_addr(f_list, dpaa2_comp->desc_bus_addr);
+ dpaa2_fl_set_len(f_list, 0x20);
+ dpaa2_fl_set_format(f_list, QDMA_FL_FMT_SBF | QDMA_FL_SL_LONG);
+
+ if (smmu_disable)
+ f_list->bmt = QDMA_FL_BMT_ENABLE; /* bypass memory translation */
+ f_list->sl = QDMA_FL_SL_LONG; /* long length */
+ f_list->f = 0; /* not the last frame list */
+ f_list->bpid = cpu_to_le16(QDMA_FL_BMT_ENABLE); /* bypass memory translation */
+}
+
+/* source and destination frame list */
+static void dpaa2_qdma_populate_frames(struct dpaa2_frame_list *f_list,
+static void dpaa2_qdma_populate_frames(struct dpaa2_fl_entry *f_list,
+ dma_addr_t dst, dma_addr_t src, size_t len, uint8_t fmt)
+{
+ /* source frame list to source buffer */
+ memset(f_list, 0, sizeof(struct dpaa2_frame_list));
+ f_list->addr_lo = src;
+ f_list->addr_hi = (src >> 32);
+ f_list->data_len.data_len_sl0 = len;
+ f_list->fmt = fmt; /* single buffer frame or scatter gather frame */
+ memset(f_list, 0, sizeof(struct dpaa2_fl_entry));
+
+
+ dpaa2_fl_set_addr(f_list, src);
+ dpaa2_fl_set_len(f_list, len);
+ dpaa2_fl_set_format(f_list, (fmt | QDMA_FL_SL_LONG)); /* single buffer frame or scatter gather frame */
+ if (smmu_disable)
+ f_list->bmt = QDMA_FL_BMT_ENABLE; /* bypass memory translation */
+ f_list->sl = QDMA_FL_SL_LONG; /* long length */
+ f_list->f = 0; /* not the last frame list */
+ f_list->bpid = cpu_to_le16(QDMA_FL_BMT_ENABLE); /* bypass memory translation */
+
+ f_list++;
+ /* destination frame list to destination buffer */
+ memset(f_list, 0, sizeof(struct dpaa2_frame_list));
+ f_list->addr_lo = dst;
+ f_list->addr_hi = (dst >> 32);
+ f_list->data_len.data_len_sl0 = len;
+ f_list->fmt = fmt; /* single buffer frame or scatter gather frame */
+ memset(f_list, 0, sizeof(struct dpaa2_fl_entry));
+
+ dpaa2_fl_set_addr(f_list, dst);
+ dpaa2_fl_set_len(f_list, len);
+ dpaa2_fl_set_format(f_list, (fmt | QDMA_FL_SL_LONG));
+ dpaa2_fl_set_final(f_list, QDMA_FL_F); /* single buffer frame or scatter gather frame */
+ if (smmu_disable)
+ f_list->bmt = QDMA_FL_BMT_ENABLE; /* bypass memory translation */
+ f_list->sl = QDMA_FL_SL_LONG; /* long length */
+ f_list->f = QDMA_FL_F; /* Final bit: 1, for last frame list */
+ f_list->bpid = cpu_to_le16(QDMA_FL_BMT_ENABLE); /* bypass memory translation */
+}
+
+static struct dma_async_tx_descriptor *dpaa2_qdma_prep_memcpy(
@ -886,7 +883,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+{
+ struct dpaa2_qdma_chan *dpaa2_chan = to_dpaa2_qdma_chan(chan);
+ struct dpaa2_qdma_comp *dpaa2_comp;
+ struct dpaa2_frame_list *f_list;
+ struct dpaa2_fl_entry *f_list;
+ uint32_t format;
+
+ dpaa2_comp = dpaa2_qdma_request_desc(dpaa2_chan);
@ -899,7 +896,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ /* populate Frame descriptor */
+ dpaa2_qdma_populate_fd(format, dpaa2_comp);
+
+ f_list = (struct dpaa2_frame_list *)dpaa2_comp->fl_virt_addr;
+ f_list = (struct dpaa2_fl_entry *)dpaa2_comp->fl_virt_addr;
+
+#ifdef LONG_FORMAT
+ /* first frame list for descriptor buffer (logn format) */
@ -1062,48 +1059,6 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ return total_len;
+}
+
+static struct dma_async_tx_descriptor *dpaa2_qdma_prep_sg(
+ struct dma_chan *chan,
+ struct scatterlist *dst_sg, u32 dst_nents,
+ struct scatterlist *src_sg, u32 src_nents,
+ unsigned long flags)
+{
+ struct dpaa2_qdma_chan *dpaa2_chan = to_dpaa2_qdma_chan(chan);
+ struct dpaa2_qdma_comp *dpaa2_comp;
+ struct dpaa2_frame_list *f_list;
+ struct device *dev = dpaa2_chan->qdma->priv->dev;
+ uint32_t total_len = 0;
+
+ /* basic sanity checks */
+ if (dst_nents == 0 || src_nents == 0)
+ return NULL;
+
+ if (dst_sg == NULL || src_sg == NULL)
+ return NULL;
+
+ /* get the descriptors required */
+ dpaa2_comp = dpaa2_qdma_request_desc(dpaa2_chan);
+
+ /* populate Frame descriptor */
+ dpaa2_qdma_populate_fd(QDMA_FD_LONG_FORMAT, dpaa2_comp);
+
+ /* prepare Scatter gather entry for source and destination */
+ total_len = dpaa2_qdma_populate_sg(dev, dpaa2_chan,
+ dpaa2_comp, dst_sg, dst_nents, src_sg, src_nents);
+
+ f_list = (struct dpaa2_frame_list *)dpaa2_comp->fl_virt_addr;
+ /* first frame list for descriptor buffer */
+ dpaa2_qdma_populate_first_framel(f_list, dpaa2_comp);
+ f_list++;
+ /* prepare Scatter gather entry for source and destination */
+ /* populate source and destination frame list table */
+ dpaa2_qdma_populate_frames(f_list, dpaa2_comp->sge_dst_bus_addr,
+ dpaa2_comp->sge_src_bus_addr,
+ total_len, QDMA_FL_FMT_SGE);
+
+ return vchan_tx_prep(&dpaa2_chan->vchan, &dpaa2_comp->vdesc, flags);
+}
+
+static enum dma_status dpaa2_qdma_tx_status(struct dma_chan *chan,
+ dma_cookie_t cookie, struct dma_tx_state *txstate)
+{
@ -1263,7 +1218,8 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+
+ /* obtain FD and process the error */
+ fd = dpaa2_dq_fd(dq);
+ status = fd->simple.ctrl & 0xff;
+
+ status = dpaa2_fd_get_ctrl(fd) & 0xff;
+ if (status)
+ dev_err(priv->dev, "FD error occurred\n");
+ found = 0;
@ -1279,8 +1235,8 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ fd_eq = (struct dpaa2_fd *)
+ dpaa2_comp->fd_virt_addr;
+
+ if (fd_eq->simple.addr ==
+ fd->simple.addr) {
+ if (le64_to_cpu(fd_eq->simple.addr) ==
+ le64_to_cpu(fd->simple.addr)) {
+
+ list_del(&dpaa2_comp->list);
+ list_add_tail(&dpaa2_comp->list,
@ -1574,7 +1530,6 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ dma_cap_set(DMA_PRIVATE, dpaa2_qdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_SLAVE, dpaa2_qdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_MEMCPY, dpaa2_qdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_SG, dpaa2_qdma->dma_dev.cap_mask);
+
+ dpaa2_qdma->dma_dev.dev = dev;
+ dpaa2_qdma->dma_dev.device_alloc_chan_resources
@ -1583,7 +1538,6 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ = dpaa2_qdma_free_chan_resources;
+ dpaa2_qdma->dma_dev.device_tx_status = dpaa2_qdma_tx_status;
+ dpaa2_qdma->dma_dev.device_prep_dma_memcpy = dpaa2_qdma_prep_memcpy;
+ dpaa2_qdma->dma_dev.device_prep_dma_sg = dpaa2_qdma_prep_sg;
+ dpaa2_qdma->dma_dev.device_issue_pending = dpaa2_qdma_issue_pending;
+
+ err = dma_async_device_register(&dpaa2_qdma->dma_dev);
@ -1675,7 +1629,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+MODULE_LICENSE("Dual BSD/GPL");
--- /dev/null
+++ b/drivers/dma/dpaa2-qdma/dpaa2-qdma.h
@@ -0,0 +1,262 @@
@@ -0,0 +1,227 @@
+/* Copyright 2015 NXP Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
@ -1777,7 +1731,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ } ctrl;
+} __attribute__((__packed__));
+
+#define QMAN_FD_FMT_ENABLE (1 << 12) /* frame list table enable */
+#define QMAN_FD_FMT_ENABLE (1) /* frame list table enable */
+#define QMAN_FD_BMT_ENABLE (1 << 15) /* bypass memory translation */
+#define QMAN_FD_BMT_DISABLE (0 << 15) /* bypass memory translation */
+#define QMAN_FD_SL_DISABLE (0 << 14) /* short lengthe disabled */
@ -1802,49 +1756,14 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+#define QMAN_FD_CBMT_DISABLE (0 << 15) /* Flow Context: 64bit virtual address */
+#define QMAN_FD_SC_DISABLE (0 << 27) /* stashing control */
+
+#define QDMA_FL_FMT_SBF 0x0 /* Single buffer frame */
+#define QDMA_FL_FMT_SBF (0x0) /* Single buffer frame */
+#define QDMA_FL_FMT_SGE 0x2 /* Scatter gather frame */
+#define QDMA_FL_BMT_ENABLE 0x1 /* enable bypass memory translation */
+#define QDMA_FL_BMT_ENABLE (0x1 << 15)/* enable bypass memory translation */
+#define QDMA_FL_BMT_DISABLE 0x0 /* enable bypass memory translation */
+#define QDMA_FL_SL_LONG 0x0 /* long length */
+#define QDMA_FL_SL_LONG (0x0 << 2)/* long length */
+#define QDMA_FL_SL_SHORT 0x1 /* short length */
+#define QDMA_FL_F 0x1 /* last frame list bit */
+#define QDMA_FL_F (0x1)/* last frame list bit */
+/*Description of Frame list table structure*/
+struct dpaa2_frame_list {
+ uint32_t addr_lo; /* lower 32 bits of address */
+ uint32_t addr_hi:17; /* upper 17 bits of address */
+ uint32_t resrvd:15;
+ union {
+ uint32_t data_len_sl0; /* If SL=0, then data length is 32 */
+ struct {
+ uint32_t data_len:18; /* IF SL=1; length is 18bit */
+ uint32_t resrvd:2;
+ uint32_t mem:12; /* Valid only when SL=1 */
+ } data_len_sl1;
+ } data_len;
+ /* word 4 */
+ uint32_t bpid:14; /* Frame buffer pool ID */
+ uint32_t ivp:1; /* Invalid Pool ID. */
+ uint32_t bmt:1; /* Bypass Memory Translation */
+ uint32_t offset:12; /* Frame offset */
+ uint32_t fmt:2; /* Frame Format */
+ uint32_t sl:1; /* Short Length */
+ uint32_t f:1; /* Final bit */
+
+ uint32_t frc; /* Frame Context */
+ /* word 6 */
+ uint32_t err:8; /* Frame errors */
+ uint32_t resrvd0:8;
+ uint32_t asal:4; /* accelerator-specific annotation length */
+ uint32_t resrvd1:1;
+ uint32_t ptv2:1;
+ uint32_t ptv1:1;
+ uint32_t pta:1; /* pass-through annotation */
+ uint32_t resrvd2:8;
+
+ uint32_t flc_lo; /* lower 32 bits fo flow context */
+ uint32_t flc_hi; /* higher 32 bits fo flow context */
+} __attribute__((__packed__));
+
+struct dpaa2_qdma_chan {
+ struct virt_dma_chan vchan;
@ -1931,7 +1850,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+
+/* FD pool size: one FD + 3 Frame list + 2 source/destination descriptor */
+#define FD_POOL_SIZE (sizeof(struct dpaa2_fd) + \
+ sizeof(struct dpaa2_frame_list) * 3 + \
+ sizeof(struct dpaa2_fl_entry) * 3 + \
+ sizeof(struct dpaa2_qdma_sd_d) * 2)
+
+/* qdma_sg_blk + 16 SGs */
@ -1940,7 +1859,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+#endif /* __DPAA2_QDMA_H */
--- /dev/null
+++ b/drivers/dma/dpaa2-qdma/dpdmai.c
@@ -0,0 +1,454 @@
@@ -0,0 +1,515 @@
+/* Copyright 2013-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
@ -1976,22 +1895,56 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+#include <linux/io.h>
+#include "fsl_dpdmai.h"
+#include "fsl_dpdmai_cmd.h"
+#include "../../../drivers/staging/fsl-mc/include/mc-sys.h"
+#include "../../../drivers/staging/fsl-mc/include/mc-cmd.h"
+#include <linux/fsl/mc.h>
+
+struct dpdmai_cmd_open {
+ __le32 dpdmai_id;
+};
+
+struct dpdmai_rsp_get_attributes {
+ __le32 id;
+ u8 num_of_priorities;
+ u8 pad0[3];
+ __le16 major;
+ __le16 minor;
+};
+
+
+struct dpdmai_cmd_queue {
+ __le32 dest_id;
+ u8 priority;
+ u8 queue;
+ u8 dest_type;
+ u8 pad;
+ __le64 user_ctx;
+ union {
+ __le32 options;
+ __le32 fqid;
+ };
+};
+
+struct dpdmai_rsp_get_tx_queue {
+ __le64 pad;
+ __le32 fqid;
+};
+
+
+int dpdmai_open(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ int dpdmai_id,
+ uint16_t *token)
+{
+ struct mc_command cmd = { 0 };
+ struct fsl_mc_command cmd = { 0 };
+ struct dpdmai_cmd_open *cmd_params;
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_OPEN,
+ cmd_flags,
+ 0);
+ DPDMAI_CMD_OPEN(cmd, dpdmai_id);
+
+ cmd_params = (struct dpdmai_cmd_open *)cmd.params;
+ cmd_params->dpdmai_id = cpu_to_le32(dpdmai_id);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
@ -1999,8 +1952,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ return err;
+
+ /* retrieve response parameters */
+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+ *token = mc_cmd_hdr_read_token(&cmd);
+ return 0;
+}
+
@ -2008,7 +1960,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+ struct fsl_mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_CLOSE,
@ -2023,7 +1975,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ const struct dpdmai_cfg *cfg,
+ uint16_t *token)
+{
+ struct mc_command cmd = { 0 };
+ struct fsl_mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
@ -2047,7 +1999,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+ struct fsl_mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_DESTROY,
@ -2062,7 +2014,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+ struct fsl_mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_ENABLE,
@ -2077,7 +2029,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+ struct fsl_mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_DISABLE,
@ -2093,7 +2045,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ uint16_t token,
+ int *en)
+{
+ struct mc_command cmd = { 0 };
+ struct fsl_mc_command cmd = { 0 };
+ int err;
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_IS_ENABLED,
@ -2115,7 +2067,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+ struct fsl_mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_RESET,
@ -2133,7 +2085,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ int *type,
+ struct dpdmai_irq_cfg *irq_cfg)
+{
+ struct mc_command cmd = { 0 };
+ struct fsl_mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
@ -2159,7 +2111,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ uint8_t irq_index,
+ struct dpdmai_irq_cfg *irq_cfg)
+{
+ struct mc_command cmd = { 0 };
+ struct fsl_mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_SET_IRQ,
@ -2177,7 +2129,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ uint8_t irq_index,
+ uint8_t *en)
+{
+ struct mc_command cmd = { 0 };
+ struct fsl_mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
@ -2203,7 +2155,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ uint8_t irq_index,
+ uint8_t en)
+{
+ struct mc_command cmd = { 0 };
+ struct fsl_mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_SET_IRQ_ENABLE,
@ -2221,7 +2173,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ uint8_t irq_index,
+ uint32_t *mask)
+{
+ struct mc_command cmd = { 0 };
+ struct fsl_mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
@ -2247,7 +2199,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ uint8_t irq_index,
+ uint32_t mask)
+{
+ struct mc_command cmd = { 0 };
+ struct fsl_mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_SET_IRQ_MASK,
@ -2265,7 +2217,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ uint8_t irq_index,
+ uint32_t *status)
+{
+ struct mc_command cmd = { 0 };
+ struct fsl_mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
@ -2291,7 +2243,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ uint8_t irq_index,
+ uint32_t status)
+{
+ struct mc_command cmd = { 0 };
+ struct fsl_mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_CLEAR_IRQ_STATUS,
@ -2308,8 +2260,9 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ uint16_t token,
+ struct dpdmai_attr *attr)
+{
+ struct mc_command cmd = { 0 };
+ struct fsl_mc_command cmd = { 0 };
+ int err;
+ struct dpdmai_rsp_get_attributes *rsp_params;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_GET_ATTR,
@ -2322,7 +2275,12 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ return err;
+
+ /* retrieve response parameters */
+ DPDMAI_RSP_GET_ATTR(cmd, attr);
+ rsp_params = (struct dpdmai_rsp_get_attributes *)cmd.params;
+ attr->id = le32_to_cpu(rsp_params->id);
+ attr->version.major = le16_to_cpu(rsp_params->major);
+ attr->version.minor = le16_to_cpu(rsp_params->minor);
+ attr->num_of_priorities = rsp_params->num_of_priorities;
+
+
+ return 0;
+}
@ -2333,13 +2291,22 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ uint8_t priority,
+ const struct dpdmai_rx_queue_cfg *cfg)
+{
+ struct mc_command cmd = { 0 };
+ struct fsl_mc_command cmd = { 0 };
+ struct dpdmai_cmd_queue *cmd_params;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_SET_RX_QUEUE,
+ cmd_flags,
+ token);
+ DPDMAI_CMD_SET_RX_QUEUE(cmd, priority, cfg);
+
+ cmd_params = (struct dpdmai_cmd_queue *)cmd.params;
+ cmd_params->dest_id = cpu_to_le32(cfg->dest_cfg.dest_id);
+ cmd_params->priority = cfg->dest_cfg.priority;
+ cmd_params->queue = priority;
+ cmd_params->dest_type = cfg->dest_cfg.dest_type;
+ cmd_params->user_ctx = cpu_to_le64(cfg->user_ctx);
+ cmd_params->options = cpu_to_le32(cfg->options);
+
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
@ -2350,14 +2317,17 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ uint16_t token,
+ uint8_t priority, struct dpdmai_rx_queue_attr *attr)
+{
+ struct mc_command cmd = { 0 };
+ struct fsl_mc_command cmd = { 0 };
+ struct dpdmai_cmd_queue *cmd_params;
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_GET_RX_QUEUE,
+ cmd_flags,
+ token);
+ DPDMAI_CMD_GET_RX_QUEUE(cmd, priority);
+
+ cmd_params = (struct dpdmai_cmd_queue *)cmd.params;
+ cmd_params->queue = priority;
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
@ -2365,7 +2335,11 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ return err;
+
+ /* retrieve response parameters */
+ DPDMAI_RSP_GET_RX_QUEUE(cmd, attr);
+ attr->dest_cfg.dest_id = le32_to_cpu(cmd_params->dest_id);
+ attr->dest_cfg.priority = cmd_params->priority;
+ attr->dest_cfg.dest_type = cmd_params->dest_type;
+ attr->user_ctx = le64_to_cpu(cmd_params->user_ctx);
+ attr->fqid = le32_to_cpu(cmd_params->fqid);
+
+ return 0;
+}
@ -2376,14 +2350,18 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ uint8_t priority,
+ struct dpdmai_tx_queue_attr *attr)
+{
+ struct mc_command cmd = { 0 };
+ struct fsl_mc_command cmd = { 0 };
+ struct dpdmai_cmd_queue *cmd_params;
+ struct dpdmai_rsp_get_tx_queue *rsp_params;
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_GET_TX_QUEUE,
+ cmd_flags,
+ token);
+ DPDMAI_CMD_GET_TX_QUEUE(cmd, priority);
+
+ cmd_params = (struct dpdmai_cmd_queue *)cmd.params;
+ cmd_params->queue = priority;
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
@ -2391,7 +2369,9 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ return err;
+
+ /* retrieve response parameters */
+ DPDMAI_RSP_GET_TX_QUEUE(cmd, attr);
+
+ rsp_params = (struct dpdmai_rsp_get_tx_queue *)cmd.params;
+ attr->fqid = le32_to_cpu(rsp_params->fqid);
+
+ return 0;
+}

90
target/linux/layerscape/patches-4.9/810-iommu-support-layerscape.patch
View File

@ -1,7 +1,7 @@
From 0a6c701f92e1aa368c44632fa0985e92703354ed Mon Sep 17 00:00:00 2001
From 89a1f0d7826df69d8e02268b97bc3da02e07203f Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Wed, 17 Jan 2018 15:35:48 +0800
Subject: [PATCH 22/30] iommu: support layerscape
Date: Thu, 5 Jul 2018 17:35:15 +0800
Subject: [PATCH 22/32] iommu: support layerscape
This is an integrated patch for layerscape smmu support.
@ -11,17 +11,17 @@ Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Signed-off-by: Sunil Goutham <sgoutham@cavium.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
drivers/iommu/amd_iommu.c | 56 ++++++----
drivers/iommu/arm-smmu-v3.c | 111 ++++++++++++++------
drivers/iommu/arm-smmu.c | 100 +++++++++++++++---
drivers/iommu/dma-iommu.c | 242 ++++++++++++++++++++++++++++++++++++-------
drivers/iommu/intel-iommu.c | 92 ++++++++++++----
drivers/iommu/iommu.c | 219 ++++++++++++++++++++++++++++++++++++---
drivers/iommu/amd_iommu.c | 56 +++++---
drivers/iommu/arm-smmu-v3.c | 111 +++++++++++-----
drivers/iommu/arm-smmu.c | 100 ++++++++++++---
drivers/iommu/dma-iommu.c | 242 +++++++++++++++++++++++++++++------
drivers/iommu/intel-iommu.c | 92 ++++++++++---
drivers/iommu/iommu.c | 240 ++++++++++++++++++++++++++++++++--
drivers/iommu/mtk_iommu.c | 2 +
drivers/iommu/mtk_iommu_v1.c | 2 +
include/linux/dma-iommu.h | 11 ++
include/linux/iommu.h | 55 +++++++---
10 files changed, 739 insertions(+), 151 deletions(-)
include/linux/iommu.h | 57 +++++++--
10 files changed, 762 insertions(+), 151 deletions(-)
--- a/drivers/iommu/amd_iommu.c
+++ b/drivers/iommu/amd_iommu.c
@ -312,7 +312,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
out_unlock:
mutex_unlock(&smmu_domain->init_mutex);
return ret;
@@ -1712,6 +1723,9 @@ arm_smmu_iova_to_phys(struct iommu_domai
@@ -1695,6 +1706,9 @@ arm_smmu_unmap(struct iommu_domain *doma
struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops;
@ -398,7 +398,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
#include <linux/spinlock.h>
#include <linux/amba/bus.h>
+#include "../staging/fsl-mc/include/mc-bus.h"
+#include <linux/fsl/mc.h>
#include "io-pgtable.h"
@ -1132,7 +1132,11 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
--- a/drivers/iommu/iommu.c
+++ b/drivers/iommu/iommu.c
@@ -36,6 +36,7 @@
@@ -33,9 +33,11 @@
#include <linux/bitops.h>
#include <linux/property.h>
#include <trace/events/iommu.h>
+#include <linux/fsl/mc.h>
static struct kset *iommu_group_kset;
static DEFINE_IDA(iommu_group_ida);
@ -1140,7 +1144,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
struct iommu_callback_data {
const struct iommu_ops *ops;
@@ -68,6 +69,13 @@ struct iommu_group_attribute {
@@ -68,6 +70,13 @@ struct iommu_group_attribute {
const char *buf, size_t count);
};
@ -1154,7 +1158,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
#define IOMMU_GROUP_ATTR(_name, _mode, _show, _store) \
struct iommu_group_attribute iommu_group_attr_##_name = \
__ATTR(_name, _mode, _show, _store)
@@ -86,6 +94,18 @@ static int __iommu_attach_group(struct i
@@ -86,6 +95,18 @@ static int __iommu_attach_group(struct i
static void __iommu_detach_group(struct iommu_domain *domain,
struct iommu_group *group);
@ -1173,7 +1177,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
static ssize_t iommu_group_attr_show(struct kobject *kobj,
struct attribute *__attr, char *buf)
{
@@ -133,8 +153,131 @@ static ssize_t iommu_group_show_name(str
@@ -133,8 +154,131 @@ static ssize_t iommu_group_show_name(str
return sprintf(buf, "%s\n", group->name);
}
@ -1305,7 +1309,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
static void iommu_group_release(struct kobject *kobj)
{
struct iommu_group *group = to_iommu_group(kobj);
@@ -212,6 +355,11 @@ struct iommu_group *iommu_group_alloc(vo
@@ -212,6 +356,11 @@ struct iommu_group *iommu_group_alloc(vo
*/
kobject_put(&group->kobj);
@ -1317,7 +1321,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
pr_debug("Allocated group %d\n", group->id);
return group;
@@ -318,7 +466,7 @@ static int iommu_group_create_direct_map
@@ -318,7 +467,7 @@ static int iommu_group_create_direct_map
struct device *dev)
{
struct iommu_domain *domain = group->default_domain;
@ -1326,7 +1330,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
struct list_head mappings;
unsigned long pg_size;
int ret = 0;
@@ -331,18 +479,21 @@ static int iommu_group_create_direct_map
@@ -331,18 +480,21 @@ static int iommu_group_create_direct_map
pg_size = 1UL << __ffs(domain->pgsize_bitmap);
INIT_LIST_HEAD(&mappings);
@ -1351,7 +1355,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
for (addr = start; addr < end; addr += pg_size) {
phys_addr_t phys_addr;
@@ -358,7 +509,7 @@ static int iommu_group_create_direct_map
@@ -358,7 +510,7 @@ static int iommu_group_create_direct_map
}
out:
@ -1360,7 +1364,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
return ret;
}
@@ -563,6 +714,19 @@ struct iommu_group *iommu_group_get(stru
@@ -563,6 +715,19 @@ struct iommu_group *iommu_group_get(stru
EXPORT_SYMBOL_GPL(iommu_group_get);
/**
@ -1380,7 +1384,34 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* iommu_group_put - Decrement group reference
* @group: the group to use
*
@@ -845,10 +1009,19 @@ struct iommu_group *iommu_group_get_for_
@@ -812,6 +977,26 @@ struct iommu_group *pci_device_group(str
return group;
}
+/* Get the IOMMU group for device on fsl-mc bus */
+struct iommu_group *fsl_mc_device_group(struct device *dev)
+{
+ struct device *cont_dev = fsl_mc_cont_dev(dev);
+ struct iommu_group *group;
+
+ /* Container device is responsible for creating the iommu group */
+ if (fsl_mc_is_cont_dev(dev)) {
+ group = iommu_group_alloc();
+ if (IS_ERR(group))
+ return NULL;
+ } else {
+ get_device(cont_dev);
+ group = iommu_group_get(cont_dev);
+ put_device(cont_dev);
+ }
+
+ return group;
+}
+
/**
* iommu_group_get_for_dev - Find or create the IOMMU group for a device
* @dev: target device
@@ -845,10 +1030,19 @@ struct iommu_group *iommu_group_get_for_
* IOMMU driver.
*/
if (!group->default_domain) {
@ -1403,7 +1434,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
}
ret = iommu_group_add_device(group, dev);
@@ -1557,20 +1730,38 @@ int iommu_domain_set_attr(struct iommu_d
@@ -1557,20 +1751,38 @@ int iommu_domain_set_attr(struct iommu_d
}
EXPORT_SYMBOL_GPL(iommu_domain_set_attr);
@ -1604,7 +1635,16 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
extern void iommu_group_put(struct iommu_group *group);
extern int iommu_group_register_notifier(struct iommu_group *group,
struct notifier_block *nb);
@@ -439,16 +460,22 @@ static inline void iommu_set_fault_handl
@@ -330,6 +351,8 @@ static inline size_t iommu_map_sg(struct
extern struct iommu_group *pci_device_group(struct device *dev);
/* Generic device grouping function */
extern struct iommu_group *generic_device_group(struct device *dev);
+/* FSL-MC device grouping function */
+struct iommu_group *fsl_mc_device_group(struct device *dev);
/**
* struct iommu_fwspec - per-device IOMMU instance data
@@ -439,16 +462,22 @@ static inline void iommu_set_fault_handl
{
}

45
target/linux/layerscape/patches-4.9/811-irqchip-support-layerscape.patch
View File

@ -1,7 +1,7 @@
From 5a5ff01c790d49c0f6fd247f68f2fd9a2128ea91 Mon Sep 17 00:00:00 2001
From dab02a7cc54494740e849cd51b554d100eb5541d Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Wed, 17 Jan 2018 15:36:28 +0800
Subject: [PATCH 23/30] irqchip: support layerscape
Date: Thu, 5 Jul 2018 17:36:09 +0800
Subject: [PATCH 23/32] irqchip: support layerscape
This is an integrated patch for layerscape gic support.
@ -9,16 +9,17 @@ Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-gic-v3-its.c | 1 +
include/linux/irqdomain.h | 36 ++++++++++++++++++++++++++++++++++++
kernel/irq/irqdomain.c | 39 +++++++++++++++++++++++++++++++++++++++
kernel/irq/msi.c | 4 ++--
5 files changed, 79 insertions(+), 2 deletions(-)
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-gic-v3-its.c | 1 +
include/linux/irqchip/arm-gic-v3.h | 3 +++
include/linux/irqdomain.h | 36 +++++++++++++++++++++++++++
kernel/irq/irqdomain.c | 39 ++++++++++++++++++++++++++++++
kernel/irq/msi.c | 4 +--
6 files changed, 82 insertions(+), 2 deletions(-)
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -74,3 +74,4 @@ obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scf
@@ -75,3 +75,4 @@ obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scf
obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o
obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
@ -33,9 +34,21 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
info->ops = &its_msi_domain_ops;
info->data = its;
inner_domain->host_data = info;
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -133,6 +133,9 @@
#define GIC_BASER_SHAREABILITY(reg, type) \
(GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
+/* encode a size field of width @w containing @n - 1 units */
+#define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0))
+
#define GICR_PROPBASER_SHAREABILITY_SHIFT (10)
#define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7)
#define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56)
--- a/include/linux/irqdomain.h
+++ b/include/linux/irqdomain.h
@@ -183,6 +183,12 @@ enum {
@@ -187,6 +187,12 @@ enum {
/* Irq domain is an IPI domain with single virq */
IRQ_DOMAIN_FLAG_IPI_SINGLE = (1 << 3),
@ -48,7 +61,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
/*
* Flags starting from IRQ_DOMAIN_FLAG_NONCORE are reserved
* for implementation specific purposes and ignored by the
@@ -216,6 +222,7 @@ struct irq_domain *irq_domain_add_legacy
@@ -220,6 +226,7 @@ struct irq_domain *irq_domain_add_legacy
void *host_data);
extern struct irq_domain *irq_find_matching_fwspec(struct irq_fwspec *fwspec,
enum irq_domain_bus_token bus_token);
@ -56,7 +69,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
extern void irq_set_default_host(struct irq_domain *host);
extern int irq_domain_alloc_descs(int virq, unsigned int nr_irqs,
irq_hw_number_t hwirq, int node,
@@ -446,6 +453,19 @@ static inline bool irq_domain_is_ipi_sin
@@ -453,6 +460,19 @@ static inline bool irq_domain_is_ipi_sin
{
return domain->flags & IRQ_DOMAIN_FLAG_IPI_SINGLE;
}
@ -76,7 +89,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
#else /* CONFIG_IRQ_DOMAIN_HIERARCHY */
static inline void irq_domain_activate_irq(struct irq_data *data) { }
static inline void irq_domain_deactivate_irq(struct irq_data *data) { }
@@ -477,6 +497,22 @@ static inline bool irq_domain_is_ipi_sin
@@ -484,6 +504,22 @@ static inline bool irq_domain_is_ipi_sin
{
return false;
}
@ -101,7 +114,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
#else /* CONFIG_IRQ_DOMAIN */
--- a/kernel/irq/irqdomain.c
+++ b/kernel/irq/irqdomain.c
@@ -278,6 +278,31 @@ struct irq_domain *irq_find_matching_fws
@@ -319,6 +319,31 @@ struct irq_domain *irq_find_matching_fws
EXPORT_SYMBOL_GPL(irq_find_matching_fwspec);
/**
@ -133,7 +146,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* irq_set_default_host() - Set a "default" irq domain
* @domain: default domain pointer
*
@@ -1408,6 +1433,20 @@ static void irq_domain_check_hierarchy(s
@@ -1420,6 +1445,20 @@ static void irq_domain_check_hierarchy(s
if (domain->ops->alloc)
domain->flags |= IRQ_DOMAIN_FLAG_HIERARCHY;
}

109
target/linux/layerscape/patches-4.9/817-usb-support-layerscape.patch
View File

@ -1,7 +1,7 @@
From a2a97f0d2c07a772899ca09967547bea6c9124c5 Mon Sep 17 00:00:00 2001
From 1d35e363dd6e8bb1733bca0dfc186e3f70e692fe Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Wed, 17 Jan 2018 15:46:03 +0800
Subject: [PATCH 29/30] usb: support layerscape
Date: Thu, 5 Jul 2018 17:38:52 +0800
Subject: [PATCH 29/32] usb: support layerscape
This is an integrated patch for layerscape usb support.
@ -17,30 +17,31 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
drivers/net/usb/cdc_ether.c | 8 +
drivers/net/usb/r8152.c | 6 +
drivers/usb/common/common.c | 50 ++++++
drivers/usb/common/common.c | 50 +++++
drivers/usb/core/hub.c | 8 +
drivers/usb/dwc3/core.c | 243 ++++++++++++++++++++++++++++-
drivers/usb/dwc3/core.h | 51 ++++++-
drivers/usb/dwc3/core.c | 243 +++++++++++++++++++++-
drivers/usb/dwc3/core.h | 51 ++++-
drivers/usb/dwc3/ep0.c | 4 +-
drivers/usb/dwc3/gadget.c | 7 +
drivers/usb/dwc3/host.c | 24 ++-
drivers/usb/gadget/udc/fsl_udc_core.c | 46 +++---
drivers/usb/gadget/udc/fsl_udc_core.c | 46 +++--
drivers/usb/gadget/udc/fsl_usb2_udc.h | 16 +-
drivers/usb/host/Kconfig | 2 +-
drivers/usb/host/ehci-fsl.c | 279 +++++++++++++++++++++++++++++++---
drivers/usb/host/Kconfig | 4 +-
drivers/usb/host/ehci-fsl.c | 279 ++++++++++++++++++++++++--
drivers/usb/host/ehci-fsl.h | 3 +
drivers/usb/host/ehci-hub.c | 4 +
drivers/usb/host/ehci.h | 9 ++
drivers/usb/host/fsl-mph-dr-of.c | 12 ++
drivers/usb/host/xhci-plat.c | 10 ++
drivers/usb/host/xhci-ring.c | 29 +++-
drivers/usb/host/xhci.c | 38 ++++-
drivers/usb/host/xhci.h | 5 +-
drivers/usb/phy/phy-fsl-usb.c | 59 +++++--
drivers/usb/host/ehci.h | 9 +
drivers/usb/host/fsl-mph-dr-of.c | 16 +-
drivers/usb/host/xhci-hub.c | 22 ++
drivers/usb/host/xhci-plat.c | 16 +-
drivers/usb/host/xhci-ring.c | 29 ++-
drivers/usb/host/xhci.c | 38 +++-
drivers/usb/host/xhci.h | 6 +-
drivers/usb/phy/phy-fsl-usb.c | 59 ++++--
drivers/usb/phy/phy-fsl-usb.h | 8 +
include/linux/usb.h | 1 +
include/linux/usb/of.h | 2 +
25 files changed, 836 insertions(+), 88 deletions(-)
26 files changed, 867 insertions(+), 92 deletions(-)
--- a/drivers/net/usb/cdc_ether.c
+++ b/drivers/net/usb/cdc_ether.c
@ -924,11 +925,13 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
#endif
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -165,7 +165,7 @@ config XPS_USB_HCD_XILINX
@@ -164,8 +164,8 @@ config XPS_USB_HCD_XILINX
devices only.
config USB_EHCI_FSL
tristate "Support for Freescale PPC on-chip EHCI USB controller"
- tristate "Support for Freescale PPC on-chip EHCI USB controller"
- depends on FSL_SOC
+ tristate "Support for Freescale QorIQ(ARM/PPC) on-chip EHCI USB controller"
+ depends on USB_EHCI_HCD
select USB_EHCI_ROOT_HUB_TT
---help---
@ -1399,6 +1402,17 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
/*
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -98,8 +98,8 @@ static struct platform_device *fsl_usb2_
pdev->dev.coherent_dma_mask = ofdev->dev.coherent_dma_mask;
- if (!pdev->dev.dma_mask)
- pdev->dev.dma_mask = &ofdev->dev.coherent_dma_mask;
+ if (!pdev->dev.dma_mask && ofdev->dev.of_node)
+ of_dma_configure(&pdev->dev, ofdev->dev.of_node);
else
dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
@@ -226,6 +226,18 @@ static int fsl_usb2_mph_dr_of_probe(stru
of_property_read_bool(np, "fsl,usb-erratum-a007792");
pdata->has_fsl_erratum_a005275 =
@ -1418,12 +1432,57 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
/*
* Determine whether phy_clk_valid needs to be checked
--- a/drivers/usb/host/xhci-hub.c
+++ b/drivers/usb/host/xhci-hub.c
@@ -562,12 +562,34 @@ void xhci_set_link_state(struct xhci_hcd
int port_id, u32 link_state)
{
u32 temp;
+ u32 portpmsc_u2_backup = 0;
+
+ /* Backup U2 timeout info before initiating U3 entry erratum A-010131 */
+ if (xhci->shared_hcd->speed >= HCD_USB3 &&
+ link_state == USB_SS_PORT_LS_U3 &&
+ (xhci->quirks & XHCI_DIS_U1U2_WHEN_U3)) {
+ portpmsc_u2_backup = readl(port_array[port_id] + PORTPMSC);
+ portpmsc_u2_backup &= PORT_U2_TIMEOUT_MASK;
+ temp = readl(port_array[port_id] + PORTPMSC);
+ temp |= PORT_U2_TIMEOUT_MASK;
+ writel(temp, port_array[port_id] + PORTPMSC);
+ }
temp = readl(port_array[port_id]);
temp = xhci_port_state_to_neutral(temp);
temp &= ~PORT_PLS_MASK;
temp |= PORT_LINK_STROBE | link_state;
writel(temp, port_array[port_id]);
+
+ /* Restore U2 timeout info after U3 entry complete */
+ if (xhci->shared_hcd->speed >= HCD_USB3 &&
+ link_state == USB_SS_PORT_LS_U3 &&
+ (xhci->quirks & XHCI_DIS_U1U2_WHEN_U3)) {
+ temp = readl(port_array[port_id] + PORTPMSC);
+ temp &= ~PORT_U2_TIMEOUT_MASK;
+ temp |= portpmsc_u2_backup;
+ writel(temp, port_array[port_id] + PORTPMSC);
+ }
}
static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -223,6 +223,16 @@ static int xhci_plat_probe(struct platfo
if (device_property_read_bool(&pdev->dev, "usb3-lpm-capable"))
xhci->quirks |= XHCI_LPM_SUPPORT;
@@ -220,8 +220,22 @@ static int xhci_plat_probe(struct platfo
goto disable_clk;
}
- if (device_property_read_bool(&pdev->dev, "usb3-lpm-capable"))
+ if (device_property_read_bool(&pdev->dev, "usb3-lpm-capable")) {
xhci->quirks |= XHCI_LPM_SUPPORT;
+ if (device_property_read_bool(&pdev->dev,
+ "snps,dis-u1u2-when-u3-quirk"))
+ xhci->quirks |= XHCI_DIS_U1U2_WHEN_U3;
+ }
+
+ if (device_property_read_bool(&pdev->dev, "quirk-reverse-in-out"))
+ xhci->quirks |= XHCI_REVERSE_IN_OUT;
+
@ -1433,10 +1492,9 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+
+ if (device_property_read_bool(&pdev->dev, "quirk-stop-ep-in-u1"))
+ xhci->quirks |= XHCI_STOP_EP_IN_U1;
+
if (device_property_read_bool(&pdev->dev, "quirk-broken-port-ped"))
xhci->quirks |= XHCI_BROKEN_PORT_PED;
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -1852,14 +1852,17 @@ static int finish_td(struct xhci_hcd *xh
@ -1551,13 +1609,14 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
#define XHCI_LINK_TRB_QUIRK (1 << 0)
#define XHCI_RESET_EP_QUIRK (1 << 1)
#define XHCI_NEC_HOST (1 << 2)
@@ -1661,6 +1661,9 @@ struct xhci_hcd {
@@ -1661,6 +1661,10 @@ struct xhci_hcd {
#define XHCI_SSIC_PORT_UNUSED (1 << 22)
#define XHCI_NO_64BIT_SUPPORT (1 << 23)
#define XHCI_MISSING_CAS (1 << 24)
+#define XHCI_REVERSE_IN_OUT (1 << 29)
+#define XHCI_STOP_TRANSFER_IN_BLOCK (1 << 30)
+#define XHCI_STOP_EP_IN_U1 (1 << 31)
+#define XHCI_DIS_U1U2_WHEN_U3 (1 << 32)
/* For controller with a broken Port Disable implementation */
#define XHCI_BROKEN_PORT_PED (1 << 25)
#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 (1 << 26)

33
target/linux/layerscape/patches-4.9/818-vfio-support-layerscape.patch
View File

@ -1,7 +1,7 @@
From 954edeee88305fecefe3f681e67a298f06e27974 Mon Sep 17 00:00:00 2001
From e6af99cc1d56322fc960d072af1a7e0e9285b90c Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Wed, 17 Jan 2018 15:48:47 +0800
Subject: [PATCH 30/30] vfio: support layerscape
Date: Thu, 5 Jul 2018 17:39:43 +0800
Subject: [PATCH 30/32] vfio: support layerscape
This is an integrated patch for layerscape vfio support.
@ -15,12 +15,12 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
drivers/vfio/Makefile | 1 +
drivers/vfio/fsl-mc/Kconfig | 9 +
drivers/vfio/fsl-mc/Makefile | 2 +
drivers/vfio/fsl-mc/vfio_fsl_mc.c | 753 ++++++++++++++++++++++++++++++
drivers/vfio/fsl-mc/vfio_fsl_mc_intr.c | 199 ++++++++
drivers/vfio/fsl-mc/vfio_fsl_mc_private.h | 55 +++
drivers/vfio/fsl-mc/vfio_fsl_mc.c | 752 ++++++++++++++++++++++
drivers/vfio/fsl-mc/vfio_fsl_mc_intr.c | 199 ++++++
drivers/vfio/fsl-mc/vfio_fsl_mc_private.h | 55 ++
drivers/vfio/vfio_iommu_type1.c | 39 +-
include/uapi/linux/vfio.h | 1 +
9 files changed, 1058 insertions(+), 2 deletions(-)
9 files changed, 1057 insertions(+), 2 deletions(-)
create mode 100644 drivers/vfio/fsl-mc/Kconfig
create mode 100644 drivers/vfio/fsl-mc/Makefile
create mode 100644 drivers/vfio/fsl-mc/vfio_fsl_mc.c
@ -61,7 +61,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+obj-$(CONFIG_VFIO_FSL_MC) += vfio_fsl_mc.o vfio_fsl_mc_intr.o
--- /dev/null
+++ b/drivers/vfio/fsl-mc/vfio_fsl_mc.c
@@ -0,0 +1,753 @@
@@ -0,0 +1,752 @@
+/*
+ * Freescale Management Complex (MC) device passthrough using VFIO
+ *
@ -83,10 +83,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+#include <linux/vfio.h>
+#include <linux/delay.h>
+
+#include "../../staging/fsl-mc/include/mc.h"
+#include "../../staging/fsl-mc/include/mc-bus.h"
+#include "../../staging/fsl-mc/include/mc-sys.h"
+#include "../../staging/fsl-mc/bus/dprc-cmd.h"
+#include <linux/fsl/mc.h>
+
+#include "vfio_fsl_mc_private.h"
+
@ -353,8 +350,9 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ uint64_t data[8];
+ int i;
+
+ /* Read ioctl supported only for DPRC device */
+ if (strcmp(vdev->mc_dev->obj_desc.type, "dprc"))
+ /* Read ioctl supported only for DPRC and DPMCP device */
+ if (strcmp(vdev->mc_dev->obj_desc.type, "dprc") &&
+ strcmp(vdev->mc_dev->obj_desc.type, "dpmcp"))
+ return -EINVAL;
+
+ if (index >= vdev->num_regions)
@ -455,8 +453,9 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+ uint64_t data[8];
+ int ret;
+
+ /* Write ioctl supported only for DPRC device */
+ if (strcmp(vdev->mc_dev->obj_desc.type, "dprc"))
+ /* Write ioctl supported only for DPRC and DPMCP device */
+ if (strcmp(vdev->mc_dev->obj_desc.type, "dprc") &&
+ strcmp(vdev->mc_dev->obj_desc.type, "dpmcp"))
+ return -EINVAL;
+
+ if (index >= vdev->num_regions)
@ -835,7 +834,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+#include <linux/eventfd.h>
+#include <linux/msi.h>
+
+#include "../../staging/fsl-mc/include/mc.h"
+#include "linux/fsl/mc.h"
+#include "vfio_fsl_mc_private.h"
+
+static irqreturn_t vfio_fsl_mc_irq_handler(int irq_num, void *arg)

542
target/linux/layerscape/patches-4.9/819-flexcan-support-layerscape.patch Normal file
View File

@ -0,0 +1,542 @@
From 2887442bd13bc8be687afc7172cb01c2b7f0dd3b Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Thu, 5 Jul 2018 17:41:14 +0800
Subject: [PATCH 31/32] flexcan: support layerscape
This is an integrated patch for layerscape flexcan support.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
drivers/net/can/flexcan.c | 212 ++++++++++++++++++++++----------------
1 file changed, 123 insertions(+), 89 deletions(-)
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -184,6 +184,7 @@
* MX53 FlexCAN2 03.00.00.00 yes no no no
* MX6s FlexCAN3 10.00.12.00 yes yes no yes
* VF610 FlexCAN3 ? no yes yes yes?
+ * LS1021A FlexCAN2 03.00.04.00 no yes no yes
*
* Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
*/
@@ -260,6 +261,10 @@ struct flexcan_priv {
struct flexcan_platform_data *pdata;
const struct flexcan_devtype_data *devtype_data;
struct regulator *reg_xceiver;
+
+ /* Read and Write APIs */
+ u32 (*read)(void __iomem *addr);
+ void (*write)(u32 val, void __iomem *addr);
};
static struct flexcan_devtype_data fsl_p1010_devtype_data = {
@@ -276,6 +281,10 @@ static struct flexcan_devtype_data fsl_v
.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_DISABLE_MECR,
};
+static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
+ .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_DISABLE_MECR,
+};
+
static const struct can_bittiming_const flexcan_bittiming_const = {
.name = DRV_NAME,
.tseg1_min = 4,
@@ -288,32 +297,38 @@ static const struct can_bittiming_const
.brp_inc = 1,
};
-/* Abstract off the read/write for arm versus ppc. This
- * assumes that PPC uses big-endian registers and everything
- * else uses little-endian registers, independent of CPU
- * endianness.
+/* FlexCAN module is essentially modelled as a little-endian IP in most
+ * SoCs, i.e the registers as well as the message buffer areas are
+ * implemented in a little-endian fashion.
+ *
+ * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
+ * module in a big-endian fashion (i.e the registers as well as the
+ * message buffer areas are implemented in a big-endian way).
+ *
+ * In addition, the FlexCAN module can be found on SoCs having ARM or
+ * PPC cores. So, we need to abstract off the register read/write
+ * functions, ensuring that these cater to all the combinations of module
+ * endianness and underlying CPU endianness.
*/
-#if defined(CONFIG_PPC)
-static inline u32 flexcan_read(void __iomem *addr)
+static inline u32 flexcan_read_be(void __iomem *addr)
{
- return in_be32(addr);
+ return ioread32be(addr);
}
-static inline void flexcan_write(u32 val, void __iomem *addr)
+static inline void flexcan_write_be(u32 val, void __iomem *addr)
{
- out_be32(addr, val);
+ iowrite32be(val, addr);
}
-#else
-static inline u32 flexcan_read(void __iomem *addr)
+
+static inline u32 flexcan_read_le(void __iomem *addr)
{
- return readl(addr);
+ return ioread32(addr);
}
-static inline void flexcan_write(u32 val, void __iomem *addr)
+static inline void flexcan_write_le(u32 val, void __iomem *addr)
{
- writel(val, addr);
+ iowrite32(val, addr);
}
-#endif
static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
{
@@ -344,14 +359,14 @@ static int flexcan_chip_enable(struct fl
unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
u32 reg;
- reg = flexcan_read(&regs->mcr);
+ reg = priv->read(&regs->mcr);
reg &= ~FLEXCAN_MCR_MDIS;
- flexcan_write(reg, &regs->mcr);
+ priv->write(reg, &regs->mcr);
- while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
+ while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
udelay(10);
- if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
+ if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
return -ETIMEDOUT;
return 0;
@@ -363,14 +378,14 @@ static int flexcan_chip_disable(struct f
unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
u32 reg;
- reg = flexcan_read(&regs->mcr);
+ reg = priv->read(&regs->mcr);
reg |= FLEXCAN_MCR_MDIS;
- flexcan_write(reg, &regs->mcr);
+ priv->write(reg, &regs->mcr);
- while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
+ while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
udelay(10);
- if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
+ if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
return -ETIMEDOUT;
return 0;
@@ -382,14 +397,14 @@ static int flexcan_chip_freeze(struct fl
unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
u32 reg;
- reg = flexcan_read(&regs->mcr);
+ reg = priv->read(&regs->mcr);
reg |= FLEXCAN_MCR_HALT;
- flexcan_write(reg, &regs->mcr);
+ priv->write(reg, &regs->mcr);
- while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
+ while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
udelay(100);
- if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
+ if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
return -ETIMEDOUT;
return 0;
@@ -401,14 +416,14 @@ static int flexcan_chip_unfreeze(struct
unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
u32 reg;
- reg = flexcan_read(&regs->mcr);
+ reg = priv->read(&regs->mcr);
reg &= ~FLEXCAN_MCR_HALT;
- flexcan_write(reg, &regs->mcr);
+ priv->write(reg, &regs->mcr);
- while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
+ while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
udelay(10);
- if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
+ if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
return -ETIMEDOUT;
return 0;
@@ -419,11 +434,11 @@ static int flexcan_chip_softreset(struct
struct flexcan_regs __iomem *regs = priv->regs;
unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
- flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
- while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
+ priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
+ while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
udelay(10);
- if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
+ if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
return -ETIMEDOUT;
return 0;
@@ -434,7 +449,7 @@ static int __flexcan_get_berr_counter(co
{
const struct flexcan_priv *priv = netdev_priv(dev);
struct flexcan_regs __iomem *regs = priv->regs;
- u32 reg = flexcan_read(&regs->ecr);
+ u32 reg = priv->read(&regs->ecr);
bec->txerr = (reg >> 0) & 0xff;
bec->rxerr = (reg >> 8) & 0xff;
@@ -491,24 +506,24 @@ static int flexcan_start_xmit(struct sk_
if (cf->can_dlc > 0) {
data = be32_to_cpup((__be32 *)&cf->data[0]);
- flexcan_write(data, &regs->mb[FLEXCAN_TX_BUF_ID].data[0]);
+ priv->write(data, &regs->mb[FLEXCAN_TX_BUF_ID].data[0]);
}
if (cf->can_dlc > 4) {
data = be32_to_cpup((__be32 *)&cf->data[4]);
- flexcan_write(data, &regs->mb[FLEXCAN_TX_BUF_ID].data[1]);
+ priv->write(data, &regs->mb[FLEXCAN_TX_BUF_ID].data[1]);
}
can_put_echo_skb(skb, dev, 0);
- flexcan_write(can_id, &regs->mb[FLEXCAN_TX_BUF_ID].can_id);
- flexcan_write(ctrl, &regs->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
+ priv->write(can_id, &regs->mb[FLEXCAN_TX_BUF_ID].can_id);
+ priv->write(ctrl, &regs->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
/* Errata ERR005829 step8:
* Write twice INACTIVE(0x8) code to first MB.
*/
- flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+ priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
&regs->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
- flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+ priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
&regs->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
return NETDEV_TX_OK;
@@ -632,8 +647,8 @@ static void flexcan_read_fifo(const stru
struct flexcan_mb __iomem *mb = &regs->mb[0];
u32 reg_ctrl, reg_id;
- reg_ctrl = flexcan_read(&mb->can_ctrl);
- reg_id = flexcan_read(&mb->can_id);
+ reg_ctrl = priv->read(&mb->can_ctrl);
+ reg_id = priv->read(&mb->can_id);
if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
else
@@ -643,12 +658,12 @@ static void flexcan_read_fifo(const stru
cf->can_id |= CAN_RTR_FLAG;
cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
- *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
- *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
+ *(__be32 *)(cf->data + 0) = cpu_to_be32(priv->read(&mb->data[0]));
+ *(__be32 *)(cf->data + 4) = cpu_to_be32(priv->read(&mb->data[1]));
/* mark as read */
- flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
- flexcan_read(&regs->timer);
+ priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
+ priv->read(&regs->timer);
}
static int flexcan_read_frame(struct net_device *dev)
@@ -685,17 +700,17 @@ static int flexcan_poll(struct napi_stru
/* The error bits are cleared on read,
* use saved value from irq handler.
*/
- reg_esr = flexcan_read(&regs->esr) | priv->reg_esr;
+ reg_esr = priv->read(&regs->esr) | priv->reg_esr;
/* handle state changes */
work_done += flexcan_poll_state(dev, reg_esr);
/* handle RX-FIFO */
- reg_iflag1 = flexcan_read(&regs->iflag1);
+ reg_iflag1 = priv->read(&regs->iflag1);
while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
work_done < quota) {
work_done += flexcan_read_frame(dev);
- reg_iflag1 = flexcan_read(&regs->iflag1);
+ reg_iflag1 = priv->read(&regs->iflag1);
}
/* report bus errors */
@@ -705,8 +720,8 @@ static int flexcan_poll(struct napi_stru
if (work_done < quota) {
napi_complete_done(napi, work_done);
/* enable IRQs */
- flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
- flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
+ priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
+ priv->write(priv->reg_ctrl_default, &regs->ctrl);
}
return work_done;
@@ -720,12 +735,12 @@ static irqreturn_t flexcan_irq(int irq,
struct flexcan_regs __iomem *regs = priv->regs;
u32 reg_iflag1, reg_esr;
- reg_iflag1 = flexcan_read(&regs->iflag1);
- reg_esr = flexcan_read(&regs->esr);
+ reg_iflag1 = priv->read(&regs->iflag1);
+ reg_esr = priv->read(&regs->esr);
/* ACK all bus error and state change IRQ sources */
if (reg_esr & FLEXCAN_ESR_ALL_INT)
- flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
+ priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
/* schedule NAPI in case of:
* - rx IRQ
@@ -739,16 +754,16 @@ static irqreturn_t flexcan_irq(int irq,
* save them for later use.
*/
priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
- flexcan_write(FLEXCAN_IFLAG_DEFAULT &
+ priv->write(FLEXCAN_IFLAG_DEFAULT &
~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->imask1);
- flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
+ priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
&regs->ctrl);
napi_schedule(&priv->napi);
}
/* FIFO overflow */
if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
- flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
+ priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
dev->stats.rx_over_errors++;
dev->stats.rx_errors++;
}
@@ -760,9 +775,9 @@ static irqreturn_t flexcan_irq(int irq,
can_led_event(dev, CAN_LED_EVENT_TX);
/* after sending a RTR frame MB is in RX mode */
- flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+ priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
&regs->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
- flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
+ priv->write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
netif_wake_queue(dev);
}
@@ -776,7 +791,7 @@ static void flexcan_set_bittiming(struct
struct flexcan_regs __iomem *regs = priv->regs;
u32 reg;
- reg = flexcan_read(&regs->ctrl);
+ reg = priv->read(&regs->ctrl);
reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
FLEXCAN_CTRL_RJW(0x3) |
FLEXCAN_CTRL_PSEG1(0x7) |
@@ -800,11 +815,11 @@ static void flexcan_set_bittiming(struct
reg |= FLEXCAN_CTRL_SMP;
netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
- flexcan_write(reg, &regs->ctrl);
+ priv->write(reg, &regs->ctrl);
/* print chip status */
netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
- flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
+ priv->read(&regs->mcr), priv->read(&regs->ctrl));
}
/* flexcan_chip_start
@@ -842,13 +857,13 @@ static int flexcan_chip_start(struct net
* choose format C
* set max mailbox number
*/
- reg_mcr = flexcan_read(&regs->mcr);
+ reg_mcr = priv->read(&regs->mcr);
reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS |
FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
- flexcan_write(reg_mcr, &regs->mcr);
+ priv->write(reg_mcr, &regs->mcr);
/* CTRL
*
@@ -861,7 +876,7 @@ static int flexcan_chip_start(struct net
* enable bus off interrupt
* (== FLEXCAN_CTRL_ERR_STATE)
*/
- reg_ctrl = flexcan_read(&regs->ctrl);
+ reg_ctrl = priv->read(&regs->ctrl);
reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
FLEXCAN_CTRL_ERR_STATE;
@@ -881,29 +896,29 @@ static int flexcan_chip_start(struct net
/* leave interrupts disabled for now */
reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
- flexcan_write(reg_ctrl, &regs->ctrl);
+ priv->write(reg_ctrl, &regs->ctrl);
/* clear and invalidate all mailboxes first */
for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->mb); i++) {
- flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
+ priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
&regs->mb[i].can_ctrl);
}
/* Errata ERR005829: mark first TX mailbox as INACTIVE */
- flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+ priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
&regs->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
/* mark TX mailbox as INACTIVE */
- flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+ priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
&regs->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
/* acceptance mask/acceptance code (accept everything) */
- flexcan_write(0x0, &regs->rxgmask);
- flexcan_write(0x0, &regs->rx14mask);
- flexcan_write(0x0, &regs->rx15mask);
+ priv->write(0x0, &regs->rxgmask);
+ priv->write(0x0, &regs->rx14mask);
+ priv->write(0x0, &regs->rx15mask);
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
- flexcan_write(0x0, &regs->rxfgmask);
+ priv->write(0x0, &regs->rxfgmask);
/* On Vybrid, disable memory error detection interrupts
* and freeze mode.
@@ -916,16 +931,16 @@ static int flexcan_chip_start(struct net
* and Correction of Memory Errors" to write to
* MECR register
*/
- reg_ctrl2 = flexcan_read(&regs->ctrl2);
+ reg_ctrl2 = priv->read(&regs->ctrl2);
reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
- flexcan_write(reg_ctrl2, &regs->ctrl2);
+ priv->write(reg_ctrl2, &regs->ctrl2);
- reg_mecr = flexcan_read(&regs->mecr);
+ reg_mecr = priv->read(&regs->mecr);
reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
- flexcan_write(reg_mecr, &regs->mecr);
+ priv->write(reg_mecr, &regs->mecr);
reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
FLEXCAN_MECR_FANCEI_MSK);
- flexcan_write(reg_mecr, &regs->mecr);
+ priv->write(reg_mecr, &regs->mecr);
}
err = flexcan_transceiver_enable(priv);
@@ -941,13 +956,13 @@ static int flexcan_chip_start(struct net
/* enable interrupts atomically */
disable_irq(dev->irq);
- flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
- flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
+ priv->write(priv->reg_ctrl_default, &regs->ctrl);
+ priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
enable_irq(dev->irq);
/* print chip status */
netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
- flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
+ priv->read(&regs->mcr), priv->read(&regs->ctrl));
return 0;
@@ -972,8 +987,8 @@ static void flexcan_chip_stop(struct net
flexcan_chip_disable(priv);
/* Disable all interrupts */
- flexcan_write(0, &regs->imask1);
- flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
+ priv->write(0, &regs->imask1);
+ priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
&regs->ctrl);
flexcan_transceiver_disable(priv);
@@ -1089,25 +1104,25 @@ static int register_flexcandev(struct ne
err = flexcan_chip_disable(priv);
if (err)
goto out_disable_per;
- reg = flexcan_read(&regs->ctrl);
+ reg = priv->read(&regs->ctrl);
reg |= FLEXCAN_CTRL_CLK_SRC;
- flexcan_write(reg, &regs->ctrl);
+ priv->write(reg, &regs->ctrl);
err = flexcan_chip_enable(priv);
if (err)
goto out_chip_disable;
/* set freeze, halt and activate FIFO, restrict register access */
- reg = flexcan_read(&regs->mcr);
+ reg = priv->read(&regs->mcr);
reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
- flexcan_write(reg, &regs->mcr);
+ priv->write(reg, &regs->mcr);
/* Currently we only support newer versions of this core
* featuring a RX FIFO. Older cores found on some Coldfire
* derivates are not yet supported.
*/
- reg = flexcan_read(&regs->mcr);
+ reg = priv->read(&regs->mcr);
if (!(reg & FLEXCAN_MCR_FEN)) {
netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
err = -ENODEV;
@@ -1135,8 +1150,12 @@ static void unregister_flexcandev(struct
static const struct of_device_id flexcan_of_match[] = {
{ .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
{ .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
+ { .compatible = "fsl,imx53-flexcan", .data = &fsl_p1010_devtype_data, },
+ { .compatible = "fsl,imx35-flexcan", .data = &fsl_p1010_devtype_data, },
+ { .compatible = "fsl,imx25-flexcan", .data = &fsl_p1010_devtype_data, },
{ .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
{ .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
+ { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, flexcan_of_match);
@@ -1213,6 +1232,21 @@ static int flexcan_probe(struct platform
dev->flags |= IFF_ECHO;
priv = netdev_priv(dev);
+
+ if (of_property_read_bool(pdev->dev.of_node, "big-endian")) {
+ priv->read = flexcan_read_be;
+ priv->write = flexcan_write_be;
+ } else {
+ if (of_device_is_compatible(pdev->dev.of_node,
+ "fsl,p1010-flexcan")) {
+ priv->read = flexcan_read_be;
+ priv->write = flexcan_write_be;
+ } else {
+ priv->read = flexcan_read_le;
+ priv->write = flexcan_write_le;
+ }
+ }
+
priv->can.clock.freq = clock_freq;
priv->can.bittiming_const = &flexcan_bittiming_const;
priv->can.do_set_mode = flexcan_set_mode;

239
target/linux/layerscape/patches-4.9/820-kvm-support-layerscape.patch Normal file
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@ -0,0 +1,239 @@
From fe22151c95c02c6bb145ea6c3685941e8fb09d60 Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Thu, 5 Jul 2018 17:43:16 +0800
Subject: [PATCH 32/32] kvm: support layerscape
This is an integrated patch for layerscape kvm support.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
arch/arm/include/asm/kvm_mmu.h | 3 +-
arch/arm/kvm/mmu.c | 56 ++++++++++++++++++++++++++++++--
arch/arm64/include/asm/kvm_mmu.h | 14 ++++++--
virt/kvm/arm/vgic/vgic-its.c | 24 +++++++++++---
virt/kvm/arm/vgic/vgic-v2.c | 3 +-
5 files changed, 88 insertions(+), 12 deletions(-)
--- a/arch/arm/include/asm/kvm_mmu.h
+++ b/arch/arm/include/asm/kvm_mmu.h
@@ -55,7 +55,8 @@ void stage2_unmap_vm(struct kvm *kvm);
int kvm_alloc_stage2_pgd(struct kvm *kvm);
void kvm_free_stage2_pgd(struct kvm *kvm);
int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
- phys_addr_t pa, unsigned long size, bool writable);
+ phys_addr_t pa, unsigned long size, bool writable,
+ pgprot_t prot);
int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -1020,9 +1020,11 @@ static int stage2_pmdp_test_and_clear_yo
* @guest_ipa: The IPA at which to insert the mapping
* @pa: The physical address of the device
* @size: The size of the mapping
+ * @prot: S2 page translation bits
*/
int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
- phys_addr_t pa, unsigned long size, bool writable)
+ phys_addr_t pa, unsigned long size, bool writable,
+ pgprot_t prot)
{
phys_addr_t addr, end;
int ret = 0;
@@ -1033,7 +1035,7 @@ int kvm_phys_addr_ioremap(struct kvm *kv
pfn = __phys_to_pfn(pa);
for (addr = guest_ipa; addr < end; addr += PAGE_SIZE) {
- pte_t pte = pfn_pte(pfn, PAGE_S2_DEVICE);
+ pte_t pte = pfn_pte(pfn, prot);
if (writable)
pte = kvm_s2pte_mkwrite(pte);
@@ -1057,6 +1059,30 @@ out:
return ret;
}
+#ifdef CONFIG_ARM64
+static pgprot_t stage1_to_stage2_pgprot(pgprot_t prot)
+{
+ switch (pgprot_val(prot) & PTE_ATTRINDX_MASK) {
+ case PTE_ATTRINDX(MT_DEVICE_nGnRE):
+ case PTE_ATTRINDX(MT_DEVICE_nGnRnE):
+ case PTE_ATTRINDX(MT_DEVICE_GRE):
+ return PAGE_S2_DEVICE;
+ case PTE_ATTRINDX(MT_NORMAL_NC):
+ case PTE_ATTRINDX(MT_NORMAL):
+ return (pgprot_val(prot) & PTE_SHARED)
+ ? PAGE_S2
+ : PAGE_S2_NS;
+ }
+
+ return PAGE_S2_DEVICE;
+}
+#else
+static pgprot_t stage1_to_stage2_pgprot(pgprot_t prot)
+{
+ return PAGE_S2_DEVICE;
+}
+#endif
+
static bool transparent_hugepage_adjust(kvm_pfn_t *pfnp, phys_addr_t *ipap)
{
kvm_pfn_t pfn = *pfnp;
@@ -1308,6 +1334,19 @@ static int user_mem_abort(struct kvm_vcp
hugetlb = true;
gfn = (fault_ipa & PMD_MASK) >> PAGE_SHIFT;
} else {
+ if (!is_vm_hugetlb_page(vma)) {
+ pte_t *pte;
+ spinlock_t *ptl;
+ pgprot_t prot;
+
+ pte = get_locked_pte(current->mm, memslot->userspace_addr, &ptl);
+ prot = stage1_to_stage2_pgprot(__pgprot(pte_val(*pte)));
+ pte_unmap_unlock(pte, ptl);
+#ifdef CONFIG_ARM64
+ if (pgprot_val(prot) == pgprot_val(PAGE_S2_NS))
+ mem_type = PAGE_S2_NS;
+#endif
+ }
/*
* Pages belonging to memslots that don't have the same
* alignment for userspace and IPA cannot be mapped using
@@ -1345,6 +1384,11 @@ static int user_mem_abort(struct kvm_vcp
if (is_error_noslot_pfn(pfn))
return -EFAULT;
+#ifdef CONFIG_ARM64
+ if (pgprot_val(mem_type) == pgprot_val(PAGE_S2_NS)) {
+ flags |= KVM_S2PTE_FLAG_IS_IOMAP;
+ } else
+#endif
if (kvm_is_device_pfn(pfn)) {
mem_type = PAGE_S2_DEVICE;
flags |= KVM_S2PTE_FLAG_IS_IOMAP;
@@ -1882,6 +1926,9 @@ int kvm_arch_prepare_memory_region(struc
gpa_t gpa = mem->guest_phys_addr +
(vm_start - mem->userspace_addr);
phys_addr_t pa;
+ pgprot_t prot;
+ pte_t *pte;
+ spinlock_t *ptl;
pa = (phys_addr_t)vma->vm_pgoff << PAGE_SHIFT;
pa += vm_start - vma->vm_start;
@@ -1891,10 +1938,13 @@ int kvm_arch_prepare_memory_region(struc
ret = -EINVAL;
goto out;
}
+ pte = get_locked_pte(current->mm, mem->userspace_addr, &ptl);
+ prot = stage1_to_stage2_pgprot(__pgprot(pte_val(*pte)));
+ pte_unmap_unlock(pte, ptl);
ret = kvm_phys_addr_ioremap(kvm, gpa, pa,
vm_end - vm_start,
- writable);
+ writable, prot);
if (ret)
break;
}
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -167,7 +167,8 @@ void stage2_unmap_vm(struct kvm *kvm);
int kvm_alloc_stage2_pgd(struct kvm *kvm);
void kvm_free_stage2_pgd(struct kvm *kvm);
int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
- phys_addr_t pa, unsigned long size, bool writable);
+ phys_addr_t pa, unsigned long size, bool writable,
+ pgprot_t prot);
int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
@@ -274,8 +275,15 @@ static inline void __coherent_cache_gues
static inline void __kvm_flush_dcache_pte(pte_t pte)
{
- struct page *page = pte_page(pte);
- kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE);
+ if (pfn_valid(pte_pfn(pte))) {
+ struct page *page = pte_page(pte);
+ kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE);
+ } else {
+ void __iomem *va = ioremap_cache_ns(pte_pfn(pte) << PAGE_SHIFT, PAGE_SIZE);
+
+ kvm_flush_dcache_to_poc(va, PAGE_SIZE);
+ iounmap(va);
+ }
}
static inline void __kvm_flush_dcache_pmd(pmd_t pmd)
--- a/virt/kvm/arm/vgic/vgic-its.c
+++ b/virt/kvm/arm/vgic/vgic-its.c
@@ -176,6 +176,8 @@ static struct its_itte *find_itte(struct
#define GIC_LPI_OFFSET 8192
+#define VITS_TYPER_DEVBITS 17
+
/*
* Finds and returns a collection in the ITS collection table.
* Must be called with the its_lock mutex held.
@@ -375,7 +377,7 @@ static unsigned long vgic_mmio_read_its_
* To avoid memory waste in the guest, we keep the number of IDBits and
* DevBits low - as least for the time being.
*/
- reg |= 0x0f << GITS_TYPER_DEVBITS_SHIFT;
+ reg |= GIC_ENCODE_SZ(VITS_TYPER_DEVBITS, 5) << GITS_TYPER_DEVBITS_SHIFT;
reg |= 0x0f << GITS_TYPER_IDBITS_SHIFT;
return extract_bytes(reg, addr & 7, len);
@@ -601,16 +603,30 @@ static int vgic_its_cmd_handle_movi(stru
* Check whether an ID can be stored into the corresponding guest table.
* For a direct table this is pretty easy, but gets a bit nasty for
* indirect tables. We check whether the resulting guest physical address
- * is actually valid (covered by a memslot and guest accessbible).
+ * is actually valid (covered by a memslot and guest accessible).
* For this we have to read the respective first level entry.
*/
-static bool vgic_its_check_id(struct vgic_its *its, u64 baser, int id)
+static bool vgic_its_check_id(struct vgic_its *its, u64 baser, u32 id)
{
int l1_tbl_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
+ u64 indirect_ptr, type = GITS_BASER_TYPE(baser);
int index;
- u64 indirect_ptr;
gfn_t gfn;
+ switch (type) {
+ case GITS_BASER_TYPE_DEVICE:
+ if (id >= BIT_ULL(VITS_TYPER_DEVBITS))
+ return false;
+ break;
+ case GITS_BASER_TYPE_COLLECTION:
+ /* as GITS_TYPER.CIL == 0, ITS supports 16-bit collection ID */
+ if (id >= BIT_ULL(16))
+ return false;
+ break;
+ default:
+ return false;
+ }
+
if (!(baser & GITS_BASER_INDIRECT)) {
phys_addr_t addr;
--- a/virt/kvm/arm/vgic/vgic-v2.c
+++ b/virt/kvm/arm/vgic/vgic-v2.c
@@ -290,7 +290,8 @@ int vgic_v2_map_resources(struct kvm *kv
if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
kvm_vgic_global_state.vcpu_base,
- KVM_VGIC_V2_CPU_SIZE, true);
+ KVM_VGIC_V2_CPU_SIZE, true,
+ PAGE_S2_DEVICE);
if (ret) {
kvm_err("Unable to remap VGIC CPU to VCPU\n");
goto out;

0
target/linux/layerscape/patches-4.9/820-rgmii-fixed-link.patch → target/linux/layerscape/patches-4.9/822-rgmii-fixed-link.patch
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