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realtek: Adding RTL930X sub-target

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This adds the RTL931X sub-target in the realtek target Makefile.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This commit is contained in:
Birger Koblitz 2022-01-10 11:30:47 +01:00 committed by Daniel Golle
parent 5cb2828092
commit a75b9e3ecb
2 changed files with 34 additions and 89 deletions
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2
target/linux/realtek/Makefile
View File

@ -7,7 +7,7 @@ BOARD:=realtek
BOARDNAME:=Realtek MIPS BOARDNAME:=Realtek MIPS
DEVICE_TYPE:=basic DEVICE_TYPE:=basic
FEATURES:=ramdisk squashfs FEATURES:=ramdisk squashfs
SUBTARGETS:=rtl838x rtl839x SUBTARGETS:=rtl838x rtl839x rtl930x
KERNEL_PATCHVER:=5.10 KERNEL_PATCHVER:=5.10

121
target/linux/realtek/dts-5.10/rtl930x.dtsi
View File

@ -2,51 +2,6 @@
/dts-v1/; /dts-v1/;
#define STRINGIZE(s) #s
#define LAN_LABEL(p, s) STRINGIZE(p ## s)
#define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)
#define INTERNAL_PHY(n) \
phy##n: ethernet-phy@##n { \
reg = <##n>; \
compatible = "ethernet-phy-ieee802.3-c22"; \
phy-is-integrated; \
};
#define EXTERNAL_PHY(n) \
phy##n: ethernet-phy@##n { \
reg = <##n>; \
compatible = "ethernet-phy-ieee802.3-c22"; \
};
#define EXTERNAL_SFP_PHY(n) \
phy##n: ethernet-phy@##n { \
compatible = "ethernet-phy-ieee802.3-c22"; \
sfp; \
media = "fibre"; \
reg = <##n>; \
};
#define SWITCH_PORT(n, s, m) \
port@##n { \
reg = <##n>; \
label = SWITCH_PORT_LABEL(s) ; \
phy-handle = <&phy##n>; \
phy-mode = #m ; \
};
#define SWITCH_SFP_PORT(n, s, m) \
port@##n { \
reg = <##n>; \
label = SWITCH_PORT_LABEL(s) ; \
phy-handle = <&phy##n>; \
phy-mode = #m ; \
fixed-link { \
speed = <1000>; \
full-duplex; \
}; \
};
/ { / {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
@ -70,7 +25,7 @@
}; };
chosen { chosen {
bootargs = "console=ttyS0,115200"; bootargs = "console=ttyS0,38400";
}; };
cpuintc: cpuintc { cpuintc: cpuintc {
@ -92,35 +47,24 @@
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x18000000 0x10000>; ranges = <0x0 0x18000000 0x10000>;
intc: rtlintc@3000 { intc: interrupt-controller@3000 {
compatible = "realtek,rtl-intc"; compatible = "realtek,rtl9300-intc", "realtek,rtl-intc";
reg = <0x3000 0x20>; reg = <0x3000 0x18>, <0x3018 0x18>;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller; interrupt-controller;
interrupt-map = #interrupt-cells = <2>;
<31 &cpuintc 1>, /* UART1 */
<30 &cpuintc 2>, /* UART0 */ interrupt-parent = <&cpuintc>;
<28 &cpuintc 1>, /* USB_H2 */ interrupts = <2>, <3>, <4>, <5>, <6>, <7>;
<24 &cpuintc 4>, /* NIC */
<23 &cpuintc 3>, /* SWCORE */
<13 &cpuintc 4>, /* GPIO_ABCD */
<11 &cpuintc 1>, /* TC4 */
<10 &cpuintc 1>, /* TC3 */
<9 &cpuintc 1>, /* TC2 */
<8 &cpuintc 1>, /* TC1 */
<7 &cpuintc 5>, /* TC0 */
<6 &cpuintc 5>, /* WDT_IP2 */
<5 &cpuintc 4>; /* WDT_IP1 */
}; };
timer: timer@3200 { rtl9300clock: rtl9300clock@3200 {
compatible = "realtek,rtl9300-timer"; compatible = "realtek,rtl9300clock";
reg = <0x3200 0x60>; reg = <0xb8003200 0x10>;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
interrupts = <8>; interrupts = <7 1>, <8 2>;
interrupt-names = "ostimer";
clocks = <&lx_clk>;
}; };
spi0: spi@1200 { spi0: spi@1200 {
@ -138,7 +82,7 @@
clocks = <&lx_clk>; clocks = <&lx_clk>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
interrupts = <30>; interrupts = <30 1>;
reg-io-width = <1>; reg-io-width = <1>;
reg-shift = <2>; reg-shift = <2>;
@ -153,7 +97,7 @@
clocks = <&lx_clk>; clocks = <&lx_clk>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
interrupts = <31>; interrupts = <31 0>;
reg-io-width = <1>; reg-io-width = <1>;
reg-shift = <2>; reg-shift = <2>;
@ -174,32 +118,32 @@
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
interrupt-names = "phase1", "phase2"; interrupt-names = "phase1", "phase2";
interrupts = <5>, <6>; interrupts = <5 4>, <6 4>;
}; };
gpio0: gpio-controller@3500 { gpio0: gpio-controller@3300 {
compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio"; compatible = "realtek,rtl9300-gpio", "realtek,otto-gpio";
reg = <0x3500 0x20>; reg = <0x3300 0x1c>, <0x3338 0x8>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
ngpios = <32>; ngpios = <24>;
interrupt-parent = <&intc>;
interrupts = <31>;
/* interrupt-controller;
* currently, RTL930x GPIO is not supported in #interrupt-cells = <2>;
* upstreamed driver (gpio-realtek-otto) interrupt-parent = <&intc>;
*/ interrupts = <13 1>;
status = "disabled";
}; };
}; };
ethernet0: ethernet@1b00a300 { ethernet0: ethernet@1b00a300 {
compatible = "realtek,rtl838x-eth"; compatible = "realtek,rtl838x-eth";
reg = <0x1b00a300 0x100>; reg = <0x1b00a300 0x100>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
interrupts = <24>; interrupts = <24 3>;
#interrupt-cells = <1>;
phy-mode = "internal"; phy-mode = "internal";
fixed-link { fixed-link {
@ -210,8 +154,9 @@
switch0: switch@1b000000 { switch0: switch@1b000000 {
compatible = "realtek,rtl83xx-switch"; compatible = "realtek,rtl83xx-switch";
status = "okay";
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
interrupts = <20>; interrupts = <23 2>;
}; };
}; };