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merge 2.6.28 patches

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SVN-Revision: 16929
This commit is contained in:
Gabor Juhos 2009-07-20 08:11:07 +00:00
parent b78215b71d
commit a6bea07a5e
8 changed files with 80 additions and 134 deletions
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0
target/linux/ppc40x/patches/101-powerpc-add-EBC_BXCR_BW-defines.patch → target/linux/ppc40x/patches/003-powerpc-add-EBC_BXCR_BW-defines.patch
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42
target/linux/ppc40x/patches/006-magicboxv2.patch
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@ -1,10 +1,11 @@
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-magicboxv2.c
@@ -0,0 +1,40 @@
@@ -0,0 +1,69 @@
+/*
+ * Old U-boot compatibility for Magicbox v2
+ *
+ * Author: Imre Kaloz <kaloz@openwrt.org>
+ * Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
@ -25,8 +26,36 @@
+
+static bd_t bd;
+
+static void fixup_cf_card(void)
+{
+#define DCRN_CPC0_PCI_BASE 0xf9
+#define CF_CS0_BASE 0xff100000
+#define CF_CS1_BASE 0xff200000
+
+ /* Turn on PerWE instead of PCIsomething */
+ mtdcr(DCRN_CPC0_PCI_BASE,
+ mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27));
+
+ /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
+
+ /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
+
+#undef DCRN_CPC0_PCI_BASE
+#undef CF_CS0_BASE
+#undef CF_CS1_BASE
+}
+
+static void magicboxv2_fixups(void)
+{
+ fixup_cf_card();
+ ibm405ep_fixup_clocks(25000000);
+ ibm4xx_sdram_fixup_memsize();
+ dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
@ -43,11 +72,12 @@
+}
--- /dev/null
+++ b/arch/powerpc/boot/dts/magicboxv2.dts
@@ -0,0 +1,250 @@
@@ -0,0 +1,259 @@
+/*
+ * Device Tree Source for Magicbox v2
+ *
+ * Copyright 2008 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright 2009 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * Based on walnut.dts
+ *
@ -229,6 +259,14 @@
+ */
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ cf_card@ff100000 {
+ compatible = "magicbox-cf";
+ reg = <0x00000000 0xff100000 0x00001000
+ 0x00000000 0xff200000 0x00001000>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >;
+ };
+
+ nor_flash@ffc00000 {
+ compatible = "cfi-flash";
+ bank-width = <2>;

40
target/linux/ppc40x/patches/007-openrb-light.patch
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@ -49,7 +49,7 @@
static int __init ppc40x_probe(void)
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-openrb-light.c
@@ -0,0 +1,41 @@
@@ -0,0 +1,69 @@
+/*
+ * Old U-boot compatibility for OpenRB Light board
+ *
@ -74,8 +74,36 @@
+
+static bd_t bd;
+
+static void fixup_cf_card(void)
+{
+#define DCRN_CPC0_PCI_BASE 0xf9
+#define CF_CS0_BASE 0xff100000
+#define CF_CS1_BASE 0xff200000
+
+ /* Turn on PerWE instead of PCIsomething */
+ mtdcr(DCRN_CPC0_PCI_BASE,
+ mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27));
+
+ /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
+
+ /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
+
+#undef DCRN_CPC0_PCI_BASE
+#undef CF_CS0_BASE
+#undef CF_CS1_BASE
+}
+
+static void openrb_light_fixups(void)
+{
+ fixup_cf_card();
+ ibm405ep_fixup_clocks(33333000);
+ ibm4xx_sdram_fixup_memsize();
+ dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
@ -93,7 +121,7 @@
+
--- /dev/null
+++ b/arch/powerpc/boot/dts/openrb-light.dts
@@ -0,0 +1,244 @@
@@ -0,0 +1,252 @@
+/*
+ * Device Tree Source for OpenRB Light board
+ *
@ -273,6 +301,14 @@
+ */
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ cf_card@ff100000 {
+ compatible = "magicbox-cf";
+ reg = <0x00000000 0xff100000 0x00001000
+ 0x00000000 0xff200000 0x00001000>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >;
+ };
+
+ nor_flash@ff800000 {
+ compatible = "cfi-flash";
+ bank-width = <2>;

39
target/linux/ppc40x/patches/102-openrb-light-cf-card-fixup.patch
View File

@ -1,39 +0,0 @@
--- a/arch/powerpc/boot/cuboot-openrb-light.c
+++ b/arch/powerpc/boot/cuboot-openrb-light.c
@@ -22,8 +22,36 @@
static bd_t bd;
+static void fixup_cf_card(void)
+{
+#define DCRN_CPC0_PCI_BASE 0xf9
+#define CF_CS0_BASE 0xff100000
+#define CF_CS1_BASE 0xff200000
+
+ /* Turn on PerWE instead of PCIsomething */
+ mtdcr(DCRN_CPC0_PCI_BASE,
+ mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27));
+
+ /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
+
+ /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
+
+#undef DCRN_CPC0_PCI_BASE
+#undef CF_CS0_BASE
+#undef CF_CS1_BASE
+}
+
static void openrb_light_fixups(void)
{
+ fixup_cf_card();
ibm405ep_fixup_clocks(33333000);
ibm4xx_sdram_fixup_memsize();
dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);

17
target/linux/ppc40x/patches/103-openrb-light-add-cf-card-to-dts.patch
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@ -1,17 +0,0 @@
--- a/arch/powerpc/boot/dts/openrb-light.dts
+++ b/arch/powerpc/boot/dts/openrb-light.dts
@@ -177,6 +177,14 @@
*/
clock-frequency = <0>; /* Filled in by zImage */
+ cf_card@ff100000 {
+ compatible = "magicbox-cf";
+ reg = <0x00000000 0xff100000 0x00001000
+ 0x00000000 0xff200000 0x00001000>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >;
+ };
+
nor_flash@ff800000 {
compatible = "cfi-flash";
bank-width = <2>;

47
target/linux/ppc40x/patches/104-magicboxv2-cf-card-fixup.patch
View File

@ -1,47 +0,0 @@
--- a/arch/powerpc/boot/cuboot-magicboxv2.c
+++ b/arch/powerpc/boot/cuboot-magicboxv2.c
@@ -2,6 +2,7 @@
* Old U-boot compatibility for Magicbox v2
*
* Author: Imre Kaloz <kaloz@openwrt.org>
+ * Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
@@ -22,8 +23,36 @@
static bd_t bd;
+static void fixup_cf_card(void)
+{
+#define DCRN_CPC0_PCI_BASE 0xf9
+#define CF_CS0_BASE 0xff100000
+#define CF_CS1_BASE 0xff200000
+
+ /* Turn on PerWE instead of PCIsomething */
+ mtdcr(DCRN_CPC0_PCI_BASE,
+ mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27));
+
+ /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
+
+ /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
+
+#undef DCRN_CPC0_PCI_BASE
+#undef CF_CS0_BASE
+#undef CF_CS1_BASE
+}
+
static void magicboxv2_fixups(void)
{
+ fixup_cf_card();
ibm405ep_fixup_clocks(25000000);
ibm4xx_sdram_fixup_memsize();
dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);

25
target/linux/ppc40x/patches/105-magicboxv2-add-cf-card-to-dts.patch
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@ -1,25 +0,0 @@
--- a/arch/powerpc/boot/dts/magicboxv2.dts
+++ b/arch/powerpc/boot/dts/magicboxv2.dts
@@ -2,6 +2,7 @@
* Device Tree Source for Magicbox v2
*
* Copyright 2008 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright 2009 Gabor Juhos <juhosg@openwrt.org>
*
* Based on walnut.dts
*
@@ -183,6 +184,14 @@
*/
clock-frequency = <0>; /* Filled in by zImage */
+ cf_card@ff100000 {
+ compatible = "magicbox-cf";
+ reg = <0x00000000 0xff100000 0x00001000
+ 0x00000000 0xff200000 0x00001000>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >;
+ };
+
nor_flash@ffc00000 {
compatible = "cfi-flash";
bank-width = <2>;