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qualcommbe: ipq95xx: Backport cpufreq patch and enable RPM
Backport CPUFreq patch and enable RPM. This is to enable CPU Frequency scaling and regulators. Link: https://github.com/openwrt/openwrt/pull/17725 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This commit is contained in:
Christian Marangi
parent
93173aee96
commit
a181fc8b31
@ -46,3 +46,15 @@ CONFIG_QCOM_PPE=y
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CONFIG_QCOM_IPA=y
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CONFIG_INTERCONNECT_QCOM=y
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CONFIG_INTERCONNECT_QCOM_OSM_L3=y
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CONFIG_MTD_SPI_NAND=y
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CONFIG_QCOM_SMD_RPM=y
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CONFIG_REGULATOR_QCOM_SMD_RPM=y
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# CONFIG_QCOM_CLK_SMD_RPM is not set
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# CONFIG_QCOM_RPMPD is not set
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# CONFIG_INTERCONNECT_QCOM_MSM8916 is not set
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# CONFIG_INTERCONNECT_QCOM_MSM8939 is not set
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# CONFIG_INTERCONNECT_QCOM_MSM8996 is not set
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# CONFIG_INTERCONNECT_QCOM_MSM8974 is not set
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# CONFIG_INTERCONNECT_QCOM_QCM2290 is not set
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# CONFIG_INTERCONNECT_QCOM_QCS404 is not set
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# CONFIG_INTERCONNECT_QCOM_SDM660 is not set
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@ -0,0 +1,68 @@
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From ba5a61a08d83b18b99c461b4ddb9009947a4aa0e Mon Sep 17 00:00:00 2001
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From: Varadarajan Narayanan <quic_varada@quicinc.com>
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Date: Tue, 31 Oct 2023 12:41:38 +0530
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Subject: [PATCH 1/2] cpufreq: qcom-nvmem: Enable cpufreq for ipq53xx
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IPQ53xx have different OPPs available for the CPU based on
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SoC variant. This can be determined through use of an eFuse
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register present in the silicon.
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Added support for ipq53xx on nvmem driver which helps to
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determine OPPs at runtime based on the eFuse register which
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has the CPU frequency limits. opp-supported-hw dt binding
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can be used to indicate the available OPPs for each limit.
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nvmem driver also creates the "cpufreq-dt" platform_device after
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passing the version matching data to the OPP framework so that the
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cpufreq-dt handles the actual cpufreq implementation.
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Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
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Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
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[ Viresh: Fixed subject ]
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Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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---
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drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
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drivers/cpufreq/qcom-cpufreq-nvmem.c | 6 ++++++
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2 files changed, 7 insertions(+)
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diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
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index 07181913448f..53da25589e5f 100644
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--- a/drivers/cpufreq/cpufreq-dt-platdev.c
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+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
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@@ -180,6 +180,7 @@ static const struct of_device_id blocklist[] __initconst = {
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{ .compatible = "ti,am62a7", },
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{ .compatible = "ti,am62p5", },
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+ { .compatible = "qcom,ipq5332", },
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{ .compatible = "qcom,ipq8064", },
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{ .compatible = "qcom,apq8064", },
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{ .compatible = "qcom,msm8974", },
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diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
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index 158c0e139185..4f7af70169e0 100644
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--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
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+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
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@@ -183,6 +183,11 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
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switch (msm_id) {
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case QCOM_ID_MSM8996:
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case QCOM_ID_APQ8096:
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+ case QCOM_ID_IPQ5332:
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+ case QCOM_ID_IPQ5322:
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+ case QCOM_ID_IPQ5312:
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+ case QCOM_ID_IPQ5302:
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+ case QCOM_ID_IPQ5300:
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drv->versions = 1 << (unsigned int)(*speedbin);
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break;
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case QCOM_ID_MSM8996SG:
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@@ -541,6 +546,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
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{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
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{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
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{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
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+ { .compatible = "qcom,ipq5332", .data = &match_data_kryo },
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{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
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{ .compatible = "qcom,apq8064", .data = &match_data_krait },
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{ .compatible = "qcom,msm8974", .data = &match_data_krait },
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--
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2.45.2
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@ -0,0 +1,64 @@
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From 5b5b5806f22390808b8e8fa180fe35b003a4a74d Mon Sep 17 00:00:00 2001
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From: Varadarajan Narayanan <quic_varada@quicinc.com>
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Date: Tue, 31 Oct 2023 12:41:39 +0530
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Subject: [PATCH 2/2] cpufreq: qcom-nvmem: Introduce cpufreq for ipq95xx
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IPQ95xx SoCs have different OPPs available for the CPU based on
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the SoC variant. This can be determined from an eFuse register
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present in the silicon.
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Added support for ipq95xx on nvmem driver which helps to
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determine OPPs at runtime based on the eFuse register which
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has the CPU frequency limits. opp-supported-hw dt binding
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can be used to indicate the available OPPs for each limit.
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Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
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Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
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Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
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[ Viresh: Fixed subject ]
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Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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---
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drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
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drivers/cpufreq/qcom-cpufreq-nvmem.c | 6 ++++++
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2 files changed, 7 insertions(+)
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diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
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index 53da25589e5f..bd1e1357cef8 100644
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--- a/drivers/cpufreq/cpufreq-dt-platdev.c
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+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
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@@ -184,6 +184,7 @@ static const struct of_device_id blocklist[] __initconst = {
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{ .compatible = "qcom,ipq5332", },
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{ .compatible = "qcom,ipq8064", },
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+ { .compatible = "qcom,ipq9574", },
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{ .compatible = "qcom,apq8064", },
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{ .compatible = "qcom,msm8974", },
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{ .compatible = "qcom,msm8960", },
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diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
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index 4f7af70169e0..6355a39418c5 100644
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--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
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+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
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@@ -188,6 +188,11 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
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case QCOM_ID_IPQ5312:
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case QCOM_ID_IPQ5302:
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case QCOM_ID_IPQ5300:
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+ case QCOM_ID_IPQ9514:
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+ case QCOM_ID_IPQ9550:
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+ case QCOM_ID_IPQ9554:
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+ case QCOM_ID_IPQ9570:
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+ case QCOM_ID_IPQ9574:
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drv->versions = 1 << (unsigned int)(*speedbin);
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break;
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case QCOM_ID_MSM8996SG:
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@@ -551,6 +556,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
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{ .compatible = "qcom,ipq5332", .data = &match_data_kryo },
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{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
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{ .compatible = "qcom,apq8064", .data = &match_data_krait },
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+ { .compatible = "qcom,ipq9574", .data = &match_data_kryo },
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{ .compatible = "qcom,msm8974", .data = &match_data_krait },
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{ .compatible = "qcom,msm8960", .data = &match_data_krait },
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{},
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--
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2.45.2
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@ -0,0 +1,110 @@
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From b36074357baf2794c825ea1c145de1d22b15380b Mon Sep 17 00:00:00 2001
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From: Varadarajan Narayanan <quic_varada@quicinc.com>
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Date: Fri, 20 Oct 2023 11:49:39 +0530
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Subject: [PATCH] arm64: dts: qcom: ipq9574: populate the opp table based on
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the eFuse
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IPQ95xx SoCs have different OPPs available for the CPU based on
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SoC variant. This can be determined from an eFuse register
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present in the silicon.
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Add support to read the eFuse and populate the OPPs based on it.
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Frequency 1.2GHz 1.8GHz 1.5GHz No opp-supported-hw
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Limit
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------------------------------------------------------------
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936000000 1 1 1 1 0xf
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1104000000 1 1 1 1 0xf
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1200000000 1 1 1 1 0xf
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1416000000 0 1 1 1 0x7
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1488000000 0 1 1 1 0x7
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1800000000 0 1 0 1 0x5
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2208000000 0 0 0 1 0x1
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-----------------------------------------------------------
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Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
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Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
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Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
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Link: https://lore.kernel.org/r/14ab08b7cfd904433ca6065fac798d4f221c9d95.1697781921.git.quic_varada@quicinc.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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arch/arm64/boot/dts/qcom/ipq9574.dtsi | 21 ++++++++++++++++++++-
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1 file changed, 20 insertions(+), 1 deletion(-)
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diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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index 8a72ad4afd03..d4b7e215fc92 100644
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--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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@@ -106,42 +106,56 @@ memory@40000000 {
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};
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cpu_opp_table: opp-table-cpu {
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- compatible = "operating-points-v2";
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+ compatible = "operating-points-v2-kryo-cpu";
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opp-shared;
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+ nvmem-cells = <&cpu_speed_bin>;
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opp-936000000 {
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opp-hz = /bits/ 64 <936000000>;
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opp-microvolt = <725000>;
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+ opp-supported-hw = <0xf>;
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clock-latency-ns = <200000>;
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};
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opp-1104000000 {
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opp-hz = /bits/ 64 <1104000000>;
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opp-microvolt = <787500>;
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+ opp-supported-hw = <0xf>;
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+ clock-latency-ns = <200000>;
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+ };
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+
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+ opp-1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <862500>;
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+ opp-supported-hw = <0xf>;
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clock-latency-ns = <200000>;
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};
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opp-1416000000 {
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opp-hz = /bits/ 64 <1416000000>;
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opp-microvolt = <862500>;
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+ opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-1488000000 {
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opp-hz = /bits/ 64 <1488000000>;
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opp-microvolt = <925000>;
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+ opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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};
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opp-1800000000 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <987500>;
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+ opp-supported-hw = <0x5>;
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clock-latency-ns = <200000>;
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};
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opp-2208000000 {
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opp-hz = /bits/ 64 <2208000000>;
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opp-microvolt = <1062500>;
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+ opp-supported-hw = <0x1>;
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clock-latency-ns = <200000>;
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};
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};
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@@ -223,6 +237,11 @@ qfprom: efuse@a4000 {
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reg = <0x000a4000 0x5a1>;
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#address-cells = <1>;
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#size-cells = <1>;
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+
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+ cpu_speed_bin: cpu-speed-bin@15 {
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+ reg = <0x15 0x2>;
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+ bits = <7 2>;
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+ };
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};
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cryptobam: dma-controller@704000 {
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--
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2.45.2
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