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ipq40xx: add IPQESS ethernet driver
IPQESS is the EDMA replacement driver for the IPQ40xx SoC built-in ethernet controller. Unlike EDMA it is Phylink based and doesnt touch PHY-s directly. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
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# SPDX-License-Identifier: GPL-2.0-only
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#
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# Makefile for the IPQ ESS driver
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#
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obj-$(CONFIG_QCOM_IPQ4019_ESS_EDMA) += ipq_ess.o
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ipq_ess-objs := ipqess.o ipqess_ethtool.o
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// SPDX-License-Identifier: (GPL-2.0 OR ISC)
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/* Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
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* Copyright (c) 2017 - 2018, John Crispin <john@phrozen.org>
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* Copyright (c) 2018 - 2019, Christian Lamparter <chunkeey@gmail.com>
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* Copyright (c) 2020 - 2021, Gabor Juhos <j4g8y7@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all copies.
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
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* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _IPQESS_H_
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#define _IPQESS_H_
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#define IPQESS_NETDEV_QUEUES 4
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#define IPQESS_TPD_EOP_SHIFT 31
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#define IPQESS_PORT_ID_SHIFT 12
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#define IPQESS_PORT_ID_MASK 0x7
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/* tpd word 3 bit 18-28 */
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#define IPQESS_TPD_PORT_BITMAP_SHIFT 18
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#define IPQESS_TPD_FROM_CPU_SHIFT 25
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#define IPQESS_RX_RING_SIZE 128
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#define IPQESS_RX_HEAD_BUFF_SIZE 1540
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#define IPQESS_TX_RING_SIZE 128
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#define IPQESS_MAX_RX_QUEUE 8
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#define IPQESS_MAX_TX_QUEUE 16
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/* Configurations */
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#define IPQESS_INTR_CLEAR_TYPE 0
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#define IPQESS_INTR_SW_IDX_W_TYPE 0
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#define IPQESS_FIFO_THRESH_TYPE 0
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#define IPQESS_RSS_TYPE 0
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#define IPQESS_RX_IMT 0x0020
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#define IPQESS_TX_IMT 0x0050
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#define IPQESS_TPD_BURST 5
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#define IPQESS_TXF_BURST 0x100
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#define IPQESS_RFD_BURST 8
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#define IPQESS_RFD_THR 16
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#define IPQESS_RFD_LTHR 0
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/* Flags used in transmit direction */
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#define IPQESS_DESC_LAST 0x1
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#define IPQESS_DESC_SINGLE 0x2
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#define IPQESS_DESC_PAGE 0x4
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struct ipqesstool_statistics {
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u32 tx_q0_pkt;
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u32 tx_q1_pkt;
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u32 tx_q2_pkt;
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u32 tx_q3_pkt;
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u32 tx_q4_pkt;
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u32 tx_q5_pkt;
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u32 tx_q6_pkt;
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u32 tx_q7_pkt;
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u32 tx_q8_pkt;
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u32 tx_q9_pkt;
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u32 tx_q10_pkt;
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u32 tx_q11_pkt;
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u32 tx_q12_pkt;
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u32 tx_q13_pkt;
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u32 tx_q14_pkt;
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u32 tx_q15_pkt;
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u32 tx_q0_byte;
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u32 tx_q1_byte;
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u32 tx_q2_byte;
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u32 tx_q3_byte;
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u32 tx_q4_byte;
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u32 tx_q5_byte;
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u32 tx_q6_byte;
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u32 tx_q7_byte;
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u32 tx_q8_byte;
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u32 tx_q9_byte;
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u32 tx_q10_byte;
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u32 tx_q11_byte;
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u32 tx_q12_byte;
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u32 tx_q13_byte;
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u32 tx_q14_byte;
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u32 tx_q15_byte;
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u32 rx_q0_pkt;
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u32 rx_q1_pkt;
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u32 rx_q2_pkt;
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u32 rx_q3_pkt;
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u32 rx_q4_pkt;
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u32 rx_q5_pkt;
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u32 rx_q6_pkt;
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u32 rx_q7_pkt;
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u32 rx_q0_byte;
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u32 rx_q1_byte;
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u32 rx_q2_byte;
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u32 rx_q3_byte;
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u32 rx_q4_byte;
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u32 rx_q5_byte;
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u32 rx_q6_byte;
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u32 rx_q7_byte;
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u32 tx_desc_error;
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};
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struct ipqess_tx_desc {
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__le16 len;
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__le16 svlan_tag;
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__le32 word1;
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__le32 addr;
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__le32 word3;
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} __aligned(16) __packed;
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struct ipqess_rx_desc {
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u16 rrd0;
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u16 rrd1;
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u16 rrd2;
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u16 rrd3;
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u16 rrd4;
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u16 rrd5;
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u16 rrd6;
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u16 rrd7;
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} __aligned(16) __packed;
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struct ipqess_buf {
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struct sk_buff *skb;
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dma_addr_t dma;
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u32 flags;
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u16 length;
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};
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struct ipqess_tx_ring {
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struct napi_struct napi_tx;
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u32 idx;
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int ring_id;
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struct ipqess *ess;
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struct netdev_queue *nq;
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struct ipqess_tx_desc *hw_desc;
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struct ipqess_buf *buf;
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dma_addr_t dma;
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u16 count;
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u16 head;
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u16 tail;
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};
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struct ipqess_rx_ring {
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struct napi_struct napi_rx;
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u32 idx;
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int ring_id;
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struct ipqess *ess;
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struct device *ppdev;
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struct ipqess_rx_desc **hw_desc;
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struct ipqess_buf *buf;
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dma_addr_t dma;
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u16 head;
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u16 tail;
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atomic_t refill_count;
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};
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struct ipqess_rx_ring_refill {
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struct ipqess_rx_ring *rx_ring;
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struct work_struct refill_work;
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};
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#define IPQESS_IRQ_NAME_LEN 32
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struct ipqess {
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struct net_device *netdev;
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void __iomem *hw_addr;
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struct clk *ess_clk;
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struct reset_control *ess_rst;
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struct ipqess_rx_ring rx_ring[IPQESS_NETDEV_QUEUES];
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struct platform_device *pdev;
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struct phylink *phylink;
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struct phylink_config phylink_config;
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struct ipqess_tx_ring tx_ring[IPQESS_NETDEV_QUEUES];
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struct ipqesstool_statistics ipqessstats;
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spinlock_t stats_lock;
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struct net_device_stats stats;
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struct ipqess_rx_ring_refill rx_refill[IPQESS_NETDEV_QUEUES];
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u32 tx_irq[IPQESS_MAX_TX_QUEUE];
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char tx_irq_names[IPQESS_MAX_TX_QUEUE][IPQESS_IRQ_NAME_LEN];
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u32 rx_irq[IPQESS_MAX_RX_QUEUE];
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char rx_irq_names[IPQESS_MAX_TX_QUEUE][IPQESS_IRQ_NAME_LEN];
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};
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static inline void build_test(void)
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{
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struct ipqess *ess;
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BUILD_BUG_ON(ARRAY_SIZE(ess->rx_ring) != ARRAY_SIZE(ess->rx_refill));
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}
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void ipqess_set_ethtool_ops(struct net_device *netdev);
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void ipqess_update_hw_stats(struct ipqess *ess);
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/* register definition */
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#define IPQESS_REG_MAS_CTRL 0x0
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#define IPQESS_REG_TIMEOUT_CTRL 0x004
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#define IPQESS_REG_DBG0 0x008
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#define IPQESS_REG_DBG1 0x00C
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#define IPQESS_REG_SW_CTRL0 0x100
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#define IPQESS_REG_SW_CTRL1 0x104
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/* Interrupt Status Register */
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#define IPQESS_REG_RX_ISR 0x200
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#define IPQESS_REG_TX_ISR 0x208
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#define IPQESS_REG_MISC_ISR 0x210
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#define IPQESS_REG_WOL_ISR 0x218
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#define IPQESS_MISC_ISR_RX_URG_Q(x) (1 << x)
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#define IPQESS_MISC_ISR_AXIR_TIMEOUT 0x00000100
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#define IPQESS_MISC_ISR_AXIR_ERR 0x00000200
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#define IPQESS_MISC_ISR_TXF_DEAD 0x00000400
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#define IPQESS_MISC_ISR_AXIW_ERR 0x00000800
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#define IPQESS_MISC_ISR_AXIW_TIMEOUT 0x00001000
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#define IPQESS_WOL_ISR 0x00000001
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/* Interrupt Mask Register */
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#define IPQESS_REG_MISC_IMR 0x214
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#define IPQESS_REG_WOL_IMR 0x218
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#define IPQESS_RX_IMR_NORMAL_MASK 0x1
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#define IPQESS_TX_IMR_NORMAL_MASK 0x1
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#define IPQESS_MISC_IMR_NORMAL_MASK 0x80001FFF
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#define IPQESS_WOL_IMR_NORMAL_MASK 0x1
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/* Edma receive consumer index */
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#define IPQESS_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) /* x is the queue id */
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/* Edma transmit consumer index */
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#define IPQESS_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) /* x is the queue id */
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/* IRQ Moderator Initial Timer Register */
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#define IPQESS_REG_IRQ_MODRT_TIMER_INIT 0x280
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#define IPQESS_IRQ_MODRT_TIMER_MASK 0xFFFF
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#define IPQESS_IRQ_MODRT_RX_TIMER_SHIFT 0
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#define IPQESS_IRQ_MODRT_TX_TIMER_SHIFT 16
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/* Interrupt Control Register */
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#define IPQESS_REG_INTR_CTRL 0x284
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#define IPQESS_INTR_CLR_TYP_SHIFT 0
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#define IPQESS_INTR_SW_IDX_W_TYP_SHIFT 1
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#define IPQESS_INTR_CLEAR_TYPE_W1 0
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#define IPQESS_INTR_CLEAR_TYPE_R 1
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/* RX Interrupt Mask Register */
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#define IPQESS_REG_RX_INT_MASK_Q(x) (0x300 + ((x) << 2)) /* x = queue id */
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/* TX Interrupt mask register */
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#define IPQESS_REG_TX_INT_MASK_Q(x) (0x340 + ((x) << 2)) /* x = queue id */
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/* Load Ptr Register
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* Software sets this bit after the initialization of the head and tail
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*/
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#define IPQESS_REG_TX_SRAM_PART 0x400
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#define IPQESS_LOAD_PTR_SHIFT 16
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/* TXQ Control Register */
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#define IPQESS_REG_TXQ_CTRL 0x404
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#define IPQESS_TXQ_CTRL_IP_OPTION_EN 0x10
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#define IPQESS_TXQ_CTRL_TXQ_EN 0x20
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#define IPQESS_TXQ_CTRL_ENH_MODE 0x40
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#define IPQESS_TXQ_CTRL_LS_8023_EN 0x80
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#define IPQESS_TXQ_CTRL_TPD_BURST_EN 0x100
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#define IPQESS_TXQ_CTRL_LSO_BREAK_EN 0x200
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#define IPQESS_TXQ_NUM_TPD_BURST_MASK 0xF
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#define IPQESS_TXQ_TXF_BURST_NUM_MASK 0xFFFF
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#define IPQESS_TXQ_NUM_TPD_BURST_SHIFT 0
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#define IPQESS_TXQ_TXF_BURST_NUM_SHIFT 16
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#define IPQESS_REG_TXF_WATER_MARK 0x408 /* In 8-bytes */
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#define IPQESS_TXF_WATER_MARK_MASK 0x0FFF
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#define IPQESS_TXF_LOW_WATER_MARK_SHIFT 0
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#define IPQESS_TXF_HIGH_WATER_MARK_SHIFT 16
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#define IPQESS_TXQ_CTRL_BURST_MODE_EN 0x80000000
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/* WRR Control Register */
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#define IPQESS_REG_WRR_CTRL_Q0_Q3 0x40c
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#define IPQESS_REG_WRR_CTRL_Q4_Q7 0x410
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#define IPQESS_REG_WRR_CTRL_Q8_Q11 0x414
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#define IPQESS_REG_WRR_CTRL_Q12_Q15 0x418
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/* Weight round robin(WRR), it takes queue as input, and computes
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* starting bits where we need to write the weight for a particular
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* queue
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*/
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#define IPQESS_WRR_SHIFT(x) (((x) * 5) % 20)
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/* Tx Descriptor Control Register */
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#define IPQESS_REG_TPD_RING_SIZE 0x41C
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#define IPQESS_TPD_RING_SIZE_SHIFT 0
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#define IPQESS_TPD_RING_SIZE_MASK 0xFFFF
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/* Transmit descriptor base address */
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#define IPQESS_REG_TPD_BASE_ADDR_Q(x) (0x420 + ((x) << 2)) /* x = queue id */
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/* TPD Index Register */
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#define IPQESS_REG_TPD_IDX_Q(x) (0x460 + ((x) << 2)) /* x = queue id */
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#define IPQESS_TPD_PROD_IDX_BITS 0x0000FFFF
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#define IPQESS_TPD_CONS_IDX_BITS 0xFFFF0000
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#define IPQESS_TPD_PROD_IDX_MASK 0xFFFF
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#define IPQESS_TPD_CONS_IDX_MASK 0xFFFF
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#define IPQESS_TPD_PROD_IDX_SHIFT 0
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#define IPQESS_TPD_CONS_IDX_SHIFT 16
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/* TX Virtual Queue Mapping Control Register */
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#define IPQESS_REG_VQ_CTRL0 0x4A0
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#define IPQESS_REG_VQ_CTRL1 0x4A4
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/* Virtual QID shift, it takes queue as input, and computes
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* Virtual QID position in virtual qid control register
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*/
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#define IPQESS_VQ_ID_SHIFT(i) (((i) * 3) % 24)
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/* Virtual Queue Default Value */
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#define IPQESS_VQ_REG_VALUE 0x240240
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/* Tx side Port Interface Control Register */
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#define IPQESS_REG_PORT_CTRL 0x4A8
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#define IPQESS_PAD_EN_SHIFT 15
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/* Tx side VLAN Configuration Register */
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#define IPQESS_REG_VLAN_CFG 0x4AC
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|
#define IPQESS_VLAN_CFG_SVLAN_TPID_SHIFT 0
|
||||||
|
#define IPQESS_VLAN_CFG_SVLAN_TPID_MASK 0xffff
|
||||||
|
#define IPQESS_VLAN_CFG_CVLAN_TPID_SHIFT 16
|
||||||
|
#define IPQESS_VLAN_CFG_CVLAN_TPID_MASK 0xffff
|
||||||
|
|
||||||
|
#define IPQESS_TX_CVLAN 16
|
||||||
|
#define IPQESS_TX_INS_CVLAN 17
|
||||||
|
#define IPQESS_TX_CVLAN_TAG_SHIFT 0
|
||||||
|
|
||||||
|
#define IPQESS_TX_SVLAN 14
|
||||||
|
#define IPQESS_TX_INS_SVLAN 15
|
||||||
|
#define IPQESS_TX_SVLAN_TAG_SHIFT 16
|
||||||
|
|
||||||
|
/* Tx Queue Packet Statistic Register */
|
||||||
|
#define IPQESS_REG_TX_STAT_PKT_Q(x) (0x700 + ((x) << 3)) /* x = queue id */
|
||||||
|
|
||||||
|
#define IPQESS_TX_STAT_PKT_MASK 0xFFFFFF
|
||||||
|
|
||||||
|
/* Tx Queue Byte Statistic Register */
|
||||||
|
#define IPQESS_REG_TX_STAT_BYTE_Q(x) (0x704 + ((x) << 3)) /* x = queue id */
|
||||||
|
|
||||||
|
/* Load Balance Based Ring Offset Register */
|
||||||
|
#define IPQESS_REG_LB_RING 0x800
|
||||||
|
#define IPQESS_LB_RING_ENTRY_MASK 0xff
|
||||||
|
#define IPQESS_LB_RING_ID_MASK 0x7
|
||||||
|
#define IPQESS_LB_RING_PROFILE_ID_MASK 0x3
|
||||||
|
#define IPQESS_LB_RING_ENTRY_BIT_OFFSET 8
|
||||||
|
#define IPQESS_LB_RING_ID_OFFSET 0
|
||||||
|
#define IPQESS_LB_RING_PROFILE_ID_OFFSET 3
|
||||||
|
#define IPQESS_LB_REG_VALUE 0x6040200
|
||||||
|
|
||||||
|
/* Load Balance Priority Mapping Register */
|
||||||
|
#define IPQESS_REG_LB_PRI_START 0x804
|
||||||
|
#define IPQESS_REG_LB_PRI_END 0x810
|
||||||
|
#define IPQESS_LB_PRI_REG_INC 4
|
||||||
|
#define IPQESS_LB_PRI_ENTRY_BIT_OFFSET 4
|
||||||
|
#define IPQESS_LB_PRI_ENTRY_MASK 0xf
|
||||||
|
|
||||||
|
/* RSS Priority Mapping Register */
|
||||||
|
#define IPQESS_REG_RSS_PRI 0x820
|
||||||
|
#define IPQESS_RSS_PRI_ENTRY_MASK 0xf
|
||||||
|
#define IPQESS_RSS_RING_ID_MASK 0x7
|
||||||
|
#define IPQESS_RSS_PRI_ENTRY_BIT_OFFSET 4
|
||||||
|
|
||||||
|
/* RSS Indirection Register */
|
||||||
|
#define IPQESS_REG_RSS_IDT(x) (0x840 + ((x) << 2)) /* x = No. of indirection table */
|
||||||
|
#define IPQESS_NUM_IDT 16
|
||||||
|
#define IPQESS_RSS_IDT_VALUE 0x64206420
|
||||||
|
|
||||||
|
/* Default RSS Ring Register */
|
||||||
|
#define IPQESS_REG_DEF_RSS 0x890
|
||||||
|
#define IPQESS_DEF_RSS_MASK 0x7
|
||||||
|
|
||||||
|
/* RSS Hash Function Type Register */
|
||||||
|
#define IPQESS_REG_RSS_TYPE 0x894
|
||||||
|
#define IPQESS_RSS_TYPE_NONE 0x01
|
||||||
|
#define IPQESS_RSS_TYPE_IPV4TCP 0x02
|
||||||
|
#define IPQESS_RSS_TYPE_IPV6_TCP 0x04
|
||||||
|
#define IPQESS_RSS_TYPE_IPV4_UDP 0x08
|
||||||
|
#define IPQESS_RSS_TYPE_IPV6UDP 0x10
|
||||||
|
#define IPQESS_RSS_TYPE_IPV4 0x20
|
||||||
|
#define IPQESS_RSS_TYPE_IPV6 0x40
|
||||||
|
#define IPQESS_RSS_HASH_MODE_MASK 0x7f
|
||||||
|
|
||||||
|
#define IPQESS_REG_RSS_HASH_VALUE 0x8C0
|
||||||
|
|
||||||
|
#define IPQESS_REG_RSS_TYPE_RESULT 0x8C4
|
||||||
|
|
||||||
|
#define IPQESS_HASH_TYPE_START 0
|
||||||
|
#define IPQESS_HASH_TYPE_END 5
|
||||||
|
#define IPQESS_HASH_TYPE_SHIFT 12
|
||||||
|
|
||||||
|
#define IPQESS_RFS_FLOW_ENTRIES 1024
|
||||||
|
#define IPQESS_RFS_FLOW_ENTRIES_MASK (IPQESS_RFS_FLOW_ENTRIES - 1)
|
||||||
|
#define IPQESS_RFS_EXPIRE_COUNT_PER_CALL 128
|
||||||
|
|
||||||
|
/* RFD Base Address Register */
|
||||||
|
#define IPQESS_REG_RFD_BASE_ADDR_Q(x) (0x950 + ((x) << 2)) /* x = queue id */
|
||||||
|
|
||||||
|
/* RFD Index Register */
|
||||||
|
#define IPQESS_REG_RFD_IDX_Q(x) (0x9B0 + ((x) << 2)) /* x = queue id */
|
||||||
|
|
||||||
|
#define IPQESS_RFD_PROD_IDX_BITS 0x00000FFF
|
||||||
|
#define IPQESS_RFD_CONS_IDX_BITS 0x0FFF0000
|
||||||
|
#define IPQESS_RFD_PROD_IDX_MASK 0xFFF
|
||||||
|
#define IPQESS_RFD_CONS_IDX_MASK 0xFFF
|
||||||
|
#define IPQESS_RFD_PROD_IDX_SHIFT 0
|
||||||
|
#define IPQESS_RFD_CONS_IDX_SHIFT 16
|
||||||
|
|
||||||
|
/* Rx Descriptor Control Register */
|
||||||
|
#define IPQESS_REG_RX_DESC0 0xA10
|
||||||
|
#define IPQESS_RFD_RING_SIZE_MASK 0xFFF
|
||||||
|
#define IPQESS_RX_BUF_SIZE_MASK 0xFFFF
|
||||||
|
#define IPQESS_RFD_RING_SIZE_SHIFT 0
|
||||||
|
#define IPQESS_RX_BUF_SIZE_SHIFT 16
|
||||||
|
|
||||||
|
#define IPQESS_REG_RX_DESC1 0xA14
|
||||||
|
#define IPQESS_RXQ_RFD_BURST_NUM_MASK 0x3F
|
||||||
|
#define IPQESS_RXQ_RFD_PF_THRESH_MASK 0x1F
|
||||||
|
#define IPQESS_RXQ_RFD_LOW_THRESH_MASK 0xFFF
|
||||||
|
#define IPQESS_RXQ_RFD_BURST_NUM_SHIFT 0
|
||||||
|
#define IPQESS_RXQ_RFD_PF_THRESH_SHIFT 8
|
||||||
|
#define IPQESS_RXQ_RFD_LOW_THRESH_SHIFT 16
|
||||||
|
|
||||||
|
/* RXQ Control Register */
|
||||||
|
#define IPQESS_REG_RXQ_CTRL 0xA18
|
||||||
|
#define IPQESS_FIFO_THRESH_TYPE_SHIF 0
|
||||||
|
#define IPQESS_FIFO_THRESH_128_BYTE 0x0
|
||||||
|
#define IPQESS_FIFO_THRESH_64_BYTE 0x1
|
||||||
|
#define IPQESS_RXQ_CTRL_RMV_VLAN 0x00000002
|
||||||
|
#define IPQESS_RXQ_CTRL_EN_MASK GENMASK(15, 8)
|
||||||
|
#define IPQESS_RXQ_CTRL_EN(__qid) BIT(8 + (__qid))
|
||||||
|
|
||||||
|
/* AXI Burst Size Config */
|
||||||
|
#define IPQESS_REG_AXIW_CTRL_MAXWRSIZE 0xA1C
|
||||||
|
#define IPQESS_AXIW_MAXWRSIZE_VALUE 0x0
|
||||||
|
|
||||||
|
/* Rx Statistics Register */
|
||||||
|
#define IPQESS_REG_RX_STAT_BYTE_Q(x) (0xA30 + ((x) << 2)) /* x = queue id */
|
||||||
|
#define IPQESS_REG_RX_STAT_PKT_Q(x) (0xA50 + ((x) << 2)) /* x = queue id */
|
||||||
|
|
||||||
|
/* WoL Pattern Length Register */
|
||||||
|
#define IPQESS_REG_WOL_PATTERN_LEN0 0xC00
|
||||||
|
#define IPQESS_WOL_PT_LEN_MASK 0xFF
|
||||||
|
#define IPQESS_WOL_PT0_LEN_SHIFT 0
|
||||||
|
#define IPQESS_WOL_PT1_LEN_SHIFT 8
|
||||||
|
#define IPQESS_WOL_PT2_LEN_SHIFT 16
|
||||||
|
#define IPQESS_WOL_PT3_LEN_SHIFT 24
|
||||||
|
|
||||||
|
#define IPQESS_REG_WOL_PATTERN_LEN1 0xC04
|
||||||
|
#define IPQESS_WOL_PT4_LEN_SHIFT 0
|
||||||
|
#define IPQESS_WOL_PT5_LEN_SHIFT 8
|
||||||
|
#define IPQESS_WOL_PT6_LEN_SHIFT 16
|
||||||
|
|
||||||
|
/* WoL Control Register */
|
||||||
|
#define IPQESS_REG_WOL_CTRL 0xC08
|
||||||
|
#define IPQESS_WOL_WK_EN 0x00000001
|
||||||
|
#define IPQESS_WOL_MG_EN 0x00000002
|
||||||
|
#define IPQESS_WOL_PT0_EN 0x00000004
|
||||||
|
#define IPQESS_WOL_PT1_EN 0x00000008
|
||||||
|
#define IPQESS_WOL_PT2_EN 0x00000010
|
||||||
|
#define IPQESS_WOL_PT3_EN 0x00000020
|
||||||
|
#define IPQESS_WOL_PT4_EN 0x00000040
|
||||||
|
#define IPQESS_WOL_PT5_EN 0x00000080
|
||||||
|
#define IPQESS_WOL_PT6_EN 0x00000100
|
||||||
|
|
||||||
|
/* MAC Control Register */
|
||||||
|
#define IPQESS_REG_MAC_CTRL0 0xC20
|
||||||
|
#define IPQESS_REG_MAC_CTRL1 0xC24
|
||||||
|
|
||||||
|
/* WoL Pattern Register */
|
||||||
|
#define IPQESS_REG_WOL_PATTERN_START 0x5000
|
||||||
|
#define IPQESS_PATTERN_PART_REG_OFFSET 0x40
|
||||||
|
|
||||||
|
|
||||||
|
/* TX descriptor fields */
|
||||||
|
#define IPQESS_TPD_HDR_SHIFT 0
|
||||||
|
#define IPQESS_TPD_PPPOE_EN 0x00000100
|
||||||
|
#define IPQESS_TPD_IP_CSUM_EN 0x00000200
|
||||||
|
#define IPQESS_TPD_TCP_CSUM_EN 0x0000400
|
||||||
|
#define IPQESS_TPD_UDP_CSUM_EN 0x00000800
|
||||||
|
#define IPQESS_TPD_CUSTOM_CSUM_EN 0x00000C00
|
||||||
|
#define IPQESS_TPD_LSO_EN 0x00001000
|
||||||
|
#define IPQESS_TPD_LSO_V2_EN 0x00002000
|
||||||
|
/* The VLAN_TAGGED bit is not used in the publicly available
|
||||||
|
* drivers. The definition has been stolen from the Atheros
|
||||||
|
* 'alx' driver (drivers/net/ethernet/atheros/alx/hw.h). It
|
||||||
|
* seems that it has the same meaning in regard to the EDMA
|
||||||
|
* hardware.
|
||||||
|
*/
|
||||||
|
#define IPQESS_TPD_VLAN_TAGGED 0x00004000
|
||||||
|
#define IPQESS_TPD_IPV4_EN 0x00010000
|
||||||
|
#define IPQESS_TPD_MSS_MASK 0x1FFF
|
||||||
|
#define IPQESS_TPD_MSS_SHIFT 18
|
||||||
|
#define IPQESS_TPD_CUSTOM_CSUM_SHIFT 18
|
||||||
|
|
||||||
|
/* RRD descriptor fields */
|
||||||
|
#define IPQESS_RRD_NUM_RFD_MASK 0x000F
|
||||||
|
#define IPQESS_RRD_PKT_SIZE_MASK 0x3FFF
|
||||||
|
#define IPQESS_RRD_SRC_PORT_NUM_MASK 0x4000
|
||||||
|
#define IPQESS_RRD_SVLAN 0x8000
|
||||||
|
#define IPQESS_RRD_FLOW_COOKIE_MASK 0x07FF;
|
||||||
|
|
||||||
|
#define IPQESS_RRD_PKT_SIZE_MASK 0x3FFF
|
||||||
|
#define IPQESS_RRD_CSUM_FAIL_MASK 0xC000
|
||||||
|
#define IPQESS_RRD_CVLAN 0x0001
|
||||||
|
#define IPQESS_RRD_DESC_VALID 0x8000
|
||||||
|
|
||||||
|
#define IPQESS_RRD_PRIORITY_SHIFT 4
|
||||||
|
#define IPQESS_RRD_PRIORITY_MASK 0x7
|
||||||
|
#define IPQESS_RRD_PORT_TYPE_SHIFT 7
|
||||||
|
#define IPQESS_RRD_PORT_TYPE_MASK 0x1F
|
||||||
|
|
||||||
|
#endif
|
@ -0,0 +1,175 @@
|
|||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR ISC)
|
||||||
|
/* Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved.
|
||||||
|
* Copyright (c) 2017 - 2018, John Crispin <john@phrozen.org>
|
||||||
|
*
|
||||||
|
* Permission to use, copy, modify, and/or distribute this software for
|
||||||
|
* any purpose with or without fee is hereby granted, provided that the
|
||||||
|
* above copyright notice and this permission notice appear in all copies.
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||||
|
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||||
|
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||||
|
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||||
|
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
|
||||||
|
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/ethtool.h>
|
||||||
|
#include <linux/netdevice.h>
|
||||||
|
#include <linux/string.h>
|
||||||
|
#include <linux/phylink.h>
|
||||||
|
|
||||||
|
#include "ipqess.h"
|
||||||
|
|
||||||
|
struct ipqesstool_stats {
|
||||||
|
uint8_t string[ETH_GSTRING_LEN];
|
||||||
|
uint32_t offset;
|
||||||
|
};
|
||||||
|
|
||||||
|
#define IPQESS_STAT(m) offsetof(struct ipqesstool_statistics, m)
|
||||||
|
#define DRVINFO_LEN 32
|
||||||
|
|
||||||
|
static const struct ipqesstool_stats ipqess_stats[] = {
|
||||||
|
{"tx_q0_pkt", IPQESS_STAT(tx_q0_pkt)},
|
||||||
|
{"tx_q1_pkt", IPQESS_STAT(tx_q1_pkt)},
|
||||||
|
{"tx_q2_pkt", IPQESS_STAT(tx_q2_pkt)},
|
||||||
|
{"tx_q3_pkt", IPQESS_STAT(tx_q3_pkt)},
|
||||||
|
{"tx_q4_pkt", IPQESS_STAT(tx_q4_pkt)},
|
||||||
|
{"tx_q5_pkt", IPQESS_STAT(tx_q5_pkt)},
|
||||||
|
{"tx_q6_pkt", IPQESS_STAT(tx_q6_pkt)},
|
||||||
|
{"tx_q7_pkt", IPQESS_STAT(tx_q7_pkt)},
|
||||||
|
{"tx_q8_pkt", IPQESS_STAT(tx_q8_pkt)},
|
||||||
|
{"tx_q9_pkt", IPQESS_STAT(tx_q9_pkt)},
|
||||||
|
{"tx_q10_pkt", IPQESS_STAT(tx_q10_pkt)},
|
||||||
|
{"tx_q11_pkt", IPQESS_STAT(tx_q11_pkt)},
|
||||||
|
{"tx_q12_pkt", IPQESS_STAT(tx_q12_pkt)},
|
||||||
|
{"tx_q13_pkt", IPQESS_STAT(tx_q13_pkt)},
|
||||||
|
{"tx_q14_pkt", IPQESS_STAT(tx_q14_pkt)},
|
||||||
|
{"tx_q15_pkt", IPQESS_STAT(tx_q15_pkt)},
|
||||||
|
{"tx_q0_byte", IPQESS_STAT(tx_q0_byte)},
|
||||||
|
{"tx_q1_byte", IPQESS_STAT(tx_q1_byte)},
|
||||||
|
{"tx_q2_byte", IPQESS_STAT(tx_q2_byte)},
|
||||||
|
{"tx_q3_byte", IPQESS_STAT(tx_q3_byte)},
|
||||||
|
{"tx_q4_byte", IPQESS_STAT(tx_q4_byte)},
|
||||||
|
{"tx_q5_byte", IPQESS_STAT(tx_q5_byte)},
|
||||||
|
{"tx_q6_byte", IPQESS_STAT(tx_q6_byte)},
|
||||||
|
{"tx_q7_byte", IPQESS_STAT(tx_q7_byte)},
|
||||||
|
{"tx_q8_byte", IPQESS_STAT(tx_q8_byte)},
|
||||||
|
{"tx_q9_byte", IPQESS_STAT(tx_q9_byte)},
|
||||||
|
{"tx_q10_byte", IPQESS_STAT(tx_q10_byte)},
|
||||||
|
{"tx_q11_byte", IPQESS_STAT(tx_q11_byte)},
|
||||||
|
{"tx_q12_byte", IPQESS_STAT(tx_q12_byte)},
|
||||||
|
{"tx_q13_byte", IPQESS_STAT(tx_q13_byte)},
|
||||||
|
{"tx_q14_byte", IPQESS_STAT(tx_q14_byte)},
|
||||||
|
{"tx_q15_byte", IPQESS_STAT(tx_q15_byte)},
|
||||||
|
{"rx_q0_pkt", IPQESS_STAT(rx_q0_pkt)},
|
||||||
|
{"rx_q1_pkt", IPQESS_STAT(rx_q1_pkt)},
|
||||||
|
{"rx_q2_pkt", IPQESS_STAT(rx_q2_pkt)},
|
||||||
|
{"rx_q3_pkt", IPQESS_STAT(rx_q3_pkt)},
|
||||||
|
{"rx_q4_pkt", IPQESS_STAT(rx_q4_pkt)},
|
||||||
|
{"rx_q5_pkt", IPQESS_STAT(rx_q5_pkt)},
|
||||||
|
{"rx_q6_pkt", IPQESS_STAT(rx_q6_pkt)},
|
||||||
|
{"rx_q7_pkt", IPQESS_STAT(rx_q7_pkt)},
|
||||||
|
{"rx_q0_byte", IPQESS_STAT(rx_q0_byte)},
|
||||||
|
{"rx_q1_byte", IPQESS_STAT(rx_q1_byte)},
|
||||||
|
{"rx_q2_byte", IPQESS_STAT(rx_q2_byte)},
|
||||||
|
{"rx_q3_byte", IPQESS_STAT(rx_q3_byte)},
|
||||||
|
{"rx_q4_byte", IPQESS_STAT(rx_q4_byte)},
|
||||||
|
{"rx_q5_byte", IPQESS_STAT(rx_q5_byte)},
|
||||||
|
{"rx_q6_byte", IPQESS_STAT(rx_q6_byte)},
|
||||||
|
{"rx_q7_byte", IPQESS_STAT(rx_q7_byte)},
|
||||||
|
{"tx_desc_error", IPQESS_STAT(tx_desc_error)},
|
||||||
|
};
|
||||||
|
|
||||||
|
static int ipqess_get_strset_count(struct net_device *netdev, int sset)
|
||||||
|
{
|
||||||
|
switch (sset) {
|
||||||
|
case ETH_SS_STATS:
|
||||||
|
return ARRAY_SIZE(ipqess_stats);
|
||||||
|
default:
|
||||||
|
netdev_dbg(netdev, "%s: Invalid string set", __func__);
|
||||||
|
return -EOPNOTSUPP;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void ipqess_get_strings(struct net_device *netdev, uint32_t stringset,
|
||||||
|
uint8_t *data)
|
||||||
|
{
|
||||||
|
uint8_t *p = data;
|
||||||
|
uint32_t i;
|
||||||
|
|
||||||
|
switch (stringset) {
|
||||||
|
case ETH_SS_STATS:
|
||||||
|
for (i = 0; i < ARRAY_SIZE(ipqess_stats); i++) {
|
||||||
|
memcpy(p, ipqess_stats[i].string,
|
||||||
|
min((size_t)ETH_GSTRING_LEN,
|
||||||
|
strlen(ipqess_stats[i].string) + 1));
|
||||||
|
p += ETH_GSTRING_LEN;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void ipqess_get_ethtool_stats(struct net_device *netdev,
|
||||||
|
struct ethtool_stats *stats,
|
||||||
|
uint64_t *data)
|
||||||
|
{
|
||||||
|
struct ipqess *ess = netdev_priv(netdev);
|
||||||
|
u32 *essstats = (u32 *)&ess->ipqessstats;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
spin_lock(&ess->stats_lock);
|
||||||
|
|
||||||
|
ipqess_update_hw_stats(ess);
|
||||||
|
|
||||||
|
for (i = 0; i < ARRAY_SIZE(ipqess_stats); i++)
|
||||||
|
data[i] = *(u32 *)(essstats + (ipqess_stats[i].offset / sizeof(u32)));
|
||||||
|
|
||||||
|
spin_unlock(&ess->stats_lock);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void ipqess_get_drvinfo(struct net_device *dev,
|
||||||
|
struct ethtool_drvinfo *info)
|
||||||
|
{
|
||||||
|
strlcpy(info->driver, "qca_ipqess", DRVINFO_LEN);
|
||||||
|
strlcpy(info->bus_info, "axi", ETHTOOL_BUSINFO_LEN);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int ipqess_get_settings(struct net_device *netdev,
|
||||||
|
struct ethtool_link_ksettings *cmd)
|
||||||
|
{
|
||||||
|
struct ipqess *ess = netdev_priv(netdev);
|
||||||
|
|
||||||
|
return phylink_ethtool_ksettings_get(ess->phylink, cmd);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int ipqess_set_settings(struct net_device *netdev,
|
||||||
|
const struct ethtool_link_ksettings *cmd)
|
||||||
|
{
|
||||||
|
struct ipqess *ess = netdev_priv(netdev);
|
||||||
|
|
||||||
|
return phylink_ethtool_ksettings_set(ess->phylink, cmd);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void ipqess_get_ringparam(struct net_device *netdev,
|
||||||
|
struct ethtool_ringparam *ring)
|
||||||
|
{
|
||||||
|
ring->tx_max_pending = IPQESS_TX_RING_SIZE;
|
||||||
|
ring->rx_max_pending = IPQESS_RX_RING_SIZE;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct ethtool_ops ipqesstool_ops = {
|
||||||
|
.get_drvinfo = &ipqess_get_drvinfo,
|
||||||
|
.get_link = ðtool_op_get_link,
|
||||||
|
.get_link_ksettings = &ipqess_get_settings,
|
||||||
|
.set_link_ksettings = &ipqess_set_settings,
|
||||||
|
.get_strings = &ipqess_get_strings,
|
||||||
|
.get_sset_count = &ipqess_get_strset_count,
|
||||||
|
.get_ethtool_stats = &ipqess_get_ethtool_stats,
|
||||||
|
.get_ringparam = ipqess_get_ringparam,
|
||||||
|
};
|
||||||
|
|
||||||
|
void ipqess_set_ethtool_ops(struct net_device *netdev)
|
||||||
|
{
|
||||||
|
netdev->ethtool_ops = &ipqesstool_ops;
|
||||||
|
}
|
@ -0,0 +1,43 @@
|
|||||||
|
From 4f488235f498db43f2412116dea6e02c7fb20216 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Robert Marko <robert.marko@sartura.hr>
|
||||||
|
Date: Mon, 1 Nov 2021 12:36:51 +0100
|
||||||
|
Subject: [PATCH] net: ethernet: qualcomm: add IPQESS support
|
||||||
|
|
||||||
|
Allow compiling the IPQESS driver that supports the
|
||||||
|
Qualcomm IPQ40xx SoC built-in ethernet controller.
|
||||||
|
|
||||||
|
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
|
||||||
|
---
|
||||||
|
drivers/net/ethernet/qualcomm/Kconfig | 11 +++++++++++
|
||||||
|
drivers/net/ethernet/qualcomm/Makefile | 1 +
|
||||||
|
2 files changed, 12 insertions(+)
|
||||||
|
|
||||||
|
--- a/drivers/net/ethernet/qualcomm/Kconfig
|
||||||
|
+++ b/drivers/net/ethernet/qualcomm/Kconfig
|
||||||
|
@@ -60,6 +60,17 @@ config QCOM_EMAC
|
||||||
|
low power, Receive-Side Scaling (RSS), and IEEE 1588-2008
|
||||||
|
Precision Clock Synchronization Protocol.
|
||||||
|
|
||||||
|
+config QCOM_IPQ4019_ESS_EDMA
|
||||||
|
+ tristate "Qualcomm Atheros IPQ4019 ESS EDMA support"
|
||||||
|
+ depends on OF
|
||||||
|
+ select PHYLINK
|
||||||
|
+ help
|
||||||
|
+ This driver supports the Qualcomm Atheros IPQ40xx built-in
|
||||||
|
+ ESS EDMA ethernet controller.
|
||||||
|
+
|
||||||
|
+ To compile this driver as a module, choose M here: the
|
||||||
|
+ module will be called ipqess.
|
||||||
|
+
|
||||||
|
source "drivers/net/ethernet/qualcomm/rmnet/Kconfig"
|
||||||
|
|
||||||
|
endif # NET_VENDOR_QUALCOMM
|
||||||
|
--- a/drivers/net/ethernet/qualcomm/Makefile
|
||||||
|
+++ b/drivers/net/ethernet/qualcomm/Makefile
|
||||||
|
@@ -10,5 +10,6 @@ obj-$(CONFIG_QCA7000_UART) += qcauart.o
|
||||||
|
qcauart-objs := qca_uart.o
|
||||||
|
|
||||||
|
obj-y += emac/
|
||||||
|
+obj-y += ipqess/
|
||||||
|
|
||||||
|
obj-$(CONFIG_RMNET) += rmnet/
|
@ -0,0 +1,81 @@
|
|||||||
|
From 44327d7098d4f32c24ec8c528e5aff6e030956bc Mon Sep 17 00:00:00 2001
|
||||||
|
From: Robert Marko <robert.marko@sartura.hr>
|
||||||
|
Date: Wed, 20 Oct 2021 13:21:45 +0200
|
||||||
|
Subject: [PATCH] arm: dts: ipq4019: add ethernet controller DT node
|
||||||
|
|
||||||
|
Since IPQ40xx SoC built-in ethernet controller now has a driver,
|
||||||
|
add its DT node so it can be used.
|
||||||
|
|
||||||
|
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
|
||||||
|
---
|
||||||
|
arch/arm/boot/dts/qcom-ipq4019.dtsi | 48 +++++++++++++++++++++++++++++
|
||||||
|
1 file changed, 48 insertions(+)
|
||||||
|
|
||||||
|
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||||
|
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||||
|
@@ -38,6 +38,7 @@
|
||||||
|
spi1 = &blsp1_spi2;
|
||||||
|
i2c0 = &blsp1_i2c3;
|
||||||
|
i2c1 = &blsp1_i2c4;
|
||||||
|
+ ethernet0 = &gmac;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
@@ -589,6 +590,57 @@
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
+ gmac: ethernet@c080000 {
|
||||||
|
+ compatible = "qcom,ipq4019-ess-edma";
|
||||||
|
+ reg = <0xc080000 0x8000>;
|
||||||
|
+ resets = <&gcc ESS_RESET>;
|
||||||
|
+ reset-names = "ess_rst";
|
||||||
|
+ clocks = <&gcc GCC_ESS_CLK>;
|
||||||
|
+ clock-names = "ess_clk";
|
||||||
|
+ interrupts = <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
|
||||||
|
+
|
||||||
|
+ status = "disabled";
|
||||||
|
+
|
||||||
|
+ phy-mode = "internal";
|
||||||
|
+ fixed-link {
|
||||||
|
+ speed = <1000>;
|
||||||
|
+ full-duplex;
|
||||||
|
+ pause;
|
||||||
|
+ asym-pause;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
mdio: mdio@90000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
@ -20,7 +20,7 @@ Signed-off-by: Robert Marko <robert.marko@sartura.hr>
|
|||||||
|
|
||||||
/ {
|
/ {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
@@ -598,22 +599,39 @@
|
@@ -645,22 +646,39 @@
|
||||||
|
|
||||||
ethphy0: ethernet-phy@0 {
|
ethphy0: ethernet-phy@0 {
|
||||||
reg = <0>;
|
reg = <0>;
|
||||||
|
@ -0,0 +1,43 @@
|
|||||||
|
From 4f488235f498db43f2412116dea6e02c7fb20216 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Robert Marko <robert.marko@sartura.hr>
|
||||||
|
Date: Mon, 1 Nov 2021 12:36:51 +0100
|
||||||
|
Subject: [PATCH] net: ethernet: qualcomm: add IPQESS support
|
||||||
|
|
||||||
|
Allow compiling the IPQESS driver that supports the
|
||||||
|
Qualcomm IPQ40xx SoC built-in ethernet controller.
|
||||||
|
|
||||||
|
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
|
||||||
|
---
|
||||||
|
drivers/net/ethernet/qualcomm/Kconfig | 11 +++++++++++
|
||||||
|
drivers/net/ethernet/qualcomm/Makefile | 1 +
|
||||||
|
2 files changed, 12 insertions(+)
|
||||||
|
|
||||||
|
--- a/drivers/net/ethernet/qualcomm/Kconfig
|
||||||
|
+++ b/drivers/net/ethernet/qualcomm/Kconfig
|
||||||
|
@@ -60,6 +60,17 @@ config QCOM_EMAC
|
||||||
|
low power, Receive-Side Scaling (RSS), and IEEE 1588-2008
|
||||||
|
Precision Clock Synchronization Protocol.
|
||||||
|
|
||||||
|
+config QCOM_IPQ4019_ESS_EDMA
|
||||||
|
+ tristate "Qualcomm Atheros IPQ4019 ESS EDMA support"
|
||||||
|
+ depends on OF
|
||||||
|
+ select PHYLINK
|
||||||
|
+ help
|
||||||
|
+ This driver supports the Qualcomm Atheros IPQ40xx built-in
|
||||||
|
+ ESS EDMA ethernet controller.
|
||||||
|
+
|
||||||
|
+ To compile this driver as a module, choose M here: the
|
||||||
|
+ module will be called ipqess.
|
||||||
|
+
|
||||||
|
source "drivers/net/ethernet/qualcomm/rmnet/Kconfig"
|
||||||
|
|
||||||
|
endif # NET_VENDOR_QUALCOMM
|
||||||
|
--- a/drivers/net/ethernet/qualcomm/Makefile
|
||||||
|
+++ b/drivers/net/ethernet/qualcomm/Makefile
|
||||||
|
@@ -10,5 +10,6 @@ obj-$(CONFIG_QCA7000_UART) += qcauart.o
|
||||||
|
qcauart-objs := qca_uart.o
|
||||||
|
|
||||||
|
obj-y += emac/
|
||||||
|
+obj-y += ipqess/
|
||||||
|
|
||||||
|
obj-$(CONFIG_RMNET) += rmnet/
|
@ -0,0 +1,81 @@
|
|||||||
|
From 44327d7098d4f32c24ec8c528e5aff6e030956bc Mon Sep 17 00:00:00 2001
|
||||||
|
From: Robert Marko <robert.marko@sartura.hr>
|
||||||
|
Date: Wed, 20 Oct 2021 13:21:45 +0200
|
||||||
|
Subject: [PATCH] arm: dts: ipq4019: add ethernet controller DT node
|
||||||
|
|
||||||
|
Since IPQ40xx SoC built-in ethernet controller now has a driver,
|
||||||
|
add its DT node so it can be used.
|
||||||
|
|
||||||
|
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
|
||||||
|
---
|
||||||
|
arch/arm/boot/dts/qcom-ipq4019.dtsi | 48 +++++++++++++++++++++++++++++
|
||||||
|
1 file changed, 48 insertions(+)
|
||||||
|
|
||||||
|
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||||
|
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||||
|
@@ -38,6 +38,7 @@
|
||||||
|
spi1 = &blsp1_spi2;
|
||||||
|
i2c0 = &blsp1_i2c3;
|
||||||
|
i2c1 = &blsp1_i2c4;
|
||||||
|
+ ethernet0 = &gmac;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
@@ -589,6 +590,57 @@
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
+ gmac: ethernet@c080000 {
|
||||||
|
+ compatible = "qcom,ipq4019-ess-edma";
|
||||||
|
+ reg = <0xc080000 0x8000>;
|
||||||
|
+ resets = <&gcc ESS_RESET>;
|
||||||
|
+ reset-names = "ess_rst";
|
||||||
|
+ clocks = <&gcc GCC_ESS_CLK>;
|
||||||
|
+ clock-names = "ess_clk";
|
||||||
|
+ interrupts = <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
|
||||||
|
+ <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
|
||||||
|
+
|
||||||
|
+ status = "disabled";
|
||||||
|
+
|
||||||
|
+ phy-mode = "internal";
|
||||||
|
+ fixed-link {
|
||||||
|
+ speed = <1000>;
|
||||||
|
+ full-duplex;
|
||||||
|
+ pause;
|
||||||
|
+ asym-pause;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
mdio: mdio@90000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
Loading…
Reference in New Issue
Block a user