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realtek: 5.15: rtl93xx: add 1000Base-X and 10GBase-CR support on SerDes
This patch adds support for 1000Base-X and 10GBase-CR directly on the SerDes lanes of rtl93xx SoCs. This fixes SFP/SFP+ support on devices like the XSG1250-12. Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
This commit is contained in:
Tobias Schramm
Sander Vanheule
parent
9fe2412e62
commit
9daf4dff6b
@ -811,8 +811,10 @@ static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
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sds_num = priv->ports[port].sds_num;
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pr_info("%s SDS is %d\n", __func__, sds_num);
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if (sds_num >= 0 && state->interface == PHY_INTERFACE_MODE_10GBASER)
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rtl9300_serdes_setup(sds_num, state->interface);
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if (sds_num >= 0 &&
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(state->interface == PHY_INTERFACE_MODE_1000BASEX ||
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state->interface == PHY_INTERFACE_MODE_10GBASER))
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rtl9300_serdes_setup(port, sds_num, state->interface);
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reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
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reg &= ~(0xf << 3);
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@ -121,7 +121,7 @@ irqreturn_t rtl839x_switch_irq(int irq, void *dev_id);
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void rtl930x_vlan_profile_dump(int index);
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int rtl9300_sds_power(int mac, int val);
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void rtl9300_sds_rst(int sds_num, u32 mode);
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int rtl9300_serdes_setup(int sds_num, phy_interface_t phy_mode);
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int rtl9300_serdes_setup(int port, int sds_num, phy_interface_t phy_mode);
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void rtl930x_print_matrix(void);
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/* RTL931x-specific */
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@ -1646,6 +1646,8 @@ static int rtl9300_read_status(struct phy_device *phydev)
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mode = rtl9300_sds_mode_get(sds_num);
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pr_info("%s got SDS mode %02x\n", __func__, mode);
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if (mode == RTL930X_SDS_OFF)
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mode = rtl9300_sds_field_r(sds_num, 0x1f, 9, 11, 7);
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if (mode == RTL930X_SDS_MODE_10GBASER) { /* 10GR mode */
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status = rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
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latch_status = rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
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@ -1662,10 +1664,13 @@ static int rtl9300_read_status(struct phy_device *phydev)
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if (latch_status) {
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phydev->link = true;
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if (mode == RTL930X_SDS_MODE_10GBASER)
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if (mode == RTL930X_SDS_MODE_10GBASER) {
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phydev->speed = SPEED_10000;
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else
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phydev->interface = PHY_INTERFACE_MODE_10GBASER;
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} else {
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phydev->speed = SPEED_1000;
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phydev->interface = PHY_INTERFACE_MODE_1000BASEX;
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}
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phydev->duplex = DUPLEX_FULL;
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}
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@ -1861,13 +1866,26 @@ void rtl9300_sds_tx_config(int sds, phy_interface_t phy_if)
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switch(phy_if) {
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case PHY_INTERFACE_MODE_1000BASEX:
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pre_amp = 0x1;
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main_amp = 0x9;
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post_amp = 0x1;
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page = 0x25;
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break;
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case PHY_INTERFACE_MODE_HSGMII:
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case PHY_INTERFACE_MODE_2500BASEX:
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pre_amp = 0;
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post_amp = 0x8;
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pre_en = 0;
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page = 0x29;
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break;
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case PHY_INTERFACE_MODE_10GBASER:
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case PHY_INTERFACE_MODE_USXGMII:
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case PHY_INTERFACE_MODE_XGMII:
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pre_en = 0;
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pre_amp = 0;
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main_amp = 0x10;
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post_amp = 0;
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post_en = 0;
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page = 0x2f;
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break;
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default:
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@ -2713,6 +2731,7 @@ u32 rtl9300_sds_sym_err_get(int sds_num, phy_interface_t phy_mode)
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case PHY_INTERFACE_MODE_XGMII:
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break;
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case PHY_INTERFACE_MODE_1000BASEX:
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case PHY_INTERFACE_MODE_10GBASER:
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v = rtl930x_read_sds_phy(sds_num, 5, 1);
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return v & 0xff;
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@ -2737,6 +2756,7 @@ int rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode)
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errors2 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
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switch (phy_mode) {
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case PHY_INTERFACE_MODE_1000BASEX:
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case PHY_INTERFACE_MODE_XGMII:
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if ((errors2 - errors1 > 100) ||
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(errors1 >= 0xffff00) || (errors2 >= 0xffff00)) {
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@ -2783,53 +2803,83 @@ void rtl9300_phy_enable_10g_1g(int sds_num)
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pr_info("%s set medium after: %08x\n", __func__, v);
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}
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static int rtl9300_sds_10g_idle(int sds_num);
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static void rtl9300_serdes_patch(int sds_num);
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#define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
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/* phy_mode = PHY_INTERFACE_MODE_10GBASER, sds_mode = 0x1a */
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int rtl9300_serdes_setup(int sds_num, phy_interface_t phy_mode)
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int rtl9300_serdes_setup(int port, int sds_num, phy_interface_t phy_mode)
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{
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int sds_mode;
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int calib_tries = 0;
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switch (phy_mode) {
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case PHY_INTERFACE_MODE_HSGMII:
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sds_mode = RTL930X_SDS_MODE_HSGMII;
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break;
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case PHY_INTERFACE_MODE_1000BASEX:
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sds_mode = RTL930X_SDS_MODE_1000BASEX;
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break;
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case PHY_INTERFACE_MODE_XGMII:
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sds_mode = RTL930X_SDS_MODE_XGMII;
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break;
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case PHY_INTERFACE_MODE_10GBASER:
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sds_mode = RTL930X_SDS_MODE_10GBASER;
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break;
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case PHY_INTERFACE_MODE_USXGMII:
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sds_mode = RTL930X_SDS_MODE_USXGMII;
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break;
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default:
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pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode));
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return -EINVAL;
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}
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/* Turn Off Serdes */
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rtl9300_sds_rst(sds_num, RTL930X_SDS_OFF);
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/* Apply serdes patches */
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rtl9300_serdes_patch(sds_num);
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/* Maybe use dal_longan_sds_init */
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/* dal_longan_construct_serdesConfig_init */ /* Serdes Construct */
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rtl9300_phy_enable_10g_1g(sds_num);
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/* Set Serdes Mode */
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rtl9300_sds_set(sds_num, RTL930X_SDS_MODE_10GBASER); /* 0x1b: RTK_MII_10GR1000BX_AUTO */
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/* Disable MAC */
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sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL + 4 * port);
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mdelay(20);
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/* Do RX calibration */
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/* ----> dal_longan_sds_mode_set */
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pr_info("%s: Configuring RTL9300 SERDES %d\n", __func__, sds_num);
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/* Configure link to MAC */
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rtl9300_serdes_mac_link_config(sds_num, true, true); /* MAC Construct */
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/* Re-Enable MAC */
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sw_w32_mask(1, 0, RTL930X_MAC_FORCE_MODE_CTRL + 4 * port);
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/* Enable SDS in desired mode */
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rtl9300_force_sds_mode(sds_num, phy_mode);
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/* Enable Fiber RX */
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rtl9300_sds_field_w(sds_num, 0x20, 2, 12, 12, 0);
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/* Calibrate SerDes receiver in loopback mode */
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rtl9300_sds_10g_idle(sds_num);
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do {
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rtl9300_do_rx_calibration(sds_num, phy_mode);
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calib_tries++;
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mdelay(50);
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} while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
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if (calib_tries >= 3)
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pr_warn("%s: SerDes RX calibration failed\n", __func__);
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/* Leave loopback mode */
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rtl9300_sds_tx_config(sds_num, phy_mode);
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return 0;
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}
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static int rtl9300_sds_10g_idle(int sds_num)
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{
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bool busy;
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int i = 0;
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do {
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if (sds_num % 2) {
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rtl9300_sds_field_w(sds_num - 1, 0x1f, 0x2, 15, 0, 53);
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busy = !!rtl9300_sds_field_r(sds_num - 1, 0x1f, 0x14, 1, 1);
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} else {
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rtl9300_sds_field_w(sds_num, 0x1f, 0x2, 15, 0, 53);
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busy = !!rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 0, 0);
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}
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i++;
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} while (busy && i < 100);
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if (i < 100)
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return 0;
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pr_warn("%s WARNING: Waiting for RX idle timed out, SDS %d\n", __func__, sds_num);
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return -EIO;
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}
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typedef struct {
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u8 page;
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u8 reg;
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@ -2927,6 +2977,23 @@ sds_config rtl9300_a_sds_10gr_lane1[] =
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{0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808},
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};
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static void rtl9300_serdes_patch(int sds_num)
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{
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if (sds_num % 2) {
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for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane1) / sizeof(sds_config); ++i) {
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rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane1[i].page,
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rtl9300_a_sds_10gr_lane1[i].reg,
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rtl9300_a_sds_10gr_lane1[i].data);
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}
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} else {
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for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane0) / sizeof(sds_config); ++i) {
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rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane0[i].page,
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rtl9300_a_sds_10gr_lane0[i].reg,
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rtl9300_a_sds_10gr_lane0[i].data);
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}
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}
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}
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int rtl9300_sds_cmu_band_get(int sds)
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{
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u32 page;
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@ -2952,113 +3019,6 @@ int rtl9300_sds_cmu_band_get(int sds)
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return cmu_band;
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}
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int rtl9300_configure_serdes(struct phy_device *phydev)
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{
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int phy_mode = PHY_INTERFACE_MODE_10GBASER;
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struct device *dev = &phydev->mdio.dev;
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int calib_tries = 0;
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u32 sds_num = 0;
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int sds_mode;
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if (dev->of_node) {
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struct device_node *dn = dev->of_node;
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int phy_addr = phydev->mdio.addr;
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if (of_property_read_u32(dn, "sds", &sds_num))
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sds_num = -1;
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pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num);
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} else {
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dev_err(dev, "No DT node.\n");
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return -EINVAL;
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}
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if (sds_num < 0)
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return 0;
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if (phy_mode != PHY_INTERFACE_MODE_10GBASER) /* TODO: for now we only patch 10GR SerDes */
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return 0;
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switch (phy_mode) {
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case PHY_INTERFACE_MODE_HSGMII:
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sds_mode = RTL930X_SDS_MODE_HSGMII;
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break;
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case PHY_INTERFACE_MODE_1000BASEX:
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sds_mode = RTL930X_SDS_MODE_1000BASEX;
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break;
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case PHY_INTERFACE_MODE_XGMII:
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sds_mode = RTL930X_SDS_MODE_XGMII;
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break;
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case PHY_INTERFACE_MODE_10GBASER:
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sds_mode = RTL930X_SDS_MODE_10GBASER;
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break;
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case PHY_INTERFACE_MODE_USXGMII:
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sds_mode = RTL930X_SDS_MODE_USXGMII;
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break;
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default:
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pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode));
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return -EINVAL;
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}
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pr_info("%s CMU BAND is %d\n", __func__, rtl9300_sds_cmu_band_get(sds_num));
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/* Turn Off Serdes */
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rtl9300_sds_rst(sds_num, RTL930X_SDS_OFF);
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pr_info("%s PATCHING SerDes %d\n", __func__, sds_num);
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if (sds_num % 2) {
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for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane1) / sizeof(sds_config); ++i) {
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rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane1[i].page,
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rtl9300_a_sds_10gr_lane1[i].reg,
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rtl9300_a_sds_10gr_lane1[i].data);
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}
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} else {
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for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane0) / sizeof(sds_config); ++i) {
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rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane0[i].page,
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rtl9300_a_sds_10gr_lane0[i].reg,
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rtl9300_a_sds_10gr_lane0[i].data);
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}
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}
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rtl9300_phy_enable_10g_1g(sds_num);
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/* Disable MAC */
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sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);
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mdelay(20);
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/* ----> dal_longan_sds_mode_set */
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pr_info("%s: Configuring RTL9300 SERDES %d, mode %02x\n", __func__, sds_num, sds_mode);
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/* Configure link to MAC */
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rtl9300_serdes_mac_link_config(sds_num, true, true); /* MAC Construct */
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/* Disable MAC */
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sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);
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mdelay(20);
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rtl9300_force_sds_mode(sds_num, PHY_INTERFACE_MODE_NA);
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/* Re-Enable MAC */
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sw_w32_mask(1, 0, RTL930X_MAC_FORCE_MODE_CTRL);
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rtl9300_force_sds_mode(sds_num, phy_mode);
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/* Do RX calibration */
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do {
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rtl9300_do_rx_calibration(sds_num, phy_mode);
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calib_tries++;
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mdelay(50);
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} while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
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if (calib_tries >= 3)
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pr_err("%s CALIBTRATION FAILED\n", __func__);
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rtl9300_sds_tx_config(sds_num, phy_mode);
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/* The clock needs only to be configured on the FPGA implementation */
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return 0;
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}
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void rtl9310_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
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{
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int l = end_bit - start_bit + 1;
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@ -3870,7 +3830,7 @@ static int rtl9300_serdes_probe(struct phy_device *phydev)
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phydev_info(phydev, "Detected internal RTL9300 Serdes\n");
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return rtl9300_configure_serdes(phydev);
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return 0;
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}
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static struct phy_driver rtl83xx_phy_driver[] = {
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