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switch driver cleanup, 1st phase

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SVN-Revision: 9324
This commit is contained in:
Gabor Juhos 2007-10-15 06:22:34 +00:00
parent 8cdc610404
commit 9d685a8597
3 changed files with 598 additions and 410 deletions
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895
target/linux/adm5120/files/drivers/net/adm5120sw.c
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87
target/linux/adm5120/files/drivers/net/adm5120sw.h
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@ -10,93 +10,8 @@
#ifndef _INCLUDE_ADM5120SW_H_
#define _INCLUDE_ADM5120SW_H_
#define SW_BASE KSEG1ADDR(0x12000000)
#define SW_DEVS 6
#define ETH_TX_TIMEOUT HZ*400
#define ETH_FCS 4;
#define ADM5120_CODE 0x00 /* CPU description */
#define ADM5120_CODE_PQFP 0x20000000 /* package type */
#define ADM5120_SW_CONF 0x20 /* Switch configuration register */
#define ADM5120_SW_CONF_BPM 0x00300000 /* Mask for backpressure mode */
#define ADM5120_CPUP_CONF 0x24 /* CPU port config */
#define ADM5120_DISCCPUPORT 0x00000001 /* disable cpu port */
#define ADM5120_CRC_PADDING 0x00000002 /* software crc */
#define ADM5120_BTM 0x00000004 /* bridge test mode */
#define ADM5120_DISUNSHIFT 9
#define ADM5120_DISUNALL 0x00007e00 /* disable unknown from all */
#define ADM5120_DISMCSHIFT 16
#define ADM5120_DISMCALL 0x003f0000 /* disable multicast from all */
#define ADM5120_PORT_CONF0 0x28
#define ADM5120_ENMC 0x00003f00 /* Enable MC routing (ex cpu) */
#define ADM5120_ENBP 0x003f0000 /* Enable Back Pressure */
#define ADM5120_PORTDISALL 0x0000003F
#define ADM5120_VLAN_GI 0x40 /* VLAN settings */
#define ADM5120_VLAN_GII 0x44
#define ADM5120_SEND_TRIG 0x48
#define ADM5120_SEND_TRIG_L 0x00000001
#define ADM5120_SEND_TRIG_H 0x00000002
#define ADM5120_MAC_WT0 0x58
#define ADM5120_MAC_WRITE 0x00000001
#define ADM5120_MAC_WRITE_DONE 0x00000002
#define ADM5120_VLAN_EN 0x00000040
#define ADM5120_MAC_WT1 0x5c
#define ADM5120_BW_CTL0 0x60 /* Bandwidth control 0 */
#define ADM5120_BW_CTL1 0x64 /* Bandwidth control 1 */
#define ADM5120_PHY_CNTL2 0x7c
#define ADM5120_AUTONEG 0x0000001f /* Auto negotiate */
#define ADM5120_NORMAL 0x01f00000 /* PHY normal mode */
#define ADM5120_AUTOMDIX 0x3e000000 /* Auto MDIX */
#define ADM5120_PHY_CNTL3 0x80
#define ADM5120_PHY_NTH 0x00000400
#define ADM5120_PRI_CNTL 0x84
#define ADM5120_INT_ST 0xb0
#define ADM5120_INT_RXH 0x0000004
#define ADM5120_INT_RXL 0x0000008
#define ADM5120_INT_HFULL 0x0000010
#define ADM5120_INT_LFULL 0x0000020
#define ADM5120_INT_TXH 0x0000001
#define ADM5120_INT_TXL 0x0000002
#define ADM5120_INT_MASK 0xb4
#define ADM5120_INTMASKALL 0x1FDEFFF /* All interrupts */
#define ADM5120_INTHANDLE (ADM5120_INT_RXH | ADM5120_INT_RXL | \
ADM5120_INT_HFULL | ADM5120_INT_LFULL | \
ADM5120_INT_TXH | ADM5120_INT_TXL)
#define ADM5120_SEND_HBADDR 0xd0
#define ADM5120_SEND_LBADDR 0xd4
#define ADM5120_RECEIVE_HBADDR 0xd8
#define ADM5120_RECEIVE_LBADDR 0xdc
struct adm5120_dma {
u32 data;
u32 cntl;
u32 len;
u32 status;
} __attribute__ ((packed));
#define ADM5120_DMA_MASK 0x01ffffff
#define ADM5120_DMA_OWN 0x80000000 /* buffer owner */
#define ADM5120_DMA_RINGEND 0x10000000 /* Last in DMA ring */
#define ADM5120_DMA_ADDR(ptr) ((u32)(ptr) & ADM5120_DMA_MASK)
#define ADM5120_DMA_PORTID 0x00007000
#define ADM5120_DMA_PORTSHIFT 12
#define ADM5120_DMA_LEN 0x07ff0000
#define ADM5120_DMA_LENSHIFT 16
#define ADM5120_DMA_FCSERR 0x00000008
#define ADM5120_DMA_TXH 2
#define ADM5120_DMA_TXL 64
#define ADM5120_DMA_RXH 2
#define ADM5120_DMA_RXL 64
#define ADM5120_DMA_RXSIZE 1550
#define ADM5120_DMA_EXTRA 20
struct adm5120_sw {
int port;
struct net_device_stats stats;
int port;
};
#define SIOCSMATRIX SIOCDEVPRIVATE

26
target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h
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@ -141,6 +141,9 @@
#define CPUP_CONF_DCPUP BIT(0) /* Disable CPU port */
#define CPUP_CONF_CRCP BIT(1) /* CRC padding from CPU */
#define CPUP_CONF_BTM BIT(2) /* Bridge Testing Mode */
#define CPUP_CONF_DUNP_SHIFT 9 /* Disable Unknown Packets for portX */
#define CPUP_CONF_DMCP_SHIFT 16 /* Disable Mcast Packets form portX */
#define CPUP_CONF_DBCP_SHIFT 24 /* Disable Bcast Packets form portX */
/* PORT_CONF0 register bits */
#define PORT_CONF0_DP_SHIFT 0 /* Disable Port */
@ -156,6 +159,26 @@
#define SEND_TRIG_STL BIT(0) /* Send Trigger Low */
#define SEND_TRIG_STH BIT(1) /* Send Trigger High */
/* MAC_WT0 register bits */
#define MAC_WT0_MAWC BIT(0) /* MAC address write command */
#define MAC_WT0_MWD_SHIFT 1
#define MAC_WT0_MWD BIT(1) /* MAC write done */
#define MAC_WT0_WFB BIT(2) /* Write Filter Bit */
#define MAC_WT0_WVN_SHIFT 3
#define MAC_WT0_WVE BIT(6) /* Write VLAN enable */
#define MAC_WT0_WPMN_SHIFT 7
#define MAC_WT0_WAF_SHIFT 13 /* Write Age Field shift */
#define MAC_WT0_WAF_EMPTY 0
#define MAC_WT0_WAF_STATIC 7
#define MAC_WT0_MAC0_SHIFT 16
#define MAC_WT0_MAC1_SHIFT 24
/* MAC_WT1 register bits */
#define MAC_WT1_MAC2_SHIFT 0
#define MAC_WT1_MAC3_SHIFT 8
#define MAC_WT1_MAC4_SHIFT 16
#define MAC_WT1_MAC5_SHIFT 24
/* BW_CNTL0/BW_CNTL1 register bits */
#define BW_CNTL_DISABLE 0x00
#define BW_CNTL_64K 0x01
@ -198,6 +221,9 @@
/* PHY_CNTL2_RMAE is bad in datasheet */
#define PHY_CNTL2_RMAE BIT(31) /* Recommended MCC Average enable */
/* PHY_CNTL3 register bits */
#define PHY_CNTL3_RNT BIT(10) /* Recommend Normal Threshold */
/* PORT_TH register bits */
#define PORT_TH_PPT_MASK BITMASK(8) /* Per Port Threshold */
#define PORT_TH_CPUT_SHIFT 8 /* CPU Port Buffer Threshold */