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ipq806x: fix missing changes in 5.4 for new cpufreq implementation
The new cpufreq dedicated driver changed the node structure on how the cache should be defined in the dts. The 5.4 dtsi addition patch has not been updated to follow the new implementation. Fix this to restore correct cache scaling and restore any performance regression. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Signed-off-by: maurerr <mariusd84@gmail.com>
This commit is contained in:
Ansuel Smith
maurerr
parent
62627a235b
commit
9ca7c3bbce
@ -26,7 +26,7 @@
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};
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cpu1: cpu@1 {
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@@ -38,11 +50,458 @@
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@@ -38,11 +50,476 @@
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next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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@ -42,19 +42,9 @@
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+ cpu-idle-states = <&CPU_SPC>;
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};
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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+ qcom,saw = <&saw_l2>;
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+ };
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+
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+ qcom,l2 {
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+ qcom,l2-rates = <384000000 1000000000 1200000000>;
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+ qcom,l2-cpufreq = <384000000 600000000 1200000000>;
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+ qcom,l2-volt = <1100000 1100000 1150000>;
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+ qcom,l2-supply = <&smb208_s1a>;
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+ };
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+
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- L2: l2-cache {
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- compatible = "cache";
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- cache-level = <2>;
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+ idle-states {
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+ CPU_SPC: spc {
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+ compatible = "qcom,idle-state-spc", "arm,idle-state";
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@ -66,6 +56,31 @@
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+ };
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+ };
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+
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+ opp_table_l2: opp_table_l2 {
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+ compatible = "operating-points-v2";
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+
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+ opp-384000000 {
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+ opp-hz = /bits/ 64 <384000000>;
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+ opp-microvolt = <1100000>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <0>;
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+ };
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+
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+ opp-1000000000 {
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+ opp-hz = /bits/ 64 <1000000000>;
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+ opp-microvolt = <1100000>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <1>;
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+ };
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+
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+ opp-1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <1150000>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <2>;
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+ };
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+ };
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+
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+ opp_table0: opp_table0 {
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+ compatible = "operating-points-v2-kryo-cpu";
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+ nvmem-cells = <&speedbin_efuse>;
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@ -78,6 +93,7 @@
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+ opp-microvolt-speed0-pvs3-v0 = <800000>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <0>;
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+ };
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+
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+ opp-600000000 {
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@ -88,6 +104,7 @@
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+ opp-microvolt-speed0-pvs3-v0 = <850000>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <1>;
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+ };
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+
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+ opp-800000000 {
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@ -98,6 +115,7 @@
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+ opp-microvolt-speed0-pvs3-v0 = <900000>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <1>;
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+ };
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+
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+ opp-1000000000 {
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@ -108,6 +126,7 @@
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+ opp-microvolt-speed0-pvs3-v0 = <950000>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <1>;
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+ };
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+
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+ opp-1200000000 {
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@ -118,6 +137,7 @@
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+ opp-microvolt-speed0-pvs3-v0 = <1000000>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <1>;
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+ };
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+
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+ opp-1400000000 {
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@ -128,6 +148,7 @@
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+ opp-microvolt-speed0-pvs3-v0 = <1050000>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <2>;
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+ };
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+ };
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+
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@ -485,7 +506,7 @@
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};
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};
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@@ -93,6 +552,15 @@
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@@ -93,6 +570,15 @@
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};
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};
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@ -501,10 +522,21 @@
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firmware {
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scm {
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compatible = "qcom,scm-ipq806x", "qcom,scm";
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@@ -120,6 +588,84 @@
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@@ -120,6 +606,95 @@
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reg-names = "lpass-lpaif";
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};
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+ L2: l2-cache {
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+ compatible = "qcom,krait-cache", "cache";
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+ cache-level = <2>;
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+ qcom,saw = <&saw_l2>;
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+
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+ clocks = <&kraitcc 4>;
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+ clock-names = "l2";
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+ l2-supply = <&smb208_s1a>;
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+ operating-points-v2 = <&opp_table_l2>;
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+ };
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+
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+ qfprom: qfprom@700000 {
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+ compatible = "qcom,qfprom", "syscon";
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+ reg = <0x700000 0x1000>;
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@ -586,7 +618,7 @@
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qcom_pinmux: pinmux@800000 {
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compatible = "qcom,ipq8064-pinctrl";
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reg = <0x800000 0x4000>;
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@@ -159,6 +705,15 @@
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@@ -159,6 +734,15 @@
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};
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};
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@ -602,7 +634,7 @@
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spi_pins: spi_pins {
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mux {
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pins = "gpio18", "gpio19", "gpio21";
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@@ -168,6 +723,53 @@
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@@ -168,6 +752,53 @@
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};
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};
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@ -656,7 +688,7 @@
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leds_pins: leds_pins {
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mux {
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pins = "gpio7", "gpio8", "gpio9",
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@@ -229,6 +831,17 @@
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@@ -229,6 +860,17 @@
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clock-output-names = "acpu1_aux";
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};
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@ -674,7 +706,7 @@
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saw0: regulator@2089000 {
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compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
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reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
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@@ -241,6 +854,17 @@
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@@ -241,6 +883,17 @@
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regulator;
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};
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@ -692,7 +724,7 @@
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gsbi2: gsbi@12480000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <2>;
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@@ -436,6 +1060,15 @@
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@@ -436,6 +1089,15 @@
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#power-domain-cells = <1>;
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};
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@ -708,7 +740,7 @@
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tcsr: syscon@1a400000 {
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compatible = "qcom,tcsr-ipq8064", "syscon";
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reg = <0x1a400000 0x100>;
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@@ -448,6 +1081,95 @@
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@@ -448,6 +1110,95 @@
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#reset-cells = <1>;
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};
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@ -804,7 +836,7 @@
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pcie0: pci@1b500000 {
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compatible = "qcom,pcie-ipq8064";
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reg = <0x1b500000 0x1000
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@@ -601,6 +1323,167 @@
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@@ -601,6 +1352,167 @@
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perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
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};
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@ -972,7 +1004,7 @@
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vsdcc_fixed: vsdcc-regulator {
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compatible = "regulator-fixed";
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regulator-name = "SDCC Power";
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@@ -676,4 +1559,17 @@
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@@ -676,4 +1588,17 @@
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};
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};
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};
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@ -1,6 +1,6 @@
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -865,6 +865,41 @@
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@@ -894,6 +894,41 @@
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reg = <0x12100000 0x10000>;
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};
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