From 9b9c6facfc9f887e5bee3628752ff4572730fbfa Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Sat, 13 Jul 2013 22:29:53 +0000 Subject: [PATCH] ar71xx: fix ar933x watchdog clock (#13866) Signed-off-by: Felix Fietkau SVN-Revision: 37273 --- ...200-MIPS-ath79-fix-ar933x-watchdog-clock.patch | 15 +++++++++++++++ ...200-MIPS-ath79-fix-ar933x-watchdog-clock.patch | 15 +++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 target/linux/ar71xx/patches-3.10/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch create mode 100644 target/linux/ar71xx/patches-3.8/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch diff --git a/target/linux/ar71xx/patches-3.10/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch b/target/linux/ar71xx/patches-3.10/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch new file mode 100644 index 00000000000..b3a3cd39f49 --- /dev/null +++ b/target/linux/ar71xx/patches-3.10/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch @@ -0,0 +1,15 @@ +From: Felix Fietkau +Subject: [PATCH] MIPS: ath79: fix ar933x watchdog clock + +Signed-off-by: Felix Fietkau +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -164,7 +164,7 @@ static void __init ar933x_clocks_init(vo + ath79_ahb_clk.rate = freq / t; + } + +- ath79_wdt_clk.rate = ath79_ref_clk.rate; ++ ath79_wdt_clk.rate = ath79_ahb_clk.rate; + ath79_uart_clk.rate = ath79_ref_clk.rate; + } + diff --git a/target/linux/ar71xx/patches-3.8/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch b/target/linux/ar71xx/patches-3.8/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch new file mode 100644 index 00000000000..b3a3cd39f49 --- /dev/null +++ b/target/linux/ar71xx/patches-3.8/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch @@ -0,0 +1,15 @@ +From: Felix Fietkau +Subject: [PATCH] MIPS: ath79: fix ar933x watchdog clock + +Signed-off-by: Felix Fietkau +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -164,7 +164,7 @@ static void __init ar933x_clocks_init(vo + ath79_ahb_clk.rate = freq / t; + } + +- ath79_wdt_clk.rate = ath79_ref_clk.rate; ++ ath79_wdt_clk.rate = ath79_ahb_clk.rate; + ath79_uart_clk.rate = ath79_ref_clk.rate; + } +