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Revert "qca-ssdk: fix unsupported scenario with PORT1 not declared in switch bmp"
This reverts commit 8cce00bc9d.
The confusion was real and this change cause regression on other
advanced devices that makes actual use of the first_phy_addr value.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This commit is contained in:
Christian Marangi
parent
8fc496be86
commit
9b4628eaee
@ -1,7 +1,7 @@
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include $(TOPDIR)/rules.mk
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PKG_NAME:=qca-ssdk
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PKG_RELEASE:=2
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PKG_RELEASE:=1
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PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-ssdk.git
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PKG_SOURCE_PROTO:=git
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@ -1,264 +0,0 @@
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From 46ed8163ac0d9a11a629f1c446e8c5e711cf35d6 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Sat, 11 Nov 2023 18:13:02 +0100
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Subject: [PATCH] malibu-phy: drop usage of first_phy_addr
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I'm very confused by this and to me it's not clear the real usage of
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this logic.
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From what I can see the usage of this is EXTREMELY FRAGILE and results
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in dangerous results if the OEM (or anyone that by chance try to
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implement things in a logical manner) deviates from the default values
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from the "magical template".
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To be in more details. With QSDK 12.4, some tweaks were done to improve
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autoneg and now on every call of port status, the phydev is tried to
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add. This resulted in the call and log spam of an error with ports that
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are actually not present on the system with qsdk reporting phydev is
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NULL. This itself is not an error and printing the error is correct.
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What is actually an error from ages is setting generic bitmap reporting
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presence of port that are actually not present. This is very common on
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OEM where the switch_lan_bmp is always a variant of 0x1e (that on bitmap
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results in PORT1 PORT2 PORT3 PORT4 present) or 0x3e (PORT1 PORT2 PORT3
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PORT4 PORT5). Reality is that many device are used as AP with one LAN
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port or one WAN port. (or even exotic configuration with PORT1 not
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present and PORT2 PORT3 PORT4 present (Xiaomi 3600)
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With this finding one can say... ok nice, then lets update the DT and
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set the correct bitmap...
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Again world is a bad place and reality is that this cause wonderful
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regression in some case of by extreme luck the first ever connected
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port working and the rest of the switch dead.
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The problem has been bisected to all the device that doesn't have the
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PORT1 declared in any of the bitmap.
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With this perfection in mind, on to the REAL problem.
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malibu_phy_hw_init FOR SOME REASON, set a global variable first_phy_addr
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to the first detected PHY addr that coincidentally is always PORT1.
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PORT1 addr is 0x0. The entire code in malibu_phy use this variable to
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derive the phy addrs in some function.
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Declaring a bitmap where the PORT1 is missing (or worse PORT4 the only
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one connected) result in first_phy_addr set to 1 or whatever phy addr is
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detected first setting wrong value all over the init stage.
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To fix this, just drop this variable and hardcode everything to assume
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the first phy adrr is ALWAYS 0 and remove calculation and use define for
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special case.
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With the following change normal switch traffic is restored and ports
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function is recovered.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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---
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src/hsl/phy/malibu_phy.c | 63 +++++++++++++++++-----------------------
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1 file changed, 26 insertions(+), 37 deletions(-)
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--- a/src/hsl/phy/malibu_phy.c
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+++ b/src/hsl/phy/malibu_phy.c
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@@ -26,8 +26,9 @@
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#include "qcaphy_common.h"
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#include "ssdk_plat.h"
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-static a_uint32_t first_phy_addr = MAX_PHY_ADDR;
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static a_uint32_t combo_phy_addr = MAX_PHY_ADDR;
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+#define PORT4_PHY_ID 0x4
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+#define PORT5_PHY_ID 0x5
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#define COMBO_PHY_ID combo_phy_addr
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/******************************************************************************
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@@ -1250,10 +1251,10 @@ sw_error_t
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malibu_phy_serdes_reset(a_uint32_t dev_id)
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{
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- hsl_phy_mii_reg_write(dev_id, first_phy_addr + MALIBU_PHY_PSGMII_ADDR_INC,
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+ hsl_phy_mii_reg_write(dev_id, MALIBU_PHY_PSGMII_ADDR_INC,
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MALIBU_MODE_RESET_REG, MALIBU_MODE_CHANAGE_RESET);
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mdelay(100);
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- hsl_phy_mii_reg_write(dev_id, first_phy_addr + MALIBU_PHY_PSGMII_ADDR_INC,
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+ hsl_phy_mii_reg_write(dev_id, MALIBU_PHY_PSGMII_ADDR_INC,
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MALIBU_MODE_RESET_REG, MALIBU_MODE_RESET_DEFAULT_VALUE);
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return SW_OK;
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@@ -1271,8 +1272,7 @@ malibu_phy_interface_set_mode(a_uint32_t
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a_uint16_t phy_data = 0;
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static fal_port_interface_mode_t phy_mode = PORT_INTERFACE_MODE_MAX;
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- if ((phy_addr < first_phy_addr) ||
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- (phy_addr > (first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)))
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+ if (phy_addr > MALIBU_PHY_MAX_ADDR_INC)
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return SW_NOT_SUPPORTED;
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/*if interface_mode have been configured, then no need to configure again*/
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if(phy_mode == interface_mode)
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@@ -1295,20 +1295,19 @@ malibu_phy_interface_set_mode(a_uint32_t
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return SW_BAD_PARAM;
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}
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- hsl_phy_modify_mii(dev_id,
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- first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG,
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+ hsl_phy_modify_mii(dev_id, MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG,
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BITS(0, 4), phy_data);
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/* reset operation */
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malibu_phy_serdes_reset(dev_id);
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if (interface_mode == PHY_PSGMII_FIBER) {
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- hsl_phy_mii_reg_write(dev_id, first_phy_addr + MALIBU_PHY_MAX_ADDR_INC,
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+ hsl_phy_mii_reg_write(dev_id, MALIBU_PHY_MAX_ADDR_INC,
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MALIBU_PHY_CHIP_CONFIG, MALIBU_MODECTRL_DFLT);
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- hsl_phy_mii_reg_write(dev_id, first_phy_addr + MALIBU_PHY_MAX_ADDR_INC,
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+ hsl_phy_mii_reg_write(dev_id, MALIBU_PHY_MAX_ADDR_INC,
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MALIBU_PHY_CONTROL, MALIBU_MIICTRL_DFLT);
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hsl_phy_phydev_autoneg_update(dev_id,
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- first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, A_FALSE, 0);
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+ MALIBU_PHY_MAX_ADDR_INC, A_FALSE, 0);
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}
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phy_mode = interface_mode;
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SSDK_DEBUG("malibu phy is configured as phy_mode:0x%x\n", phy_mode);
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@@ -1329,13 +1328,12 @@ malibu_phy_interface_get_mode(a_uint32_t
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a_uint16_t phy_data;
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a_uint16_t copper_mode;
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- if ((phy_addr < first_phy_addr) ||
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- (phy_addr > (first_phy_addr + MALIBU_PHY_MAX_ADDR_INC))) {
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+ if (phy_addr > MALIBU_PHY_MAX_ADDR_INC) {
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return SW_NOT_SUPPORTED;
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}
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phy_data = hsl_phy_mii_reg_read(dev_id,
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- first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG);
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+ MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG);
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copper_mode = ((phy_data & MALIBU_PHY_COPPER_MODE) >> 0xf);
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phy_data &= 0x000f;
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@@ -1344,13 +1342,13 @@ malibu_phy_interface_get_mode(a_uint32_t
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*interface_mode = PHY_PSGMII_BASET;
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break;
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case MALIBU_PHY_PSGMII_BX1000:
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- if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)
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+ if (phy_addr == MALIBU_PHY_MAX_ADDR_INC)
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*interface_mode = PHY_PSGMII_BX1000;
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else
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*interface_mode = PHY_PSGMII_BASET;
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break;
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case MALIBU_PHY_PSGMII_FX100:
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- if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)
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+ if (phy_addr == MALIBU_PHY_MAX_ADDR_INC)
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*interface_mode = PHY_PSGMII_FX100;
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else
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*interface_mode = PHY_PSGMII_BASET;
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@@ -1359,14 +1357,14 @@ malibu_phy_interface_get_mode(a_uint32_t
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if (copper_mode) {
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*interface_mode = PHY_PSGMII_BASET;
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} else {
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- if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)
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+ if (phy_addr == MALIBU_PHY_MAX_ADDR_INC)
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*interface_mode = PHY_PSGMII_FIBER;
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else
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*interface_mode = PHY_PSGMII_BASET;
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}
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break;
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case MALIBU_PHY_SGMII_BASET:
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- if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)
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+ if (phy_addr == MALIBU_PHY_MAX_ADDR_INC)
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*interface_mode = PHY_SGMII_BASET;
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else
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*interface_mode = PORT_QSGMII;
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@@ -1392,13 +1390,12 @@ malibu_phy_interface_get_mode_status(a_u
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a_uint16_t phy_data, phy_mode, phy_mode_status;
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a_uint16_t copper_mode;
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- if ((phy_addr < first_phy_addr) ||
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- (phy_addr > (first_phy_addr + MALIBU_PHY_MAX_ADDR_INC))) {
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+ if (phy_addr > MALIBU_PHY_MAX_ADDR_INC) {
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return SW_NOT_SUPPORTED;
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}
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phy_data = hsl_phy_mii_reg_read(dev_id,
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- first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG);
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+ MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG);
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copper_mode = ((phy_data & MALIBU_PHY_COPPER_MODE) >> 0xf);
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phy_mode = phy_data & 0x000f;
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phy_mode_status = (phy_data & 0x00f0) >> 0x4;
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@@ -1407,7 +1404,7 @@ malibu_phy_interface_get_mode_status(a_u
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if (copper_mode) {
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*interface_mode_status = PHY_PSGMII_BASET;
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} else {
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- if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)
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+ if (phy_addr == MALIBU_PHY_MAX_ADDR_INC)
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*interface_mode_status = PHY_PSGMII_FIBER;
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else
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*interface_mode_status = PHY_PSGMII_BASET;
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@@ -1418,19 +1415,19 @@ malibu_phy_interface_get_mode_status(a_u
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*interface_mode_status = PHY_PSGMII_BASET;
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break;
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case MALIBU_PHY_PSGMII_BX1000:
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- if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)
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+ if (phy_addr == MALIBU_PHY_MAX_ADDR_INC)
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*interface_mode_status = PHY_PSGMII_BX1000;
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else
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*interface_mode_status = PHY_PSGMII_BASET;
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break;
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case MALIBU_PHY_PSGMII_FX100:
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- if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)
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+ if (phy_addr == MALIBU_PHY_MAX_ADDR_INC)
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*interface_mode_status = PHY_PSGMII_FX100;
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else
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*interface_mode_status = PHY_PSGMII_BASET;
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break;
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case MALIBU_PHY_SGMII_BASET:
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- if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)
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+ if (phy_addr == MALIBU_PHY_MAX_ADDR_INC)
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*interface_mode_status = PHY_SGMII_BASET;
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else
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*interface_mode_status = PORT_QSGMII;
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@@ -1795,10 +1792,6 @@ malibu_phy_hw_init(a_uint32_t dev_id, a_
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{
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phy_cnt ++;
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phy_addr = qca_ssdk_port_to_phy_addr(dev_id, port_id);
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- if (phy_addr < first_phy_addr)
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- {
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- first_phy_addr = phy_addr;
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- }
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/*enable phy power saving function by default */
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malibu_phy_set_8023az(dev_id, phy_addr, A_TRUE);
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malibu_phy_set_powersave(dev_id, phy_addr, A_TRUE);
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@@ -1824,29 +1817,25 @@ malibu_phy_hw_init(a_uint32_t dev_id, a_
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MALIBU_EXTENDED_NEXT_PAGE_EN, 0);
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}
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}
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- /* qca 8072 two ports phy chip's firstly address to init phy chip */
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- if ((phy_cnt == QCA8072_PHY_NUM) && (first_phy_addr >= 0x3)) {
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- first_phy_addr = first_phy_addr - 0x3;
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- }
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/*workaround to enable AZ transmitting ability*/
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- hsl_phy_mmd_reg_write(dev_id, first_phy_addr + 5, A_FALSE, MALIBU_PHY_MMD1_NUM,
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+ hsl_phy_mmd_reg_write(dev_id, PORT5_PHY_ID, A_FALSE, MALIBU_PHY_MMD1_NUM,
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MALIBU_PSGMII_MODE_CTRL, MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VALUE);
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/* adjust psgmii serdes tx amp */
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- hsl_phy_mii_reg_write(dev_id, first_phy_addr + 5,
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+ hsl_phy_mii_reg_write(dev_id, PORT5_PHY_ID,
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MALIBU_PSGMII_TX_DRIVER_1_CTRL, MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP);
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/* to avoid psgmii module goes into hibernation, work with psgmii self test*/
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- hsl_phy_modify_mmd(dev_id, first_phy_addr + 4, A_FALSE, MALIBU_PHY_MMD3_NUM,
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+ hsl_phy_modify_mmd(dev_id, PORT4_PHY_ID, A_FALSE, MALIBU_PHY_MMD3_NUM,
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MALIBU_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL, BIT(1), 0);
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mode = ssdk_dt_global_get_mac_mode(dev_id, 0);
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if (mode == PORT_WRAPPER_PSGMII_FIBER)
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- malibu_phy_interface_set_mode(dev_id, first_phy_addr, PHY_PSGMII_FIBER);
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+ malibu_phy_interface_set_mode(dev_id, 0x0, PHY_PSGMII_FIBER);
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/*init combo phy address*/
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- combo_phy_addr = first_phy_addr+4;
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+ combo_phy_addr = PORT4_PHY_ID;
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return SW_OK;
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}
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