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kernel: remove ocf support, cryptodev-linux should be used instead

Browse Source 
Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
Felix Fietkau 2016-05-12 18:38:51 +02:00
parent 3d6d5ccf59
commit 98010ab489
226 changed files with 4 additions and 94740 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
package/kernel/linux/modules/crypto.mk
View File

@ -631,54 +631,6 @@ endif
$(eval $(call KernelPackage,crypto-misc))
define KernelPackage/crypto-ocf
TITLE:=OCF modules
DEPENDS:=+@OPENSSL_ENGINE_CRYPTO @!TARGET_uml +kmod-crypto-manager
KCONFIG:= \
CONFIG_OCF_OCF \
CONFIG_OCF_CRYPTODEV \
CONFIG_OCF_CRYPTOSOFT \
CONFIG_OCF_FIPS=y \
CONFIG_OCF_RANDOMHARVEST=y
FILES:= \
$(LINUX_DIR)/crypto/ocf/ocf.ko \
$(LINUX_DIR)/crypto/ocf/cryptodev.ko \
$(LINUX_DIR)/crypto/ocf/cryptosoft.ko
AUTOLOAD:=$(call AutoLoad,09, \
ocf \
cryptodev \
cryptosoft \
)
$(call AddDepends/crypto)
endef
$(eval $(call KernelPackage,crypto-ocf))
define KernelPackage/crypto-ocf-hifn7751
TITLE:=OCF support for Hifn 6500/7751/7811/795x, Invertex AEON and NetSec 7751 devices
DEPENDS:=+@OPENSSL_ENGINE_CRYPTO @PCI_SUPPORT @!TARGET_uml kmod-crypto-ocf
KCONFIG:=CONFIG_OCF_HIFN
FILES:=$(LINUX_DIR)/crypto/ocf/hifn/hifn7751.ko
AUTOLOAD:=$(call AutoLoad,10,hifn7751)
$(call AddDepends/crypto)
endef
$(eval $(call KernelPackage,crypto-ocf-hifn7751))
define KernelPackage/crypto-ocf-hifnhipp
TITLE:=OCF support for Hifn 7855/8155 devices
DEPENDS:=+@OPENSSL_ENGINE_CRYPTO @PCI_SUPPORT @!TARGET_uml kmod-crypto-ocf
KCONFIG:=CONFIG_OCF_HIFNHIPP
FILES:=$(LINUX_DIR)/crypto/ocf/hifn/hifnHIPP.ko
AUTOLOAD:=$(call AutoLoad,10,hifnHIPP)
$(call AddDepends/crypto)
endef
$(eval $(call KernelPackage,crypto-ocf-hifnhipp))
define KernelPackage/crypto-null
TITLE:=Null CryptoAPI module
KCONFIG:=CONFIG_CRYPTO_NULL

2
target/linux/brcm47xx/generic/profiles/WGT634U.mk
View File

@ -7,7 +7,7 @@
define Profile/WGT634U
NAME:=Netgear WGT634U
PACKAGES:=kmod-b44 kmod-ath5k kmod-usb-core kmod-usb2 kmod-ocf-ubsec-ssb
PACKAGES:=kmod-b44 kmod-ath5k kmod-usb-core kmod-usb2
endef
define Profile/WGT634U/Description

2
target/linux/brcm47xx/generic/profiles/WRT350Nv1.mk
View File

@ -7,7 +7,7 @@
define Profile/WRT350Nv1
NAME:=Linksys WRT350Nv1
PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-tg3 kmod-ocf-ubsec-ssb
PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-tg3
endef
define Profile/WRT350Nv1/Description

2
target/linux/brcm47xx/legacy/profiles/WGT634U.mk
View File

@ -7,7 +7,7 @@
define Profile/WGT634U
NAME:=Netgear WGT634U
PACKAGES:=kmod-ath5k kmod-usb-core kmod-usb2 kmod-ocf-ubsec-ssb
PACKAGES:=kmod-ath5k kmod-usb-core kmod-usb2
endef
define Profile/WGT634U/Description

15
target/linux/brcm47xx/modules.mk
View File

@ -5,21 +5,6 @@
# See /LICENSE for more information.
#
define KernelPackage/ocf-ubsec-ssb
TITLE:=BCM5365P IPSec Core driver
DEPENDS:=@TARGET_brcm47xx @!TARGET_brcm47xx_mips74k +kmod-crypto-ocf
KCONFIG:=CONFIG_OCF_UBSEC_SSB
FILES:=$(LINUX_DIR)/crypto/ocf/ubsec_ssb/ubsec_ssb.ko
AUTOLOAD:=$(call AutoLoad,10,ubsec_ssb)
$(call AddDepends/crypto)
endef
define KernelPackage/ocf-ubsec-ssb/description
This package contains the OCF driver for the BCM5365p IPSec Core
endef
$(eval $(call KernelPackage,ocf-ubsec-ssb))
define KernelPackage/bgmac
TITLE:=Broadcom bgmac driver
KCONFIG:=CONFIG_BGMAC

13
target/linux/generic/config-3.18
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@ -2701,19 +2701,6 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_OABI_COMPAT is not set
# CONFIG_OBS600 is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_OCF_BENCH is not set
# CONFIG_OCF_C7108 is not set
# CONFIG_OCF_CRYPTOCTEON is not set
# CONFIG_OCF_EP80579 is not set
# CONFIG_OCF_HIFN is not set
# CONFIG_OCF_HIFNHIPP is not set
# CONFIG_OCF_IXP4XX is not set
# CONFIG_OCF_KIRKWOOD is not set
# CONFIG_OCF_OCF is not set
# CONFIG_OCF_OCFNULL is not set
# CONFIG_OCF_SAFE is not set
# CONFIG_OCF_TALITOS is not set
# CONFIG_OCF_UBSEC_SSB is not set
# CONFIG_OC_ETM is not set
# CONFIG_OF_SELFTEST is not set
# CONFIG_OMAP2_DSS_DEBUG is not set

13
target/linux/generic/config-4.1
View File

@ -2799,19 +2799,6 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_OABI_COMPAT is not set
# CONFIG_OBS600 is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_OCF_BENCH is not set
# CONFIG_OCF_C7108 is not set
# CONFIG_OCF_CRYPTOCTEON is not set
# CONFIG_OCF_EP80579 is not set
# CONFIG_OCF_HIFN is not set
# CONFIG_OCF_HIFNHIPP is not set
# CONFIG_OCF_IXP4XX is not set
# CONFIG_OCF_KIRKWOOD is not set
# CONFIG_OCF_OCF is not set
# CONFIG_OCF_OCFNULL is not set
# CONFIG_OCF_SAFE is not set
# CONFIG_OCF_TALITOS is not set
# CONFIG_OCF_UBSEC_SSB is not set
# CONFIG_OC_ETM is not set
# CONFIG_OF_OVERLAY is not set
# CONFIG_OF_SELFTEST is not set

13
target/linux/generic/config-4.4
View File

@ -2771,19 +2771,6 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_OABI_COMPAT is not set
# CONFIG_OBS600 is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_OCF_BENCH is not set
# CONFIG_OCF_C7108 is not set
# CONFIG_OCF_CRYPTOCTEON is not set
# CONFIG_OCF_EP80579 is not set
# CONFIG_OCF_HIFN is not set
# CONFIG_OCF_HIFNHIPP is not set
# CONFIG_OCF_IXP4XX is not set
# CONFIG_OCF_KIRKWOOD is not set
# CONFIG_OCF_OCF is not set
# CONFIG_OCF_OCFNULL is not set
# CONFIG_OCF_SAFE is not set
# CONFIG_OCF_TALITOS is not set
# CONFIG_OCF_UBSEC_SSB is not set
# CONFIG_OF_OVERLAY is not set
# CONFIG_OF_UNITTEST is not set
# CONFIG_OMAP2_DSS_DEBUG is not set

38
target/linux/generic/files/crypto/ocf/Config.in
View File

@ -1,38 +0,0 @@
#############################################################################
mainmenu_option next_comment
comment 'OCF Configuration'
tristate 'OCF (Open Cryptograhic Framework)' CONFIG_OCF_OCF
dep_mbool ' enable fips RNG checks (fips check on RNG data before use)' \
CONFIG_OCF_FIPS $CONFIG_OCF_OCF
dep_mbool ' enable harvesting entropy for /dev/random' \
CONFIG_OCF_RANDOMHARVEST $CONFIG_OCF_OCF
dep_tristate ' cryptodev (user space support)' \
CONFIG_OCF_CRYPTODEV $CONFIG_OCF_OCF
dep_tristate ' cryptosoft (software crypto engine)' \
CONFIG_OCF_CRYPTOSOFT $CONFIG_OCF_OCF
dep_tristate ' safenet (HW crypto engine)' \
CONFIG_OCF_SAFE $CONFIG_OCF_OCF
dep_tristate ' IXP4xx (HW crypto engine)' \
CONFIG_OCF_IXP4XX $CONFIG_OCF_OCF
dep_mbool ' Enable IXP4xx HW to perform SHA1 and MD5 hashing (very slow)' \
CONFIG_OCF_IXP4XX_SHA1_MD5 $CONFIG_OCF_IXP4XX
dep_tristate ' hifn (HW crypto engine)' \
CONFIG_OCF_HIFN $CONFIG_OCF_OCF
dep_tristate ' talitos (HW crypto engine)' \
CONFIG_OCF_TALITOS $CONFIG_OCF_OCF
dep_tristate ' pasemi (HW crypto engine)' \
CONFIG_OCF_PASEMI $CONFIG_OCF_OCF
dep_tristate ' ep80579 (HW crypto engine)' \
CONFIG_OCF_EP80579 $CONFIG_OCF_OCF
dep_tristate ' Micronas c7108 (HW crypto engine)' \
CONFIG_OCF_C7108 $CONFIG_OCF_OCF
dep_tristate ' uBsec BCM5365 (HW crypto engine)'
CONFIG_OCF_UBSEC_SSB $CONFIG_OCF_OCF
dep_tristate ' ocfnull (does no crypto)' \
CONFIG_OCF_OCFNULL $CONFIG_OCF_OCF
dep_tristate ' ocf-bench (HW crypto in-kernel benchmark)' \
CONFIG_OCF_BENCH $CONFIG_OCF_OCF
endmenu
#############################################################################

128
target/linux/generic/files/crypto/ocf/Kconfig
View File

@ -1,128 +0,0 @@
menu "OCF Configuration"
config OCF_OCF
tristate "OCF (Open Cryptograhic Framework)"
help
A linux port of the OpenBSD/FreeBSD crypto framework.
config OCF_RANDOMHARVEST
bool "crypto random --- harvest entropy for /dev/random"
depends on OCF_OCF
help
Includes code to harvest random numbers from devices that support it.
config OCF_FIPS
bool "enable fips RNG checks"
depends on OCF_OCF && OCF_RANDOMHARVEST
help
Run all RNG provided data through a fips check before
adding it /dev/random's entropy pool.
config OCF_CRYPTODEV
tristate "cryptodev (user space support)"
depends on OCF_OCF
help
The user space API to access crypto hardware.
config OCF_CRYPTOSOFT
tristate "cryptosoft (software crypto engine)"
depends on OCF_OCF
select CRYPTO
select CRYPTO_HASH
select CRYPTO_BLKCIPHER
help
A software driver for the OCF framework that uses
the kernel CryptoAPI.
config OCF_SAFE
tristate "safenet (HW crypto engine)"
depends on OCF_OCF
help
A driver for a number of the safenet Excel crypto accelerators.
Currently tested and working on the 1141 and 1741.
config OCF_IXP4XX
tristate "IXP4xx (HW crypto engine)"
depends on OCF_OCF
help
XScale IXP4xx crypto accelerator driver. Requires the
Intel Access library.
config OCF_IXP4XX_SHA1_MD5
bool "IXP4xx SHA1 and MD5 Hashing"
depends on OCF_IXP4XX
help
Allows the IXP4xx crypto accelerator to perform SHA1 and MD5 hashing.
Note: this is MUCH slower than using cryptosoft (software crypto engine).
config OCF_HIFN
tristate "hifn (HW crypto engine)"
depends on OCF_OCF && PCI
help
OCF driver for various HIFN based crypto accelerators.
(7951, 7955, 7956, 7751, 7811)
config OCF_HIFNHIPP
tristate "Hifn HIPP (HW packet crypto engine)"
depends on OCF_OCF
help
OCF driver for various HIFN (HIPP) based crypto accelerators
(7855)
config OCF_TALITOS
tristate "talitos (HW crypto engine)"
depends on OCF_OCF
help
OCF driver for Freescale's security engine (SEC/talitos).
config OCF_PASEMI
tristate "pasemi (HW crypto engine)"
depends on OCF_OCF && PPC_PASEMI
help
OCF driver for the PA Semi PWRficient DMA Engine
config OCF_EP80579
tristate "ep80579 (HW crypto engine)"
depends on OCF_OCF
help
OCF driver for the Intel EP80579 Integrated Processor Product Line.
config OCF_CRYPTOCTEON
tristate "cryptocteon (HW crypto engine)"
depends on OCF_OCF
help
OCF driver for the Cavium OCTEON Processors.
config OCF_KIRKWOOD
tristate "kirkwood (HW crypto engine)"
depends on OCF_OCF
help
OCF driver for the Marvell Kirkwood (88F6xxx) Processors.
config OCF_C7108
tristate "Micronas 7108 (HW crypto engine)"
depends on OCF_OCF
help
OCF driver for the Microna 7108 Cipher processors.
config OCF_UBSEC_SSB
tristate "uBsec BCM5365 (HW crypto engine)"
depends on OCF_OCF
help
OCF driver for uBsec BCM5365 hardware crypto accelerator.
config OCF_OCFNULL
tristate "ocfnull (fake crypto engine)"
depends on OCF_OCF
help
OCF driver for measuring ipsec overheads (does no crypto)
config OCF_BENCH
tristate "ocf-bench (HW crypto in-kernel benchmark)"
depends on OCF_OCF
help
A very simple encryption test for the in-kernel interface
of OCF. Also includes code to benchmark the IXP Access library
for comparison.
endmenu

148
target/linux/generic/files/crypto/ocf/Makefile
View File

@ -1,148 +0,0 @@
# for SGlinux builds
-include $(ROOTDIR)/modules/.config
OCF_OBJS = crypto.o criov.o
ifdef CONFIG_OCF_RANDOMHARVEST
OCF_OBJS += random.o
endif
ifdef CONFIG_OCF_FIPS
OCF_OBJS += rndtest.o
endif
# Add in autoconf.h to get #defines for CONFIG_xxx
AUTOCONF_H=$(ROOTDIR)/modules/autoconf.h
ifeq ($(AUTOCONF_H), $(wildcard $(AUTOCONF_H)))
EXTRA_CFLAGS += -include $(AUTOCONF_H)
export EXTRA_CFLAGS
endif
ifndef obj
obj ?= .
_obj = subdir
mod-subdirs := safe hifn ixp4xx talitos ocfnull
export-objs += crypto.o criov.o random.o
list-multi += ocf.o
_slash :=
else
_obj = obj
_slash := /
endif
EXTRA_CFLAGS += -I$(obj)/.
obj-$(CONFIG_OCF_OCF) += ocf.o
obj-$(CONFIG_OCF_CRYPTODEV) += cryptodev.o
obj-$(CONFIG_OCF_CRYPTOSOFT) += cryptosoft.o
obj-$(CONFIG_OCF_BENCH) += ocf-bench.o
$(_obj)-$(CONFIG_OCF_SAFE) += safe$(_slash)
$(_obj)-$(CONFIG_OCF_HIFN) += hifn$(_slash)
$(_obj)-$(CONFIG_OCF_IXP4XX) += ixp4xx$(_slash)
$(_obj)-$(CONFIG_OCF_TALITOS) += talitos$(_slash)
$(_obj)-$(CONFIG_OCF_PASEMI) += pasemi$(_slash)
$(_obj)-$(CONFIG_OCF_EP80579) += ep80579$(_slash)
$(_obj)-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon$(_slash)
$(_obj)-$(CONFIG_OCF_KIRKWOOD) += kirkwood$(_slash)
$(_obj)-$(CONFIG_OCF_OCFNULL) += ocfnull$(_slash)
$(_obj)-$(CONFIG_OCF_C7108) += c7108$(_slash)
$(_obj)-$(CONFIG_OCF_UBSEC_SSB) += ubsec_ssb$(_slash)
ocf-objs := $(OCF_OBJS)
dummy:
@echo "Please consult the README for how to build OCF."
@echo "If you can't wait then the following should do it:"
@echo ""
@echo " make ocf_modules"
@echo " sudo make ocf_install"
@echo ""
@exit 1
$(list-multi) dummy1: $(ocf-objs)
$(LD) -r -o $@ $(ocf-objs)
.PHONY:
clean:
rm -f *.o *.ko .*.o.flags .*.ko.cmd .*.o.cmd .*.mod.o.cmd *.mod.c
rm -f */*.o */*.ko */.*.o.cmd */.*.ko.cmd */.*.mod.o.cmd */*.mod.c */.*.o.flags
rm -f */modules.order */modules.builtin modules.order modules.builtin
ifdef TOPDIR
-include $(TOPDIR)/Rules.make
endif
#
# targets to build easily on the current machine
#
ocf_make:
make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m
make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_CRYPTOSOFT=m
-make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_BENCH=m
-make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_OCFNULL=m
-make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_HIFN=m
ocf_modules:
$(MAKE) ocf_make OCF_TARGET=modules
ocf_install:
$(MAKE) ocf_make OCF_TARGET="modules modules_install"
depmod
mkdir -p /usr/include/crypto
cp cryptodev.h /usr/include/crypto/.
#
# generate full kernel patches for 2.4 and 2.6 kernels to make patching
# your kernel easier
#
.PHONY: patch
patch:
patchbase=.; \
[ -d $$patchbase/patches ] || patchbase=..; \
patch=ocf-linux-base.patch; \
patch24=ocf-linux-24.patch; \
patch26=ocf-linux-26.patch; \
patch3=ocf-linux-3.patch; \
( \
find . -name Makefile; \
find . -name Config.in; \
find . -name Kconfig; \
find . -name README; \
find . -name '*.[ch]' | grep -v '.mod.c'; \
) | while read t; do \
diff -Nau /dev/null $$t | sed 's?^+++ \./?+++ linux/crypto/ocf/?'; \
done > $$patch; \
cat $$patchbase/patches/linux-2.4.35-ocf.patch $$patch > $$patch24; \
cat $$patchbase/patches/linux-2.6.38-ocf.patch $$patch > $$patch26; \
cat $$patchbase/patches/linux-3.2.1-ocf.patch $$patch > $$patch3; \
#
# this target probably does nothing for anyone but me - davidm
#
.PHONY: release
release:
REL=`date +%Y%m%d`; RELDIR=/tmp/ocf-linux-$$REL; \
CURDIR=`pwd`; \
rm -rf /tmp/ocf-linux-$$REL*; \
mkdir -p $$RELDIR/ocf; \
mkdir -p $$RELDIR/patches; \
mkdir -p $$RELDIR/crypto-tools; \
cp README* $$RELDIR/.; \
cp patches/[!C]* $$RELDIR/patches/.; \
cp tools/[!C]* $$RELDIR/crypto-tools/.; \
cp -r [!C]* Config.in $$RELDIR/ocf/.; \
rm -rf $$RELDIR/ocf/patches $$RELDIR/ocf/tools; \
rm -f $$RELDIR/ocf/README*; \
cp $$CURDIR/../../user/crypto-tools/[!C]* $$RELDIR/crypto-tools/.; \
make -C $$RELDIR/crypto-tools clean; \
make -C $$RELDIR/ocf clean; \
find $$RELDIR/ocf -name CVS | xargs rm -rf; \
cd $$RELDIR/..; \
tar cvf ocf-linux-$$REL.tar ocf-linux-$$REL; \
gzip -9n ocf-linux-$$REL.tar

12
target/linux/generic/files/crypto/ocf/c7108/Makefile
View File

@ -1,12 +0,0 @@
# for SGlinux builds
-include $(ROOTDIR)/modules/.config
obj-$(CONFIG_OCF_C7108) += aes-7108.o
obj ?= .
EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/
ifdef TOPDIR
-include $(TOPDIR)/Rules.make
endif

841
target/linux/generic/files/crypto/ocf/c7108/aes-7108.c
View File

@ -1,841 +0,0 @@
/*
* Copyright (C) 2006 Micronas USA
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Effort sponsored in part by the Defense Advanced Research Projects
* Agency (DARPA) and Air Force Research Laboratory, Air Force
* Materiel Command, USAF, under agreement number F30602-01-2-0537.
*
*/
//#include <linux/config.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/wait.h>
#include <linux/crypto.h>
#include <linux/mm.h>
#include <linux/skbuff.h>
#include <linux/random.h>
#include <asm/io.h>
#include <asm/delay.h>
//#include <asm/scatterlist.h>
#include <linux/scatterlist.h>
#include <linux/dma-mapping.h>
#include <linux/highmem.h>
#include <cryptodev.h>
#include <uio.h>
#include <aes-7108.h>
/* Runtime mode */
static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR;
//static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC;
static int32_t c7108_id = -1;
static struct cipher_7108 **c7108_sessions = NULL;
static u_int32_t c7108_sesnum = 0;
static unsigned long iobar;
/* Crypto entry points */
static int c7108_process(void *, struct cryptop *, int);
static int c7108_newsession(void *, u_int32_t *, struct cryptoini *);
static int c7108_freesession(void *, u_int64_t);
/* Globals */
static int debug = 0;
static spinlock_t csr_mutex;
/* Generic controller-based lock */
#define AES_LOCK()\
spin_lock(&csr_mutex)
#define AES_UNLOCK()\
spin_unlock(&csr_mutex)
/* 7108 AES register access */
#define c7108_reg_wr8(a,d) iowrite8(d, (void*)(iobar+(a)))
#define c7108_reg_wr16(a,d) iowrite16(d, (void*)(iobar+(a)))
#define c7108_reg_wr32(a,d) iowrite32(d, (void*)(iobar+(a)))
#define c7108_reg_rd8(a) ioread8((void*)(iobar+(a)))
#define c7108_reg_rd16(a) ioread16((void*)(iobar+(a)))
#define c7108_reg_rd32(a) ioread32((void*)(iobar+(a)))
static int
c7108_xlate_key(int klen, u8* k8ptr, u32* k32ptr)
{
int i, nw=0;
nw = ((klen >= 256) ? 8 : (klen >= 192) ? 6 : 4);
for ( i = 0; i < nw; i++) {
k32ptr[i] = (k8ptr[i+3] << 24) | (k8ptr[i+2] << 16) |
(k8ptr[i+1] << 8) | k8ptr[i];
}
return 0;
}
static int
c7108_cache_key(int klen, u32* k32ptr, u8* k8ptr)
{
int i, nb=0;
u8* ptr = (u8*)k32ptr;
nb = ((klen >= 256) ? 32 : (klen >= 192) ? 24 : 16);
for ( i = 0; i < nb; i++)
k8ptr[i] = ptr[i];
return 0;
}
static int
c7108_aes_setup_dma(u32 src, u32 dst, u32 len)
{
if (len < 16) {
printk("len < 16\n");
return -10;
}
if (len % 16) {
printk("len not multiple of 16\n");
return -11;
}
c7108_reg_wr16(C7108_AES_DMA_SRC0_LO, (u16) src);
c7108_reg_wr16(C7108_AES_DMA_SRC0_HI, (u16)((src & 0xffff0000) >> 16));
c7108_reg_wr16(C7108_AES_DMA_DST0_LO, (u16) dst);
c7108_reg_wr16(C7108_AES_DMA_DST0_HI, (u16)((dst & 0xffff0000) >> 16));
c7108_reg_wr16(C7108_AES_DMA_LEN, (u16) ((len / 16) - 1));
return 0;
}
static int
c7108_aes_set_hw_iv(u8 iv[16])
{
c7108_reg_wr16(C7108_AES_IV0_LO, (u16) ((iv[1] << 8) | iv[0]));
c7108_reg_wr16(C7108_AES_IV0_HI, (u16) ((iv[3] << 8) | iv[2]));
c7108_reg_wr16(C7108_AES_IV1_LO, (u16) ((iv[5] << 8) | iv[4]));
c7108_reg_wr16(C7108_AES_IV1_HI, (u16) ((iv[7] << 8) | iv[6]));
c7108_reg_wr16(C7108_AES_IV2_LO, (u16) ((iv[9] << 8) | iv[8]));
c7108_reg_wr16(C7108_AES_IV2_HI, (u16) ((iv[11] << 8) | iv[10]));
c7108_reg_wr16(C7108_AES_IV3_LO, (u16) ((iv[13] << 8) | iv[12]));
c7108_reg_wr16(C7108_AES_IV3_HI, (u16) ((iv[15] << 8) | iv[14]));
return 0;
}
static void
c7108_aes_read_dkey(u32 * dkey)
{
dkey[0] = (c7108_reg_rd16(C7108_AES_EKEY0_HI) << 16) |
c7108_reg_rd16(C7108_AES_EKEY0_LO);
dkey[1] = (c7108_reg_rd16(C7108_AES_EKEY1_HI) << 16) |
c7108_reg_rd16(C7108_AES_EKEY1_LO);
dkey[2] = (c7108_reg_rd16(C7108_AES_EKEY2_HI) << 16) |
c7108_reg_rd16(C7108_AES_EKEY2_LO);
dkey[3] = (c7108_reg_rd16(C7108_AES_EKEY3_HI) << 16) |
c7108_reg_rd16(C7108_AES_EKEY3_LO);
dkey[4] = (c7108_reg_rd16(C7108_AES_EKEY4_HI) << 16) |
c7108_reg_rd16(C7108_AES_EKEY4_LO);
dkey[5] = (c7108_reg_rd16(C7108_AES_EKEY5_HI) << 16) |
c7108_reg_rd16(C7108_AES_EKEY5_LO);
dkey[6] = (c7108_reg_rd16(C7108_AES_EKEY6_HI) << 16) |
c7108_reg_rd16(C7108_AES_EKEY6_LO);
dkey[7] = (c7108_reg_rd16(C7108_AES_EKEY7_HI) << 16) |
c7108_reg_rd16(C7108_AES_EKEY7_LO);
}
static int
c7108_aes_cipher(int op,
u32 dst,
u32 src,
u32 len,
int klen,
u16 mode,
u32 key[8],
u8 iv[16])
{
int rv = 0, cnt=0;
u16 ctrl = 0, stat = 0;
AES_LOCK();
/* Setup key length */
if (klen == 128) {
ctrl |= C7108_AES_KEY_LEN_128;
} else if (klen == 192) {
ctrl |= C7108_AES_KEY_LEN_192;
} else if (klen == 256) {
ctrl |= C7108_AES_KEY_LEN_256;
} else {
AES_UNLOCK();
return -3;
}
/* Check opcode */
if (C7108_AES_ENCRYPT == op) {
ctrl |= C7108_AES_ENCRYPT;
} else if (C7108_AES_DECRYPT == op) {
ctrl |= C7108_AES_DECRYPT;
} else {
AES_UNLOCK();
return -4;
}
/* check mode */
if ( (mode != C7108_AES_CTRL_MODE_CBC) &&
(mode != C7108_AES_CTRL_MODE_CFB) &&
(mode != C7108_AES_CTRL_MODE_OFB) &&
(mode != C7108_AES_CTRL_MODE_CTR) &&
(mode != C7108_AES_CTRL_MODE_ECB) ) {
AES_UNLOCK();
return -5;
}
/* Now set mode */
ctrl |= mode;
/* For CFB, OFB, and CTR, neither backward key
* expansion nor key inversion is required.
*/
if ( (C7108_AES_DECRYPT == op) &&
(C7108_AES_CTRL_MODE_CBC == mode ||
C7108_AES_CTRL_MODE_ECB == mode ) ){
/* Program Key */
c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[4]);
c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[4] >> 16));
c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[5]);
c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[5] >> 16));
c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[6]);
c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[6] >> 16));
c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[7]);
c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[7] >> 16));
c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[2]);
c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[2] >> 16));
c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[3]);
c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[3] >> 16));
if (192 == klen) {
c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[7]);
c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[7] >> 16));
c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[7]);
c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[7] >> 16));
} else if (256 == klen) {
/* 256 */
c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[0]);
c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[0] >> 16));
c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[1]);
c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[1] >> 16));
}
} else {
/* Program Key */
c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[0]);
c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[0] >> 16));
c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[1]);
c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[1] >> 16));
c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[2]);
c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[2] >> 16));
c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[3]);
c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[3] >> 16));
c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[4]);
c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[4] >> 16));
c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[5]);
c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[5] >> 16));
c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[6]);
c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[6] >> 16));
c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[7]);
c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[7] >> 16));
}
/* Set IV always */
c7108_aes_set_hw_iv(iv);
/* Program DMA addresses */
if ((rv = c7108_aes_setup_dma(src, dst, len)) < 0) {
AES_UNLOCK();
return rv;
}
/* Start AES cipher */
c7108_reg_wr16(C7108_AES_CTRL, ctrl | C7108_AES_GO);
//printk("Ctrl: 0x%x\n", ctrl | C7108_AES_GO);
do {
/* TODO: interrupt mode */
// printk("aes_stat=0x%x\n", stat);
//udelay(100);
} while ((cnt++ < 1000000) &&
!((stat=c7108_reg_rd16(C7108_AES_CTRL))&C7108_AES_OP_DONE));
if ((mode == C7108_AES_CTRL_MODE_ECB)||
(mode == C7108_AES_CTRL_MODE_CBC)) {
/* Save out key when the lock is held ... */
c7108_aes_read_dkey(key);
}
AES_UNLOCK();
return 0;
}
/*
* Generate a new crypto device session.
*/
static int
c7108_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri)
{
struct cipher_7108 **swd;
u_int32_t i;
char *algo;
int mode, xfm_type;
dprintk("%s()\n", __FUNCTION__);
if (sid == NULL || cri == NULL) {
dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__);
return EINVAL;
}
if (c7108_sessions) {
for (i = 1; i < c7108_sesnum; i++)
if (c7108_sessions[i] == NULL)
break;
} else
i = 1; /* NB: to silence compiler warning */
if (c7108_sessions == NULL || i == c7108_sesnum) {
if (c7108_sessions == NULL) {
i = 1; /* We leave c7108_sessions[0] empty */
c7108_sesnum = CRYPTO_SW_SESSIONS;
} else
c7108_sesnum *= 2;
swd = kmalloc(c7108_sesnum * sizeof(struct cipher_7108 *),
GFP_ATOMIC);
if (swd == NULL) {
/* Reset session number */
if (c7108_sesnum == CRYPTO_SW_SESSIONS)
c7108_sesnum = 0;
else
c7108_sesnum /= 2;
dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__);
return ENOBUFS;
}
memset(swd, 0, c7108_sesnum * sizeof(struct cipher_7108 *));
/* Copy existing sessions */
if (c7108_sessions) {
memcpy(swd, c7108_sessions,
(c7108_sesnum / 2) * sizeof(struct cipher_7108 *));
kfree(c7108_sessions);
}
c7108_sessions = swd;
}
swd = &c7108_sessions[i];
*sid = i;
while (cri) {
*swd = (struct cipher_7108 *)
kmalloc(sizeof(struct cipher_7108), GFP_ATOMIC);
if (*swd == NULL) {
c7108_freesession(NULL, i);
dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__);
return ENOBUFS;
}
memset(*swd, 0, sizeof(struct cipher_7108));
algo = NULL;
mode = 0;
xfm_type = HW_TYPE_CIPHER;
switch (cri->cri_alg) {
case CRYPTO_AES_CBC:
algo = "aes";
mode = CRYPTO_TFM_MODE_CBC;
c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC;
break;
#if 0
case CRYPTO_AES_CTR:
algo = "aes_ctr";
mode = CRYPTO_TFM_MODE_CBC;
c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR;
break;
case CRYPTO_AES_ECB:
algo = "aes_ecb";
mode = CRYPTO_TFM_MODE_CBC;
c7108_crypto_mode = C7108_AES_CTRL_MODE_ECB;
break;
case CRYPTO_AES_OFB:
algo = "aes_ofb";
mode = CRYPTO_TFM_MODE_CBC;
c7108_crypto_mode = C7108_AES_CTRL_MODE_OFB;
break;
case CRYPTO_AES_CFB:
algo = "aes_cfb";
mode = CRYPTO_TFM_MODE_CBC;
c7108_crypto_mode = C7108_AES_CTRL_MODE_CFB;
break;
#endif
default:
printk("unsupported crypto algorithm: %d\n",
cri->cri_alg);
return -EINVAL;
break;
}
if (!algo || !*algo) {
printk("cypher_7108_crypto: Unknown algo 0x%x\n",
cri->cri_alg);
c7108_freesession(NULL, i);
return EINVAL;
}
if (xfm_type == HW_TYPE_CIPHER) {
if (debug) {
dprintk("%s key:", __FUNCTION__);
for (i = 0; i < (cri->cri_klen + 7) / 8; i++)
dprintk("%s0x%02x", (i % 8) ? " " : "\n ",
cri->cri_key[i]);
dprintk("\n");
}
} else if (xfm_type == SW_TYPE_HMAC ||
xfm_type == SW_TYPE_HASH) {
printk("cypher_7108_crypto: HMAC unsupported!\n");
return -EINVAL;
c7108_freesession(NULL, i);
} else {
printk("cypher_7108_crypto: "
"Unhandled xfm_type %d\n", xfm_type);
c7108_freesession(NULL, i);
return EINVAL;
}
(*swd)->cri_alg = cri->cri_alg;
(*swd)->xfm_type = xfm_type;
cri = cri->cri_next;
swd = &((*swd)->next);
}
return 0;
}
/*
* Free a session.
*/
static int
c7108_freesession(void *arg, u_int64_t tid)
{
struct cipher_7108 *swd;
u_int32_t sid = CRYPTO_SESID2LID(tid);
dprintk("%s()\n", __FUNCTION__);
if (sid > c7108_sesnum || c7108_sessions == NULL ||
c7108_sessions[sid] == NULL) {
dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__);
return(EINVAL);
}
/* Silently accept and return */
if (sid == 0)
return(0);
while ((swd = c7108_sessions[sid]) != NULL) {
c7108_sessions[sid] = swd->next;
kfree(swd);
}
return 0;
}
/*
* Process a hardware request.
*/
static int
c7108_process(void *arg, struct cryptop *crp, int hint)
{
struct cryptodesc *crd;
struct cipher_7108 *sw;
u_int32_t lid;
int type;
u32 hwkey[8];
#define SCATTERLIST_MAX 16
struct scatterlist sg[SCATTERLIST_MAX];
int sg_num, sg_len, skip;
struct sk_buff *skb = NULL;
struct uio *uiop = NULL;
dprintk("%s()\n", __FUNCTION__);
/* Sanity check */
if (crp == NULL) {
dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__);
return EINVAL;
}
crp->crp_etype = 0;
if (crp->crp_desc == NULL || crp->crp_buf == NULL) {
dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__);
crp->crp_etype = EINVAL;
goto done;
}
lid = crp->crp_sid & 0xffffffff;
if (lid >= c7108_sesnum || lid == 0 || c7108_sessions == NULL ||
c7108_sessions[lid] == NULL) {
crp->crp_etype = ENOENT;
dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__);
goto done;
}
/*
* do some error checking outside of the loop for SKB and IOV
* processing this leaves us with valid skb or uiop pointers
* for later
*/
if (crp->crp_flags & CRYPTO_F_SKBUF) {
skb = (struct sk_buff *) crp->crp_buf;
if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) {
printk("%s,%d: %d nr_frags > SCATTERLIST_MAX",
__FILE__, __LINE__,
skb_shinfo(skb)->nr_frags);
goto done;
}
} else if (crp->crp_flags & CRYPTO_F_IOV) {
uiop = (struct uio *) crp->crp_buf;
if (uiop->uio_iovcnt > SCATTERLIST_MAX) {
printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX",
__FILE__, __LINE__,
uiop->uio_iovcnt);
goto done;
}
}
/* Go through crypto descriptors, processing as we go */
for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
/*
* Find the crypto context.
*
* XXX Note that the logic here prevents us from having
* XXX the same algorithm multiple times in a session
* XXX (or rather, we can but it won't give us the right
* XXX results). To do that, we'd need some way of differentiating
* XXX between the various instances of an algorithm (so we can
* XXX locate the correct crypto context).
*/
for (sw = c7108_sessions[lid];
sw && sw->cri_alg != crd->crd_alg;
sw = sw->next)
;
/* No such context ? */
if (sw == NULL) {
crp->crp_etype = EINVAL;
dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__);
goto done;
}
skip = crd->crd_skip;
/*
* setup the SG list skip from the start of the buffer
*/
memset(sg, 0, sizeof(sg));
if (crp->crp_flags & CRYPTO_F_SKBUF) {
int i, len;
type = CRYPTO_BUF_SKBUF;
sg_num = 0;
sg_len = 0;
if (skip < skb_headlen(skb)) {
//sg[sg_num].page = virt_to_page(skb->data + skip);
//sg[sg_num].offset = offset_in_page(skb->data + skip);
len = skb_headlen(skb) - skip;
if (len + sg_len > crd->crd_len)
len = crd->crd_len - sg_len;
//sg[sg_num].length = len;
sg_set_page(&sg[sg_num], virt_to_page(skb->data + skip), len, offset_in_page(skb->data + skip));
sg_len += sg[sg_num].length;
sg_num++;
skip = 0;
} else
skip -= skb_headlen(skb);
for (i = 0; sg_len < crd->crd_len &&
i < skb_shinfo(skb)->nr_frags &&
sg_num < SCATTERLIST_MAX; i++) {
if (skip < skb_shinfo(skb)->frags[i].size) {
//sg[sg_num].page = skb_frag_page(&skb_shinfo(skb)->frags[i]);
//sg[sg_num].offset = skb_shinfo(skb)->frags[i].page_offset + skip;
len = skb_shinfo(skb)->frags[i].size - skip;
if (len + sg_len > crd->crd_len)
len = crd->crd_len - sg_len;
//sg[sg_num].length = len;
sg_set_page(&sg[sg_num], skb_frag_page(&skb_shinfo(skb)->frags[i]), len, skb_shinfo(skb)->frags[i].page_offset + skip);
sg_len += sg[sg_num].length;
sg_num++;
skip = 0;
} else
skip -= skb_shinfo(skb)->frags[i].size;
}
} else if (crp->crp_flags & CRYPTO_F_IOV) {
int len;
type = CRYPTO_BUF_IOV;
sg_len = 0;
for (sg_num = 0; sg_len < crd->crd_len &&
sg_num < uiop->uio_iovcnt &&
sg_num < SCATTERLIST_MAX; sg_num++) {
if (skip < uiop->uio_iov[sg_num].iov_len) {
//sg[sg_num].page = virt_to_page(uiop->uio_iov[sg_num].iov_base+skip);
//sg[sg_num].offset = offset_in_page(uiop->uio_iov[sg_num].iov_base+skip);
len = uiop->uio_iov[sg_num].iov_len - skip;
if (len + sg_len > crd->crd_len)
len = crd->crd_len - sg_len;
//sg[sg_num].length = len;
sg_set_page(&sg[sg_num], virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), len, offset_in_page(uiop->uio_iov[sg_num].iov_base+skip));
sg_len += sg[sg_num].length;
skip = 0;
} else
skip -= uiop->uio_iov[sg_num].iov_len;
}
} else {
type = CRYPTO_BUF_CONTIG;
//sg[0].page = virt_to_page(crp->crp_buf + skip);
//sg[0].offset = offset_in_page(crp->crp_buf + skip);
sg_len = (crp->crp_ilen - skip);
if (sg_len > crd->crd_len)
sg_len = crd->crd_len;
//sg[0].length = sg_len;
sg_set_page(&sg[0], virt_to_page(crp->crp_buf + skip), sg_len, offset_in_page(crp->crp_buf + skip));
sg_num = 1;
}
if (sg_num > 0)
sg_mark_end(&sg[sg_num-1]);
switch (sw->xfm_type) {
case HW_TYPE_CIPHER: {
unsigned char iv[64];
unsigned char *ivp = iv;
int i;
int ivsize = 16; /* fixed for AES */
int blocksize = 16; /* fixed for AES */
if (sg_len < blocksize) {
crp->crp_etype = EINVAL;
dprintk("%s,%d: EINVAL len %d < %d\n",
__FILE__, __LINE__,
sg_len,
blocksize);
goto done;
}
if (ivsize > sizeof(iv)) {
crp->crp_etype = EINVAL;
dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__);
goto done;
}
if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */
if (crd->crd_flags & CRD_F_IV_EXPLICIT) {
ivp = crd->crd_iv;
} else {
get_random_bytes(ivp, ivsize);
}
/*
* do we have to copy the IV back to the buffer ?
*/
if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) {
crypto_copyback(crp->crp_buf,
crd->crd_inject,
ivsize,
(caddr_t)ivp);
}
c7108_xlate_key(crd->crd_klen,
(u8*)crd->crd_key, (u32*)hwkey);
/* Encrypt SG list */
for (i = 0; i < sg_num; i++) {
sg[i].dma_address =
dma_map_single(NULL,
kmap(sg_page(&sg[i])) + sg[i].offset, sg_len, DMA_BIDIRECTIONAL);
#if 0
printk("sg[%d]:0x%08x, off 0x%08x "
"kmap 0x%08x phys 0x%08x\n",
i, sg[i].page, sg[i].offset,
kmap(sg[i].page) + sg[i].offset,
sg[i].dma_address);
#endif
c7108_aes_cipher(C7108_AES_ENCRYPT,
sg[i].dma_address,
sg[i].dma_address,
sg_len,
crd->crd_klen,
c7108_crypto_mode,
hwkey,
ivp);
if ((c7108_crypto_mode == C7108_AES_CTRL_MODE_CBC)||
(c7108_crypto_mode == C7108_AES_CTRL_MODE_ECB)) {
/* Read back expanded key and cache it in key
* context.
* NOTE: for ECB/CBC modes only (not CTR, CFB, OFB)
* where you set the key once.
*/
c7108_cache_key(crd->crd_klen,
(u32*)hwkey, (u8*)crd->crd_key);
#if 0
printk("%s expanded key:", __FUNCTION__);
for (i = 0; i < (crd->crd_klen + 7) / 8; i++)
printk("%s0x%02x", (i % 8) ? " " : "\n ",
crd->crd_key[i]);
printk("\n");
#endif
}
}
}
else { /*decrypt */
if (crd->crd_flags & CRD_F_IV_EXPLICIT) {
ivp = crd->crd_iv;
} else {
crypto_copydata(crp->crp_buf, crd->crd_inject,
ivsize, (caddr_t)ivp);
}
c7108_xlate_key(crd->crd_klen,
(u8*)crd->crd_key, (u32*)hwkey);
/* Decrypt SG list */
for (i = 0; i < sg_num; i++) {
sg[i].dma_address =
dma_map_single(NULL,
kmap(sg_page(&sg[i])) + sg[i].offset,
sg_len, DMA_BIDIRECTIONAL);
#if 0
printk("sg[%d]:0x%08x, off 0x%08x "
"kmap 0x%08x phys 0x%08x\n",
i, sg[i].page, sg[i].offset,
kmap(sg[i].page) + sg[i].offset,
sg[i].dma_address);
#endif
c7108_aes_cipher(C7108_AES_DECRYPT,
sg[i].dma_address,
sg[i].dma_address,
sg_len,
crd->crd_klen,
c7108_crypto_mode,
hwkey,
ivp);
}
}
} break;
case SW_TYPE_HMAC:
case SW_TYPE_HASH:
crp->crp_etype = EINVAL;
goto done;
break;
case SW_TYPE_COMP:
crp->crp_etype = EINVAL;
goto done;
break;
default:
/* Unknown/unsupported algorithm */
dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__);
crp->crp_etype = EINVAL;
goto done;
}
}
done:
crypto_done(crp);
return 0;
}
static struct {
softc_device_decl sc_dev;
} a7108dev;
static device_method_t a7108_methods = {
/* crypto device methods */
DEVMETHOD(cryptodev_newsession, c7108_newsession),
DEVMETHOD(cryptodev_freesession, c7108_freesession),
DEVMETHOD(cryptodev_process, c7108_process),
DEVMETHOD(cryptodev_kprocess, NULL)
};
static int
cypher_7108_crypto_init(void)
{
dprintk("%s(%p)\n", __FUNCTION__, cypher_7108_crypto_init);
iobar = (unsigned long)ioremap(CCU_AES_REG_BASE, 0x4000);
printk("7108: AES @ 0x%08x (0x%08x phys) %s mode\n",
iobar, CCU_AES_REG_BASE,
c7108_crypto_mode & C7108_AES_CTRL_MODE_CBC ? "CBC" :
c7108_crypto_mode & C7108_AES_CTRL_MODE_ECB ? "ECB" :
c7108_crypto_mode & C7108_AES_CTRL_MODE_CTR ? "CTR" :
c7108_crypto_mode & C7108_AES_CTRL_MODE_CFB ? "CFB" :
c7108_crypto_mode & C7108_AES_CTRL_MODE_OFB ? "OFB" : "???");
csr_mutex = SPIN_LOCK_UNLOCKED;
memset(&a7108dev, 0, sizeof(a7108dev));
softc_device_init(&a7108dev, "aes7108", 0, a7108_methods);
c7108_id = crypto_get_driverid(softc_get_device(&a7108dev), CRYPTOCAP_F_HARDWARE);
if (c7108_id < 0)
panic("7108: crypto device cannot initialize!");
// crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0, c7108_newsession, c7108_freesession, c7108_process, NULL);
crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0);
return(0);
}
static void
cypher_7108_crypto_exit(void)
{
dprintk("%s()\n", __FUNCTION__);
crypto_unregister_all(c7108_id);
c7108_id = -1;
}
module_init(cypher_7108_crypto_init);
module_exit(cypher_7108_crypto_exit);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_DESCRIPTION("Cypher 7108 Crypto (OCF module for kernel crypto)");

134
target/linux/generic/files/crypto/ocf/c7108/aes-7108.h
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@ -1,134 +0,0 @@
/*
* Copyright (C) 2006 Micronas USA
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Effort sponsored in part by the Defense Advanced Research Projects
* Agency (DARPA) and Air Force Research Laboratory, Air Force
* Materiel Command, USAF, under agreement number F30602-01-2-0537.
*
*/
#ifndef __AES_7108_H__
#define __AES_7108_H__
/* Cypher 7108 AES Controller Hardware */
#define CCU_REG_BASE 0x1b500000
#define CCU_AES_REG_BASE (CCU_REG_BASE + 0x100)
#define C7108_AES_KEY0_LO (0x0000)
#define C7108_AES_KEY0_HI (0x0004)
#define C7108_AES_KEY1_LO (0x0008)
#define C7108_AES_KEY1_HI (0x000c)
#define C7108_AES_KEY2_LO (0x0010)
#define C7108_AES_KEY2_HI (0x0014)
#define C7108_AES_KEY3_LO (0x0018)
#define C7108_AES_KEY3_HI (0x001c)
#define C7108_AES_KEY4_LO (0x0020)
#define C7108_AES_KEY4_HI (0x0024)
#define C7108_AES_KEY5_LO (0x0028)
#define C7108_AES_KEY5_HI (0x002c)
#define C7108_AES_KEY6_LO (0x0030)
#define C7108_AES_KEY6_HI (0x0034)
#define C7108_AES_KEY7_LO (0x0038)
#define C7108_AES_KEY7_HI (0x003c)
#define C7108_AES_IV0_LO (0x0040)
#define C7108_AES_IV0_HI (0x0044)
#define C7108_AES_IV1_LO (0x0048)
#define C7108_AES_IV1_HI (0x004c)
#define C7108_AES_IV2_LO (0x0050)
#define C7108_AES_IV2_HI (0x0054)
#define C7108_AES_IV3_LO (0x0058)
#define C7108_AES_IV3_HI (0x005c)
#define C7108_AES_DMA_SRC0_LO (0x0068) /* Bits 0:15 */
#define C7108_AES_DMA_SRC0_HI (0x006c) /* Bits 27:16 */
#define C7108_AES_DMA_DST0_LO (0x0070) /* Bits 0:15 */
#define C7108_AES_DMA_DST0_HI (0x0074) /* Bits 27:16 */
#define C7108_AES_DMA_LEN (0x0078) /*Bytes:(Count+1)x16 */
/* AES/Copy engine control register */
#define C7108_AES_CTRL (0x007c) /* AES control */
#define C7108_AES_CTRL_RS (1<<0) /* Which set of src/dst to use */
/* AES Cipher mode, controlled by setting Bits 2:0 */
#define C7108_AES_CTRL_MODE_CBC 0
#define C7108_AES_CTRL_MODE_CFB (1<<0)
#define C7108_AES_CTRL_MODE_OFB (1<<1)
#define C7108_AES_CTRL_MODE_CTR ((1<<0)|(1<<1))
#define C7108_AES_CTRL_MODE_ECB (1<<2)
/* AES Key length , Bits 5:4 */
#define C7108_AES_KEY_LEN_128 0 /* 00 */
#define C7108_AES_KEY_LEN_192 (1<<4) /* 01 */
#define C7108_AES_KEY_LEN_256 (1<<5) /* 10 */
/* AES Operation (crypt/decrypt), Bit 3 */
#define C7108_AES_DECRYPT (1<<3) /* Clear for encrypt */
#define C7108_AES_ENCRYPT 0
#define C7108_AES_INTR (1<<13) /* Set on done trans from 0->1*/
#define C7108_AES_GO (1<<14) /* Run */
#define C7108_AES_OP_DONE (1<<15) /* Set when complete */
/* Expanded key registers */
#define C7108_AES_EKEY0_LO (0x0080)
#define C7108_AES_EKEY0_HI (0x0084)
#define C7108_AES_EKEY1_LO (0x0088)
#define C7108_AES_EKEY1_HI (0x008c)
#define C7108_AES_EKEY2_LO (0x0090)
#define C7108_AES_EKEY2_HI (0x0094)
#define C7108_AES_EKEY3_LO (0x0098)
#define C7108_AES_EKEY3_HI (0x009c)
#define C7108_AES_EKEY4_LO (0x00a0)
#define C7108_AES_EKEY4_HI (0x00a4)
#define C7108_AES_EKEY5_LO (0x00a8)
#define C7108_AES_EKEY5_HI (0x00ac)
#define C7108_AES_EKEY6_LO (0x00b0)
#define C7108_AES_EKEY6_HI (0x00b4)
#define C7108_AES_EKEY7_LO (0x00b8)
#define C7108_AES_EKEY7_HI (0x00bc)
#define C7108_AES_OK (0x00fc) /* Reset: "OK" */
#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK)
/* Software session entry */
#define HW_TYPE_CIPHER 0
#define SW_TYPE_HMAC 1
#define SW_TYPE_AUTH2 2
#define SW_TYPE_HASH 3
#define SW_TYPE_COMP 4
struct cipher_7108 {
int xfm_type;
int cri_alg;
union {
struct {
char sw_key[HMAC_BLOCK_LEN];
int sw_klen;
int sw_authlen;
} hmac;
} u;
struct cipher_7108 *next;
};
#endif /* __C7108_AES_7108_H__ */

215
target/linux/generic/files/crypto/ocf/criov.c
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@ -1,215 +0,0 @@
/* $OpenBSD: criov.c,v 1.9 2002/01/29 15:48:29 jason Exp $ */
/*
* Linux port done by David McCullough <david_mccullough@mcafee.com>
* Copyright (C) 2006-2010 David McCullough
* Copyright (C) 2004-2005 Intel Corporation.
* The license and original author are listed below.
*
* Copyright (c) 1999 Theo de Raadt
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
__FBSDID("$FreeBSD: src/sys/opencrypto/criov.c,v 1.5 2006/06/04 22:15:13 pjd Exp $");
*/
#include <linux/version.h>
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED)
#include <linux/config.h>
#endif
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/uio.h>
#include <linux/skbuff.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <asm/io.h>
#include <uio.h>
#include <cryptodev.h>
/*
* This macro is only for avoiding code duplication, as we need to skip
* given number of bytes in the same way in three functions below.
*/
#define CUIO_SKIP() do { \
KASSERT(off >= 0, ("%s: off %d < 0", __func__, off)); \
KASSERT(len >= 0, ("%s: len %d < 0", __func__, len)); \
while (off > 0) { \
KASSERT(iol >= 0, ("%s: empty in skip", __func__)); \
if (off < iov->iov_len) \
break; \
off -= iov->iov_len; \
iol--; \
iov++; \
} \
} while (0)
void
cuio_copydata(struct uio* uio, int off, int len, caddr_t cp)
{
struct iovec *iov = uio->uio_iov;
int iol = uio->uio_iovcnt;
unsigned count;
CUIO_SKIP();
while (len > 0) {
KASSERT(iol >= 0, ("%s: empty", __func__));
count = min((int)(iov->iov_len - off), len);
memcpy(cp, ((caddr_t)iov->iov_base) + off, count);
len -= count;
cp += count;
off = 0;
iol--;
iov++;
}
}
void
cuio_copyback(struct uio* uio, int off, int len, caddr_t cp)
{
struct iovec *iov = uio->uio_iov;
int iol = uio->uio_iovcnt;
unsigned count;
CUIO_SKIP();
while (len > 0) {
KASSERT(iol >= 0, ("%s: empty", __func__));
count = min((int)(iov->iov_len - off), len);
memcpy(((caddr_t)iov->iov_base) + off, cp, count);
len -= count;
cp += count;
off = 0;
iol--;
iov++;
}
}
/*
* Return a pointer to iov/offset of location in iovec list.
*/
struct iovec *
cuio_getptr(struct uio *uio, int loc, int *off)
{
struct iovec *iov = uio->uio_iov;
int iol = uio->uio_iovcnt;
while (loc >= 0) {
/* Normal end of search */
if (loc < iov->iov_len) {
*off = loc;
return (iov);
}
loc -= iov->iov_len;
if (iol == 0) {
if (loc == 0) {
/* Point at the end of valid data */
*off = iov->iov_len;
return (iov);
} else
return (NULL);
} else {
iov++, iol--;
}
}
return (NULL);
}
EXPORT_SYMBOL(cuio_copyback);
EXPORT_SYMBOL(cuio_copydata);
EXPORT_SYMBOL(cuio_getptr);
static void
skb_copy_bits_back(struct sk_buff *skb, int offset, caddr_t cp, int len)
{
int i;
if (offset < skb_headlen(skb)) {
memcpy(skb->data + offset, cp, min_t(int, skb_headlen(skb), len));
len -= skb_headlen(skb);
cp += skb_headlen(skb);
}
offset -= skb_headlen(skb);
for (i = 0; len > 0 && i < skb_shinfo(skb)->nr_frags; i++) {
if (offset < skb_shinfo(skb)->frags[i].size) {
memcpy(page_address(skb_frag_page(&skb_shinfo(skb)->frags[i])) +
skb_shinfo(skb)->frags[i].page_offset,
cp, min_t(int, skb_shinfo(skb)->frags[i].size, len));
len -= skb_shinfo(skb)->frags[i].size;
cp += skb_shinfo(skb)->frags[i].size;
}
offset -= skb_shinfo(skb)->frags[i].size;
}
}
void
crypto_copyback(int flags, caddr_t buf, int off, int size, caddr_t in)
{
if ((flags & CRYPTO_F_SKBUF) != 0)
skb_copy_bits_back((struct sk_buff *)buf, off, in, size);
else if ((flags & CRYPTO_F_IOV) != 0)
cuio_copyback((struct uio *)buf, off, size, in);
else
bcopy(in, buf + off, size);
}
void
crypto_copydata(int flags, caddr_t buf, int off, int size, caddr_t out)
{
if ((flags & CRYPTO_F_SKBUF) != 0)
skb_copy_bits((struct sk_buff *)buf, off, out, size);
else if ((flags & CRYPTO_F_IOV) != 0)
cuio_copydata((struct uio *)buf, off, size, out);
else
bcopy(buf + off, out, size);
}
int
crypto_apply(int flags, caddr_t buf, int off, int len,
int (*f)(void *, void *, u_int), void *arg)
{
#if 0
int error;
if ((flags & CRYPTO_F_SKBUF) != 0)
error = XXXXXX((struct mbuf *)buf, off, len, f, arg);
else if ((flags & CRYPTO_F_IOV) != 0)
error = cuio_apply((struct uio *)buf, off, len, f, arg);
else
error = (*f)(arg, buf + off, len);
return (error);
#else
KASSERT(0, ("crypto_apply not implemented!\n"));
#endif
return 0;
}
EXPORT_SYMBOL(crypto_copyback);
EXPORT_SYMBOL(crypto_copydata);
EXPORT_SYMBOL(crypto_apply);

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target/linux/generic/files/crypto/ocf/crypto.c
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17
target/linux/generic/files/crypto/ocf/cryptocteon/Makefile
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# for SGlinux builds
-include $(ROOTDIR)/modules/.config
obj-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon.o
obj ?= .
EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/
ifdef CONFIG_OCF_CRYPTOCTEON
# you need the cavium crypto component installed
EXTRA_CFLAGS += -I$(ROOTDIR)/prop/include
endif
ifdef TOPDIR
-include $(TOPDIR)/Rules.make
endif

11
target/linux/generic/files/crypto/ocf/cryptocteon/README.txt
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@ -1,11 +0,0 @@
You will need the CRYPTO package installed to build this driver, and
potentially the ADK.
cavium_crypto sourced from:
adk/components/source/cavium_ipsec_kame/cavium_ipsec.c
and significantly modified to suit use with OCF. All original
copyright/ownership headers retained.

2283
target/linux/generic/files/crypto/ocf/cryptocteon/cavium_crypto.c
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576
target/linux/generic/files/crypto/ocf/cryptocteon/cryptocteon.c
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/*
* Octeon Crypto for OCF
*
* Written by David McCullough <david_mccullough@mcafee.com>
* Copyright (C) 2009-2010 David McCullough
*
* LICENSE TERMS
*
* The free distribution and use of this software in both source and binary
* form is allowed (with or without changes) provided that:
*
* 1. distributions of this source code include the above copyright
* notice, this list of conditions and the following disclaimer;
*
* 2. distributions in binary form include the above copyright
* notice, this list of conditions and the following disclaimer
* in the documentation and/or other associated materials;
*
* 3. the copyright holder's name is not used to endorse products
* built using this software without specific written permission.
*
* DISCLAIMER
*
* This software is provided 'as is' with no explicit or implied warranties
* in respect of its properties, including, but not limited to, correctness
* and/or fitness for purpose.
* ---------------------------------------------------------------------------
*/
#include <linux/version.h>
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED)
#include <linux/config.h>
#endif
#include <linux/module.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/wait.h>
#include <linux/crypto.h>
#include <linux/mm.h>
#include <linux/skbuff.h>
#include <linux/random.h>
#include <linux/scatterlist.h>
#include <cryptodev.h>
#include <uio.h>
struct {
softc_device_decl sc_dev;
} octo_softc;
#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK)
struct octo_sess {
int octo_encalg;
#define MAX_CIPHER_KEYLEN 64
char octo_enckey[MAX_CIPHER_KEYLEN];
int octo_encklen;
int octo_macalg;
#define MAX_HASH_KEYLEN 64
char octo_mackey[MAX_HASH_KEYLEN];
int octo_macklen;
int octo_mackey_set;
int octo_mlen;
int octo_ivsize;
int (*octo_encrypt)(struct octo_sess *od,
struct scatterlist *sg, int sg_len,
int auth_off, int auth_len,
int crypt_off, int crypt_len,
int icv_off, uint8_t *ivp);
int (*octo_decrypt)(struct octo_sess *od,
struct scatterlist *sg, int sg_len,
int auth_off, int auth_len,
int crypt_off, int crypt_len,
int icv_off, uint8_t *ivp);
uint64_t octo_hminner[3];
uint64_t octo_hmouter[3];
};
int32_t octo_id = -1;
module_param(octo_id, int, 0444);
MODULE_PARM_DESC(octo_id, "Read-Only OCF ID for cryptocteon driver");
static struct octo_sess **octo_sessions = NULL;
static u_int32_t octo_sesnum = 0;
static int octo_process(device_t, struct cryptop *, int);
static int octo_newsession(device_t, u_int32_t *, struct cryptoini *);
static int octo_freesession(device_t, u_int64_t);
static device_method_t octo_methods = {
/* crypto device methods */
DEVMETHOD(cryptodev_newsession, octo_newsession),
DEVMETHOD(cryptodev_freesession,octo_freesession),
DEVMETHOD(cryptodev_process, octo_process),
};
#define debug octo_debug
int octo_debug = 0;
module_param(octo_debug, int, 0644);
MODULE_PARM_DESC(octo_debug, "Enable debug");
#include "cavium_crypto.c"
/*
* Generate a new octo session. We artifically limit it to a single
* hash/cipher or hash-cipher combo just to make it easier, most callers
* do not expect more than this anyway.
*/
static int
octo_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri)
{
struct cryptoini *c, *encini = NULL, *macini = NULL;
struct octo_sess **ocd;
int i;
dprintk("%s()\n", __FUNCTION__);
if (sid == NULL || cri == NULL) {
dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__);
return EINVAL;
}
/*
* To keep it simple, we only handle hash, cipher or hash/cipher in a
* session, you cannot currently do multiple ciphers/hashes in one
* session even though it would be possibel to code this driver to
* handle it.
*/
for (i = 0, c = cri; c && i < 2; i++) {
if (c->cri_alg == CRYPTO_MD5_HMAC ||
c->cri_alg == CRYPTO_SHA1_HMAC ||
c->cri_alg == CRYPTO_NULL_HMAC) {
if (macini) {
break;
}
macini = c;
}
if (c->cri_alg == CRYPTO_DES_CBC ||
c->cri_alg == CRYPTO_3DES_CBC ||
c->cri_alg == CRYPTO_AES_CBC ||
c->cri_alg == CRYPTO_NULL_CBC) {
if (encini) {
break;
}
encini = c;
}
c = c->cri_next;
}
if (!macini && !encini) {
dprintk("%s,%d - EINVAL bad cipher/hash or combination\n",
__FILE__, __LINE__);
return EINVAL;
}
if (c) {
dprintk("%s,%d - EINVAL cannot handle chained cipher/hash combos\n",
__FILE__, __LINE__);
return EINVAL;
}
/*
* So we have something we can do, lets setup the session
*/
if (octo_sessions) {
for (i = 1; i < octo_sesnum; i++)
if (octo_sessions[i] == NULL)
break;
} else
i = 1; /* NB: to silence compiler warning */
if (octo_sessions == NULL || i == octo_sesnum) {
if (octo_sessions == NULL) {
i = 1; /* We leave octo_sessions[0] empty */
octo_sesnum = CRYPTO_SW_SESSIONS;
} else
octo_sesnum *= 2;
ocd = kmalloc(octo_sesnum * sizeof(struct octo_sess *), SLAB_ATOMIC);
if (ocd == NULL) {
/* Reset session number */
if (octo_sesnum == CRYPTO_SW_SESSIONS)
octo_sesnum = 0;
else
octo_sesnum /= 2;
dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__);
return ENOBUFS;
}
memset(ocd, 0, octo_sesnum * sizeof(struct octo_sess *));
/* Copy existing sessions */
if (octo_sessions) {
memcpy(ocd, octo_sessions,
(octo_sesnum / 2) * sizeof(struct octo_sess *));
kfree(octo_sessions);
}
octo_sessions = ocd;
}
ocd = &octo_sessions[i];
*sid = i;
*ocd = (struct octo_sess *) kmalloc(sizeof(struct octo_sess), SLAB_ATOMIC);
if (*ocd == NULL) {
octo_freesession(NULL, i);
dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__);
return ENOBUFS;
}
memset(*ocd, 0, sizeof(struct octo_sess));
if (encini && encini->cri_key) {
(*ocd)->octo_encklen = (encini->cri_klen + 7) / 8;
memcpy((*ocd)->octo_enckey, encini->cri_key, (*ocd)->octo_encklen);
}
if (macini && macini->cri_key) {
(*ocd)->octo_macklen = (macini->cri_klen + 7) / 8;
memcpy((*ocd)->octo_mackey, macini->cri_key, (*ocd)->octo_macklen);
}
(*ocd)->octo_mlen = 0;
if (encini && encini->cri_mlen)
(*ocd)->octo_mlen = encini->cri_mlen;
else if (macini && macini->cri_mlen)
(*ocd)->octo_mlen = macini->cri_mlen;
else
(*ocd)->octo_mlen = 12;
/*
* point c at the enc if it exists, otherwise the mac
*/
c = encini ? encini : macini;
switch (c->cri_alg) {
case CRYPTO_DES_CBC:
case CRYPTO_3DES_CBC:
(*ocd)->octo_ivsize = 8;
switch (macini ? macini->cri_alg : -1) {
case CRYPTO_MD5_HMAC:
(*ocd)->octo_encrypt = octo_des_cbc_md5_encrypt;
(*ocd)->octo_decrypt = octo_des_cbc_md5_decrypt;
octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner,
(*ocd)->octo_hmouter);
break;
case CRYPTO_SHA1_HMAC:
(*ocd)->octo_encrypt = octo_des_cbc_sha1_encrypt;
(*ocd)->octo_decrypt = octo_des_cbc_sha1_decrypt;
octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner,
(*ocd)->octo_hmouter);
break;
case -1:
(*ocd)->octo_encrypt = octo_des_cbc_encrypt;
(*ocd)->octo_decrypt = octo_des_cbc_decrypt;
break;
default:
octo_freesession(NULL, i);
dprintk("%s,%d: EINVALn", __FILE__, __LINE__);
return EINVAL;
}
break;
case CRYPTO_AES_CBC:
(*ocd)->octo_ivsize = 16;
switch (macini ? macini->cri_alg : -1) {
case CRYPTO_MD5_HMAC:
(*ocd)->octo_encrypt = octo_aes_cbc_md5_encrypt;
(*ocd)->octo_decrypt = octo_aes_cbc_md5_decrypt;
octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner,
(*ocd)->octo_hmouter);
break;
case CRYPTO_SHA1_HMAC:
(*ocd)->octo_encrypt = octo_aes_cbc_sha1_encrypt;
(*ocd)->octo_decrypt = octo_aes_cbc_sha1_decrypt;
octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner,
(*ocd)->octo_hmouter);
break;
case -1:
(*ocd)->octo_encrypt = octo_aes_cbc_encrypt;
(*ocd)->octo_decrypt = octo_aes_cbc_decrypt;
break;
default:
octo_freesession(NULL, i);
dprintk("%s,%d: EINVALn", __FILE__, __LINE__);
return EINVAL;
}
break;
case CRYPTO_MD5_HMAC:
(*ocd)->octo_encrypt = octo_null_md5_encrypt;
(*ocd)->octo_decrypt = octo_null_md5_encrypt; /* encrypt == decrypt */
octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner,
(*ocd)->octo_hmouter);
break;
case CRYPTO_SHA1_HMAC:
(*ocd)->octo_encrypt = octo_null_sha1_encrypt;
(*ocd)->octo_decrypt = octo_null_sha1_encrypt; /* encrypt == decrypt */
octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner,
(*ocd)->octo_hmouter);
break;
default:
octo_freesession(NULL, i);
dprintk("%s,%d: EINVALn", __FILE__, __LINE__);
return EINVAL;
}
(*ocd)->octo_encalg = encini ? encini->cri_alg : -1;
(*ocd)->octo_macalg = macini ? macini->cri_alg : -1;
return 0;
}
/*
* Free a session.
*/
static int
octo_freesession(device_t dev, u_int64_t tid)
{
u_int32_t sid = CRYPTO_SESID2LID(tid);
dprintk("%s()\n", __FUNCTION__);
if (sid > octo_sesnum || octo_sessions == NULL ||
octo_sessions[sid] == NULL) {
dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__);
return(EINVAL);
}
/* Silently accept and return */
if (sid == 0)
return(0);
if (octo_sessions[sid])
kfree(octo_sessions[sid]);
octo_sessions[sid] = NULL;
return 0;
}
/*
* Process a request.
*/
static int
octo_process(device_t dev, struct cryptop *crp, int hint)
{
struct cryptodesc *crd;
struct octo_sess *od;
u_int32_t lid;
#define SCATTERLIST_MAX 16
struct scatterlist sg[SCATTERLIST_MAX];
int sg_num, sg_len;
struct sk_buff *skb = NULL;
struct uio *uiop = NULL;
struct cryptodesc *enccrd = NULL, *maccrd = NULL;
unsigned char *ivp = NULL;
unsigned char iv_data[HASH_MAX_LEN];
int auth_off = 0, auth_len = 0, crypt_off = 0, crypt_len = 0, icv_off = 0;
dprintk("%s()\n", __FUNCTION__);
/* Sanity check */
if (crp == NULL) {
dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__);
return EINVAL;
}
crp->crp_etype = 0;
if (crp->crp_desc == NULL || crp->crp_buf == NULL) {
dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__);
crp->crp_etype = EINVAL;
goto done;
}
lid = crp->crp_sid & 0xffffffff;
if (lid >= octo_sesnum || lid == 0 || octo_sessions == NULL ||
octo_sessions[lid] == NULL) {
crp->crp_etype = ENOENT;
dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__);
goto done;
}
od = octo_sessions[lid];
/*
* do some error checking outside of the loop for SKB and IOV processing
* this leaves us with valid skb or uiop pointers for later
*/
if (crp->crp_flags & CRYPTO_F_SKBUF) {
skb = (struct sk_buff *) crp->crp_buf;
if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) {
printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__,
skb_shinfo(skb)->nr_frags);
goto done;
}
} else if (crp->crp_flags & CRYPTO_F_IOV) {
uiop = (struct uio *) crp->crp_buf;
if (uiop->uio_iovcnt > SCATTERLIST_MAX) {
printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__,
uiop->uio_iovcnt);
goto done;
}
}
/* point our enccrd and maccrd appropriately */
crd = crp->crp_desc;
if (crd->crd_alg == od->octo_encalg) enccrd = crd;
if (crd->crd_alg == od->octo_macalg) maccrd = crd;
crd = crd->crd_next;
if (crd) {
if (crd->crd_alg == od->octo_encalg) enccrd = crd;
if (crd->crd_alg == od->octo_macalg) maccrd = crd;
crd = crd->crd_next;
}
if (crd) {
crp->crp_etype = EINVAL;
dprintk("%s,%d: ENOENT - descriptors do not match session\n",
__FILE__, __LINE__);
goto done;
}
if (enccrd) {
if (enccrd->crd_flags & CRD_F_ENCRYPT) {
if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
ivp = enccrd->crd_iv;
else
read_random((ivp = iv_data), od->octo_ivsize);
if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0)
crypto_copyback(crp->crp_flags, crp->crp_buf,
enccrd->crd_inject, od->octo_ivsize, ivp);
} else {
if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) {
ivp = enccrd->crd_iv;
} else {
ivp = iv_data;
crypto_copydata(crp->crp_flags, crp->crp_buf,
enccrd->crd_inject, od->octo_ivsize, (caddr_t) ivp);
}
}
if (maccrd) {
auth_off = maccrd->crd_skip;
auth_len = maccrd->crd_len;
icv_off = maccrd->crd_inject;
}
crypt_off = enccrd->crd_skip;
crypt_len = enccrd->crd_len;
} else { /* if (maccrd) */
auth_off = maccrd->crd_skip;
auth_len = maccrd->crd_len;
icv_off = maccrd->crd_inject;
}
/*
* setup the SG list to cover the buffer
*/
memset(sg, 0, sizeof(sg));
if (crp->crp_flags & CRYPTO_F_SKBUF) {
int i, len;
sg_num = 0;
sg_len = 0;
len = skb_headlen(skb);
sg_set_page(&sg[sg_num], virt_to_page(skb->data), len,
offset_in_page(skb->data));
sg_len += len;
sg_num++;
for (i = 0; i < skb_shinfo(skb)->nr_frags && sg_num < SCATTERLIST_MAX;
i++) {
len = skb_shinfo(skb)->frags[i].size;
sg_set_page(&sg[sg_num], skb_frag_page(&skb_shinfo(skb)->frags[i]),
len, skb_shinfo(skb)->frags[i].page_offset);
sg_len += len;
sg_num++;
}
} else if (crp->crp_flags & CRYPTO_F_IOV) {
int len;
sg_len = 0;
for (sg_num = 0; sg_len < crp->crp_ilen &&
sg_num < uiop->uio_iovcnt &&
sg_num < SCATTERLIST_MAX; sg_num++) {
len = uiop->uio_iov[sg_num].iov_len;
sg_set_page(&sg[sg_num],
virt_to_page(uiop->uio_iov[sg_num].iov_base), len,
offset_in_page(uiop->uio_iov[sg_num].iov_base));
sg_len += len;
}
} else {
sg_len = crp->crp_ilen;
sg_set_page(&sg[0], virt_to_page(crp->crp_buf), sg_len,
offset_in_page(crp->crp_buf));
sg_num = 1;
}
if (sg_num > 0)
sg_mark_end(&sg[sg_num-1]);
/*
* setup a new explicit key
*/
if (enccrd) {
if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
od->octo_encklen = (enccrd->crd_klen + 7) / 8;
memcpy(od->octo_enckey, enccrd->crd_key, od->octo_encklen);
}
}
if (maccrd) {
if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
od->octo_macklen = (maccrd->crd_klen + 7) / 8;
memcpy(od->octo_mackey, maccrd->crd_key, od->octo_macklen);
od->octo_mackey_set = 0;
}
if (!od->octo_mackey_set) {
octo_calc_hash(maccrd->crd_alg == CRYPTO_MD5_HMAC ? 0 : 1,
maccrd->crd_key, od->octo_hminner, od->octo_hmouter);
od->octo_mackey_set = 1;
}
}
if (!enccrd || (enccrd->crd_flags & CRD_F_ENCRYPT))
(*od->octo_encrypt)(od, sg, sg_len,
auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp);
else
(*od->octo_decrypt)(od, sg, sg_len,
auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp);
done:
crypto_done(crp);
return 0;
}
static int
cryptocteon_init(void)
{
dprintk("%s(%p)\n", __FUNCTION__, cryptocteon_init);
softc_device_init(&octo_softc, "cryptocteon", 0, octo_methods);
octo_id = crypto_get_driverid(softc_get_device(&octo_softc),
CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SYNC);
if (octo_id < 0) {
printk("Cryptocteon device cannot initialize!");
return -ENODEV;
}
crypto_register(octo_id, CRYPTO_MD5_HMAC, 0,0);
crypto_register(octo_id, CRYPTO_SHA1_HMAC, 0,0);
//crypto_register(octo_id, CRYPTO_MD5, 0,0);
//crypto_register(octo_id, CRYPTO_SHA1, 0,0);
crypto_register(octo_id, CRYPTO_DES_CBC, 0,0);
crypto_register(octo_id, CRYPTO_3DES_CBC, 0,0);
crypto_register(octo_id, CRYPTO_AES_CBC, 0,0);
return(0);
}
static void
cryptocteon_exit(void)
{
dprintk("%s()\n", __FUNCTION__);
crypto_unregister_all(octo_id);
octo_id = -1;
}
module_init(cryptocteon_init);
module_exit(cryptocteon_exit);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_AUTHOR("David McCullough <david_mccullough@mcafee.com>");
MODULE_DESCRIPTION("Cryptocteon (OCF module for Cavium OCTEON crypto)");

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target/linux/generic/files/crypto/ocf/cryptodev.c
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480
target/linux/generic/files/crypto/ocf/cryptodev.h
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@ -1,480 +0,0 @@
/* $FreeBSD: src/sys/opencrypto/cryptodev.h,v 1.25 2007/05/09 19:37:02 gnn Exp $ */
/* $OpenBSD: cryptodev.h,v 1.31 2002/06/11 11:14:29 beck Exp $ */
/*-
* Linux port done by David McCullough <david_mccullough@mcafee.com>
* Copyright (C) 2006-2010 David McCullough
* Copyright (C) 2004-2005 Intel Corporation.
* The license and original author are listed below.
*
* The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu)
* Copyright (c) 2002-2006 Sam Leffler, Errno Consulting
*
* This code was written by Angelos D. Keromytis in Athens, Greece, in
* February 2000. Network Security Technologies Inc. (NSTI) kindly
* supported the development of this code.
*
* Copyright (c) 2000 Angelos D. Keromytis
*
* Permission to use, copy, and modify this software with or without fee
* is hereby granted, provided that this entire notice is included in
* all source code copies of any software which is or includes a copy or
* modification of this software.
*
* THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY
* REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE
* MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR
* PURPOSE.
*
* Copyright (c) 2001 Theo de Raadt
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Effort sponsored in part by the Defense Advanced Research Projects
* Agency (DARPA) and Air Force Research Laboratory, Air Force
* Materiel Command, USAF, under agreement number F30602-01-2-0537.
*
*/
#ifndef _CRYPTO_CRYPTO_H_
#define _CRYPTO_CRYPTO_H_
/* Some initial values */
#define CRYPTO_DRIVERS_INITIAL 4
#define CRYPTO_SW_SESSIONS 32
/* Hash values */
#define NULL_HASH_LEN 0
#define MD5_HASH_LEN 16
#define SHA1_HASH_LEN 20
#define RIPEMD160_HASH_LEN 20
#define SHA2_256_HASH_LEN 32
#define SHA2_384_HASH_LEN 48
#define SHA2_512_HASH_LEN 64
#define MD5_KPDK_HASH_LEN 16
#define SHA1_KPDK_HASH_LEN 20
/* Maximum hash algorithm result length */
#define HASH_MAX_LEN SHA2_512_HASH_LEN /* Keep this updated */
/* HMAC values */
#define NULL_HMAC_BLOCK_LEN 1
#define MD5_HMAC_BLOCK_LEN 64
#define SHA1_HMAC_BLOCK_LEN 64
#define RIPEMD160_HMAC_BLOCK_LEN 64
#define SHA2_256_HMAC_BLOCK_LEN 64
#define SHA2_384_HMAC_BLOCK_LEN 128
#define SHA2_512_HMAC_BLOCK_LEN 128
/* Maximum HMAC block length */
#define HMAC_MAX_BLOCK_LEN SHA2_512_HMAC_BLOCK_LEN /* Keep this updated */
#define HMAC_IPAD_VAL 0x36
#define HMAC_OPAD_VAL 0x5C
/* Encryption algorithm block sizes */
#define NULL_BLOCK_LEN 1
#define DES_BLOCK_LEN 8
#define DES3_BLOCK_LEN 8
#define BLOWFISH_BLOCK_LEN 8
#define SKIPJACK_BLOCK_LEN 8
#define CAST128_BLOCK_LEN 8
#define RIJNDAEL128_BLOCK_LEN 16
#define AES_BLOCK_LEN RIJNDAEL128_BLOCK_LEN
#define CAMELLIA_BLOCK_LEN 16
#define ARC4_BLOCK_LEN 1
#define EALG_MAX_BLOCK_LEN AES_BLOCK_LEN /* Keep this updated */
/* Encryption algorithm min and max key sizes */
#define NULL_MIN_KEY_LEN 0
#define NULL_MAX_KEY_LEN 0
#define DES_MIN_KEY_LEN 8
#define DES_MAX_KEY_LEN 8
#define DES3_MIN_KEY_LEN 24
#define DES3_MAX_KEY_LEN 24
#define BLOWFISH_MIN_KEY_LEN 4
#define BLOWFISH_MAX_KEY_LEN 56
#define SKIPJACK_MIN_KEY_LEN 10
#define SKIPJACK_MAX_KEY_LEN 10
#define CAST128_MIN_KEY_LEN 5
#define CAST128_MAX_KEY_LEN 16
#define RIJNDAEL128_MIN_KEY_LEN 16
#define RIJNDAEL128_MAX_KEY_LEN 32
#define AES_MIN_KEY_LEN RIJNDAEL128_MIN_KEY_LEN
#define AES_MAX_KEY_LEN RIJNDAEL128_MAX_KEY_LEN
#define CAMELLIA_MIN_KEY_LEN 16
#define CAMELLIA_MAX_KEY_LEN 32
#define ARC4_MIN_KEY_LEN 1
#define ARC4_MAX_KEY_LEN 256
/* Max size of data that can be processed */
#define CRYPTO_MAX_DATA_LEN 64*1024 - 1
#define CRYPTO_ALGORITHM_MIN 1
#define CRYPTO_DES_CBC 1
#define CRYPTO_3DES_CBC 2
#define CRYPTO_BLF_CBC 3
#define CRYPTO_CAST_CBC 4
#define CRYPTO_SKIPJACK_CBC 5
#define CRYPTO_MD5_HMAC 6
#define CRYPTO_SHA1_HMAC 7
#define CRYPTO_RIPEMD160_HMAC 8
#define CRYPTO_MD5_KPDK 9
#define CRYPTO_SHA1_KPDK 10
#define CRYPTO_RIJNDAEL128_CBC 11 /* 128 bit blocksize */
#define CRYPTO_AES_CBC 11 /* 128 bit blocksize -- the same as above */
#define CRYPTO_ARC4 12
#define CRYPTO_MD5 13
#define CRYPTO_SHA1 14
#define CRYPTO_NULL_HMAC 15
#define CRYPTO_NULL_CBC 16
#define CRYPTO_DEFLATE_COMP 17 /* Deflate compression algorithm */
#define CRYPTO_SHA2_256_HMAC 18
#define CRYPTO_SHA2_384_HMAC 19
#define CRYPTO_SHA2_512_HMAC 20
#define CRYPTO_CAMELLIA_CBC 21
#define CRYPTO_SHA2_256 22
#define CRYPTO_SHA2_384 23
#define CRYPTO_SHA2_512 24
#define CRYPTO_RIPEMD160 25
#define CRYPTO_LZS_COMP 26
#define CRYPTO_ALGORITHM_MAX 26 /* Keep updated - see above */
/* Algorithm flags */
#define CRYPTO_ALG_FLAG_SUPPORTED 0x01 /* Algorithm is supported */
#define CRYPTO_ALG_FLAG_RNG_ENABLE 0x02 /* Has HW RNG for DH/DSA */
#define CRYPTO_ALG_FLAG_DSA_SHA 0x04 /* Can do SHA on msg */
/*
* Crypto driver/device flags. They can set in the crid
* parameter when creating a session or submitting a key
* op to affect the device/driver assigned. If neither
* of these are specified then the crid is assumed to hold
* the driver id of an existing (and suitable) device that
* must be used to satisfy the request.
*/
#define CRYPTO_FLAG_HARDWARE 0x01000000 /* hardware accelerated */
#define CRYPTO_FLAG_SOFTWARE 0x02000000 /* software implementation */
/* NB: deprecated */
struct session_op {
u_int32_t cipher; /* ie. CRYPTO_DES_CBC */
u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */
u_int32_t keylen; /* cipher key */
caddr_t key;
int mackeylen; /* mac key */
caddr_t mackey;
u_int32_t ses; /* returns: session # */
};
struct session2_op {
u_int32_t cipher; /* ie. CRYPTO_DES_CBC */
u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */
u_int32_t keylen; /* cipher key */
caddr_t key;
int mackeylen; /* mac key */
caddr_t mackey;
u_int32_t ses; /* returns: session # */
int crid; /* driver id + flags (rw) */
int pad[4]; /* for future expansion */
};
struct crypt_op {
u_int32_t ses;
u_int16_t op; /* i.e. COP_ENCRYPT */
#define COP_NONE 0
#define COP_ENCRYPT 1
#define COP_DECRYPT 2
u_int16_t flags;
#define COP_F_BATCH 0x0008 /* Batch op if possible */
u_int len;
caddr_t src, dst; /* become iov[] inside kernel */
caddr_t mac; /* must be big enough for chosen MAC */
caddr_t iv;
};
/*
* Parameters for looking up a crypto driver/device by
* device name or by id. The latter are returned for
* created sessions (crid) and completed key operations.
*/
struct crypt_find_op {
int crid; /* driver id + flags */
char name[32]; /* device/driver name */
};
/* bignum parameter, in packed bytes, ... */
struct crparam {
caddr_t crp_p;
u_int crp_nbits;
};
#define CRK_MAXPARAM 8
struct crypt_kop {
u_int crk_op; /* ie. CRK_MOD_EXP or other */
u_int crk_status; /* return status */
u_short crk_iparams; /* # of input parameters */
u_short crk_oparams; /* # of output parameters */
u_int crk_crid; /* NB: only used by CIOCKEY2 (rw) */
struct crparam crk_param[CRK_MAXPARAM];
};
#define CRK_ALGORITM_MIN 0
#define CRK_MOD_EXP 0
#define CRK_MOD_EXP_CRT 1
#define CRK_DSA_SIGN 2
#define CRK_DSA_VERIFY 3
#define CRK_DH_COMPUTE_KEY 4
#define CRK_ALGORITHM_MAX 4 /* Keep updated - see below */
#define CRF_MOD_EXP (1 << CRK_MOD_EXP)
#define CRF_MOD_EXP_CRT (1 << CRK_MOD_EXP_CRT)
#define CRF_DSA_SIGN (1 << CRK_DSA_SIGN)
#define CRF_DSA_VERIFY (1 << CRK_DSA_VERIFY)
#define CRF_DH_COMPUTE_KEY (1 << CRK_DH_COMPUTE_KEY)
/*
* done against open of /dev/crypto, to get a cloned descriptor.
* Please use F_SETFD against the cloned descriptor.
*/
#define CRIOGET _IOWR('c', 100, u_int32_t)
#define CRIOASYMFEAT CIOCASYMFEAT
#define CRIOFINDDEV CIOCFINDDEV
/* the following are done against the cloned descriptor */
#define CIOCGSESSION _IOWR('c', 101, struct session_op)
#define CIOCFSESSION _IOW('c', 102, u_int32_t)
#define CIOCCRYPT _IOWR('c', 103, struct crypt_op)
#define CIOCKEY _IOWR('c', 104, struct crypt_kop)
#define CIOCASYMFEAT _IOR('c', 105, u_int32_t)
#define CIOCGSESSION2 _IOWR('c', 106, struct session2_op)
#define CIOCKEY2 _IOWR('c', 107, struct crypt_kop)
#define CIOCFINDDEV _IOWR('c', 108, struct crypt_find_op)
struct cryptotstat {
struct timespec acc; /* total accumulated time */
struct timespec min; /* min time */
struct timespec max; /* max time */
u_int32_t count; /* number of observations */
};
struct cryptostats {
u_int32_t cs_ops; /* symmetric crypto ops submitted */
u_int32_t cs_errs; /* symmetric crypto ops that failed */
u_int32_t cs_kops; /* asymetric/key ops submitted */
u_int32_t cs_kerrs; /* asymetric/key ops that failed */
u_int32_t cs_intrs; /* crypto swi thread activations */
u_int32_t cs_rets; /* crypto return thread activations */
u_int32_t cs_blocks; /* symmetric op driver block */
u_int32_t cs_kblocks; /* symmetric op driver block */
/*
* When CRYPTO_TIMING is defined at compile time and the
* sysctl debug.crypto is set to 1, the crypto system will
* accumulate statistics about how long it takes to process
* crypto requests at various points during processing.
*/
struct cryptotstat cs_invoke; /* crypto_dipsatch -> crypto_invoke */
struct cryptotstat cs_done; /* crypto_invoke -> crypto_done */
struct cryptotstat cs_cb; /* crypto_done -> callback */
struct cryptotstat cs_finis; /* callback -> callback return */
u_int32_t cs_drops; /* crypto ops dropped due to congestion */
};
#ifdef __KERNEL__
/* Standard initialization structure beginning */
struct cryptoini {
int cri_alg; /* Algorithm to use */
int cri_klen; /* Key length, in bits */
int cri_mlen; /* Number of bytes we want from the
entire hash. 0 means all. */
caddr_t cri_key; /* key to use */
u_int8_t cri_iv[EALG_MAX_BLOCK_LEN]; /* IV to use */
struct cryptoini *cri_next;
};
/* Describe boundaries of a single crypto operation */
struct cryptodesc {
int crd_skip; /* How many bytes to ignore from start */
int crd_len; /* How many bytes to process */
int crd_inject; /* Where to inject results, if applicable */
int crd_flags;
#define CRD_F_ENCRYPT 0x01 /* Set when doing encryption */
#define CRD_F_IV_PRESENT 0x02 /* When encrypting, IV is already in
place, so don't copy. */
#define CRD_F_IV_EXPLICIT 0x04 /* IV explicitly provided */
#define CRD_F_DSA_SHA_NEEDED 0x08 /* Compute SHA-1 of buffer for DSA */
#define CRD_F_KEY_EXPLICIT 0x10 /* Key explicitly provided */
#define CRD_F_COMP 0x0f /* Set when doing compression */
struct cryptoini CRD_INI; /* Initialization/context data */
#define crd_iv CRD_INI.cri_iv
#define crd_key CRD_INI.cri_key
#define crd_alg CRD_INI.cri_alg
#define crd_klen CRD_INI.cri_klen
#define crd_mlen CRD_INI.cri_mlen
struct cryptodesc *crd_next;
};
/* Structure describing complete operation */
struct cryptop {
struct list_head crp_next;
wait_queue_head_t crp_waitq;
u_int64_t crp_sid; /* Session ID */
int crp_ilen; /* Input data total length */
int crp_olen; /* Result total length */
int crp_etype; /*
* Error type (zero means no error).
* All error codes except EAGAIN
* indicate possible data corruption (as in,
* the data have been touched). On all
* errors, the crp_sid may have changed
* (reset to a new one), so the caller
* should always check and use the new
* value on future requests.
*/
int crp_flags;
#define CRYPTO_F_SKBUF 0x0001 /* Input/output are skbuf chains */
#define CRYPTO_F_IOV 0x0002 /* Input/output are uio */
#define CRYPTO_F_REL 0x0004 /* Must return data in same place */
#define CRYPTO_F_BATCH 0x0008 /* Batch op if possible */
#define CRYPTO_F_CBIMM 0x0010 /* Do callback immediately */
#define CRYPTO_F_DONE 0x0020 /* Operation completed */
#define CRYPTO_F_CBIFSYNC 0x0040 /* Do CBIMM if op is synchronous */
caddr_t crp_buf; /* Data to be processed */
caddr_t crp_opaque; /* Opaque pointer, passed along */
struct cryptodesc *crp_desc; /* Linked list of processing descriptors */
int (*crp_callback)(struct cryptop *); /* Callback function */
};
#define CRYPTO_BUF_CONTIG 0x0
#define CRYPTO_BUF_IOV 0x1
#define CRYPTO_BUF_SKBUF 0x2
#define CRYPTO_OP_DECRYPT 0x0
#define CRYPTO_OP_ENCRYPT 0x1
/*
* Hints passed to process methods.
*/
#define CRYPTO_HINT_MORE 0x1 /* more ops coming shortly */
struct cryptkop {
struct list_head krp_next;
wait_queue_head_t krp_waitq;
int krp_flags;
#define CRYPTO_KF_DONE 0x0001 /* Operation completed */
#define CRYPTO_KF_CBIMM 0x0002 /* Do callback immediately */
u_int krp_op; /* ie. CRK_MOD_EXP or other */
u_int krp_status; /* return status */
u_short krp_iparams; /* # of input parameters */
u_short krp_oparams; /* # of output parameters */
u_int krp_crid; /* desired device, etc. */
u_int32_t krp_hid;
struct crparam krp_param[CRK_MAXPARAM]; /* kvm */
int (*krp_callback)(struct cryptkop *);
};
#include <ocf-compat.h>
/*
* Session ids are 64 bits. The lower 32 bits contain a "local id" which
* is a driver-private session identifier. The upper 32 bits contain a
* "hardware id" used by the core crypto code to identify the driver and
* a copy of the driver's capabilities that can be used by client code to
* optimize operation.
*/
#define CRYPTO_SESID2HID(_sid) (((_sid) >> 32) & 0x00ffffff)
#define CRYPTO_SESID2CAPS(_sid) (((_sid) >> 32) & 0xff000000)
#define CRYPTO_SESID2LID(_sid) (((u_int32_t) (_sid)) & 0xffffffff)
extern int crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int hard);
extern int crypto_freesession(u_int64_t sid);
#define CRYPTOCAP_F_HARDWARE CRYPTO_FLAG_HARDWARE
#define CRYPTOCAP_F_SOFTWARE CRYPTO_FLAG_SOFTWARE
#define CRYPTOCAP_F_SYNC 0x04000000 /* operates synchronously */
extern int32_t crypto_get_driverid(device_t dev, int flags);
extern int crypto_find_driver(const char *);
extern device_t crypto_find_device_byhid(int hid);
extern int crypto_getcaps(int hid);
extern int crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen,
u_int32_t flags);
extern int crypto_kregister(u_int32_t, int, u_int32_t);
extern int crypto_unregister(u_int32_t driverid, int alg);
extern int crypto_unregister_all(u_int32_t driverid);
extern int crypto_dispatch(struct cryptop *crp);
extern int crypto_kdispatch(struct cryptkop *);
#define CRYPTO_SYMQ 0x1
#define CRYPTO_ASYMQ 0x2
extern int crypto_unblock(u_int32_t, int);
extern void crypto_done(struct cryptop *crp);
extern void crypto_kdone(struct cryptkop *);
extern int crypto_getfeat(int *);
extern void crypto_freereq(struct cryptop *crp);
extern struct cryptop *crypto_getreq(int num);
extern int crypto_usercrypto; /* userland may do crypto requests */
extern int crypto_userasymcrypto; /* userland may do asym crypto reqs */
extern int crypto_devallowsoft; /* only use hardware crypto */
/*
* random number support, crypto_unregister_all will unregister
*/
extern int crypto_rregister(u_int32_t driverid,
int (*read_random)(void *arg, u_int32_t *buf, int len), void *arg);
extern int crypto_runregister_all(u_int32_t driverid);
/*
* Crypto-related utility routines used mainly by drivers.
*
* XXX these don't really belong here; but for now they're
* kept apart from the rest of the system.
*/
struct uio;
extern void cuio_copydata(struct uio* uio, int off, int len, caddr_t cp);
extern void cuio_copyback(struct uio* uio, int off, int len, caddr_t cp);
extern struct iovec *cuio_getptr(struct uio *uio, int loc, int *off);
extern void crypto_copyback(int flags, caddr_t buf, int off, int size,
caddr_t in);
extern void crypto_copydata(int flags, caddr_t buf, int off, int size,
caddr_t out);
extern int crypto_apply(int flags, caddr_t buf, int off, int len,
int (*f)(void *, void *, u_int), void *arg);
#endif /* __KERNEL__ */
#endif /* _CRYPTO_CRYPTO_H_ */

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#########################################################################
#
# Targets supported
# all - builds everything and installs
# install - identical to all
# depend - build dependencies
# clean - clears derived objects except the .depend files
# distclean- clears all derived objects and the .depend file
#
# @par
# This file is provided under a dual BSD/GPLv2 license. When using or
# redistributing this file, you may do so under either license.
#
# GPL LICENSE SUMMARY
#
# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of version 2 of the GNU General Public License as
# published by the Free Software Foundation.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
# The full GNU General Public License is included in this distribution
# in the file called LICENSE.GPL.
#
# Contact Information:
# Intel Corporation
#
# BSD LICENSE
#
# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# * Neither the name of Intel Corporation nor the names of its
# contributors may be used to endorse or promote products derived
# from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#
# version: Security.L.1.0.2-229
############################################################################
####################Common variables and definitions########################
ifndef ICP_ROOT
$(warning ICP_ROOT is undefined. Please set the path to EP80579 release package directory \
"-> setenv ICP_ROOT <path>")
all fastdep:
:
else
ifndef KERNEL_SOURCE_ROOT
$(error KERNEL_SOURCE_ROOT is undefined. Please set the path to the kernel source directory \
"-> setenv KERNEL_SOURCE_ROOT <path>")
endif
# Ensure The ENV_DIR environmental var is defined.
ifndef ICP_ENV_DIR
$(error ICP_ENV_DIR is undefined. Please set the path to EP80579 driver environment.mk file \
"-> setenv ICP_ENV_DIR <path>")
endif
#Add your project environment Makefile
include ${ICP_ENV_DIR}/environment.mk
#include the makefile with all the default and common Make variable definitions
include ${ICP_BUILDSYSTEM_PATH}/build_files/common.mk
#Add the name for the executable, Library or Module output definitions
OUTPUT_NAME= icp_ocf
# List of Source Files to be compiled
SOURCES= icp_common.c icp_sym.c icp_asym.c icp_ocf_linux.c
#common includes between all supported OSes
INCLUDES= -I ${ICP_API_DIR} -I${ICP_LAC_API} \
-I${ICP_OCF_SRC_DIR}
# The location of the os level makefile needs to be changed.
include ${ICP_ENV_DIR}/${ICP_OS}_${ICP_OS_LEVEL}.mk
# On the line directly below list the outputs you wish to build for,
# e.g "lib_static lib_shared exe module" as shown below
install: module
###################Include rules makefiles########################
include ${ICP_BUILDSYSTEM_PATH}/build_files/rules.mk
###################End of Rules inclusion#########################
endif

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###########################################################################
#
# This file is provided under a dual BSD/GPLv2 license. When using or
# redistributing this file, you may do so under either license.
#
# GPL LICENSE SUMMARY
#
# Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of version 2 of the GNU General Public License as
# published by the Free Software Foundation.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
# The full GNU General Public License is included in this distribution
# in the file called LICENSE.GPL.
#
# Contact Information:
# Intel Corporation
#
# BSD LICENSE
#
# Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# * Neither the name of Intel Corporation nor the names of its
# contributors may be used to endorse or promote products derived
# from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#
# version: Security.L.1.0.130
#
###########################################################################
ICP_LAC_API=$(ICP_ROOT)/Acceleration/include/lac
ICP_BTR_API=$(ICP_ROOT)/Acceleration/include/btr
ICP_API_DIR=$(ICP_ROOT)/Acceleration/include
ICP_OCF_SHIM_DIR?=$(KERNEL_SOURCE_ROOT)/crypto/ocf/
ifeq ($(wildcard $(ICP_OCF_SHIM_DIR)),)
ICP_OCF_SHIM_DIR?=$(ROOTDIR)/modules/ocf/
endif
ICP_OS_LEVEL?=kernel_space
ICP_OS?=linux_2.6
ICP_CORE?=ia

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/*************************************************************************
*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
* The full GNU General Public License is included in this distribution
* in the file called LICENSE.GPL.
*
* Contact Information:
* Intel Corporation
*
* BSD LICENSE
*
* Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* version: Security.L.1.0.2-229
*
***************************************************************************/
/*
* An OCF module that uses Intel® QuickAssist Integrated Accelerator to do the
* crypto.
*
* This driver requires the ICP Access Library that is available from Intel in
* order to operate.
*/
#include "icp_ocf.h"
#define ICP_OCF_COMP_NAME "ICP_OCF"
#define ICP_OCF_VER_MAIN (2)
#define ICP_OCF_VER_MJR (1)
#define ICP_OCF_VER_MNR (0)
#define MAX_DEREG_RETRIES (100)
#define DEFAULT_DEREG_RETRIES (10)
#define DEFAULT_DEREG_DELAY_IN_JIFFIES (10)
/* This defines the maximum number of sessions possible between OCF
and the OCF EP80579 Driver. If set to zero, there is no limit. */
#define DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT (0)
#define NUM_SUPPORTED_CAPABILITIES (21)
/*Slab zone names*/
#define ICP_SESSION_DATA_NAME "icp_ocf.SesDat"
#define ICP_OP_DATA_NAME "icp_ocf.OpDat"
#define ICP_DH_NAME "icp_ocf.DH"
#define ICP_MODEXP_NAME "icp_ocf.ModExp"
#define ICP_RSA_DECRYPT_NAME "icp_ocf.RSAdec"
#define ICP_RSA_PKEY_NAME "icp_ocf.RSApk"
#define ICP_DSA_SIGN_NAME "icp_ocf.DSAsg"
#define ICP_DSA_VER_NAME "icp_ocf.DSAver"
#define ICP_RAND_VAL_NAME "icp_ocf.DSArnd"
#define ICP_FLAT_BUFF_NAME "icp_ocf.FB"
/*Slabs zones*/
icp_kmem_cache drvSessionData_zone = NULL;
icp_kmem_cache drvOpData_zone = NULL;
icp_kmem_cache drvDH_zone = NULL;
icp_kmem_cache drvLnModExp_zone = NULL;
icp_kmem_cache drvRSADecrypt_zone = NULL;
icp_kmem_cache drvRSAPrivateKey_zone = NULL;
icp_kmem_cache drvDSARSSign_zone = NULL;
icp_kmem_cache drvDSARSSignKValue_zone = NULL;
icp_kmem_cache drvDSAVerify_zone = NULL;
/*Slab zones for flatbuffers and bufferlist*/
icp_kmem_cache drvFlatBuffer_zone = NULL;
static inline int icp_cache_null_check(void)
{
return (drvSessionData_zone && drvOpData_zone
&& drvDH_zone && drvLnModExp_zone && drvRSADecrypt_zone
&& drvRSAPrivateKey_zone && drvDSARSSign_zone
&& drvDSARSSign_zone && drvDSARSSignKValue_zone
&& drvDSAVerify_zone && drvFlatBuffer_zone);
}
/*Function to free all allocated slab caches before exiting the module*/
static void icp_ocfDrvFreeCaches(void);
int32_t icp_ocfDrvDriverId = INVALID_DRIVER_ID;
/* Module parameter - gives the number of times LAC deregistration shall be
re-tried */
int num_dereg_retries = DEFAULT_DEREG_RETRIES;
/* Module parameter - gives the delay time in jiffies before a LAC session
shall be attempted to be deregistered again */
int dereg_retry_delay_in_jiffies = DEFAULT_DEREG_DELAY_IN_JIFFIES;
/* Module parameter - gives the maximum number of sessions possible between
OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/
int max_sessions = DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT;
/* This is set when the module is removed from the system, no further
processing can take place if this is set */
icp_atomic_t icp_ocfDrvIsExiting = ICP_ATOMIC_INIT(0);
/* This is used to show how many lac sessions were not deregistered*/
icp_atomic_t lac_session_failed_dereg_count = ICP_ATOMIC_INIT(0);
/* This is used to track the number of registered sessions between OCF and
* and the OCF EP80579 driver, when max_session is set to value other than
* zero. This ensures that the max_session set for the OCF and the driver
* is equal to the LAC registered sessions */
icp_atomic_t num_ocf_to_drv_registered_sessions = ICP_ATOMIC_INIT(0);
/* Head of linked list used to store session data */
icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead;
icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList;
icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock;
/*Below pointer is only used in linux, FreeBSD uses the name to
create its own variable name*/
icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ = NULL;
ICP_WORKQUEUE_DEFINE_THREAD(icp_ocfDrvFreeLacSessionWorkQ);
struct icp_drvBuffListInfo defBuffListInfo;
/* Name : icp_ocfDrvInit
*
* Description : This function will register all the symmetric and asymmetric
* functionality that will be accelerated by the hardware. It will also
* get a unique driver ID from the OCF and initialise all slab caches
*/
ICP_MODULE_INIT_FUNC(icp_ocfDrvInit)
{
int ocfStatus = 0;
IPRINTK("=== %s ver %d.%d.%d ===\n", ICP_OCF_COMP_NAME,
ICP_OCF_VER_MAIN, ICP_OCF_VER_MJR, ICP_OCF_VER_MNR);
if (MAX_DEREG_RETRIES < num_dereg_retries) {
EPRINTK("Session deregistration retry count set to greater "
"than %d", MAX_DEREG_RETRIES);
icp_module_return_code(EINVAL);
}
/* Initialize and Start the Cryptographic component */
if (CPA_STATUS_SUCCESS !=
cpaCyStartInstance(CPA_INSTANCE_HANDLE_SINGLE)) {
EPRINTK("Failed to initialize and start the instance "
"of the Cryptographic component.\n");
return icp_module_return_code(EINVAL);
}
icp_spin_lock_init(&icp_ocfDrvSymSessInfoListSpinlock);
/* Set the default size of BufferList to allocate */
memset(&defBuffListInfo, 0, sizeof(struct icp_drvBuffListInfo));
if (ICP_OCF_DRV_STATUS_SUCCESS !=
icp_ocfDrvBufferListMemInfo(ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS,
&defBuffListInfo)) {
EPRINTK("Failed to get bufferlist memory info.\n");
return icp_module_return_code(ENOMEM);
}
/*Register OCF EP80579 Driver with OCF */
icp_ocfDrvDriverId = ICP_CRYPTO_GET_DRIVERID();
if (icp_ocfDrvDriverId < 0) {
EPRINTK("%s : ICP driver failed to register with OCF!\n",
__FUNCTION__);
return icp_module_return_code(ENODEV);
}
/*Create all the slab caches used by the OCF EP80579 Driver */
drvSessionData_zone =
ICP_CACHE_CREATE(ICP_SESSION_DATA_NAME, struct icp_drvSessionData);
/*
* Allocation of the OpData includes the allocation space for meta data.
* The memory after the opData structure is reserved for this meta data.
*/
drvOpData_zone =
icp_kmem_cache_create(ICP_OP_DATA_NAME,
sizeof(struct icp_drvOpData) +
defBuffListInfo.metaSize,
ICP_KERNEL_CACHE_ALIGN,
ICP_KERNEL_CACHE_NOINIT);
drvDH_zone = ICP_CACHE_CREATE(ICP_DH_NAME, CpaCyDhPhase1KeyGenOpData);
drvLnModExp_zone =
ICP_CACHE_CREATE(ICP_MODEXP_NAME, CpaCyLnModExpOpData);
drvRSADecrypt_zone =
ICP_CACHE_CREATE(ICP_RSA_DECRYPT_NAME, CpaCyRsaDecryptOpData);
drvRSAPrivateKey_zone =
ICP_CACHE_CREATE(ICP_RSA_PKEY_NAME, CpaCyRsaPrivateKey);
drvDSARSSign_zone =
ICP_CACHE_CREATE(ICP_DSA_SIGN_NAME, CpaCyDsaRSSignOpData);
/*too awkward to use a macro here */
drvDSARSSignKValue_zone =
ICP_CACHE_CREATE(ICP_RAND_VAL_NAME,
DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES);
drvDSAVerify_zone =
ICP_CACHE_CREATE(ICP_DSA_VER_NAME, CpaCyDsaVerifyOpData);
drvFlatBuffer_zone =
ICP_CACHE_CREATE(ICP_FLAT_BUFF_NAME, CpaFlatBuffer);
if (0 == icp_cache_null_check()) {
icp_ocfDrvFreeCaches();
EPRINTK("%s() line %d: Not enough memory!\n",
__FUNCTION__, __LINE__);
return ENOMEM;
}
/* Register the ICP symmetric crypto support. */
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_NULL_CBC, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_DES_CBC, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_3DES_CBC, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_AES_CBC, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_ARC4, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5_HMAC, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1_HMAC, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256_HMAC,
ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384_HMAC,
ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512, ocfStatus);
ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512_HMAC,
ocfStatus);
/* Register the ICP asymmetric algorithm support */
ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DH_COMPUTE_KEY,
ocfStatus);
ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP, ocfStatus);
ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP_CRT, ocfStatus);
ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_SIGN, ocfStatus);
ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_VERIFY, ocfStatus);
/* Register the ICP random number generator support */
ICP_REG_RAND_WITH_OCF(icp_ocfDrvDriverId,
icp_ocfDrvReadRandom, NULL, ocfStatus);
if (OCF_ZERO_FUNCTIONALITY_REGISTERED == ocfStatus) {
DPRINTK("%s: Failed to register any device capabilities\n",
__FUNCTION__);
icp_ocfDrvFreeCaches();
icp_ocfDrvDriverId = INVALID_DRIVER_ID;
return icp_module_return_code(ECANCELED);
}
DPRINTK("%s: Registered %d of %d device capabilities\n",
__FUNCTION__, ocfStatus, NUM_SUPPORTED_CAPABILITIES);
/*Session data linked list used during module exit */
ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead);
ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead_FreeMemList);
ICP_WORKQUEUE_CREATE(icp_ocfDrvFreeLacSessionWorkQ, "icpwq");
if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) {
EPRINTK("%s: Failed to create single "
"thread workqueue\n", __FUNCTION__);
icp_ocfDrvFreeCaches();
icp_ocfDrvDriverId = INVALID_DRIVER_ID;
return icp_module_return_code(ENOMEM);
}
return icp_module_return_code(0);
}
/* Name : icp_ocfDrvExit
*
* Description : This function will deregister all the symmetric sessions
* registered with the LAC component. It will also deregister all symmetric
* and asymmetric functionality that can be accelerated by the hardware via OCF
* and random number generation if it is enabled.
*/
ICP_MODULE_EXIT_FUNC(icp_ocfDrvExit)
{
CpaStatus lacStatus = CPA_STATUS_SUCCESS;
struct icp_drvSessionData *sessionData = NULL;
struct icp_drvSessionData *tempSessionData = NULL;
int i, remaining_delay_time_in_jiffies = 0;
/* For FreeBSD the invariant macro below makes function to return */
/* with EBUSY value in the case of any session which has been regi- */
/* stered with LAC not being deregistered. */
/* The Linux implementation is empty since it is purely to compensate */
/* for a limitation of the FreeBSD 7.1 Opencrypto framework. */
ICP_MODULE_EXIT_INV();
/* There is a possibility of a process or new session command being */
/* sent before this variable is incremented. The aim of this variable */
/* is to stop a loop of calls creating a deadlock situation which */
/* would prevent the driver from exiting. */
icp_atomic_set(&icp_ocfDrvIsExiting, 1);
/*Existing sessions will be routed to another driver after these calls */
crypto_unregister_all(icp_ocfDrvDriverId);
crypto_runregister_all(icp_ocfDrvDriverId);
if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) {
DPRINTK("%s: workqueue already "
"destroyed, therefore module exit "
" function already called. Exiting.\n", __FUNCTION__);
return ICP_MODULE_EXIT_FUNC_RETURN_VAL;
}
/*If any sessions are waiting to be deregistered, do that. This also
flushes the work queue */
ICP_WORKQUEUE_DESTROY(icp_ocfDrvFreeLacSessionWorkQ);
/*ENTER CRITICAL SECTION */
icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock);
ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData,
&icp_ocfDrvGlobalSymListHead, listNode) {
for (i = 0; i < num_dereg_retries; i++) {
/*No harm if bad input - LAC will handle error cases */
if (ICP_SESSION_RUNNING == tempSessionData->inUse) {
lacStatus =
cpaCySymRemoveSession
(CPA_INSTANCE_HANDLE_SINGLE,
tempSessionData->sessHandle);
if (CPA_STATUS_SUCCESS == lacStatus) {
/* Succesfully deregistered */
break;
} else if (CPA_STATUS_RETRY != lacStatus) {
icp_atomic_inc
(&lac_session_failed_dereg_count);
break;
}
/*schedule_timout returns the time left for completion if
* this task is set to TASK_INTERRUPTIBLE */
remaining_delay_time_in_jiffies =
dereg_retry_delay_in_jiffies;
while (0 > remaining_delay_time_in_jiffies) {
remaining_delay_time_in_jiffies =
icp_schedule_timeout
(&icp_ocfDrvSymSessInfoListSpinlock,
remaining_delay_time_in_jiffies);
}
DPRINTK
("%s(): Retry %d to deregistrate the session\n",
__FUNCTION__, i);
}
}
/*remove from current list */
ICP_LIST_DEL(tempSessionData, listNode);
/*add to free mem linked list */
ICP_LIST_ADD(tempSessionData,
&icp_ocfDrvGlobalSymListHead_FreeMemList,
listNode);
}
/*EXIT CRITICAL SECTION */
icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock);
/*set back to initial values */
sessionData = NULL;
/*still have a reference in our list! */
tempSessionData = NULL;
/*free memory */
ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData,
&icp_ocfDrvGlobalSymListHead_FreeMemList,
listNode) {
ICP_LIST_DEL(tempSessionData, listNode);
/* Free allocated CpaCySymSessionCtx */
if (NULL != tempSessionData->sessHandle) {
icp_kfree(tempSessionData->sessHandle);
}
memset(tempSessionData, 0, sizeof(struct icp_drvSessionData));
ICP_CACHE_FREE(drvSessionData_zone, tempSessionData);
}
if (0 != icp_atomic_read(&lac_session_failed_dereg_count)) {
DPRINTK("%s(): %d LAC sessions were not deregistered "
"correctly. This is not a clean exit! \n",
__FUNCTION__,
icp_atomic_read(&lac_session_failed_dereg_count));
}
icp_ocfDrvFreeCaches();
icp_ocfDrvDriverId = INVALID_DRIVER_ID;
icp_spin_lock_destroy(&icp_ocfDrvSymSessInfoListSpinlock);
/* Shutdown the Cryptographic component */
lacStatus = cpaCyStopInstance(CPA_INSTANCE_HANDLE_SINGLE);
if (CPA_STATUS_SUCCESS != lacStatus) {
DPRINTK("%s(): Failed to stop instance of the "
"Cryptographic component.(status == %d)\n",
__FUNCTION__, lacStatus);
}
return ICP_MODULE_EXIT_FUNC_RETURN_VAL;
}
/* Name : icp_ocfDrvFreeCaches
*
* Description : This function deregisters all slab caches
*/
static void icp_ocfDrvFreeCaches(void)
{
icp_atomic_set(&icp_ocfDrvIsExiting, 1);
/*Sym Zones */
ICP_CACHE_DESTROY(drvSessionData_zone);
ICP_CACHE_DESTROY(drvOpData_zone);
/*Asym zones */
ICP_CACHE_DESTROY(drvDH_zone);
ICP_CACHE_DESTROY(drvLnModExp_zone);
ICP_CACHE_DESTROY(drvRSADecrypt_zone);
ICP_CACHE_DESTROY(drvRSAPrivateKey_zone);
ICP_CACHE_DESTROY(drvDSARSSignKValue_zone);
ICP_CACHE_DESTROY(drvDSARSSign_zone);
ICP_CACHE_DESTROY(drvDSAVerify_zone);
/*FlatBuffer and BufferList Zones */
ICP_CACHE_DESTROY(drvFlatBuffer_zone);
}
/* Name : icp_ocfDrvDeregRetry
*
* Description : This function will try to farm the session deregistration
* off to a work queue. If it fails, nothing more can be done and it
* returns an error
*/
int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister)
{
struct icp_ocfDrvFreeLacSession *workstore = NULL;
DPRINTK("%s(): Retry - Deregistering session (%p)\n",
__FUNCTION__, sessionToDeregister);
/*make sure the session is not available to be allocated during this
process */
icp_atomic_inc(&lac_session_failed_dereg_count);
/*Farm off to work queue */
workstore =
icp_kmalloc(sizeof(struct icp_ocfDrvFreeLacSession), ICP_M_NOWAIT);
if (NULL == workstore) {
DPRINTK("%s(): unable to free session - no memory available "
"for work queue\n", __FUNCTION__);
return ENOMEM;
}
workstore->sessionToDeregister = sessionToDeregister;
icp_init_work(&(workstore->work),
icp_ocfDrvDeferedFreeLacSessionTaskFn, workstore);
ICP_WORKQUEUE_ENQUEUE(icp_ocfDrvFreeLacSessionWorkQ,
&(workstore->work));
return ICP_OCF_DRV_STATUS_SUCCESS;
}
/* Name : icp_ocfDrvDeferedFreeLacSessionProcess
*
* Description : This function will retry (module input parameter)
* 'num_dereg_retries' times to deregister any symmetric session that recieves a
* CPA_STATUS_RETRY message from the LAC component. This function is run in
* Thread context because it is called from a worker thread
*/
void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg)
{
struct icp_ocfDrvFreeLacSession *workstore = NULL;
CpaCySymSessionCtx sessionToDeregister = NULL;
int i = 0;
int remaining_delay_time_in_jiffies = 0;
CpaStatus lacStatus = CPA_STATUS_SUCCESS;
workstore = (struct icp_ocfDrvFreeLacSession *)arg;
if (NULL == workstore) {
DPRINTK("%s() function called with null parameter \n",
__FUNCTION__);
return;
}
sessionToDeregister = workstore->sessionToDeregister;
icp_kfree(workstore);
/*if exiting, give deregistration one more blast only */
if (icp_atomic_read(&icp_ocfDrvIsExiting) == CPA_TRUE) {
lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE,
sessionToDeregister);
if (lacStatus != CPA_STATUS_SUCCESS) {
DPRINTK("%s() Failed to Dereg LAC session %p "
"during module exit\n", __FUNCTION__,
sessionToDeregister);
return;
}
icp_atomic_dec(&lac_session_failed_dereg_count);
return;
}
for (i = 0; i <= num_dereg_retries; i++) {
lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE,
sessionToDeregister);
if (lacStatus == CPA_STATUS_SUCCESS) {
icp_atomic_dec(&lac_session_failed_dereg_count);
return;
}
if (lacStatus != CPA_STATUS_RETRY) {
DPRINTK("%s() Failed to deregister session - lacStatus "
" = %d", __FUNCTION__, lacStatus);
break;
}
/*schedule_timout returns the time left for completion if this
task is set to TASK_INTERRUPTIBLE */
remaining_delay_time_in_jiffies = dereg_retry_delay_in_jiffies;
while (0 < remaining_delay_time_in_jiffies) {
remaining_delay_time_in_jiffies =
icp_schedule_timeout(NULL,
remaining_delay_time_in_jiffies);
}
}
DPRINTK("%s(): Unable to deregister session\n", __FUNCTION__);
DPRINTK("%s(): Number of unavailable LAC sessions = %d\n", __FUNCTION__,
icp_atomic_read(&lac_session_failed_dereg_count));
}
/* Name : icp_ocfDrvPtrAndLenToFlatBuffer
*
* Description : This function converts a "pointer and length" buffer
* structure to Fredericksburg Flat Buffer (CpaFlatBuffer) format.
*
* This function assumes that the data passed in are valid.
*/
inline void
icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len,
CpaFlatBuffer * pFlatBuffer)
{
pFlatBuffer->pData = pData;
pFlatBuffer->dataLenInBytes = len;
}
/* Name : icp_ocfDrvPtrAndLenToBufferList
*
* Description : This function converts a "pointer and length" buffer
* structure to Fredericksburg Scatter/Gather Buffer (CpaBufferList) format.
*
* This function assumes that the data passed in are valid.
*/
inline void
icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length,
CpaBufferList * pBufferList)
{
pBufferList->numBuffers = 1;
pBufferList->pBuffers->pData = pDataIn;
pBufferList->pBuffers->dataLenInBytes = length;
}
/* Name : icp_ocfDrvBufferListToPtrAndLen
*
* Description : This function converts Fredericksburg Scatter/Gather Buffer
* (CpaBufferList) format to a "pointer and length" buffer structure.
*
* This function assumes that the data passed in are valid.
*/
inline void
icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList,
void **ppDataOut, uint32_t * pLength)
{
*ppDataOut = pBufferList->pBuffers->pData;
*pLength = pBufferList->pBuffers->dataLenInBytes;
}
/* Name : icp_ocfDrvBufferListMemInfo
*
* Description : This function will set the number of flat buffers in
* bufferlist, the size of memory to allocate for the pPrivateMetaData
* member of the CpaBufferList.
*/
int
icp_ocfDrvBufferListMemInfo(uint16_t numBuffers,
struct icp_drvBuffListInfo *buffListInfo)
{
buffListInfo->numBuffers = numBuffers;
if (CPA_STATUS_SUCCESS !=
cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE,
buffListInfo->numBuffers,
&(buffListInfo->metaSize))) {
EPRINTK("%s() Failed to get buffer list meta size.\n",
__FUNCTION__);
return ICP_OCF_DRV_STATUS_FAIL;
}
return ICP_OCF_DRV_STATUS_SUCCESS;
}
/* Name : icp_ocfDrvFreeFlatBuffer
*
* Description : This function will deallocate flat buffer.
*/
inline void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer)
{
if (pFlatBuffer != NULL) {
memset(pFlatBuffer, 0, sizeof(CpaFlatBuffer));
ICP_CACHE_FREE(drvFlatBuffer_zone, pFlatBuffer);
}
}
/* Name : icp_ocfDrvAllocMetaData
*
* Description : This function will allocate memory for the
* pPrivateMetaData member of CpaBufferList.
*/
inline int
icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList,
struct icp_drvOpData *pOpData)
{
Cpa32U metaSize = 0;
if (pBufferList->numBuffers <= ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) {
uint8_t *pOpDataStartAddr = (uint8_t *) pOpData;
if (0 == defBuffListInfo.metaSize) {
pBufferList->pPrivateMetaData = NULL;
return ICP_OCF_DRV_STATUS_SUCCESS;
}
/*
* The meta data allocation has been included as part of the
* op data. It has been pre-allocated in memory just after the
* icp_drvOpData structure.
*/
pBufferList->pPrivateMetaData = (void *)(pOpDataStartAddr +
sizeof(struct
icp_drvOpData));
} else {
if (CPA_STATUS_SUCCESS !=
cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE,
pBufferList->numBuffers,
&metaSize)) {
EPRINTK("%s() Failed to get buffer list meta size.\n",
__FUNCTION__);
return ICP_OCF_DRV_STATUS_FAIL;
}
if (0 == metaSize) {
pBufferList->pPrivateMetaData = NULL;
return ICP_OCF_DRV_STATUS_SUCCESS;
}
pBufferList->pPrivateMetaData =
icp_kmalloc(metaSize, ICP_M_NOWAIT);
}
if (NULL == pBufferList->pPrivateMetaData) {
EPRINTK("%s() Failed to allocate pPrivateMetaData.\n",
__FUNCTION__);
return ICP_OCF_DRV_STATUS_FAIL;
}
return ICP_OCF_DRV_STATUS_SUCCESS;
}
/* Name : icp_ocfDrvFreeMetaData
*
* Description : This function will deallocate pPrivateMetaData memory.
*/
inline void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList)
{
if (NULL == pBufferList->pPrivateMetaData) {
return;
}
/*
* Only free the meta data if the BufferList has more than
* ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS number of buffers.
* Otherwise, the meta data shall be freed when the icp_drvOpData is
* freed.
*/
if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < pBufferList->numBuffers) {
icp_kfree(pBufferList->pPrivateMetaData);
}
}
/* Module declaration, init and exit functions */
ICP_DECLARE_MODULE(icp_ocf, icp_ocfDrvInit, icp_ocfDrvExit);
ICP_MODULE_DESCRIPTION("OCF Driver for Intel Quick Assist crypto acceleration");
ICP_MODULE_VERSION(icp_ocf, ICP_OCF_VER_MJR);
ICP_MODULE_LICENSE("Dual BSD/GPL");
ICP_MODULE_AUTHOR("Intel");
/* Module parameters */
ICP_MODULE_PARAM_INT(icp_ocf, num_dereg_retries,
"Number of times to retry LAC Sym Session Deregistration. "
"Default 10, Max 100");
ICP_MODULE_PARAM_INT(icp_ocf, dereg_retry_delay_in_jiffies, "Delay in jiffies "
"(added to a schedule() function call) before a LAC Sym "
"Session Dereg is retried. Default 10");
ICP_MODULE_PARAM_INT(icp_ocf, max_sessions,
"This sets the maximum number of sessions "
"between OCF and this driver. If this value is set to zero,"
"max session count checking is disabled. Default is zero(0)");
/* Module dependencies */
#define MODULE_MIN_VER 1
#define CRYPTO_MAX_VER 3
#define LAC_MAX_VER 2
ICP_MODULE_DEPEND(icp_ocf, crypto, MODULE_MIN_VER, MODULE_MIN_VER,
CRYPTO_MAX_VER);
ICP_MODULE_DEPEND(icp_ocf, cryptodev, MODULE_MIN_VER, MODULE_MIN_VER,
CRYPTO_MAX_VER);
ICP_MODULE_DEPEND(icp_ocf, icp_crypto, MODULE_MIN_VER, MODULE_MIN_VER,
LAC_MAX_VER);

376
target/linux/generic/files/crypto/ocf/ep80579/icp_ocf.h
View File

@ -1,376 +0,0 @@
/***************************************************************************
*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
* The full GNU General Public License is included in this distribution
* in the file called LICENSE.GPL.
*
* Contact Information:
* Intel Corporation
*
* BSD LICENSE
*
* Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* version: Security.L.1.0.2-229
*
***************************************************************************/
/*
* OCF driver header file for the Intel ICP processor.
*/
#ifndef ICP_OCF_H_
#define ICP_OCF_H_
#include <cpa.h>
#include <cpa_cy_im.h>
#include <cpa_cy_sym.h>
#include <cpa_cy_rand.h>
#include <cpa_cy_dh.h>
#include <cpa_cy_rsa.h>
#include <cpa_cy_ln.h>
#include <cpa_cy_common.h>
#include <cpa_cy_dsa.h>
#include "icp_os.h"
#define NUM_BITS_IN_BYTE (8)
#define NUM_BITS_IN_BYTE_MINUS_ONE (NUM_BITS_IN_BYTE -1)
#define INVALID_DRIVER_ID (-1)
#define RETURN_RAND_NUM_GEN_FAILED (-1)
/*This is the max block cipher initialisation vector*/
#define MAX_IV_LEN_IN_BYTES (20)
/*This is used to check whether the OCF to this driver session limit has
been disabled*/
#define NO_OCF_TO_DRV_MAX_SESSIONS (0)
/*OCF values mapped here*/
#define ICP_SHA1_DIGEST_SIZE_IN_BYTES (SHA1_HASH_LEN)
#define ICP_SHA256_DIGEST_SIZE_IN_BYTES (SHA2_256_HASH_LEN)
#define ICP_SHA384_DIGEST_SIZE_IN_BYTES (SHA2_384_HASH_LEN)
#define ICP_SHA512_DIGEST_SIZE_IN_BYTES (SHA2_512_HASH_LEN)
#define ICP_MD5_DIGEST_SIZE_IN_BYTES (MD5_HASH_LEN)
#define ARC4_COUNTER_LEN (ARC4_BLOCK_LEN)
#define OCF_REGISTRATION_STATUS_SUCCESS (0)
#define OCF_ZERO_FUNCTIONALITY_REGISTERED (0)
#define ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR (0)
#define ICP_OCF_DRV_STATUS_SUCCESS (0)
#define ICP_OCF_DRV_STATUS_FAIL (1)
/*Turn on/off debug options*/
#define ICP_OCF_PRINT_DEBUG_MESSAGES (0)
#define ICP_OCF_PRINT_KERN_ALERT (1)
#define ICP_OCF_PRINT_KERN_ERRS (1)
#if ICP_OCF_PRINT_DEBUG_MESSAGES == 1
#define DPRINTK(args...) \
{ \
ICP_IPRINTK(args); \
}
#else //ICP_OCF_PRINT_DEBUG_MESSAGES == 1
#define DPRINTK(args...)
#endif //ICP_OCF_PRINT_DEBUG_MESSAGES == 1
#if ICP_OCF_PRINT_KERN_ALERT == 1
#define APRINTK(args...) \
{ \
ICP_APRINTK(args); \
}
#else //ICP_OCF_PRINT_KERN_ALERT == 1
#define APRINTK(args...)
#endif //ICP_OCF_PRINT_KERN_ALERT == 1
#if ICP_OCF_PRINT_KERN_ERRS == 1
#define EPRINTK(args...) \
{ \
ICP_EPRINTK(args); \
}
#else //ICP_OCF_PRINT_KERN_ERRS == 1
#define EPRINTK(args...)
#endif //ICP_OCF_PRINT_KERN_ERRS == 1
#define IPRINTK(args...) \
{ \
ICP_IPRINTK(args); \
}
/*DSA Prime Q size in bytes (as defined in the standard) */
#define DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES (20)
#define BITS_TO_BYTES(bytes, bits) \
bytes = (bits + NUM_BITS_IN_BYTE_MINUS_ONE) / NUM_BITS_IN_BYTE
typedef enum {
ICP_OCF_DRV_ALG_CIPHER = 0,
ICP_OCF_DRV_ALG_HASH
} icp_ocf_drv_alg_type_t;
typedef ICP_LIST_HEAD(icp_drvSessionListHead_s,
icp_drvSessionData) icp_drvSessionListHead_t;
/*Values used to derisk chances of performs being called against
deregistered sessions (for which the slab page has been reclaimed)
This is not a fix - since page frames are reclaimed from a slab, one cannot
rely on that memory not being re-used by another app.*/
typedef enum {
ICP_SESSION_INITIALISED = 0x5C5C5C,
ICP_SESSION_RUNNING = 0x005C00,
ICP_SESSION_DEREGISTERED = 0xC5C5C5
} usage_derisk;
/* This struct is required for deferred session
deregistration as a work queue function can
only have one argument*/
struct icp_ocfDrvFreeLacSession {
CpaCySymSessionCtx sessionToDeregister;
icp_workstruct work;
};
/*
This is the OCF<->OCF_DRV session object:
1.listNode
The first member is a listNode. These session objects are added to a linked
list in order to make it easier to remove them all at session exit time.
2.inUse
The second member is used to give the session object state and derisk the
possibility of OCF batch calls executing against a deregistered session (as
described above).
3.sessHandle
The third member is a LAC<->OCF_DRV session handle (initialised with the first
perform request for that session).
4.lacSessCtx
The fourth is the LAC session context. All the parameters for this structure
are only known when the first perform request for this session occurs. That is
why the OCF EP80579 Driver only registers a new LAC session at perform time
*/
struct icp_drvSessionData {
ICP_LIST_ENTRY(icp_drvSessionData) listNode;
usage_derisk inUse;
CpaCySymSessionCtx sessHandle;
CpaCySymSessionSetupData lacSessCtx;
};
/* These are all defined in icp_common.c */
extern icp_atomic_t lac_session_failed_dereg_count;
extern icp_atomic_t icp_ocfDrvIsExiting;
extern icp_atomic_t num_ocf_to_drv_registered_sessions;
extern int32_t icp_ocfDrvDriverId;
extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead;
extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList;
extern icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ;
extern icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock;
/*Slab zones for symettric functionality, instantiated in icp_common.c*/
extern icp_kmem_cache drvSessionData_zone;
extern icp_kmem_cache drvOpData_zone;
/*Slabs zones for asymettric functionality, instantiated in icp_common.c*/
extern icp_kmem_cache drvDH_zone;
extern icp_kmem_cache drvLnModExp_zone;
extern icp_kmem_cache drvRSADecrypt_zone;
extern icp_kmem_cache drvRSAPrivateKey_zone;
extern icp_kmem_cache drvDSARSSign_zone;
extern icp_kmem_cache drvDSARSSignKValue_zone;
extern icp_kmem_cache drvDSAVerify_zone;
/* Module parameters defined in icp_cpmmon.c*/
/* Module parameters - gives the number of times LAC deregistration shall be
re-tried */
extern int num_dereg_retries;
/* Module parameter - gives the delay time in jiffies before a LAC session
shall be attempted to be deregistered again */
extern int dereg_retry_delay_in_jiffies;
/* Module parameter - gives the maximum number of sessions possible between
OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/
extern int max_sessions;
/*Slab zones for flatbuffers and bufferlist*/
extern icp_kmem_cache drvFlatBuffer_zone;
#define ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS (16)
struct icp_drvBuffListInfo {
Cpa16U numBuffers;
Cpa32U metaSize;
Cpa32U metaOffset;
Cpa32U buffListSize;
};
extern struct icp_drvBuffListInfo defBuffListInfo;
/* This struct is used to keep a reference to the relevant node in the list
of sessionData structs, to the buffer type required by OCF and to the OCF
provided crp struct that needs to be returned. All this info is needed in
the callback function.*/
struct icp_drvOpData {
CpaCySymOpData lacOpData;
uint32_t digestSizeInBytes;
struct cryptop *crp;
uint8_t bufferType;
uint8_t ivData[MAX_IV_LEN_IN_BYTES];
uint16_t numBufferListArray;
CpaBufferList srcBuffer;
CpaFlatBuffer bufferListArray[ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS];
CpaBoolean verifyResult;
};
/* Create a new session between OCF and this driver*/
int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sild,
struct cryptoini *cri);
/* Free a session between this driver and the Quick Assist Framework*/
int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid);
/* Defer freeing a Quick Assist session*/
void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg);
/* Process OCF cryptographic request for a symmetric algorithm*/
int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint);
/* Process OCF cryptographic request for an asymmetric algorithm*/
int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint);
/* Populate a buffer with random data*/
int icp_ocfDrvReadRandom(void *arg, uint32_t * buf, int maxwords);
/* Retry Quick Assist session deregistration*/
int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister);
/* Convert an OS scatter gather list to a CPA buffer list*/
int icp_ocfDrvPacketBuffToBufferList(icp_packet_buffer_t * pPacketBuffer,
CpaBufferList * bufferList);
/* Convert a CPA buffer list to an OS scatter gather list*/
int icp_ocfDrvBufferListToPacketBuff(CpaBufferList * bufferList,
icp_packet_buffer_t ** pPacketBuffer);
/* Get the number of buffers in an OS scatter gather list*/
uint16_t icp_ocfDrvGetPacketBuffFrags(icp_packet_buffer_t * pPacketBuffer);
/* Convert a single OS buffer to a CPA Flat Buffer*/
void icp_ocfDrvSinglePacketBuffToFlatBuffer(icp_packet_buffer_t * pPacketBuffer,
CpaFlatBuffer * pFlatBuffer);
/* Add pointer and length to a CPA Flat Buffer structure*/
void icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len,
CpaFlatBuffer * pFlatBuffer);
/* Convert pointer and length values to a CPA buffer list*/
void icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length,
CpaBufferList * pBufferList);
/* Convert a CPA buffer list to pointer and length values*/
void icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList,
void **ppDataOut, uint32_t * pLength);
/* Set the number of flat buffers in bufferlist and the size of memory
to allocate for the pPrivateMetaData member of the CpaBufferList.*/
int icp_ocfDrvBufferListMemInfo(uint16_t numBuffers,
struct icp_drvBuffListInfo *buffListInfo);
/* Find pointer position of the digest within an OS scatter gather list*/
uint8_t *icp_ocfDrvPacketBufferDigestPointerFind(struct icp_drvOpData
*drvOpData,
int offsetInBytes,
uint32_t digestSizeInBytes);
/*This top level function is used to find a pointer to where a digest is
stored/needs to be inserted. */
uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData *drvOpData,
struct cryptodesc *crp_desc);
/* Free a CPA flat buffer*/
void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer);
/* This function will allocate memory for the pPrivateMetaData
member of CpaBufferList. */
int icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList,
struct icp_drvOpData *pOpData);
/* Free data allocated for the pPrivateMetaData
member of CpaBufferList.*/
void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList);
#define ICP_CACHE_CREATE(cache_ID, cache_name) \
icp_kmem_cache_create(cache_ID, sizeof(cache_name),ICP_KERNEL_CACHE_ALIGN,\
ICP_KERNEL_CACHE_NOINIT)
#define ICP_CACHE_FREE(args...) \
icp_kmem_cache_free (args)
#define ICP_CACHE_DESTROY(slab_zone)\
{\
if(NULL != slab_zone){\
icp_kmem_cache_destroy(slab_zone);\
slab_zone = NULL;\
}\
}
#endif
/* ICP_OCF_H_ */

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target/linux/generic/files/crypto/ocf/ep80579/linux_2.6_kernel_space.mk
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###################
# @par
# This file is provided under a dual BSD/GPLv2 license. When using or
# redistributing this file, you may do so under either license.
#
# GPL LICENSE SUMMARY
#
# Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of version 2 of the GNU General Public License as
# published by the Free Software Foundation.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
# The full GNU General Public License is included in this distribution
# in the file called LICENSE.GPL.
#
# Contact Information:
# Intel Corporation
#
# BSD LICENSE
#
# Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# * Neither the name of Intel Corporation nor the names of its
# contributors may be used to endorse or promote products derived
# from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#
# version: Security.L.1.0.130
###################
#specific include directories in kernel space
INCLUDES+=#e.g. -I$(OSAL_DIR)/include \
#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include
EXTRA_CFLAGS += $(INCLUDES) -O2 -Wall
EXTRA_LDFLAGS +=-whole-archive

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# for SGlinux builds
-include $(ROOTDIR)/modules/.config
obj-$(CONFIG_OCF_HIFN) += hifn7751.o
obj-$(CONFIG_OCF_HIFNHIPP) += hifnHIPP.o
obj ?= .
EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/
ifdef TOPDIR
-include $(TOPDIR)/Rules.make
endif

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/* $FreeBSD: src/sys/dev/hifn/hifn7751reg.h,v 1.7 2007/03/21 03:42:49 sam Exp $ */
/* $OpenBSD: hifn7751reg.h,v 1.35 2002/04/08 17:49:42 jason Exp $ */
/*-
* Invertex AEON / Hifn 7751 driver
* Copyright (c) 1999 Invertex Inc. All rights reserved.
* Copyright (c) 1999 Theo de Raadt
* Copyright (c) 2000-2001 Network Security Technologies, Inc.
* http://www.netsec.net
*
* Please send any comments, feedback, bug-fixes, or feature requests to
* software@invertex.com.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Effort sponsored in part by the Defense Advanced Research Projects
* Agency (DARPA) and Air Force Research Laboratory, Air Force
* Materiel Command, USAF, under agreement number F30602-01-2-0537.
*
*/
#ifndef __HIFN_H__
#define __HIFN_H__
/*
* Some PCI configuration space offset defines. The names were made
* identical to the names used by the Linux kernel.
*/
#define HIFN_BAR0 PCIR_BAR(0) /* PUC register map */
#define HIFN_BAR1 PCIR_BAR(1) /* DMA register map */
#define HIFN_TRDY_TIMEOUT 0x40
#define HIFN_RETRY_TIMEOUT 0x41
/*
* PCI vendor and device identifiers
* (the names are preserved from their OpenBSD source).
*/
#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */
#define PCI_PRODUCT_HIFN_7751 0x0005 /* 7751 */
#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */
#define PCI_PRODUCT_HIFN_7811 0x0007 /* 7811 */
#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */
#define PCI_PRODUCT_HIFN_7951 0x0012 /* 7951 */
#define PCI_PRODUCT_HIFN_7955 0x0020 /* 7954/7955 */
#define PCI_PRODUCT_HIFN_7956 0x001d /* 7956 */
#define PCI_VENDOR_INVERTEX 0x14e1 /* Invertex */
#define PCI_PRODUCT_INVERTEX_AEON 0x0005 /* AEON */
#define PCI_VENDOR_NETSEC 0x1660 /* NetSec */
#define PCI_PRODUCT_NETSEC_7751 0x7751 /* 7751 */
/*
* The values below should multiple of 4 -- and be large enough to handle
* any command the driver implements.
*
* MAX_COMMAND = base command + mac command + encrypt command +
* mac-key + rc4-key
* MAX_RESULT = base result + mac result + mac + encrypt result
*
*
*/
#define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260)
#define HIFN_MAX_RESULT (8 + 4 + 20 + 4)
/*
* hifn_desc_t
*
* Holds an individual descriptor for any of the rings.
*/
typedef struct hifn_desc {
volatile u_int32_t l; /* length and status bits */
volatile u_int32_t p;
} hifn_desc_t;
/*
* Masks for the "length" field of struct hifn_desc.
*/
#define HIFN_D_LENGTH 0x0000ffff /* length bit mask */
#define HIFN_D_MASKDONEIRQ 0x02000000 /* mask the done interrupt */
#define HIFN_D_DESTOVER 0x04000000 /* destination overflow */
#define HIFN_D_OVER 0x08000000 /* overflow */
#define HIFN_D_LAST 0x20000000 /* last descriptor in chain */
#define HIFN_D_JUMP 0x40000000 /* jump descriptor */
#define HIFN_D_VALID 0x80000000 /* valid bit */
/*
* Processing Unit Registers (offset from BASEREG0)
*/
#define HIFN_0_PUDATA 0x00 /* Processing Unit Data */
#define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */
#define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */
#define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */
#define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */
#define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */
#define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */
#define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */
#define HIFN_0_PUCTRL2 0x28 /* Processing Unit Control (2nd map) */
#define HIFN_0_MUTE1 0x80
#define HIFN_0_MUTE2 0x90
#define HIFN_0_SPACESIZE 0x100 /* Register space size */
/* Processing Unit Control Register (HIFN_0_PUCTRL) */
#define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */
#define HIFN_PUCTRL_STOP 0x0008 /* stop pu */
#define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */
#define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */
#define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */
/* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */
#define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */
#define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */
#define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
#define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
#define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */
#define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */
#define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */
#define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */
#define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */
#define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */
/* Processing Unit Configuration Register (HIFN_0_PUCNFG) */
#define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */
#define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */
#define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */
#define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */
#define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */
#define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */
#define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */
#define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */
#define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */
#define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */
#define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */
#define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */
#define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */
#define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */
#define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */
#define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */
#define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */
#define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */
#define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */
#define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */
#define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */
#define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */
#define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */
/* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */
#define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */
#define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */
#define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
#define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
#define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */
#define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */
#define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */
#define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */
#define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */
#define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */
/* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */
#define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */
#define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */
#define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
#define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
#define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */
#define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */
#define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */
#define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */
#define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */
#define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */
#define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */
#define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */
#define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */
#define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */
#define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */
#define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */
#define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */
/* FIFO Status Register (HIFN_0_FIFOSTAT) */
#define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */
#define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */
/* FIFO Configuration Register (HIFN_0_FIFOCNFG) */
#define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as this value */
/*
* DMA Interface Registers (offset from BASEREG1)
*/
#define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */
#define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */
#define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */
#define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */
#define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */
#define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */
#define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */
#define HIFN_1_PLL 0x4c /* 7955/7956: PLL config */
#define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */
#define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */
#define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */
#define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */
#define HIFN_1_DMA_CNFG2 0x6c /* 7955/7956: dma config #2 */
#define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */
#define HIFN_1_REVID 0x98 /* Revision ID */
#define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */
#define HIFN_1_PUB_BASE 0x300 /* Public Base Address */
#define HIFN_1_PUB_OPLEN 0x304 /* 7951-compat Public Operand Length */
#define HIFN_1_PUB_OP 0x308 /* 7951-compat Public Operand */
#define HIFN_1_PUB_STATUS 0x30c /* 7951-compat Public Status */
#define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */
#define HIFN_1_RNG_CONFIG 0x314 /* RNG config */
#define HIFN_1_RNG_DATA 0x318 /* RNG data */
#define HIFN_1_PUB_MODE 0x320 /* PK mode */
#define HIFN_1_PUB_FIFO_OPLEN 0x380 /* first element of oplen fifo */
#define HIFN_1_PUB_FIFO_OP 0x384 /* first element of op fifo */
#define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */
#define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */
/* DMA Status and Control Register (HIFN_1_DMA_CSR) */
#define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */
#define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */
#define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */
#define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */
#define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */
#define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */
#define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */
#define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */
#define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */
#define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */
#define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */
#define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */
#define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */
#define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */
#define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */
#define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */
#define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */
#define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */
#define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */
#define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */
#define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */
#define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */
#define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */
#define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */
#define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */
#define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */
#define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */
#define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */
#define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */
#define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */
#define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */
#define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */
#define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */
#define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */
#define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */
#define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */
#define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */
#define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */
/* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */
#define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */
#define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */
#define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */
#define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */
#define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */
#define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */
#define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */
#define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */
#define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */
#define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */
#define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */
#define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */
#define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */
#define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */
#define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */
#define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */
#define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */
#define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */
#define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */
#define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */
#define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */
#define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */
/* DMA Configuration Register (HIFN_1_DMA_CNFG) */
#define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */
#define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */
#define HIFN_DMACNFG_UNLOCK 0x00000800
#define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */
#define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */
#define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */
#define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */
#define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */
/* DMA Configuration Register (HIFN_1_DMA_CNFG2) */
#define HIFN_DMACNFG2_PKSWAP32 (1 << 19) /* swap the OPLEN/OP reg */
#define HIFN_DMACNFG2_PKSWAP8 (1 << 18) /* swap the bits of OPLEN/OP */
#define HIFN_DMACNFG2_BAR0_SWAP32 (1<<17) /* swap the bytes of BAR0 */
#define HIFN_DMACNFG2_BAR1_SWAP8 (1<<16) /* swap the bits of BAR0 */
#define HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT 12
#define HIFN_DMACNFG2_INIT_READ_BURST_SHIFT 8
#define HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT 4
#define HIFN_DMACNFG2_TGT_READ_BURST_SHIFT 0
/* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */
#define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */
/* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */
#define HIFN_7811_RNGCFG_PRE1 0x00000f00 /* first prescalar */
#define HIFN_7811_RNGCFG_OPRE 0x00000080 /* output prescalar */
#define HIFN_7811_RNGCFG_DEFL 0x00000f80 /* 2 words/ 1/100 sec */
/* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */
#define HIFN_7811_RNGSTS_RDY 0x00004000 /* two numbers in FIFO */
#define HIFN_7811_RNGSTS_UFL 0x00001000 /* rng underflow */
/* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */
#define HIFN_MIPSRST_BAR2SIZE 0xffff0000 /* sdram size */
#define HIFN_MIPSRST_GPRAMINIT 0x00008000 /* gpram can be accessed */
#define HIFN_MIPSRST_CRAMINIT 0x00004000 /* ctxram can be accessed */
#define HIFN_MIPSRST_LED2 0x00000400 /* external LED2 */
#define HIFN_MIPSRST_LED1 0x00000200 /* external LED1 */
#define HIFN_MIPSRST_LED0 0x00000100 /* external LED0 */
#define HIFN_MIPSRST_MIPSDIS 0x00000004 /* disable MIPS */
#define HIFN_MIPSRST_MIPSRST 0x00000002 /* warm reset MIPS */
#define HIFN_MIPSRST_MIPSCOLD 0x00000001 /* cold reset MIPS */
/* Public key reset register (HIFN_1_PUB_RESET) */
#define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */
/* Public operation register (HIFN_1_PUB_OP) */
#define HIFN_PUBOP_AOFFSET 0x0000003e /* A offset */
#define HIFN_PUBOP_BOFFSET 0x00000fc0 /* B offset */
#define HIFN_PUBOP_MOFFSET 0x0003f000 /* M offset */
#define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */
#define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */
#define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */
#define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */
#define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */
#define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */
#define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */
#define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */
#define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */
#define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */
#define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */
#define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */
#define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular Red */
#define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular Exp */
/* Public operand length register (HIFN_1_PUB_OPLEN) */
#define HIFN_PUBOPLEN_MODLEN 0x0000007f
#define HIFN_PUBOPLEN_EXPLEN 0x0003ff80
#define HIFN_PUBOPLEN_REDLEN 0x003c0000
/* Public status register (HIFN_1_PUB_STATUS) */
#define HIFN_PUBSTS_DONE 0x00000001 /* operation done */
#define HIFN_PUBSTS_CARRY 0x00000002 /* carry */
#define HIFN_PUBSTS_FIFO_EMPTY 0x00000100 /* fifo empty */
#define HIFN_PUBSTS_FIFO_FULL 0x00000200 /* fifo full */
#define HIFN_PUBSTS_FIFO_OVFL 0x00000400 /* fifo overflow */
#define HIFN_PUBSTS_FIFO_WRITE 0x000f0000 /* fifo write */
#define HIFN_PUBSTS_FIFO_READ 0x0f000000 /* fifo read */
/* Public interrupt enable register (HIFN_1_PUB_IEN) */
#define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */
/* Random number generator config register (HIFN_1_RNG_CONFIG) */
#define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */
/*
* Register offsets in register set 1
*/
#define HIFN_UNLOCK_SECRET1 0xf4
#define HIFN_UNLOCK_SECRET2 0xfc
/*
* PLL config register
*
* This register is present only on 7954/7955/7956 parts. It must be
* programmed according to the bus interface method used by the h/w.
* Note that the parts require a stable clock. Since the PCI clock
* may vary the reference clock must usually be used. To avoid
* overclocking the core logic, setup must be done carefully, refer
* to the driver for details. The exact multiplier required varies
* by part and system configuration; refer to the Hifn documentation.
*/
#define HIFN_PLL_REF_SEL 0x00000001 /* REF/HBI clk selection */
#define HIFN_PLL_BP 0x00000002 /* bypass (used during setup) */
/* bit 2 reserved */
#define HIFN_PLL_PK_CLK_SEL 0x00000008 /* public key clk select */
#define HIFN_PLL_PE_CLK_SEL 0x00000010 /* packet engine clk select */
/* bits 5-9 reserved */
#define HIFN_PLL_MBSET 0x00000400 /* must be set to 1 */
#define HIFN_PLL_ND 0x00003800 /* Fpll_ref multiplier select */
#define HIFN_PLL_ND_SHIFT 11
#define HIFN_PLL_ND_2 0x00000000 /* 2x */
#define HIFN_PLL_ND_4 0x00000800 /* 4x */
#define HIFN_PLL_ND_6 0x00001000 /* 6x */
#define HIFN_PLL_ND_8 0x00001800 /* 8x */
#define HIFN_PLL_ND_10 0x00002000 /* 10x */
#define HIFN_PLL_ND_12 0x00002800 /* 12x */
/* bits 14-15 reserved */
#define HIFN_PLL_IS 0x00010000 /* charge pump current select */
/* bits 17-31 reserved */
/*
* Board configuration specifies only these bits.
*/
#define HIFN_PLL_CONFIG (HIFN_PLL_IS|HIFN_PLL_ND|HIFN_PLL_REF_SEL)
/*
* Public Key Engine Mode Register
*/
#define HIFN_PKMODE_HOSTINVERT (1 << 0) /* HOST INVERT */
#define HIFN_PKMODE_ENHANCED (1 << 1) /* Enable enhanced mode */
/*********************************************************************
* Structs for board commands
*
*********************************************************************/
/*
* Structure to help build up the command data structure.
*/
typedef struct hifn_base_command {
volatile u_int16_t masks;
volatile u_int16_t session_num;
volatile u_int16_t total_source_count;
volatile u_int16_t total_dest_count;
} hifn_base_command_t;
#define HIFN_BASE_CMD_MAC 0x0400
#define HIFN_BASE_CMD_CRYPT 0x0800
#define HIFN_BASE_CMD_DECODE 0x2000
#define HIFN_BASE_CMD_SRCLEN_M 0xc000
#define HIFN_BASE_CMD_SRCLEN_S 14
#define HIFN_BASE_CMD_DSTLEN_M 0x3000
#define HIFN_BASE_CMD_DSTLEN_S 12
#define HIFN_BASE_CMD_LENMASK_HI 0x30000
#define HIFN_BASE_CMD_LENMASK_LO 0x0ffff
/*
* Structure to help build up the command data structure.
*/
typedef struct hifn_crypt_command {
volatile u_int16_t masks;
volatile u_int16_t header_skip;
volatile u_int16_t source_count;
volatile u_int16_t reserved;
} hifn_crypt_command_t;
#define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */
#define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */
#define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */
#define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */
#define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */
#define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */
#define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */
#define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */
#define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */
#define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */
#define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */
#define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */
#define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */
#define HIFN_CRYPT_CMD_SRCLEN_M 0xc000
#define HIFN_CRYPT_CMD_SRCLEN_S 14
#define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */
#define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */
#define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */
#define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */
/*
* Structure to help build up the command data structure.
*/
typedef struct hifn_mac_command {
volatile u_int16_t masks;
volatile u_int16_t header_skip;
volatile u_int16_t source_count;
volatile u_int16_t reserved;
} hifn_mac_command_t;
#define HIFN_MAC_CMD_ALG_MASK 0x0001
#define HIFN_MAC_CMD_ALG_SHA1 0x0000
#define HIFN_MAC_CMD_ALG_MD5 0x0001
#define HIFN_MAC_CMD_MODE_MASK 0x000c
#define HIFN_MAC_CMD_MODE_HMAC 0x0000
#define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004
#define HIFN_MAC_CMD_MODE_HASH 0x0008
#define HIFN_MAC_CMD_MODE_FULL 0x0004
#define HIFN_MAC_CMD_TRUNC 0x0010
#define HIFN_MAC_CMD_RESULT 0x0020
#define HIFN_MAC_CMD_APPEND 0x0040
#define HIFN_MAC_CMD_SRCLEN_M 0xc000
#define HIFN_MAC_CMD_SRCLEN_S 14
/*
* MAC POS IPsec initiates authentication after encryption on encodes
* and before decryption on decodes.
*/
#define HIFN_MAC_CMD_POS_IPSEC 0x0200
#define HIFN_MAC_CMD_NEW_KEY 0x0800
/*
* The poll frequency and poll scalar defines are unshifted values used
* to set fields in the DMA Configuration Register.
*/
#ifndef HIFN_POLL_FREQUENCY
#define HIFN_POLL_FREQUENCY 0x1
#endif
#ifndef HIFN_POLL_SCALAR
#define HIFN_POLL_SCALAR 0x0
#endif
#define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */
#define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */
#endif /* __HIFN_H__ */

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target/linux/generic/files/crypto/ocf/hifn/hifn7751var.h
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@ -1,368 +0,0 @@
/* $FreeBSD: src/sys/dev/hifn/hifn7751var.h,v 1.9 2007/03/21 03:42:49 sam Exp $ */
/* $OpenBSD: hifn7751var.h,v 1.42 2002/04/08 17:49:42 jason Exp $ */
/*-
* Invertex AEON / Hifn 7751 driver
* Copyright (c) 1999 Invertex Inc. All rights reserved.
* Copyright (c) 1999 Theo de Raadt
* Copyright (c) 2000-2001 Network Security Technologies, Inc.
* http://www.netsec.net
*
* Please send any comments, feedback, bug-fixes, or feature requests to
* software@invertex.com.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Effort sponsored in part by the Defense Advanced Research Projects
* Agency (DARPA) and Air Force Research Laboratory, Air Force
* Materiel Command, USAF, under agreement number F30602-01-2-0537.
*
*/
#ifndef __HIFN7751VAR_H__
#define __HIFN7751VAR_H__
#ifdef __KERNEL__
/*
* Some configurable values for the driver. By default command+result
* descriptor rings are the same size. The src+dst descriptor rings
* are sized at 3.5x the number of potential commands. Slower parts
* (e.g. 7951) tend to run out of src descriptors; faster parts (7811)
* src+cmd/result descriptors. It's not clear that increasing the size
* of the descriptor rings helps performance significantly as other
* factors tend to come into play (e.g. copying misaligned packets).
*/
#define HIFN_D_CMD_RSIZE 24 /* command descriptors */
#define HIFN_D_SRC_RSIZE ((HIFN_D_CMD_RSIZE * 7) / 2) /* source descriptors */
#define HIFN_D_RES_RSIZE HIFN_D_CMD_RSIZE /* result descriptors */
#define HIFN_D_DST_RSIZE HIFN_D_SRC_RSIZE /* destination descriptors */
/*
* Length values for cryptography
*/
#define HIFN_DES_KEY_LENGTH 8
#define HIFN_3DES_KEY_LENGTH 24
#define HIFN_MAX_CRYPT_KEY_LENGTH HIFN_3DES_KEY_LENGTH
#define HIFN_IV_LENGTH 8
#define HIFN_AES_IV_LENGTH 16
#define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH
/*
* Length values for authentication
*/
#define HIFN_MAC_KEY_LENGTH 64
#define HIFN_MD5_LENGTH 16
#define HIFN_SHA1_LENGTH 20
#define HIFN_MAC_TRUNC_LENGTH 12
#define MAX_SCATTER 64
/*
* Data structure to hold all 4 rings and any other ring related data.
*/
struct hifn_dma {
/*
* Descriptor rings. We add +1 to the size to accomidate the
* jump descriptor.
*/
struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1];
struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1];
struct hifn_desc dstr[HIFN_D_DST_RSIZE+1];
struct hifn_desc resr[HIFN_D_RES_RSIZE+1];
struct hifn_command *hifn_commands[HIFN_D_RES_RSIZE];
u_char command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND];
u_char result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT];
u_int32_t slop[HIFN_D_CMD_RSIZE];
u_int64_t test_src, test_dst;
/*
* Our current positions for insertion and removal from the desriptor
* rings.
*/
int cmdi, srci, dsti, resi;
volatile int cmdu, srcu, dstu, resu;
int cmdk, srck, dstk, resk;
};
struct hifn_session {
int hs_used;
int hs_mlen;
};
#define HIFN_RING_SYNC(sc, r, i, f) \
/* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */
#define HIFN_CMDR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), cmdr, (i), (f))
#define HIFN_RESR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), resr, (i), (f))
#define HIFN_SRCR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), srcr, (i), (f))
#define HIFN_DSTR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), dstr, (i), (f))
#define HIFN_CMD_SYNC(sc, i, f) \
/* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */
#define HIFN_RES_SYNC(sc, i, f) \
/* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */
typedef int bus_size_t;
/*
* Holds data specific to a single HIFN board.
*/
struct hifn_softc {
softc_device_decl sc_dev;
struct pci_dev *sc_pcidev; /* PCI device pointer */
spinlock_t sc_mtx; /* per-instance lock */
int sc_num; /* for multiple devs */
ocf_iomem_t sc_bar0;
bus_size_t sc_bar0_lastreg;/* bar0 last reg written */
ocf_iomem_t sc_bar1;
bus_size_t sc_bar1_lastreg;/* bar1 last reg written */
int sc_irq;
u_int32_t sc_dmaier;
u_int32_t sc_drammodel; /* 1=dram, 0=sram */
u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */
struct hifn_dma *sc_dma;
dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */
int sc_dmansegs;
int32_t sc_cid;
int sc_maxses;
int sc_nsessions;
struct hifn_session *sc_sessions;
int sc_ramsize;
int sc_flags;
#define HIFN_HAS_RNG 0x1 /* includes random number generator */
#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */
#define HIFN_HAS_AES 0x4 /* includes AES support */
#define HIFN_IS_7811 0x8 /* Hifn 7811 part */
#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */
struct timer_list sc_tickto; /* for managing DMA */
int sc_rngfirst;
int sc_rnghz; /* RNG polling frequency */
int sc_c_busy; /* command ring busy */
int sc_s_busy; /* source data ring busy */
int sc_d_busy; /* destination data ring busy */
int sc_r_busy; /* result ring busy */
int sc_active; /* for initial countdown */
int sc_needwakeup; /* ops q'd wating on resources */
int sc_curbatch; /* # ops submitted w/o int */
int sc_suspended;
#ifdef HIFN_VULCANDEV
struct cdev *sc_pkdev;
#endif
};
#define HIFN_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags)
#define HIFN_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags)
/*
* hifn_command_t
*
* This is the control structure used to pass commands to hifn_encrypt().
*
* flags
* -----
* Flags is the bitwise "or" values for command configuration. A single
* encrypt direction needs to be set:
*
* HIFN_ENCODE or HIFN_DECODE
*
* To use cryptography, a single crypto algorithm must be included:
*
* HIFN_CRYPT_3DES or HIFN_CRYPT_DES
*
* To use authentication is used, a single MAC algorithm must be included:
*
* HIFN_MAC_MD5 or HIFN_MAC_SHA1
*
* By default MD5 uses a 16 byte hash and SHA-1 uses a 20 byte hash.
* If the value below is set, hash values are truncated or assumed
* truncated to 12 bytes:
*
* HIFN_MAC_TRUNC
*
* Keys for encryption and authentication can be sent as part of a command,
* or the last key value used with a particular session can be retrieved
* and used again if either of these flags are not specified.
*
* HIFN_CRYPT_NEW_KEY, HIFN_MAC_NEW_KEY
*
* session_num
* -----------
* A number between 0 and 2048 (for DRAM models) or a number between
* 0 and 768 (for SRAM models). Those who don't want to use session
* numbers should leave value at zero and send a new crypt key and/or
* new MAC key on every command. If you use session numbers and
* don't send a key with a command, the last key sent for that same
* session number will be used.
*
* Warning: Using session numbers and multiboard at the same time
* is currently broken.
*
* mbuf
* ----
* Either fill in the mbuf pointer and npa=0 or
* fill packp[] and packl[] and set npa to > 0
*
* mac_header_skip
* ---------------
* The number of bytes of the source_buf that are skipped over before
* authentication begins. This must be a number between 0 and 2^16-1
* and can be used by IPsec implementers to skip over IP headers.
* *** Value ignored if authentication not used ***
*
* crypt_header_skip
* -----------------
* The number of bytes of the source_buf that are skipped over before
* the cryptographic operation begins. This must be a number between 0
* and 2^16-1. For IPsec, this number will always be 8 bytes larger
* than the auth_header_skip (to skip over the ESP header).
* *** Value ignored if cryptography not used ***
*
*/
struct hifn_operand {
union {
struct sk_buff *skb;
struct uio *io;
unsigned char *buf;
} u;
void *map;
bus_size_t mapsize;
int nsegs;
struct {
dma_addr_t ds_addr;
int ds_len;
} segs[MAX_SCATTER];
};
struct hifn_command {
u_int16_t session_num;
u_int16_t base_masks, cry_masks, mac_masks;
u_int8_t iv[HIFN_MAX_IV_LENGTH], *ck, mac[HIFN_MAC_KEY_LENGTH];
int cklen;
int sloplen, slopidx;
struct hifn_operand src;
struct hifn_operand dst;
struct hifn_softc *softc;
struct cryptop *crp;
struct cryptodesc *enccrd, *maccrd;
};
#define src_skb src.u.skb
#define src_io src.u.io
#define src_map src.map
#define src_mapsize src.mapsize
#define src_segs src.segs
#define src_nsegs src.nsegs
#define src_buf src.u.buf
#define dst_skb dst.u.skb
#define dst_io dst.u.io
#define dst_map dst.map
#define dst_mapsize dst.mapsize
#define dst_segs dst.segs
#define dst_nsegs dst.nsegs
#define dst_buf dst.u.buf
/*
* Return values for hifn_crypto()
*/
#define HIFN_CRYPTO_SUCCESS 0
#define HIFN_CRYPTO_BAD_INPUT (-1)
#define HIFN_CRYPTO_RINGS_FULL (-2)
/**************************************************************************
*
* Function: hifn_crypto
*
* Purpose: Called by external drivers to begin an encryption on the
* HIFN board.
*
* Blocking/Non-blocking Issues
* ============================
* The driver cannot block in hifn_crypto (no calls to tsleep) currently.
* hifn_crypto() returns HIFN_CRYPTO_RINGS_FULL if there is not enough
* room in any of the rings for the request to proceed.
*
* Return Values
* =============
* 0 for success, negative values on error
*
* Defines for negative error codes are:
*
* HIFN_CRYPTO_BAD_INPUT : The passed in command had invalid settings.
* HIFN_CRYPTO_RINGS_FULL : All DMA rings were full and non-blocking
* behaviour was requested.
*
*************************************************************************/
/*
* Convert back and forth from 'sid' to 'card' and 'session'
*/
#define HIFN_CARD(sid) (((sid) & 0xf0000000) >> 28)
#define HIFN_SESSION(sid) ((sid) & 0x000007ff)
#define HIFN_SID(crd,ses) (((crd) << 28) | ((ses) & 0x7ff))
#endif /* _KERNEL */
struct hifn_stats {
u_int64_t hst_ibytes;
u_int64_t hst_obytes;
u_int32_t hst_ipackets;
u_int32_t hst_opackets;
u_int32_t hst_invalid;
u_int32_t hst_nomem; /* malloc or one of hst_nomem_* */
u_int32_t hst_abort;
u_int32_t hst_noirq; /* IRQ for no reason */
u_int32_t hst_totbatch; /* ops submitted w/o interrupt */
u_int32_t hst_maxbatch; /* max ops submitted together */
u_int32_t hst_unaligned; /* unaligned src caused copy */
/*
* The following divides hst_nomem into more specific buckets.
*/
u_int32_t hst_nomem_map; /* bus_dmamap_create failed */
u_int32_t hst_nomem_load; /* bus_dmamap_load_* failed */
u_int32_t hst_nomem_mbuf; /* MGET* failed */
u_int32_t hst_nomem_mcl; /* MCLGET* failed */
u_int32_t hst_nomem_cr; /* out of command/result descriptor */
u_int32_t hst_nomem_sd; /* out of src/dst descriptors */
};
#endif /* __HIFN7751VAR_H__ */

421
target/linux/generic/files/crypto/ocf/hifn/hifnHIPP.c
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@ -1,421 +0,0 @@
/*-
* Driver for Hifn HIPP-I/II chipset
* Copyright (c) 2006 Michael Richardson <mcr@xelerance.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Effort sponsored by Hifn Inc.
*
*/
/*
* Driver for various Hifn encryption processors.
*/
#include <linux/version.h>
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED)
#include <linux/config.h>
#endif
#include <linux/module.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/wait.h>
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/random.h>
#include <linux/skbuff.h>
#include <linux/uio.h>
#include <linux/sysfs.h>
#include <linux/miscdevice.h>
#include <asm/io.h>
#include <cryptodev.h>
#include "hifnHIPPreg.h"
#include "hifnHIPPvar.h"
#if 1
#define DPRINTF(a...) if (hipp_debug) { \
printk("%s: ", sc ? \
device_get_nameunit(sc->sc_dev) : "hifn"); \
printk(a); \
} else
#else
#define DPRINTF(a...)
#endif
typedef int bus_size_t;
static inline int
pci_get_revid(struct pci_dev *dev)
{
u8 rid = 0;
pci_read_config_byte(dev, PCI_REVISION_ID, &rid);
return rid;
}
#define debug hipp_debug
int hipp_debug = 0;
module_param(hipp_debug, int, 0644);
MODULE_PARM_DESC(hipp_debug, "Enable debug");
int hipp_maxbatch = 1;
module_param(hipp_maxbatch, int, 0644);
MODULE_PARM_DESC(hipp_maxbatch, "max ops to batch w/o interrupt");
static int hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent);
static void hipp_remove(struct pci_dev *dev);
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19)
static irqreturn_t hipp_intr(int irq, void *arg);
#else
static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs);
#endif
static int hipp_num_chips = 0;
static struct hipp_softc *hipp_chip_idx[HIPP_MAX_CHIPS];
static int hipp_newsession(device_t, u_int32_t *, struct cryptoini *);
static int hipp_freesession(device_t, u_int64_t);
static int hipp_process(device_t, struct cryptop *, int);
static device_method_t hipp_methods = {
/* crypto device methods */
DEVMETHOD(cryptodev_newsession, hipp_newsession),
DEVMETHOD(cryptodev_freesession,hipp_freesession),
DEVMETHOD(cryptodev_process, hipp_process),
};
static __inline u_int32_t
READ_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg)
{
u_int32_t v = readl(sc->sc_bar[barno] + reg);
//sc->sc_bar0_lastreg = (bus_size_t) -1;
return (v);
}
static __inline void
WRITE_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg, u_int32_t val)
{
writel(val, sc->sc_bar[barno] + reg);
}
#define READ_REG_0(sc, reg) READ_REG(sc, 0, reg)
#define WRITE_REG_0(sc, reg, val) WRITE_REG(sc,0, reg, val)
#define READ_REG_1(sc, reg) READ_REG(sc, 1, reg)
#define WRITE_REG_1(sc, reg, val) WRITE_REG(sc,1, reg, val)
static int
hipp_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri)
{
return EINVAL;
}
static int
hipp_freesession(device_t dev, u_int64_t tid)
{
return EINVAL;
}
static int
hipp_process(device_t dev, struct cryptop *crp, int hint)
{
return EINVAL;
}
static const char*
hipp_partname(struct hipp_softc *sc, char buf[128], size_t blen)
{
char *n = NULL;
switch (pci_get_vendor(sc->sc_pcidev)) {
case PCI_VENDOR_HIFN:
switch (pci_get_device(sc->sc_pcidev)) {
case PCI_PRODUCT_HIFN_7855: n = "Hifn 7855";
case PCI_PRODUCT_HIFN_8155: n = "Hifn 8155";
case PCI_PRODUCT_HIFN_6500: n = "Hifn 6500";
}
}
if(n==NULL) {
snprintf(buf, blen, "VID=%02x,PID=%02x",
pci_get_vendor(sc->sc_pcidev),
pci_get_device(sc->sc_pcidev));
} else {
buf[0]='\0';
strncat(buf, n, blen);
}
return buf;
}
struct hipp_fs_entry {
struct attribute attr;
/* other stuff */
};
static ssize_t
cryptoid_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct hipp_softc *sc;
sc = pci_get_drvdata(to_pci_dev (dev));
return sprintf (buf, "%d\n", sc->sc_cid);
}
struct device_attribute hipp_dev_cryptoid = __ATTR_RO(cryptoid);
/*
* Attach an interface that successfully probed.
*/
static int
hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent)
{
struct hipp_softc *sc = NULL;
int i;
//char rbase;
//u_int16_t ena;
int rev;
//int rseg;
int rc;
DPRINTF("%s()\n", __FUNCTION__);
if (pci_enable_device(dev) < 0)
return(-ENODEV);
if (pci_set_mwi(dev))
return(-ENODEV);
if (!dev->irq) {
printk("hifn: found device with no IRQ assigned. check BIOS settings!");
pci_disable_device(dev);
return(-ENODEV);
}
sc = (struct hipp_softc *) kmalloc(sizeof(*sc), GFP_KERNEL);
if (!sc)
return(-ENOMEM);
memset(sc, 0, sizeof(*sc));
softc_device_init(sc, "hifn-hipp", hipp_num_chips, hipp_methods);
sc->sc_pcidev = dev;
sc->sc_irq = -1;
sc->sc_cid = -1;
sc->sc_num = hipp_num_chips++;
if (sc->sc_num < HIPP_MAX_CHIPS)
hipp_chip_idx[sc->sc_num] = sc;
pci_set_drvdata(sc->sc_pcidev, sc);
spin_lock_init(&sc->sc_mtx);
/*
* Setup PCI resources.
* The READ_REG_0, WRITE_REG_0, READ_REG_1,
* and WRITE_REG_1 macros throughout the driver are used
* to permit better debugging.
*/
for(i=0; i<4; i++) {
unsigned long mem_start, mem_len;
mem_start = pci_resource_start(sc->sc_pcidev, i);
mem_len = pci_resource_len(sc->sc_pcidev, i);
sc->sc_barphy[i] = (caddr_t)mem_start;
sc->sc_bar[i] = (ocf_iomem_t) ioremap(mem_start, mem_len);
if (!sc->sc_bar[i]) {
device_printf(sc->sc_dev, "cannot map bar%d register space\n", i);
goto fail;
}
}
//hipp_reset_board(sc, 0);
pci_set_master(sc->sc_pcidev);
/*
* Arrange the interrupt line.
*/
rc = request_irq(dev->irq, hipp_intr, IRQF_SHARED, "hifn", sc);
if (rc) {
device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc);
goto fail;
}
sc->sc_irq = dev->irq;
rev = READ_REG_1(sc, HIPP_1_REVID) & 0xffff;
{
char b[32];
device_printf(sc->sc_dev, "%s, rev %u",
hipp_partname(sc, b, sizeof(b)), rev);
}
#if 0
if (sc->sc_flags & HIFN_IS_7956)
printf(", pll=0x%x<%s clk, %ux mult>",
sc->sc_pllconfig,
sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci",
2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11));
#endif
printf("\n");
sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE);
if (sc->sc_cid < 0) {
device_printf(sc->sc_dev, "could not get crypto driver id\n");
goto fail;
}
#if 0 /* cannot work with a non-GPL module */
/* make a sysfs entry to let the world know what entry we got */
sysfs_create_file(&sc->sc_pcidev->dev.kobj, &hipp_dev_cryptoid.attr);
#endif
#if 0
init_timer(&sc->sc_tickto);
sc->sc_tickto.function = hifn_tick;
sc->sc_tickto.data = (unsigned long) sc->sc_num;
mod_timer(&sc->sc_tickto, jiffies + HZ);
#endif
#if 0 /* no code here yet ?? */
crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
#endif
return (0);
fail:
if (sc->sc_cid >= 0)
crypto_unregister_all(sc->sc_cid);
if (sc->sc_irq != -1)
free_irq(sc->sc_irq, sc);
#if 0
if (sc->sc_dma) {
/* Turn off DMA polling */
WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
pci_free_consistent(sc->sc_pcidev,
sizeof(*sc->sc_dma),
sc->sc_dma, sc->sc_dma_physaddr);
}
#endif
kfree(sc);
return (-ENXIO);
}
/*
* Detach an interface that successfully probed.
*/
static void
hipp_remove(struct pci_dev *dev)
{
struct hipp_softc *sc = pci_get_drvdata(dev);
unsigned long l_flags;
DPRINTF("%s()\n", __FUNCTION__);
/* disable interrupts */
HIPP_LOCK(sc);
#if 0
WRITE_REG_1(sc, HIFN_1_DMA_IER, 0);
HIFN_UNLOCK(sc);
/*XXX other resources */
del_timer_sync(&sc->sc_tickto);
/* Turn off DMA polling */
WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
#endif
crypto_unregister_all(sc->sc_cid);
free_irq(sc->sc_irq, sc);
#if 0
pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma),
sc->sc_dma, sc->sc_dma_physaddr);
#endif
}
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19)
static irqreturn_t hipp_intr(int irq, void *arg)
#else
static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs)
#endif
{
struct hipp_softc *sc = arg;
sc = sc; /* shut up compiler */
return IRQ_HANDLED;
}
static struct pci_device_id hipp_pci_tbl[] = {
{ PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7855,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
{ PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_8155,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
{ 0 }, /* terminating entry */
};
MODULE_DEVICE_TABLE(pci, hipp_pci_tbl);
static struct pci_driver hipp_driver = {
.name = "hipp",
.id_table = hipp_pci_tbl,
.probe = hipp_probe,
.remove = hipp_remove,
/* add PM stuff here one day */
};
static int __init hipp_init (void)
{
struct hipp_softc *sc = NULL;
int rc;
DPRINTF("%s(%p)\n", __FUNCTION__, hipp_init);
rc = pci_register_driver(&hipp_driver);
pci_register_driver_compat(&hipp_driver, rc);
return rc;
}
static void __exit hipp_exit (void)
{
pci_unregister_driver(&hipp_driver);
}
module_init(hipp_init);
module_exit(hipp_exit);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_AUTHOR("Michael Richardson <mcr@xelerance.com>");
MODULE_DESCRIPTION("OCF driver for hifn HIPP-I/II PCI crypto devices");

46
target/linux/generic/files/crypto/ocf/hifn/hifnHIPPreg.h
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@ -1,46 +0,0 @@
/*-
* Hifn HIPP-I/HIPP-II (7855/8155) driver.
* Copyright (c) 2006 Michael Richardson <mcr@xelerance.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Effort sponsored by Hifn inc.
*
*/
#ifndef __HIFNHIPP_H__
#define __HIFNHIPP_H__
/*
* PCI vendor and device identifiers
*/
#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */
#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */
#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */
#define PCI_PRODUCT_HIFN_8155 0x999 /* XXX 8155 */
#define HIPP_1_REVID 0x01 /* BOGUS */
#endif /* __HIPP_H__ */

93
target/linux/generic/files/crypto/ocf/hifn/hifnHIPPvar.h
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@ -1,93 +0,0 @@
/*
* Hifn HIPP-I/HIPP-II (7855/8155) driver.
* Copyright (c) 2006 Michael Richardson <mcr@xelerance.com> *
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Effort sponsored by Hifn inc.
*
*/
#ifndef __HIFNHIPPVAR_H__
#define __HIFNHIPPVAR_H__
#define HIPP_MAX_CHIPS 8
/*
* Holds data specific to a single Hifn HIPP-I board.
*/
struct hipp_softc {
softc_device_decl sc_dev;
struct pci_dev *sc_pcidev; /* device backpointer */
ocf_iomem_t sc_bar[5];
caddr_t sc_barphy[5]; /* physical address */
int sc_num; /* for multiple devs */
spinlock_t sc_mtx; /* per-instance lock */
int32_t sc_cid;
int sc_irq;
#if 0
u_int32_t sc_dmaier;
u_int32_t sc_drammodel; /* 1=dram, 0=sram */
u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */
struct hifn_dma *sc_dma;
dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */
int sc_dmansegs;
int sc_maxses;
int sc_nsessions;
struct hifn_session *sc_sessions;
int sc_ramsize;
int sc_flags;
#define HIFN_HAS_RNG 0x1 /* includes random number generator */
#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */
#define HIFN_HAS_AES 0x4 /* includes AES support */
#define HIFN_IS_7811 0x8 /* Hifn 7811 part */
#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */
struct timer_list sc_tickto; /* for managing DMA */
int sc_rngfirst;
int sc_rnghz; /* RNG polling frequency */
int sc_c_busy; /* command ring busy */
int sc_s_busy; /* source data ring busy */
int sc_d_busy; /* destination data ring busy */
int sc_r_busy; /* result ring busy */
int sc_active; /* for initial countdown */
int sc_needwakeup; /* ops q'd wating on resources */
int sc_curbatch; /* # ops submitted w/o int */
int sc_suspended;
struct miscdevice sc_miscdev;
#endif
};
#define HIPP_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags)
#define HIPP_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags)
#endif /* __HIFNHIPPVAR_H__ */

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target/linux/generic/files/crypto/ocf/ixp4xx/Makefile
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@ -1,104 +0,0 @@
# for SGlinux builds
-include $(ROOTDIR)/modules/.config
#
# You will need to point this at your Intel ixp425 includes, this portion
# of the Makefile only really works under SGLinux with the appropriate libs
# installed. They can be downloaded from http://www.snapgear.org/
#
ifeq ($(CONFIG_CPU_IXP46X),y)
IXPLATFORM = ixp46X
else
ifeq ($(CONFIG_CPU_IXP43X),y)
IXPLATFORM = ixp43X
else
IXPLATFORM = ixp42X
endif
endif
ifdef CONFIG_IXP400_LIB_2_4
IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp400_xscale_sw
OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp_osal
endif
ifdef CONFIG_IXP400_LIB_2_1
IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp400_xscale_sw
OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp_osal
endif
ifdef CONFIG_IXP400_LIB_2_0
IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp400_xscale_sw
OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp_osal
endif
ifdef IX_XSCALE_SW
ifdef CONFIG_IXP400_LIB_2_4
IXP_CFLAGS = \
-I$(ROOTDIR)/. \
-I$(IX_XSCALE_SW)/src/include \
-I$(OSAL_DIR)/common/include/ \
-I$(OSAL_DIR)/common/include/modules/ \
-I$(OSAL_DIR)/common/include/modules/ddk/ \
-I$(OSAL_DIR)/common/include/modules/bufferMgt/ \
-I$(OSAL_DIR)/common/include/modules/ioMem/ \
-I$(OSAL_DIR)/common/os/linux/include/ \
-I$(OSAL_DIR)/common/os/linux/include/core/ \
-I$(OSAL_DIR)/common/os/linux/include/modules/ \
-I$(OSAL_DIR)/common/os/linux/include/modules/ddk/ \
-I$(OSAL_DIR)/common/os/linux/include/modules/bufferMgt/ \
-I$(OSAL_DIR)/common/os/linux/include/modules/ioMem/ \
-I$(OSAL_DIR)/platforms/$(IXPLATFORM)/include/ \
-I$(OSAL_DIR)/platforms/$(IXPLATFORM)/os/linux/include/ \
-DENABLE_IOMEM -DENABLE_BUFFERMGT -DENABLE_DDK \
-DUSE_IXP4XX_CRYPTO
else
IXP_CFLAGS = \
-I$(ROOTDIR)/. \
-I$(IX_XSCALE_SW)/src/include \
-I$(OSAL_DIR)/ \
-I$(OSAL_DIR)/os/linux/include/ \
-I$(OSAL_DIR)/os/linux/include/modules/ \
-I$(OSAL_DIR)/os/linux/include/modules/ioMem/ \
-I$(OSAL_DIR)/os/linux/include/modules/bufferMgt/ \
-I$(OSAL_DIR)/os/linux/include/core/ \
-I$(OSAL_DIR)/os/linux/include/platforms/ \
-I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ \
-I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp425 \
-I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp465 \
-I$(OSAL_DIR)/os/linux/include/core/ \
-I$(OSAL_DIR)/include/ \
-I$(OSAL_DIR)/include/modules/ \
-I$(OSAL_DIR)/include/modules/bufferMgt/ \
-I$(OSAL_DIR)/include/modules/ioMem/ \
-I$(OSAL_DIR)/include/platforms/ \
-I$(OSAL_DIR)/include/platforms/ixp400/ \
-DUSE_IXP4XX_CRYPTO
endif
endif
ifdef CONFIG_IXP400_LIB_1_4
IXP_CFLAGS = \
-I$(ROOTDIR)/. \
-I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/include \
-I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/linux \
-DUSE_IXP4XX_CRYPTO
endif
ifndef IXPDIR
IXPDIR = ixp-version-is-not-supported
endif
ifeq ($(CONFIG_CPU_IXP46X),y)
IXP_CFLAGS += -D__ixp46X
else
ifeq ($(CONFIG_CPU_IXP43X),y)
IXP_CFLAGS += -D__ixp43X
else
IXP_CFLAGS += -D__ixp42X
endif
endif
obj-$(CONFIG_OCF_IXP4XX) += ixp4xx.o
obj ?= .
EXTRA_CFLAGS += $(IXP_CFLAGS) -I$(obj)/.. -I$(obj)/.
ifdef TOPDIR
-include $(TOPDIR)/Rules.make
endif

1339
target/linux/generic/files/crypto/ocf/ixp4xx/ixp4xx.c
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19
target/linux/generic/files/crypto/ocf/kirkwood/Makefile
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# for SGlinux builds
-include $(ROOTDIR)/modules/.config
obj-$(CONFIG_OCF_KIRKWOOD) += mv_cesa.o
mv_cesa-y := cesa/mvCesa.o cesa/mvLru.o cesa/mvMD5.o cesa/mvSHA1.o cesa/AES/mvAesAlg.o cesa/AES/mvAesApi.o cesa/mvCesaDebug.o cesa_ocf_drv.o
# Extra objects required by the CESA driver
mv_cesa-y += mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.o mvHal/kw_family/boardEnv/mvBoardEnvLib.o mvHal/mv_hal/twsi/mvTwsi.o mvHal/kw_family/ctrlEnv/sys/mvCpuIf.o mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.o mvHal/kw_family/ctrlEnv/sys/mvSysDram.o mvHal/linux_oss/mvOs.o mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.o mvHal/mv_hal/gpp/mvGpp.o mvHal/kw_family/ctrlEnv/sys/mvSysPex.o mvHal/mv_hal/pex/mvPex.o mvHal/kw_family/boardEnv/mvBoardEnvSpec.o mvHal/common/mvCommon.o mvHal/common/mvDebug.o mvHal/kw_family/ctrlEnv/sys/mvSysCesa.o
ifdef src
EXTRA_CFLAGS += -I$(src)/.. -I$(src)/cesa -I$(src)/mvHal -I$(src)/mvHal/common -I$(src)/mvHal/kw_family -I$(src)/mvHal/mv_hal -I$(src)/mvHal/linux_oss -I$(src)
endif
EXTRA_CFLAGS += -DMV_LINUX -DMV_CPU_LE -DMV_ARM -DMV_INCLUDE_CESA -DMV_INCLUDE_PEX -DMV_CACHE_COHERENCY=3
ifdef TOPDIR
-include $(TOPDIR)/Rules.make
endif

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target/linux/generic/files/crypto/ocf/kirkwood/cesa/AES/mvAes.h
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/* mvAes.h v2.0 August '99
* Reference ANSI C code
*/
/* AES Cipher header file for ANSI C Submissions
Lawrence E. Bassham III
Computer Security Division
National Institute of Standards and Technology
April 15, 1998
This sample is to assist implementers developing to the Cryptographic
API Profile for AES Candidate Algorithm Submissions. Please consult this
document as a cross-reference.
ANY CHANGES, WHERE APPROPRIATE, TO INFORMATION PROVIDED IN THIS FILE
MUST BE DOCUMENTED. CHANGES ARE ONLY APPROPRIATE WHERE SPECIFIED WITH
THE STRING "CHANGE POSSIBLE". FUNCTION CALLS AND THEIR PARAMETERS CANNOT
BE CHANGED. STRUCTURES CAN BE ALTERED TO ALLOW IMPLEMENTERS TO INCLUDE
IMPLEMENTATION SPECIFIC INFORMATION.
*/
/* Includes:
Standard include files
*/
#include "mvOs.h"
/* Error Codes - CHANGE POSSIBLE: inclusion of additional error codes */
/* Key direction is invalid, e.g., unknown value */
#define AES_BAD_KEY_DIR -1
/* Key material not of correct length */
#define AES_BAD_KEY_MAT -2
/* Key passed is not valid */
#define AES_BAD_KEY_INSTANCE -3
/* Params struct passed to cipherInit invalid */
#define AES_BAD_CIPHER_MODE -4
/* Cipher in wrong state (e.g., not initialized) */
#define AES_BAD_CIPHER_STATE -5
#define AES_BAD_CIPHER_INSTANCE -7
/* Function protoypes */
/* CHANGED: makeKey(): parameter blockLen added
this parameter is absolutely necessary if you want to
setup the round keys in a variable block length setting
cipherInit(): parameter blockLen added (for obvious reasons)
*/
int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen);
int aesBlockEncrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen,
MV_U32 *plain, int numBlocks, MV_U32 *cipher);
int aesBlockDecrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen,
MV_U32 *plain, int numBlocks, MV_U32 *cipher);

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target/linux/generic/files/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c
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/* rijndael-alg-ref.c v2.0 August '99
* Reference ANSI C code
* authors: Paulo Barreto
* Vincent Rijmen, K.U.Leuven
*
* This code is placed in the public domain.
*/
#include "mvOs.h"
#include "mvAesAlg.h"
#include "mvAesBoxes.dat"
MV_U8 mul1(MV_U8 aa, MV_U8 bb);
void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC);
void ShiftRow128Enc(MV_U8 a[4][MAXBC]);
void ShiftRow128Dec(MV_U8 a[4][MAXBC]);
void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]);
void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]);
void InvMixColumn(MV_U8 a[4][MAXBC]);
#define mul(aa, bb) (mask[bb] & Alogtable[aa + Logtable[bb]])
MV_U8 mul1(MV_U8 aa, MV_U8 bb)
{
return mask[bb] & Alogtable[aa + Logtable[bb]];
}
void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC)
{
/* Exor corresponding text input and round key input bytes
*/
((MV_U32*)(&(a[0][0])))[0] ^= ((MV_U32*)(&(rk[0][0])))[0];
((MV_U32*)(&(a[1][0])))[0] ^= ((MV_U32*)(&(rk[1][0])))[0];
((MV_U32*)(&(a[2][0])))[0] ^= ((MV_U32*)(&(rk[2][0])))[0];
((MV_U32*)(&(a[3][0])))[0] ^= ((MV_U32*)(&(rk[3][0])))[0];
}
void ShiftRow128Enc(MV_U8 a[4][MAXBC]) {
/* Row 0 remains unchanged
* The other three rows are shifted a variable amount
*/
MV_U8 tmp[MAXBC];
tmp[0] = a[1][1];
tmp[1] = a[1][2];
tmp[2] = a[1][3];
tmp[3] = a[1][0];
((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0];
/*
a[1][0] = tmp[0];
a[1][1] = tmp[1];
a[1][2] = tmp[2];
a[1][3] = tmp[3];
*/
tmp[0] = a[2][2];
tmp[1] = a[2][3];
tmp[2] = a[2][0];
tmp[3] = a[2][1];
((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0];
/*
a[2][0] = tmp[0];
a[2][1] = tmp[1];
a[2][2] = tmp[2];
a[2][3] = tmp[3];
*/
tmp[0] = a[3][3];
tmp[1] = a[3][0];
tmp[2] = a[3][1];
tmp[3] = a[3][2];
((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0];
/*
a[3][0] = tmp[0];
a[3][1] = tmp[1];
a[3][2] = tmp[2];
a[3][3] = tmp[3];
*/
}
void ShiftRow128Dec(MV_U8 a[4][MAXBC]) {
/* Row 0 remains unchanged
* The other three rows are shifted a variable amount
*/
MV_U8 tmp[MAXBC];
tmp[0] = a[1][3];
tmp[1] = a[1][0];
tmp[2] = a[1][1];
tmp[3] = a[1][2];
((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0];
/*
a[1][0] = tmp[0];
a[1][1] = tmp[1];
a[1][2] = tmp[2];
a[1][3] = tmp[3];
*/
tmp[0] = a[2][2];
tmp[1] = a[2][3];
tmp[2] = a[2][0];
tmp[3] = a[2][1];
((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0];
/*
a[2][0] = tmp[0];
a[2][1] = tmp[1];
a[2][2] = tmp[2];
a[2][3] = tmp[3];
*/
tmp[0] = a[3][1];
tmp[1] = a[3][2];
tmp[2] = a[3][3];
tmp[3] = a[3][0];
((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0];
/*
a[3][0] = tmp[0];
a[3][1] = tmp[1];
a[3][2] = tmp[2];
a[3][3] = tmp[3];
*/
}
void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]) {
/* Replace every byte of the input by the byte at that place
* in the nonlinear S-box
*/
int i, j;
for(i = 0; i < 4; i++)
for(j = 0; j < 4; j++) a[i][j] = box[a[i][j]] ;
}
void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]) {
/* Mix the four bytes of every column in a linear way
*/
MV_U8 b[4][MAXBC];
int i, j;
for(j = 0; j < 4; j++){
b[0][j] = mul(25,a[0][j]) ^ mul(1,a[1][j]) ^ a[2][j] ^ a[3][j];
b[1][j] = mul(25,a[1][j]) ^ mul(1,a[2][j]) ^ a[3][j] ^ a[0][j];
b[2][j] = mul(25,a[2][j]) ^ mul(1,a[3][j]) ^ a[0][j] ^ a[1][j];
b[3][j] = mul(25,a[3][j]) ^ mul(1,a[0][j]) ^ a[1][j] ^ a[2][j];
}
for(i = 0; i < 4; i++)
/*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/
((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0] ^ ((MV_U32*)(&(rk[i][0])))[0];;
}
void InvMixColumn(MV_U8 a[4][MAXBC]) {
/* Mix the four bytes of every column in a linear way
* This is the opposite operation of Mixcolumn
*/
MV_U8 b[4][MAXBC];
int i, j;
for(j = 0; j < 4; j++){
b[0][j] = mul(223,a[0][j]) ^ mul(104,a[1][j]) ^ mul(238,a[2][j]) ^ mul(199,a[3][j]);
b[1][j] = mul(223,a[1][j]) ^ mul(104,a[2][j]) ^ mul(238,a[3][j]) ^ mul(199,a[0][j]);
b[2][j] = mul(223,a[2][j]) ^ mul(104,a[3][j]) ^ mul(238,a[0][j]) ^ mul(199,a[1][j]);
b[3][j] = mul(223,a[3][j]) ^ mul(104,a[0][j]) ^ mul(238,a[1][j]) ^ mul(199,a[2][j]);
}
for(i = 0; i < 4; i++)
/*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/
((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0];
}
int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 W[MAXROUNDS+1][4][MAXBC])
{
/* Calculate the necessary round keys
* The number of calculations depends on keyBits and blockBits
*/
int KC, BC, ROUNDS;
int i, j, t, rconpointer = 0;
MV_U8 tk[4][MAXKC];
switch (keyBits) {
case 128: KC = 4; break;
case 192: KC = 6; break;
case 256: KC = 8; break;
default : return (-1);
}
switch (blockBits) {
case 128: BC = 4; break;
case 192: BC = 6; break;
case 256: BC = 8; break;
default : return (-2);
}
switch (keyBits >= blockBits ? keyBits : blockBits) {
case 128: ROUNDS = 10; break;
case 192: ROUNDS = 12; break;
case 256: ROUNDS = 14; break;
default : return (-3); /* this cannot happen */
}
for(j = 0; j < KC; j++)
for(i = 0; i < 4; i++)
tk[i][j] = k[i][j];
t = 0;
/* copy values into round key array */
for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++)
for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j];
while (t < (ROUNDS+1)*BC) { /* while not enough round key material calculated */
/* calculate new values */
for(i = 0; i < 4; i++)
tk[i][0] ^= S[tk[(i+1)%4][KC-1]];
tk[0][0] ^= rcon[rconpointer++];
if (KC != 8)
for(j = 1; j < KC; j++)
for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1];
else {
for(j = 1; j < KC/2; j++)
for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1];
for(i = 0; i < 4; i++) tk[i][KC/2] ^= S[tk[i][KC/2 - 1]];
for(j = KC/2 + 1; j < KC; j++)
for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1];
}
/* copy values into round key array */
for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++)
for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j];
}
return 0;
}
int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds)
{
/* Encryption of one block.
*/
int r, BC, ROUNDS;
BC = 4;
ROUNDS = rounds;
/* begin with a key addition
*/
KeyAddition(a,rk[0],BC);
/* ROUNDS-1 ordinary rounds
*/
for(r = 1; r < ROUNDS; r++) {
Substitution(a,S);
ShiftRow128Enc(a);
MixColumn(a, rk[r]);
/*KeyAddition(a,rk[r],BC);*/
}
/* Last round is special: there is no MixColumn
*/
Substitution(a,S);
ShiftRow128Enc(a);
KeyAddition(a,rk[ROUNDS],BC);
return 0;
}
int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds)
{
int r, BC, ROUNDS;
BC = 4;
ROUNDS = rounds;
/* To decrypt: apply the inverse operations of the encrypt routine,
* in opposite order
*
* (KeyAddition is an involution: it 's equal to its inverse)
* (the inverse of Substitution with table S is Substitution with the inverse table of S)
* (the inverse of Shiftrow is Shiftrow over a suitable distance)
*/
/* First the special round:
* without InvMixColumn
* with extra KeyAddition
*/
KeyAddition(a,rk[ROUNDS],BC);
ShiftRow128Dec(a);
Substitution(a,Si);
/* ROUNDS-1 ordinary rounds
*/
for(r = ROUNDS-1; r > 0; r--) {
KeyAddition(a,rk[r],BC);
InvMixColumn(a);
ShiftRow128Dec(a);
Substitution(a,Si);
}
/* End with the extra key addition
*/
KeyAddition(a,rk[0],BC);
return 0;
}

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target/linux/generic/files/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h
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/* rijndael-alg-ref.h v2.0 August '99
* Reference ANSI C code
* authors: Paulo Barreto
* Vincent Rijmen, K.U.Leuven
*/
#ifndef __RIJNDAEL_ALG_H
#define __RIJNDAEL_ALG_H
#define MAXBC (128/32)
#define MAXKC (256/32)
#define MAXROUNDS 14
int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 rk[MAXROUNDS+1][4][MAXBC]);
int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds);
int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds);
#endif /* __RIJNDAEL_ALG_H */

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target/linux/generic/files/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c
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/* rijndael-api-ref.c v2.1 April 2000
* Reference ANSI C code
* authors: v2.0 Paulo Barreto
* Vincent Rijmen, K.U.Leuven
* v2.1 Vincent Rijmen, K.U.Leuven
*
* This code is placed in the public domain.
*/
#include "mvOs.h"
#include "mvAes.h"
#include "mvAesAlg.h"
/* Defines:
Add any additional defines you need
*/
#define MODE_ECB 1 /* Are we ciphering in ECB mode? */
#define MODE_CBC 2 /* Are we ciphering in CBC mode? */
#define MODE_CFB1 3 /* Are we ciphering in 1-bit CFB mode? */
int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen)
{
MV_U8 W[MAXROUNDS+1][4][MAXBC];
MV_U8 k[4][MAXKC];
MV_U8 j;
int i, rounds, KC;
if (expandedKey == NULL)
{
return AES_BAD_KEY_INSTANCE;
}
if (!((keyLen == 128) || (keyLen == 192) || (keyLen == 256)))
{
return AES_BAD_KEY_MAT;
}
if (keyMaterial == NULL)
{
return AES_BAD_KEY_MAT;
}
/* initialize key schedule: */
for(i=0; i<keyLen/8; i++)
{
j = keyMaterial[i];
k[i % 4][i / 4] = j;
}
rijndaelKeySched (k, keyLen, blockLen, W);
#ifdef MV_AES_DEBUG
{
MV_U8* pW = &W[0][0][0];
int x;
mvOsPrintf("Expended Key: size = %d\n", sizeof(W));
for(i=0; i<sizeof(W); i++)
{
mvOsPrintf("%02x ", pW[i]);
}
for(i=0; i<MAXROUNDS+1; i++)
{
mvOsPrintf("\n Round #%02d: ", i);
for(x=0; x<MAXBC; x++)
{
mvOsPrintf("%02x%02x%02x%02x ",
W[i][0][x], W[i][1][x], W[i][2][x], W[i][3][x]);
}
mvOsPrintf("\n");
}
}
#endif /* MV_AES_DEBUG */
switch (keyLen)
{
case 128:
rounds = 10;
KC = 4;
break;
case 192:
rounds = 12;
KC = 6;
break;
case 256:
rounds = 14;
KC = 8;
break;
default :
return (-1);
}
for(i=0; i<MAXBC; i++)
{
for(j=0; j<4; j++)
{
expandedKey[i*4+j] = W[rounds][j][i];
}
}
for(; i<KC; i++)
{
for(j=0; j<4; j++)
{
expandedKey[i*4+j] = W[rounds-1][j][i+MAXBC-KC];
}
}
return 0;
}
int aesBlockEncrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen,
MV_U32 *plain, int numBlocks, MV_U32 *cipher)
{
int i, j, t;
MV_U8 block[4][MAXBC];
int rounds;
char *input, *outBuffer;
input = (char*)plain;
outBuffer = (char*)cipher;
/* check parameter consistency: */
if( (expandedKey == NULL) || ((keyLen != 128) && (keyLen != 192) && (keyLen != 256)))
{
return AES_BAD_KEY_MAT;
}
if ((mode != MODE_ECB && mode != MODE_CBC))
{
return AES_BAD_CIPHER_STATE;
}
switch (keyLen)
{
case 128: rounds = 10; break;
case 192: rounds = 12; break;
case 256: rounds = 14; break;
default : return (-3); /* this cannot happen */
}
switch (mode)
{
case MODE_ECB:
for (i = 0; i < numBlocks; i++)
{
for (j = 0; j < 4; j++)
{
for(t = 0; t < 4; t++)
/* parse input stream into rectangular array */
block[t][j] = input[16*i+4*j+t] & 0xFF;
}
rijndaelEncrypt128(block, (MV_U8 (*)[4][MAXBC])expandedKey, rounds);
for (j = 0; j < 4; j++)
{
/* parse rectangular array into output ciphertext bytes */
for(t = 0; t < 4; t++)
outBuffer[16*i+4*j+t] = (MV_U8) block[t][j];
}
}
break;
case MODE_CBC:
for (j = 0; j < 4; j++)
{
for(t = 0; t < 4; t++)
/* parse initial value into rectangular array */
block[t][j] = IV[t+4*j] & 0xFF;
}
for (i = 0; i < numBlocks; i++)
{
for (j = 0; j < 4; j++)
{
for(t = 0; t < 4; t++)
/* parse input stream into rectangular array and exor with
IV or the previous ciphertext */
block[t][j] ^= input[16*i+4*j+t] & 0xFF;
}
rijndaelEncrypt128(block, (MV_U8 (*)[4][MAXBC])expandedKey, rounds);
for (j = 0; j < 4; j++)
{
/* parse rectangular array into output ciphertext bytes */
for(t = 0; t < 4; t++)
outBuffer[16*i+4*j+t] = (MV_U8) block[t][j];
}
}
break;
default: return AES_BAD_CIPHER_STATE;
}
return 0;
}
int aesBlockDecrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen,
MV_U32 *srcData, int numBlocks, MV_U32 *dstData)
{
int i, j, t;
MV_U8 block[4][MAXBC];
MV_U8 iv[4][MAXBC];
int rounds;
char *input, *outBuffer;
input = (char*)srcData;
outBuffer = (char*)dstData;
if (expandedKey == NULL)
{
return AES_BAD_KEY_MAT;
}
/* check parameter consistency: */
if (keyLen != 128 && keyLen != 192 && keyLen != 256)
{
return AES_BAD_KEY_MAT;
}
if ((mode != MODE_ECB && mode != MODE_CBC))
{
return AES_BAD_CIPHER_STATE;
}
switch (keyLen)
{
case 128: rounds = 10; break;
case 192: rounds = 12; break;
case 256: rounds = 14; break;
default : return (-3); /* this cannot happen */
}
switch (mode)
{
case MODE_ECB:
for (i = 0; i < numBlocks; i++)
{
for (j = 0; j < 4; j++)
{
for(t = 0; t < 4; t++)
{
/* parse input stream into rectangular array */
block[t][j] = input[16*i+4*j+t] & 0xFF;
}
}
rijndaelDecrypt128(block, (MV_U8 (*)[4][MAXBC])expandedKey, rounds);
for (j = 0; j < 4; j++)
{
/* parse rectangular array into output ciphertext bytes */
for(t = 0; t < 4; t++)
outBuffer[16*i+4*j+t] = (MV_U8) block[t][j];
}
}
break;
case MODE_CBC:
/* first block */
for (j = 0; j < 4; j++)
{
for(t = 0; t < 4; t++)
{
/* parse input stream into rectangular array */
block[t][j] = input[4*j+t] & 0xFF;
iv[t][j] = block[t][j];
}
}
rijndaelDecrypt128(block, (MV_U8 (*)[4][MAXBC])expandedKey, rounds);
for (j = 0; j < 4; j++)
{
/* exor the IV and parse rectangular array into output ciphertext bytes */
for(t = 0; t < 4; t++)
{
outBuffer[4*j+t] = (MV_U8) (block[t][j] ^ IV[t+4*j]);
IV[t+4*j] = iv[t][j];
}
}
/* next blocks */
for (i = 1; i < numBlocks; i++)
{
for (j = 0; j < 4; j++)
{
for(t = 0; t < 4; t++)
{
/* parse input stream into rectangular array */
iv[t][j] = input[16*i+4*j+t] & 0xFF;
block[t][j] = iv[t][j];
}
}
rijndaelDecrypt128(block, (MV_U8 (*)[4][MAXBC])expandedKey, rounds);
for (j = 0; j < 4; j++)
{
/* exor previous ciphertext block and parse rectangular array
into output ciphertext bytes */
for(t = 0; t < 4; t++)
{
outBuffer[16*i+4*j+t] = (MV_U8) (block[t][j] ^ IV[t+4*j]);
IV[t+4*j] = iv[t][j];
}
}
}
break;
default: return AES_BAD_CIPHER_STATE;
}
return 0;
}

123
target/linux/generic/files/crypto/ocf/kirkwood/cesa/AES/mvAesBoxes.dat
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@ -1,123 +0,0 @@
static MV_U8 mask[256] = {
0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
};
static MV_U8 Logtable[256] = {
0, 0, 25, 1, 50, 2, 26, 198, 75, 199, 27, 104, 51, 238, 223, 3,
100, 4, 224, 14, 52, 141, 129, 239, 76, 113, 8, 200, 248, 105, 28, 193,
125, 194, 29, 181, 249, 185, 39, 106, 77, 228, 166, 114, 154, 201, 9, 120,
101, 47, 138, 5, 33, 15, 225, 36, 18, 240, 130, 69, 53, 147, 218, 142,
150, 143, 219, 189, 54, 208, 206, 148, 19, 92, 210, 241, 64, 70, 131, 56,
102, 221, 253, 48, 191, 6, 139, 98, 179, 37, 226, 152, 34, 136, 145, 16,
126, 110, 72, 195, 163, 182, 30, 66, 58, 107, 40, 84, 250, 133, 61, 186,
43, 121, 10, 21, 155, 159, 94, 202, 78, 212, 172, 229, 243, 115, 167, 87,
175, 88, 168, 80, 244, 234, 214, 116, 79, 174, 233, 213, 231, 230, 173, 232,
44, 215, 117, 122, 235, 22, 11, 245, 89, 203, 95, 176, 156, 169, 81, 160,
127, 12, 246, 111, 23, 196, 73, 236, 216, 67, 31, 45, 164, 118, 123, 183,
204, 187, 62, 90, 251, 96, 177, 134, 59, 82, 161, 108, 170, 85, 41, 157,
151, 178, 135, 144, 97, 190, 220, 252, 188, 149, 207, 205, 55, 63, 91, 209,
83, 57, 132, 60, 65, 162, 109, 71, 20, 42, 158, 93, 86, 242, 211, 171,
68, 17, 146, 217, 35, 32, 46, 137, 180, 124, 184, 38, 119, 153, 227, 165,
103, 74, 237, 222, 197, 49, 254, 24, 13, 99, 140, 128, 192, 247, 112, 7,
};
static MV_U8 Alogtable[512] = {
1, 3, 5, 15, 17, 51, 85, 255, 26, 46, 114, 150, 161, 248, 19, 53,
95, 225, 56, 72, 216, 115, 149, 164, 247, 2, 6, 10, 30, 34, 102, 170,
229, 52, 92, 228, 55, 89, 235, 38, 106, 190, 217, 112, 144, 171, 230, 49,
83, 245, 4, 12, 20, 60, 68, 204, 79, 209, 104, 184, 211, 110, 178, 205,
76, 212, 103, 169, 224, 59, 77, 215, 98, 166, 241, 8, 24, 40, 120, 136,
131, 158, 185, 208, 107, 189, 220, 127, 129, 152, 179, 206, 73, 219, 118, 154,
181, 196, 87, 249, 16, 48, 80, 240, 11, 29, 39, 105, 187, 214, 97, 163,
254, 25, 43, 125, 135, 146, 173, 236, 47, 113, 147, 174, 233, 32, 96, 160,
251, 22, 58, 78, 210, 109, 183, 194, 93, 231, 50, 86, 250, 21, 63, 65,
195, 94, 226, 61, 71, 201, 64, 192, 91, 237, 44, 116, 156, 191, 218, 117,
159, 186, 213, 100, 172, 239, 42, 126, 130, 157, 188, 223, 122, 142, 137, 128,
155, 182, 193, 88, 232, 35, 101, 175, 234, 37, 111, 177, 200, 67, 197, 84,
252, 31, 33, 99, 165, 244, 7, 9, 27, 45, 119, 153, 176, 203, 70, 202,
69, 207, 74, 222, 121, 139, 134, 145, 168, 227, 62, 66, 198, 81, 243, 14,
18, 54, 90, 238, 41, 123, 141, 140, 143, 138, 133, 148, 167, 242, 13, 23,
57, 75, 221, 124, 132, 151, 162, 253, 28, 36, 108, 180, 199, 82, 246, 1,
3, 5, 15, 17, 51, 85, 255, 26, 46, 114, 150, 161, 248, 19, 53,
95, 225, 56, 72, 216, 115, 149, 164, 247, 2, 6, 10, 30, 34, 102, 170,
229, 52, 92, 228, 55, 89, 235, 38, 106, 190, 217, 112, 144, 171, 230, 49,
83, 245, 4, 12, 20, 60, 68, 204, 79, 209, 104, 184, 211, 110, 178, 205,
76, 212, 103, 169, 224, 59, 77, 215, 98, 166, 241, 8, 24, 40, 120, 136,
131, 158, 185, 208, 107, 189, 220, 127, 129, 152, 179, 206, 73, 219, 118, 154,
181, 196, 87, 249, 16, 48, 80, 240, 11, 29, 39, 105, 187, 214, 97, 163,
254, 25, 43, 125, 135, 146, 173, 236, 47, 113, 147, 174, 233, 32, 96, 160,
251, 22, 58, 78, 210, 109, 183, 194, 93, 231, 50, 86, 250, 21, 63, 65,
195, 94, 226, 61, 71, 201, 64, 192, 91, 237, 44, 116, 156, 191, 218, 117,
159, 186, 213, 100, 172, 239, 42, 126, 130, 157, 188, 223, 122, 142, 137, 128,
155, 182, 193, 88, 232, 35, 101, 175, 234, 37, 111, 177, 200, 67, 197, 84,
252, 31, 33, 99, 165, 244, 7, 9, 27, 45, 119, 153, 176, 203, 70, 202,
69, 207, 74, 222, 121, 139, 134, 145, 168, 227, 62, 66, 198, 81, 243, 14,
18, 54, 90, 238, 41, 123, 141, 140, 143, 138, 133, 148, 167, 242, 13, 23,
57, 75, 221, 124, 132, 151, 162, 253, 28, 36, 108, 180, 199, 82, 246, 1,
};
static MV_U8 S[256] = {
99, 124, 119, 123, 242, 107, 111, 197, 48, 1, 103, 43, 254, 215, 171, 118,
202, 130, 201, 125, 250, 89, 71, 240, 173, 212, 162, 175, 156, 164, 114, 192,
183, 253, 147, 38, 54, 63, 247, 204, 52, 165, 229, 241, 113, 216, 49, 21,
4, 199, 35, 195, 24, 150, 5, 154, 7, 18, 128, 226, 235, 39, 178, 117,
9, 131, 44, 26, 27, 110, 90, 160, 82, 59, 214, 179, 41, 227, 47, 132,
83, 209, 0, 237, 32, 252, 177, 91, 106, 203, 190, 57, 74, 76, 88, 207,
208, 239, 170, 251, 67, 77, 51, 133, 69, 249, 2, 127, 80, 60, 159, 168,
81, 163, 64, 143, 146, 157, 56, 245, 188, 182, 218, 33, 16, 255, 243, 210,
205, 12, 19, 236, 95, 151, 68, 23, 196, 167, 126, 61, 100, 93, 25, 115,
96, 129, 79, 220, 34, 42, 144, 136, 70, 238, 184, 20, 222, 94, 11, 219,
224, 50, 58, 10, 73, 6, 36, 92, 194, 211, 172, 98, 145, 149, 228, 121,
231, 200, 55, 109, 141, 213, 78, 169, 108, 86, 244, 234, 101, 122, 174, 8,
186, 120, 37, 46, 28, 166, 180, 198, 232, 221, 116, 31, 75, 189, 139, 138,
112, 62, 181, 102, 72, 3, 246, 14, 97, 53, 87, 185, 134, 193, 29, 158,
225, 248, 152, 17, 105, 217, 142, 148, 155, 30, 135, 233, 206, 85, 40, 223,
140, 161, 137, 13, 191, 230, 66, 104, 65, 153, 45, 15, 176, 84, 187, 22,
};
static MV_U8 Si[256] = {
82, 9, 106, 213, 48, 54, 165, 56, 191, 64, 163, 158, 129, 243, 215, 251,
124, 227, 57, 130, 155, 47, 255, 135, 52, 142, 67, 68, 196, 222, 233, 203,
84, 123, 148, 50, 166, 194, 35, 61, 238, 76, 149, 11, 66, 250, 195, 78,
8, 46, 161, 102, 40, 217, 36, 178, 118, 91, 162, 73, 109, 139, 209, 37,
114, 248, 246, 100, 134, 104, 152, 22, 212, 164, 92, 204, 93, 101, 182, 146,
108, 112, 72, 80, 253, 237, 185, 218, 94, 21, 70, 87, 167, 141, 157, 132,
144, 216, 171, 0, 140, 188, 211, 10, 247, 228, 88, 5, 184, 179, 69, 6,
208, 44, 30, 143, 202, 63, 15, 2, 193, 175, 189, 3, 1, 19, 138, 107,
58, 145, 17, 65, 79, 103, 220, 234, 151, 242, 207, 206, 240, 180, 230, 115,
150, 172, 116, 34, 231, 173, 53, 133, 226, 249, 55, 232, 28, 117, 223, 110,
71, 241, 26, 113, 29, 41, 197, 137, 111, 183, 98, 14, 170, 24, 190, 27,
252, 86, 62, 75, 198, 210, 121, 32, 154, 219, 192, 254, 120, 205, 90, 244,
31, 221, 168, 51, 136, 7, 199, 49, 177, 18, 16, 89, 39, 128, 236, 95,
96, 81, 127, 169, 25, 181, 74, 13, 45, 229, 122, 159, 147, 201, 156, 239,
160, 224, 59, 77, 174, 42, 245, 176, 200, 235, 187, 60, 131, 83, 153, 97,
23, 43, 4, 126, 186, 119, 214, 38, 225, 105, 20, 99, 85, 33, 12, 125,
};
/*
static MV_U8 iG[4][4] = {
{0x0e, 0x09, 0x0d, 0x0b},
{0x0b, 0x0e, 0x09, 0x0d},
{0x0d, 0x0b, 0x0e, 0x09},
{0x09, 0x0d, 0x0b, 0x0e},
};
*/
static MV_U32 rcon[30] = {
0x01,0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, };

3126
target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvCesa.c
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File diff suppressed because it is too large Load Diff

412
target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvCesa.h
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@ -1,412 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/*******************************************************************************
* mvCesa.h - Header File for Cryptographic Engines and Security Accelerator
*
* DESCRIPTION:
* This header file contains macros typedefs and function declaration for
* the Marvell Cryptographic Engines and Security Accelerator.
*
*******************************************************************************/
#ifndef __mvCesa_h__
#define __mvCesa_h__
#include "mvOs.h"
#include "mvCommon.h"
#include "mvDebug.h"
#include "ctrlEnv/mvCtrlEnvSpec.h"
#include "cesa/mvMD5.h"
#include "cesa/mvSHA1.h"
#include "cesa/mvCesa.h"
#include "cesa/AES/mvAes.h"
#include "mvSysHwConfig.h"
#ifdef MV_INCLUDE_IDMA
#include "idma/mvIdma.h"
#include "idma/mvIdmaRegs.h"
#else
/* Redefine MV_DMA_DESC structure */
typedef struct _mvDmaDesc
{
MV_U32 byteCnt; /* The total number of bytes to transfer */
MV_U32 phySrcAdd; /* The physical source address */
MV_U32 phyDestAdd; /* The physical destination address */
MV_U32 phyNextDescPtr; /* If we are using chain mode DMA transfer, */
/* then this pointer should point to the */
/* physical address of the next descriptor, */
/* otherwise it should be NULL. */
}MV_DMA_DESC;
#endif /* MV_INCLUDE_IDMA */
#include "cesa/mvCesaRegs.h"
#define MV_CESA_AUTH_BLOCK_SIZE 64 /* bytes */
#define MV_CESA_MD5_DIGEST_SIZE 16 /* bytes */
#define MV_CESA_SHA1_DIGEST_SIZE 20 /* bytes */
#define MV_CESA_MAX_DIGEST_SIZE MV_CESA_SHA1_DIGEST_SIZE
#define MV_CESA_DES_KEY_LENGTH 8 /* bytes = 64 bits */
#define MV_CESA_3DES_KEY_LENGTH 24 /* bytes = 192 bits */
#define MV_CESA_AES_128_KEY_LENGTH 16 /* bytes = 128 bits */
#define MV_CESA_AES_192_KEY_LENGTH 24 /* bytes = 192 bits */
#define MV_CESA_AES_256_KEY_LENGTH 32 /* bytes = 256 bits */
#define MV_CESA_MAX_CRYPTO_KEY_LENGTH MV_CESA_AES_256_KEY_LENGTH
#define MV_CESA_DES_BLOCK_SIZE 8 /* bytes = 64 bits */
#define MV_CESA_3DES_BLOCK_SIZE 8 /* bytes = 64 bits */
#define MV_CESA_AES_BLOCK_SIZE 16 /* bytes = 128 bits */
#define MV_CESA_MAX_IV_LENGTH MV_CESA_AES_BLOCK_SIZE
#define MV_CESA_MAX_MAC_KEY_LENGTH 64 /* bytes */
typedef struct
{
MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH];
MV_U8 macKey[MV_CESA_MAX_MAC_KEY_LENGTH];
MV_CESA_OPERATION operation;
MV_CESA_DIRECTION direction;
MV_CESA_CRYPTO_ALG cryptoAlgorithm;
MV_CESA_CRYPTO_MODE cryptoMode;
MV_U8 cryptoKeyLength;
MV_CESA_MAC_MODE macMode;
MV_U8 macKeyLength;
MV_U8 digestSize;
} MV_CESA_OPEN_SESSION;
typedef struct
{
MV_BUF_INFO *pFrags;
MV_U16 numFrags;
MV_U16 mbufSize;
} MV_CESA_MBUF;
typedef struct
{
void* pReqPrv; /* instead of reqId */
MV_U32 retCode;
MV_16 sessionId;
} MV_CESA_RESULT;
typedef void (*MV_CESA_CALLBACK) (MV_CESA_RESULT* pResult);
typedef struct
{
void* pReqPrv; /* instead of reqId */
MV_CESA_MBUF* pSrc;
MV_CESA_MBUF* pDst;
MV_CESA_CALLBACK* pFuncCB;
MV_16 sessionId;
MV_U16 ivFromUser;
MV_U16 ivOffset;
MV_U16 cryptoOffset;
MV_U16 cryptoLength;
MV_U16 digestOffset;
MV_U16 macOffset;
MV_U16 macLength;
MV_BOOL skipFlush;
} MV_CESA_COMMAND;
MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, void *osHandle);
MV_STATUS mvCesaFinish (void);
MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid);
MV_STATUS mvCesaSessionClose(short sid);
MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize);
MV_STATUS mvCesaAction (MV_CESA_COMMAND* pCmd);
MV_U32 mvCesaInProcessGet(void);
MV_STATUS mvCesaReadyDispatch(void);
MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult);
MV_BOOL mvCesaIsReady(void);
int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset);
MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDst, MV_CESA_MBUF* pSrcMbuf,
int offset, int size);
MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrc, MV_CESA_MBUF* pDstMbuf,
int offset, int size);
MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset,
MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size);
/********** Debug functions ********/
void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size);
void mvCesaDebugSA(short sid, int mode);
void mvCesaDebugStats(void);
void mvCesaDebugStatsClear(void);
void mvCesaDebugRegs(void);
void mvCesaDebugStatus(void);
void mvCesaDebugQueue(int mode);
void mvCesaDebugSram(int mode);
void mvCesaDebugSAD(int mode);
/******** CESA Private definitions ********/
#if (MV_CESA_VERSION >= 2)
#if (MV_CACHE_COHERENCY == MV_CACHE_COHER_SW)
#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_128B) \
| MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \
| MV_CESA_TDMA_OUTSTAND_READ_EN_MASK \
| MV_CESA_TDMA_NO_BYTE_SWAP_MASK \
| MV_CESA_TDMA_ENABLE_MASK
#else
#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_32B) \
| MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \
/*| MV_CESA_TDMA_OUTSTAND_READ_EN_MASK */\
| MV_CESA_TDMA_ENABLE_MASK
#endif
#else
#define MV_CESA_IDMA_CTRL_LOW_VALUE ICCLR_DST_BURST_LIM_128BYTE \
| ICCLR_SRC_BURST_LIM_128BYTE \
| ICCLR_INT_MODE_MASK \
| ICCLR_BLOCK_MODE \
| ICCLR_CHAN_ENABLE \
| ICCLR_DESC_MODE_16M
#endif /* MV_CESA_VERSION >= 2 */
#define MV_CESA_MAX_PKT_SIZE (64 * 1024)
#define MV_CESA_MAX_MBUF_FRAGS 20
#define MV_CESA_MAX_REQ_FRAGS ( (MV_CESA_MAX_PKT_SIZE / MV_CESA_MAX_BUF_SIZE) + 1)
#define MV_CESA_MAX_DMA_DESC (MV_CESA_MAX_MBUF_FRAGS*2 + 5)
#define MAX_CESA_CHAIN_LENGTH 20
typedef enum
{
MV_CESA_IDLE = 0,
MV_CESA_PENDING,
MV_CESA_PROCESS,
MV_CESA_READY,
#if (MV_CESA_VERSION >= 3)
MV_CESA_CHAIN,
#endif
} MV_CESA_STATE;
/* Session database */
/* Map of Key materials of the session in SRAM.
* Each field must be 8 byte aligned
* Total size: 32 + 24 + 24 = 80 bytes
*/
typedef struct
{
MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH];
MV_U8 macInnerIV[MV_CESA_MAX_DIGEST_SIZE];
MV_U8 reservedInner[4];
MV_U8 macOuterIV[MV_CESA_MAX_DIGEST_SIZE];
MV_U8 reservedOuter[4];
} MV_CESA_SRAM_SA;
typedef struct
{
MV_CESA_SRAM_SA* pSramSA;
MV_U32 config;
MV_U8 cryptoKeyLength;
MV_U8 cryptoIvSize;
MV_U8 cryptoBlockSize;
MV_U8 digestSize;
MV_U8 macKeyLength;
MV_U8 valid;
MV_U8 ctrMode;
MV_U32 count;
} MV_CESA_SA;
/* DMA list management */
typedef struct
{
MV_DMA_DESC* pDmaFirst;
MV_DMA_DESC* pDmaLast;
} MV_CESA_DMA;
typedef struct
{
MV_U8 numFrag;
MV_U8 nextFrag;
int bufOffset;
int cryptoSize;
int macSize;
int newDigestOffset;
MV_U8 orgDigest[MV_CESA_MAX_DIGEST_SIZE];
} MV_CESA_FRAGS;
/* Request queue */
typedef struct
{
MV_U8 state;
MV_U8 fragMode;
MV_U8 fixOffset;
MV_CESA_COMMAND* pCmd;
MV_CESA_COMMAND* pOrgCmd;
MV_BUF_INFO dmaDescBuf;
MV_CESA_DMA dma[MV_CESA_MAX_REQ_FRAGS];
MV_BUF_INFO cesaDescBuf;
MV_CESA_DESC* pCesaDesc;
MV_CESA_FRAGS frags;
} MV_CESA_REQ;
/* SRAM map */
/* Total SRAM size calculation */
/* SRAM size =
* MV_CESA_MAX_BUF_SIZE +
* sizeof(MV_CESA_DESC) +
* MV_CESA_MAX_IV_LENGTH +
* MV_CESA_MAX_IV_LENGTH +
* MV_CESA_MAX_DIGEST_SIZE +
* sizeof(MV_CESA_SRAM_SA)
* = 1600 + 32 + 16 + 16 + 24 + 80 + 280 (reserved) = 2048 bytes
* = 3200 + 32 + 16 + 16 + 24 + 80 + 728 (reserved) = 4096 bytes
*/
typedef struct
{
MV_U8 buf[MV_CESA_MAX_BUF_SIZE];
MV_CESA_DESC desc;
MV_U8 cryptoIV[MV_CESA_MAX_IV_LENGTH];
MV_U8 tempCryptoIV[MV_CESA_MAX_IV_LENGTH];
MV_U8 tempDigest[MV_CESA_MAX_DIGEST_SIZE+4];
MV_CESA_SRAM_SA sramSA;
} MV_CESA_SRAM_MAP;
typedef struct
{
MV_U32 openedCount;
MV_U32 closedCount;
MV_U32 fragCount;
MV_U32 reqCount;
MV_U32 maxReqCount;
MV_U32 procCount;
MV_U32 readyCount;
MV_U32 notReadyCount;
MV_U32 startCount;
#if (MV_CESA_VERSION >= 3)
MV_U32 maxChainUsage;
#endif
} MV_CESA_STATS;
/* External variables */
extern MV_CESA_STATS cesaStats;
extern MV_CESA_FRAGS cesaFrags;
extern MV_BUF_INFO cesaSramSaBuf;
extern MV_CESA_SA* pCesaSAD;
extern MV_U16 cesaMaxSA;
extern MV_CESA_REQ* pCesaReqFirst;
extern MV_CESA_REQ* pCesaReqLast;
extern MV_CESA_REQ* pCesaReqEmpty;
extern MV_CESA_REQ* pCesaReqProcess;
extern int cesaQueueDepth;
extern int cesaReqResources;
#if (MV_CESA_VERSION>= 3)
extern MV_U32 cesaChainLength;
#endif
extern MV_CESA_SRAM_MAP* cesaSramVirtPtr;
extern MV_U32 cesaSramPhysAddr;
static INLINE MV_ULONG mvCesaVirtToPhys(MV_BUF_INFO* pBufInfo, void* pVirt)
{
return (pBufInfo->bufPhysAddr + ((MV_U8*)pVirt - pBufInfo->bufVirtPtr));
}
/* Additional DEBUG functions */
void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode);
void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode);
void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc);
#endif /* __mvCesa_h__ */

484
target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvCesaDebug.c
View File

@ -1,484 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "mvOs.h"
#include "mvDebug.h"
#include "cesa/mvMD5.h"
#include "cesa/mvSHA1.h"
#include "cesa/mvCesa.h"
#include "cesa/mvCesaRegs.h"
#include "cesa/AES/mvAes.h"
static const char* mvCesaDebugStateStr(MV_CESA_STATE state)
{
switch(state)
{
case MV_CESA_IDLE:
return "Idle";
case MV_CESA_PENDING:
return "Pend";
case MV_CESA_PROCESS:
return "Proc";
case MV_CESA_READY:
return "Ready";
default:
break;
}
return "Unknown";
}
static const char* mvCesaDebugOperStr(MV_CESA_OPERATION oper)
{
switch(oper)
{
case MV_CESA_MAC_ONLY:
return "MacOnly";
case MV_CESA_CRYPTO_ONLY:
return "CryptoOnly";
case MV_CESA_MAC_THEN_CRYPTO:
return "MacCrypto";
case MV_CESA_CRYPTO_THEN_MAC:
return "CryptoMac";
default:
break;
}
return "Null";
}
static const char* mvCesaDebugCryptoAlgStr(MV_CESA_CRYPTO_ALG cryptoAlg)
{
switch(cryptoAlg)
{
case MV_CESA_CRYPTO_DES:
return "DES";
case MV_CESA_CRYPTO_3DES:
return "3DES";
case MV_CESA_CRYPTO_AES:
return "AES";
default:
break;
}
return "Null";
}
static const char* mvCesaDebugMacModeStr(MV_CESA_MAC_MODE macMode)
{
switch(macMode)
{
case MV_CESA_MAC_MD5:
return "MD5";
case MV_CESA_MAC_SHA1:
return "SHA1";
case MV_CESA_MAC_HMAC_MD5:
return "HMAC-MD5";
case MV_CESA_MAC_HMAC_SHA1:
return "HMAC_SHA1";
default:
break;
}
return "Null";
}
void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode)
{
mvOsPrintf("pCmd=%p, pReqPrv=%p, pSrc=%p, pDst=%p, pCB=%p, sid=%d\n",
pCmd, pCmd->pReqPrv, pCmd->pSrc, pCmd->pDst,
pCmd->pFuncCB, pCmd->sessionId);
mvOsPrintf("isUser=%d, ivOffs=%d, crOffs=%d, crLen=%d, digest=%d, macOffs=%d, macLen=%d\n",
pCmd->ivFromUser, pCmd->ivOffset, pCmd->cryptoOffset, pCmd->cryptoLength,
pCmd->digestOffset, pCmd->macOffset, pCmd->macLength);
}
/* no need to use in tool */
void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size)
{
int frag, len, fragOffset;
if(str != NULL)
mvOsPrintf("%s: pMbuf=%p, numFrags=%d, mbufSize=%d\n",
str, pMbuf, pMbuf->numFrags, pMbuf->mbufSize);
frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset);
if(frag == MV_INVALID)
{
mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset);
return;
}
for(; frag<pMbuf->numFrags; frag++)
{
mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n",
frag, pMbuf->pFrags[frag].bufVirtPtr,
pMbuf->pFrags[frag].bufSize);
if(size > 0)
{
len = MV_MIN(pMbuf->pFrags[frag].bufSize, size);
mvDebugMemDump(pMbuf->pFrags[frag].bufVirtPtr+fragOffset, len, 1);
size -= len;
fragOffset = 0;
}
}
}
void mvCesaDebugRegs(void)
{
mvOsPrintf("\t CESA Registers:\n");
mvOsPrintf("MV_CESA_CMD_REG : 0x%X = 0x%08x\n",
MV_CESA_CMD_REG,
MV_REG_READ( MV_CESA_CMD_REG ) );
mvOsPrintf("MV_CESA_CHAN_DESC_OFFSET_REG : 0x%X = 0x%08x\n",
MV_CESA_CHAN_DESC_OFFSET_REG,
MV_REG_READ(MV_CESA_CHAN_DESC_OFFSET_REG) );
mvOsPrintf("MV_CESA_CFG_REG : 0x%X = 0x%08x\n",
MV_CESA_CFG_REG,
MV_REG_READ( MV_CESA_CFG_REG ) );
mvOsPrintf("MV_CESA_STATUS_REG : 0x%X = 0x%08x\n",
MV_CESA_STATUS_REG,
MV_REG_READ( MV_CESA_STATUS_REG ) );
mvOsPrintf("MV_CESA_ISR_CAUSE_REG : 0x%X = 0x%08x\n",
MV_CESA_ISR_CAUSE_REG,
MV_REG_READ( MV_CESA_ISR_CAUSE_REG ) );
mvOsPrintf("MV_CESA_ISR_MASK_REG : 0x%X = 0x%08x\n",
MV_CESA_ISR_MASK_REG,
MV_REG_READ( MV_CESA_ISR_MASK_REG ) );
#if (MV_CESA_VERSION >= 2)
mvOsPrintf("MV_CESA_TDMA_CTRL_REG : 0x%X = 0x%08x\n",
MV_CESA_TDMA_CTRL_REG,
MV_REG_READ( MV_CESA_TDMA_CTRL_REG ) );
mvOsPrintf("MV_CESA_TDMA_BYTE_COUNT_REG : 0x%X = 0x%08x\n",
MV_CESA_TDMA_BYTE_COUNT_REG,
MV_REG_READ( MV_CESA_TDMA_BYTE_COUNT_REG ) );
mvOsPrintf("MV_CESA_TDMA_SRC_ADDR_REG : 0x%X = 0x%08x\n",
MV_CESA_TDMA_SRC_ADDR_REG,
MV_REG_READ( MV_CESA_TDMA_SRC_ADDR_REG ) );
mvOsPrintf("MV_CESA_TDMA_DST_ADDR_REG : 0x%X = 0x%08x\n",
MV_CESA_TDMA_DST_ADDR_REG,
MV_REG_READ( MV_CESA_TDMA_DST_ADDR_REG ) );
mvOsPrintf("MV_CESA_TDMA_NEXT_DESC_PTR_REG : 0x%X = 0x%08x\n",
MV_CESA_TDMA_NEXT_DESC_PTR_REG,
MV_REG_READ( MV_CESA_TDMA_NEXT_DESC_PTR_REG ) );
mvOsPrintf("MV_CESA_TDMA_CURR_DESC_PTR_REG : 0x%X = 0x%08x\n",
MV_CESA_TDMA_CURR_DESC_PTR_REG,
MV_REG_READ( MV_CESA_TDMA_CURR_DESC_PTR_REG ) );
mvOsPrintf("MV_CESA_TDMA_ERROR_CAUSE_REG : 0x%X = 0x%08x\n",
MV_CESA_TDMA_ERROR_CAUSE_REG,
MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) );
mvOsPrintf("MV_CESA_TDMA_ERROR_MASK_REG : 0x%X = 0x%08x\n",
MV_CESA_TDMA_ERROR_MASK_REG,
MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) );
#endif
}
void mvCesaDebugStatus(void)
{
mvOsPrintf("\n\t CESA Status\n\n");
mvOsPrintf("pReqQ=%p, qDepth=%d, reqSize=%ld bytes, qRes=%d, ",
pCesaReqFirst, cesaQueueDepth, sizeof(MV_CESA_REQ),
cesaReqResources);
#if (MV_CESA_VERSION >= 3)
mvOsPrintf("chainLength=%u\n",cesaChainLength);
#else
mvOsPrintf("\n");
#endif
mvOsPrintf("pSAD=%p, maxSA=%d, sizeSA=%ld bytes\n",
pCesaSAD, cesaMaxSA, sizeof(MV_CESA_SA));
mvOsPrintf("\n");
mvCesaDebugRegs();
mvCesaDebugStats();
mvCesaDebugStatsClear();
}
void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc)
{
mvOsPrintf("config=0x%08x, crSrcOffs=0x%04x, crDstOffs=0x%04x\n",
pDesc->config, pDesc->cryptoSrcOffset, pDesc->cryptoDstOffset);
mvOsPrintf("crLen=0x%04x, crKeyOffs=0x%04x, ivOffs=0x%04x, ivBufOffs=0x%04x\n",
pDesc->cryptoDataLen, pDesc->cryptoKeyOffset,
pDesc->cryptoIvOffset, pDesc->cryptoIvBufOffset);
mvOsPrintf("macSrc=0x%04x, digest=0x%04x, macLen=0x%04x, inIv=0x%04x, outIv=0x%04x\n",
pDesc->macSrcOffset, pDesc->macDigestOffset, pDesc->macDataLen,
pDesc->macInnerIvOffset, pDesc->macOuterIvOffset);
}
void mvCesaDebugQueue(int mode)
{
mvOsPrintf("\n\t CESA Request Queue:\n\n");
mvOsPrintf("pFirstReq=%p, pLastReq=%p, qDepth=%d, reqSize=%ld bytes\n",
pCesaReqFirst, pCesaReqLast, cesaQueueDepth, sizeof(MV_CESA_REQ));
mvOsPrintf("pEmpty=%p, pProcess=%p, qResources=%d\n",
pCesaReqEmpty, pCesaReqProcess,
cesaReqResources);
if(mode != 0)
{
int count = 0;
MV_CESA_REQ* pReq = pCesaReqFirst;
for(count=0; count<cesaQueueDepth; count++)
{
/* Print out requsts */
mvOsPrintf("%02d. pReq=%p, state=%s, frag=0x%x, pCmd=%p, pDma=%p, pDesc=%p\n",
count, pReq, mvCesaDebugStateStr(pReq->state),
pReq->fragMode, pReq->pCmd, pReq->dma[0].pDmaFirst, &pReq->pCesaDesc[0]);
if(pReq->fragMode != MV_CESA_FRAG_NONE)
{
int frag;
mvOsPrintf("pFrags=%p, num=%d, next=%d, bufOffset=%d, cryptoSize=%d, macSize=%d\n",
&pReq->frags, pReq->frags.numFrag, pReq->frags.nextFrag,
pReq->frags.bufOffset, pReq->frags.cryptoSize, pReq->frags.macSize);
for(frag=0; frag<pReq->frags.numFrag; frag++)
{
mvOsPrintf("#%d: pDmaFirst=%p, pDesc=%p\n", frag,
pReq->dma[frag].pDmaFirst, &pReq->pCesaDesc[frag]);
}
}
if(mode > 1)
{
/* Print out Command */
mvCesaDebugCmd(pReq->pCmd, mode);
/* Print out Descriptor */
mvCesaDebugDescriptor(&pReq->pCesaDesc[0]);
}
pReq++;
}
}
}
void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode)
{
if(pSramSA == NULL)
{
mvOsPrintf("cesaSramSA: Unexpected pSramSA=%p\n", pSramSA);
return;
}
mvOsPrintf("pSramSA=%p, sizeSramSA=%ld bytes\n",
pSramSA, sizeof(MV_CESA_SRAM_SA));
if(mode != 0)
{
mvOsPrintf("cryptoKey=%p, maxCryptoKey=%d bytes\n",
pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH);
mvDebugMemDump(pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH, 1);
mvOsPrintf("macInnerIV=%p, maxInnerIV=%d bytes\n",
pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE);
mvDebugMemDump(pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE, 1);
mvOsPrintf("macOuterIV=%p, maxOuterIV=%d bytes\n",
pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE);
mvDebugMemDump(pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE, 1);
}
}
void mvCesaDebugSA(short sid, int mode)
{
MV_CESA_OPERATION oper;
MV_CESA_DIRECTION dir;
MV_CESA_CRYPTO_ALG cryptoAlg;
MV_CESA_CRYPTO_MODE cryptoMode;
MV_CESA_MAC_MODE macMode;
MV_CESA_SA* pSA = &pCesaSAD[sid];
if( (pSA->valid) || ((pSA->count != 0) && (mode > 0)) || (mode >= 2) )
{
mvOsPrintf("\n\nCESA SA Entry #%d (%p) - %s (count=%d)\n",
sid, pSA,
pSA->valid ? "Valid" : "Invalid", pSA->count);
oper = (pSA->config & MV_CESA_OPERATION_MASK) >> MV_CESA_OPERATION_OFFSET;
dir = (pSA->config & MV_CESA_DIRECTION_MASK) >> MV_CESA_DIRECTION_BIT;
mvOsPrintf("%s - %s ", mvCesaDebugOperStr(oper),
(dir == MV_CESA_DIR_ENCODE) ? "Encode" : "Decode");
if(oper != MV_CESA_MAC_ONLY)
{
cryptoAlg = (pSA->config & MV_CESA_CRYPTO_ALG_MASK) >> MV_CESA_CRYPTO_ALG_OFFSET;
cryptoMode = (pSA->config & MV_CESA_CRYPTO_MODE_MASK) >> MV_CESA_CRYPTO_MODE_BIT;
mvOsPrintf("- %s - %s ", mvCesaDebugCryptoAlgStr(cryptoAlg),
(cryptoMode == MV_CESA_CRYPTO_ECB) ? "ECB" : "CBC");
}
if(oper != MV_CESA_CRYPTO_ONLY)
{
macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET;
mvOsPrintf("- %s ", mvCesaDebugMacModeStr(macMode));
}
mvOsPrintf("\n");
if(mode > 0)
{
mvOsPrintf("config=0x%08x, cryptoKeySize=%d, digestSize=%d\n",
pCesaSAD[sid].config, pCesaSAD[sid].cryptoKeyLength,
pCesaSAD[sid].digestSize);
mvCesaDebugSramSA(pCesaSAD[sid].pSramSA, mode);
}
}
}
/**/
void mvCesaDebugSram(int mode)
{
mvOsPrintf("\n\t SRAM contents: size=%ld, pVirt=%p\n\n",
sizeof(MV_CESA_SRAM_MAP), cesaSramVirtPtr);
mvOsPrintf("\n\t Sram buffer: size=%d, pVirt=%p\n",
MV_CESA_MAX_BUF_SIZE, cesaSramVirtPtr->buf);
if(mode != 0)
mvDebugMemDump(cesaSramVirtPtr->buf, 64, 1);
mvOsPrintf("\n");
mvOsPrintf("\n\t Sram descriptor: size=%ld, pVirt=%p\n",
sizeof(MV_CESA_DESC), &cesaSramVirtPtr->desc);
if(mode != 0)
{
mvOsPrintf("\n");
mvCesaDebugDescriptor(&cesaSramVirtPtr->desc);
}
mvOsPrintf("\n\t Sram IV: size=%d, pVirt=%p\n",
MV_CESA_MAX_IV_LENGTH, &cesaSramVirtPtr->cryptoIV);
if(mode != 0)
{
mvOsPrintf("\n");
mvDebugMemDump(cesaSramVirtPtr->cryptoIV, MV_CESA_MAX_IV_LENGTH, 1);
}
mvOsPrintf("\n");
mvCesaDebugSramSA(&cesaSramVirtPtr->sramSA, 0);
}
void mvCesaDebugSAD(int mode)
{
int sid;
mvOsPrintf("\n\t Cesa SAD status: pSAD=%p, maxSA=%d\n",
pCesaSAD, cesaMaxSA);
for(sid=0; sid<cesaMaxSA; sid++)
{
mvCesaDebugSA(sid, mode);
}
}
void mvCesaDebugStats(void)
{
mvOsPrintf("\n\t Cesa Statistics\n");
mvOsPrintf("Opened=%u, Closed=%u\n",
cesaStats.openedCount, cesaStats.closedCount);
mvOsPrintf("Req=%u, maxReq=%u, frags=%u, start=%u\n",
cesaStats.reqCount, cesaStats.maxReqCount,
cesaStats.fragCount, cesaStats.startCount);
#if (MV_CESA_VERSION >= 3)
mvOsPrintf("maxChainUsage=%u\n",cesaStats.maxChainUsage);
#endif
mvOsPrintf("\n");
mvOsPrintf("proc=%u, ready=%u, notReady=%u\n",
cesaStats.procCount, cesaStats.readyCount, cesaStats.notReadyCount);
}
void mvCesaDebugStatsClear(void)
{
memset(&cesaStats, 0, sizeof(cesaStats));
}

357
target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvCesaRegs.h
View File

@ -1,357 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __mvCesaRegs_h__
#define __mvCesaRegs_h__
#include "mvTypes.h"
typedef struct
{
/* word 0 */
MV_U32 config;
/* word 1 */
MV_U16 cryptoSrcOffset;
MV_U16 cryptoDstOffset;
/* word 2 */
MV_U16 cryptoDataLen;
MV_U16 reserved1;
/* word 3 */
MV_U16 cryptoKeyOffset;
MV_U16 reserved2;
/* word 4 */
MV_U16 cryptoIvOffset;
MV_U16 cryptoIvBufOffset;
/* word 5 */
MV_U16 macSrcOffset;
MV_U16 macTotalLen;
/* word 6 */
MV_U16 macDigestOffset;
MV_U16 macDataLen;
/* word 7 */
MV_U16 macInnerIvOffset;
MV_U16 macOuterIvOffset;
} MV_CESA_DESC;
/* operation */
typedef enum
{
MV_CESA_MAC_ONLY = 0,
MV_CESA_CRYPTO_ONLY = 1,
MV_CESA_MAC_THEN_CRYPTO = 2,
MV_CESA_CRYPTO_THEN_MAC = 3,
MV_CESA_MAX_OPERATION
} MV_CESA_OPERATION;
#define MV_CESA_OPERATION_OFFSET 0
#define MV_CESA_OPERATION_MASK (0x3 << MV_CESA_OPERATION_OFFSET)
/* mac algorithm */
typedef enum
{
MV_CESA_MAC_NULL = 0,
MV_CESA_MAC_MD5 = 4,
MV_CESA_MAC_SHA1 = 5,
MV_CESA_MAC_HMAC_MD5 = 6,
MV_CESA_MAC_HMAC_SHA1 = 7,
} MV_CESA_MAC_MODE;
#define MV_CESA_MAC_MODE_OFFSET 4
#define MV_CESA_MAC_MODE_MASK (0x7 << MV_CESA_MAC_MODE_OFFSET)
typedef enum
{
MV_CESA_MAC_DIGEST_FULL = 0,
MV_CESA_MAC_DIGEST_96B = 1,
} MV_CESA_MAC_DIGEST_SIZE;
#define MV_CESA_MAC_DIGEST_SIZE_BIT 7
#define MV_CESA_MAC_DIGEST_SIZE_MASK (1 << MV_CESA_MAC_DIGEST_SIZE_BIT)
typedef enum
{
MV_CESA_CRYPTO_NULL = 0,
MV_CESA_CRYPTO_DES = 1,
MV_CESA_CRYPTO_3DES = 2,
MV_CESA_CRYPTO_AES = 3,
} MV_CESA_CRYPTO_ALG;
#define MV_CESA_CRYPTO_ALG_OFFSET 8
#define MV_CESA_CRYPTO_ALG_MASK (0x3 << MV_CESA_CRYPTO_ALG_OFFSET)
/* direction */
typedef enum
{
MV_CESA_DIR_ENCODE = 0,
MV_CESA_DIR_DECODE = 1,
} MV_CESA_DIRECTION;
#define MV_CESA_DIRECTION_BIT 12
#define MV_CESA_DIRECTION_MASK (1 << MV_CESA_DIRECTION_BIT)
/* crypto IV mode */
typedef enum
{
MV_CESA_CRYPTO_ECB = 0,
MV_CESA_CRYPTO_CBC = 1,
/* NO HW Support */
MV_CESA_CRYPTO_CTR = 10,
} MV_CESA_CRYPTO_MODE;
#define MV_CESA_CRYPTO_MODE_BIT 16
#define MV_CESA_CRYPTO_MODE_MASK (1 << MV_CESA_CRYPTO_MODE_BIT)
/* 3DES mode */
typedef enum
{
MV_CESA_CRYPTO_3DES_EEE = 0,
MV_CESA_CRYPTO_3DES_EDE = 1,
} MV_CESA_CRYPTO_3DES_MODE;
#define MV_CESA_CRYPTO_3DES_MODE_BIT 20
#define MV_CESA_CRYPTO_3DES_MODE_MASK (1 << MV_CESA_CRYPTO_3DES_MODE_BIT)
/* AES Key Length */
typedef enum
{
MV_CESA_CRYPTO_AES_KEY_128 = 0,
MV_CESA_CRYPTO_AES_KEY_192 = 1,
MV_CESA_CRYPTO_AES_KEY_256 = 2,
} MV_CESA_CRYPTO_AES_KEY_LEN;
#define MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET 24
#define MV_CESA_CRYPTO_AES_KEY_LEN_MASK (0x3 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET)
/* Fragmentation mode */
typedef enum
{
MV_CESA_FRAG_NONE = 0,
MV_CESA_FRAG_FIRST = 1,
MV_CESA_FRAG_LAST = 2,
MV_CESA_FRAG_MIDDLE = 3,
} MV_CESA_FRAG_MODE;
#define MV_CESA_FRAG_MODE_OFFSET 30
#define MV_CESA_FRAG_MODE_MASK (0x3 << MV_CESA_FRAG_MODE_OFFSET)
/*---------------------------------------------------------------------------*/
/********** Security Accelerator Command Register **************/
#define MV_CESA_CMD_REG (MV_CESA_REG_BASE + 0xE00)
#define MV_CESA_CMD_CHAN_ENABLE_BIT 0
#define MV_CESA_CMD_CHAN_ENABLE_MASK (1 << MV_CESA_CMD_CHAN_ENABLE_BIT)
#define MV_CESA_CMD_CHAN_DISABLE_BIT 2
#define MV_CESA_CMD_CHAN_DISABLE_MASK (1 << MV_CESA_CMD_CHAN_DISABLE_BIT)
/********** Security Accelerator Descriptor Pointers Register **********/
#define MV_CESA_CHAN_DESC_OFFSET_REG (MV_CESA_REG_BASE + 0xE04)
/********** Security Accelerator Configuration Register **********/
#define MV_CESA_CFG_REG (MV_CESA_REG_BASE + 0xE08)
#define MV_CESA_CFG_STOP_DIGEST_ERR_BIT 0
#define MV_CESA_CFG_STOP_DIGEST_ERR_MASK (1 << MV_CESA_CFG_STOP_DIGEST_ERR_BIT)
#define MV_CESA_CFG_WAIT_DMA_BIT 7
#define MV_CESA_CFG_WAIT_DMA_MASK (1 << MV_CESA_CFG_WAIT_DMA_BIT)
#define MV_CESA_CFG_ACT_DMA_BIT 9
#define MV_CESA_CFG_ACT_DMA_MASK (1 << MV_CESA_CFG_ACT_DMA_BIT)
#define MV_CESA_CFG_CHAIN_MODE_BIT 11
#define MV_CESA_CFG_CHAIN_MODE_MASK (1 << MV_CESA_CFG_CHAIN_MODE_BIT)
/********** Security Accelerator Status Register ***********/
#define MV_CESA_STATUS_REG (MV_CESA_REG_BASE + 0xE0C)
#define MV_CESA_STATUS_ACTIVE_BIT 0
#define MV_CESA_STATUS_ACTIVE_MASK (1 << MV_CESA_STATUS_ACTIVE_BIT)
#define MV_CESA_STATUS_DIGEST_ERR_BIT 8
#define MV_CESA_STATUS_DIGEST_ERR_MASK (1 << MV_CESA_STATUS_DIGEST_ERR_BIT)
/* Cryptographic Engines and Security Accelerator Interrupt Cause Register */
#define MV_CESA_ISR_CAUSE_REG (MV_CESA_REG_BASE + 0xE20)
/* Cryptographic Engines and Security Accelerator Interrupt Mask Register */
#define MV_CESA_ISR_MASK_REG (MV_CESA_REG_BASE + 0xE24)
#define MV_CESA_CAUSE_AUTH_MASK (1 << 0)
#define MV_CESA_CAUSE_DES_MASK (1 << 1)
#define MV_CESA_CAUSE_AES_ENCR_MASK (1 << 2)
#define MV_CESA_CAUSE_AES_DECR_MASK (1 << 3)
#define MV_CESA_CAUSE_DES_ALL_MASK (1 << 4)
#define MV_CESA_CAUSE_ACC_BIT 5
#define MV_CESA_CAUSE_ACC_MASK (1 << MV_CESA_CAUSE_ACC_BIT)
#define MV_CESA_CAUSE_ACC_DMA_BIT 7
#define MV_CESA_CAUSE_ACC_DMA_MASK (1 << MV_CESA_CAUSE_ACC_DMA_BIT)
#define MV_CESA_CAUSE_ACC_DMA_ALL_MASK (3 << MV_CESA_CAUSE_ACC_DMA_BIT)
#define MV_CESA_CAUSE_DMA_COMPL_BIT 9
#define MV_CESA_CAUSE_DMA_COMPL_MASK (1 << MV_CESA_CAUSE_DMA_COMPL_BIT)
#define MV_CESA_CAUSE_DMA_OWN_ERR_BIT 10
#define MV_CESA_CAUSE_DMA_OWN_ERR_MASK (1 < MV_CESA_CAUSE_DMA_OWN_ERR_BIT)
#define MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT 11
#define MV_CESA_CAUSE_DMA_CHAIN_PKT_MASK (1 < MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT)
#define MV_CESA_AUTH_DATA_IN_REG (MV_CESA_REG_BASE + 0xd38)
#define MV_CESA_AUTH_BIT_COUNT_LOW_REG (MV_CESA_REG_BASE + 0xd20)
#define MV_CESA_AUTH_BIT_COUNT_HIGH_REG (MV_CESA_REG_BASE + 0xd24)
#define MV_CESA_AUTH_INIT_VAL_DIGEST_REG(i) (MV_CESA_REG_BASE + 0xd00 + (i<<2))
#define MV_CESA_AUTH_INIT_VAL_DIGEST_A_REG (MV_CESA_REG_BASE + 0xd00)
#define MV_CESA_AUTH_INIT_VAL_DIGEST_B_REG (MV_CESA_REG_BASE + 0xd04)
#define MV_CESA_AUTH_INIT_VAL_DIGEST_C_REG (MV_CESA_REG_BASE + 0xd08)
#define MV_CESA_AUTH_INIT_VAL_DIGEST_D_REG (MV_CESA_REG_BASE + 0xd0c)
#define MV_CESA_AUTH_INIT_VAL_DIGEST_E_REG (MV_CESA_REG_BASE + 0xd10)
#define MV_CESA_AUTH_COMMAND_REG (MV_CESA_REG_BASE + 0xd18)
#define MV_CESA_AUTH_ALGORITHM_BIT 0
#define MV_CESA_AUTH_ALGORITHM_MD5 (0<<AUTH_ALGORITHM_BIT)
#define MV_CESA_AUTH_ALGORITHM_SHA1 (1<<AUTH_ALGORITHM_BIT)
#define MV_CESA_AUTH_IV_MODE_BIT 1
#define MV_CESA_AUTH_IV_MODE_INIT (0<<AUTH_IV_MODE_BIT)
#define MV_CESA_AUTH_IV_MODE_CONTINUE (1<<AUTH_IV_MODE_BIT)
#define MV_CESA_AUTH_DATA_BYTE_SWAP_BIT 2
#define MV_CESA_AUTH_DATA_BYTE_SWAP_MASK (1<<AUTH_DATA_BYTE_SWAP_BIT)
#define MV_CESA_AUTH_IV_BYTE_SWAP_BIT 4
#define MV_CESA_AUTH_IV_BYTE_SWAP_MASK (1<<AUTH_IV_BYTE_SWAP_BIT)
#define MV_CESA_AUTH_TERMINATION_BIT 31
#define MV_CESA_AUTH_TERMINATION_MASK (1<<AUTH_TERMINATION_BIT)
/*************** TDMA Control Register ************************************************/
#define MV_CESA_TDMA_CTRL_REG (MV_CESA_TDMA_REG_BASE + 0x840)
#define MV_CESA_TDMA_BURST_32B 3
#define MV_CESA_TDMA_BURST_128B 4
#define MV_CESA_TDMA_DST_BURST_OFFSET 0
#define MV_CESA_TDMA_DST_BURST_ALL_MASK (0x7<<MV_CESA_TDMA_DST_BURST_OFFSET)
#define MV_CESA_TDMA_DST_BURST_MASK(burst) ((burst)<<MV_CESA_TDMA_DST_BURST_OFFSET)
#define MV_CESA_TDMA_OUTSTAND_READ_EN_BIT 4
#define MV_CESA_TDMA_OUTSTAND_READ_EN_MASK (1<<MV_CESA_TDMA_OUTSTAND_READ_EN_BIT)
#define MV_CESA_TDMA_SRC_BURST_OFFSET 6
#define MV_CESA_TDMA_SRC_BURST_ALL_MASK (0x7<<MV_CESA_TDMA_SRC_BURST_OFFSET)
#define MV_CESA_TDMA_SRC_BURST_MASK(burst) ((burst)<<MV_CESA_TDMA_SRC_BURST_OFFSET)
#define MV_CESA_TDMA_CHAIN_MODE_BIT 9
#define MV_CESA_TDMA_NON_CHAIN_MODE_MASK (1<<MV_CESA_TDMA_CHAIN_MODE_BIT)
#define MV_CESA_TDMA_BYTE_SWAP_BIT 11
#define MV_CESA_TDMA_BYTE_SWAP_MASK (0 << MV_CESA_TDMA_BYTE_SWAP_BIT)
#define MV_CESA_TDMA_NO_BYTE_SWAP_MASK (1 << MV_CESA_TDMA_BYTE_SWAP_BIT)
#define MV_CESA_TDMA_ENABLE_BIT 12
#define MV_CESA_TDMA_ENABLE_MASK (1<<MV_CESA_TDMA_ENABLE_BIT)
#define MV_CESA_TDMA_FETCH_NEXT_DESC_BIT 13
#define MV_CESA_TDMA_FETCH_NEXT_DESC_MASK (1<<MV_CESA_TDMA_FETCH_NEXT_DESC_BIT)
#define MV_CESA_TDMA_CHAN_ACTIVE_BIT 14
#define MV_CESA_TDMA_CHAN_ACTIVE_MASK (1<<MV_CESA_TDMA_CHAN_ACTIVE_BIT)
/*------------------------------------------------------------------------------------*/
#define MV_CESA_TDMA_BYTE_COUNT_REG (MV_CESA_TDMA_REG_BASE + 0x800)
#define MV_CESA_TDMA_SRC_ADDR_REG (MV_CESA_TDMA_REG_BASE + 0x810)
#define MV_CESA_TDMA_DST_ADDR_REG (MV_CESA_TDMA_REG_BASE + 0x820)
#define MV_CESA_TDMA_NEXT_DESC_PTR_REG (MV_CESA_TDMA_REG_BASE + 0x830)
#define MV_CESA_TDMA_CURR_DESC_PTR_REG (MV_CESA_TDMA_REG_BASE + 0x870)
#define MV_CESA_TDMA_ERROR_CAUSE_REG (MV_CESA_TDMA_REG_BASE + 0x8C0)
#define MV_CESA_TDMA_ERROR_MASK_REG (MV_CESA_TDMA_REG_BASE + 0x8C4)
#endif /* __mvCesaRegs_h__ */

3096
target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvCesaTest.c
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4
target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvCompVer.txt
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@ -1,4 +0,0 @@
Global HAL Version: FEROCEON_HAL_3_1_7
Unit HAL Version: 3.1.4
Description: This component includes an implementation of the unit HAL drivers

158
target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvLru.c
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@ -1,158 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "mvOs.h"
#include "mvLru.h"
/* LRU Cache support */
/* Init LRU cache database */
MV_LRU_CACHE* mvLruCacheInit(int numOfEntries)
{
int i;
MV_LRU_CACHE* pLruCache;
pLruCache = mvOsMalloc(sizeof(MV_LRU_CACHE));
if(pLruCache == NULL)
{
return NULL;
}
memset(pLruCache, 0, sizeof(MV_LRU_CACHE));
pLruCache->table = mvOsMalloc(numOfEntries*sizeof(MV_LRU_ENTRY));
if(pLruCache->table == NULL)
{
mvOsFree(pLruCache);
return NULL;
}
memset(pLruCache->table, 0, numOfEntries*sizeof(MV_LRU_ENTRY));
pLruCache->tableSize = numOfEntries;
for(i=0; i<numOfEntries; i++)
{
pLruCache->table[i].next = i+1;
pLruCache->table[i].prev = i-1;
}
pLruCache->least = 0;
pLruCache->most = numOfEntries-1;
return pLruCache;
}
void mvLruCacheFinish(MV_LRU_CACHE* pLruCache)
{
mvOsFree(pLruCache->table);
mvOsFree(pLruCache);
}
/* Update LRU cache database after using cache Index */
void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx)
{
int prev, next;
if(cacheIdx == pLruHndl->most)
return;
next = pLruHndl->table[cacheIdx].next;
if(cacheIdx == pLruHndl->least)
{
pLruHndl->least = next;
}
else
{
prev = pLruHndl->table[cacheIdx].prev;
pLruHndl->table[next].prev = prev;
pLruHndl->table[prev].next = next;
}
pLruHndl->table[pLruHndl->most].next = cacheIdx;
pLruHndl->table[cacheIdx].prev = pLruHndl->most;
pLruHndl->most = cacheIdx;
}
/* Delete LRU cache entry */
void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx)
{
int prev, next;
if(cacheIdx == pLruHndl->least)
return;
prev = pLruHndl->table[cacheIdx].prev;
if(cacheIdx == pLruHndl->most)
{
pLruHndl->most = prev;
}
else
{
next = pLruHndl->table[cacheIdx].next;
pLruHndl->table[next].prev = prev;
pLruHndl->table[prev].next = next;
}
pLruHndl->table[pLruHndl->least].prev = cacheIdx;
pLruHndl->table[cacheIdx].next = pLruHndl->least;
pLruHndl->least = cacheIdx;
}

112
target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvLru.h
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@ -1,112 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/*******************************************************************************
* mvLru.h - Header File for Least Recently Used Cache algorithm
*
* DESCRIPTION:
* This header file contains macros typedefs and function declaration for
* the Least Recently Used Cache algorithm.
*
*******************************************************************************/
#ifndef __mvLru_h__
#define __mvLru_h__
typedef struct
{
int next;
int prev;
} MV_LRU_ENTRY;
typedef struct
{
int least;
int most;
MV_LRU_ENTRY* table;
int tableSize;
}MV_LRU_CACHE;
/* Find Cache index for replacement LRU */
static INLINE int mvLruCacheIdxFind(MV_LRU_CACHE* pLruHndl)
{
return pLruHndl->least;
}
/* Init LRU cache module */
MV_LRU_CACHE* mvLruCacheInit(int numOfEntries);
/* Finish LRU cache module */
void mvLruCacheFinish(MV_LRU_CACHE* pLruHndl);
/* Update LRU cache database after using cache Index */
void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx);
/* Delete LRU cache entry */
void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx);
#endif /* __mvLru_h__ */

349
target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvMD5.c
View File

@ -1,349 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "mvOs.h"
#include "mvMD5.h"
static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]);
#ifdef MV_CPU_LE
#define mvByteReverse(buf, len) /* Nothing */
#else
static void mvByteReverse(unsigned char *buf, unsigned longs);
/*
* Note: this code is harmless on little-endian machines.
*/
static void mvByteReverse(unsigned char *buf, unsigned longs)
{
MV_U32 t;
do
{
t = (MV_U32) ((unsigned) buf[3] << 8 | buf[2]) << 16 |
((unsigned) buf[1] << 8 | buf[0]);
*(MV_U32 *) buf = t;
buf += 4;
} while (--longs);
}
#endif
/*
* Start MD5 accumulation. Set bit count to 0 and buffer to mysterious
* initialization constants.
*/
void mvMD5Init(MV_MD5_CONTEXT *ctx)
{
ctx->buf[0] = 0x67452301;
ctx->buf[1] = 0xefcdab89;
ctx->buf[2] = 0x98badcfe;
ctx->buf[3] = 0x10325476;
ctx->bits[0] = 0;
ctx->bits[1] = 0;
}
/*
* Update context to reflect the concatenation of another buffer full
* of bytes.
*/
void mvMD5Update(MV_MD5_CONTEXT *ctx, unsigned char const *buf, unsigned len)
{
MV_U32 t;
/* Update bitcount */
t = ctx->bits[0];
if ((ctx->bits[0] = t + ((MV_U32) len << 3)) < t)
ctx->bits[1]++; /* Carry from low to high */
ctx->bits[1] += len >> 29;
t = (t >> 3) & 0x3f; /* Bytes already in shsInfo->data */
/* Handle any leading odd-sized chunks */
if (t)
{
unsigned char *p = (unsigned char *) ctx->in + t;
t = 64 - t;
if (len < t)
{
memcpy(p, buf, len);
return;
}
memcpy(p, buf, t);
mvByteReverse(ctx->in, MV_MD5_MAC_LEN);
mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in);
buf += t;
len -= t;
}
/* Process data in 64-byte chunks */
while (len >= 64)
{
memcpy(ctx->in, buf, 64);
mvByteReverse(ctx->in, MV_MD5_MAC_LEN);
mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in);
buf += 64;
len -= 64;
}
/* Handle any remaining bytes of data. */
memcpy(ctx->in, buf, len);
}
/*
* Final wrapup - pad to 64-byte boundary with the bit pattern
* 1 0* (64-bit count of bits processed, MSB-first)
*/
void mvMD5Final(unsigned char digest[MV_MD5_MAC_LEN], MV_MD5_CONTEXT *ctx)
{
unsigned count;
unsigned char *p;
/* Compute number of bytes mod 64 */
count = (ctx->bits[0] >> 3) & 0x3F;
/* Set the first char of padding to 0x80. This is safe since there is
always at least one byte free */
p = ctx->in + count;
*p++ = 0x80;
/* Bytes of padding needed to make 64 bytes */
count = 64 - 1 - count;
/* Pad out to 56 mod 64 */
if (count < 8)
{
/* Two lots of padding: Pad the first block to 64 bytes */
memset(p, 0, count);
mvByteReverse(ctx->in, MV_MD5_MAC_LEN);
mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in);
/* Now fill the next block with 56 bytes */
memset(ctx->in, 0, 56);
}
else
{
/* Pad block to 56 bytes */
memset(p, 0, count - 8);
}
mvByteReverse(ctx->in, 14);
/* Append length in bits and transform */
((MV_U32 *) ctx->in)[14] = ctx->bits[0];
((MV_U32 *) ctx->in)[15] = ctx->bits[1];
mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in);
mvByteReverse((unsigned char *) ctx->buf, 4);
memcpy(digest, ctx->buf, MV_MD5_MAC_LEN);
memset(ctx, 0, sizeof(ctx)); /* In case it's sensitive */
}
/* The four core functions - F1 is optimized somewhat */
/* #define F1(x, y, z) (x & y | ~x & z) */
#define F1(x, y, z) (z ^ (x & (y ^ z)))
#define F2(x, y, z) F1(z, x, y)
#define F3(x, y, z) (x ^ y ^ z)
#define F4(x, y, z) (y ^ (x | ~z))
/* This is the central step in the MD5 algorithm. */
#define MD5STEP(f, w, x, y, z, data, s) \
( w += f(x, y, z) + data, w = w<<s | w>>(32-s), w += x )
/*
* The core of the MD5 algorithm, this alters an existing MD5 hash to
* reflect the addition of 16 longwords of new data. MD5Update blocks
* the data and converts bytes into longwords for this routine.
*/
static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN])
{
register MV_U32 a, b, c, d;
a = buf[0];
b = buf[1];
c = buf[2];
d = buf[3];
MD5STEP(F1, a, b, c, d, in[0] + 0xd76aa478, 7);
MD5STEP(F1, d, a, b, c, in[1] + 0xe8c7b756, 12);
MD5STEP(F1, c, d, a, b, in[2] + 0x242070db, 17);
MD5STEP(F1, b, c, d, a, in[3] + 0xc1bdceee, 22);
MD5STEP(F1, a, b, c, d, in[4] + 0xf57c0faf, 7);
MD5STEP(F1, d, a, b, c, in[5] + 0x4787c62a, 12);
MD5STEP(F1, c, d, a, b, in[6] + 0xa8304613, 17);
MD5STEP(F1, b, c, d, a, in[7] + 0xfd469501, 22);
MD5STEP(F1, a, b, c, d, in[8] + 0x698098d8, 7);
MD5STEP(F1, d, a, b, c, in[9] + 0x8b44f7af, 12);
MD5STEP(F1, c, d, a, b, in[10] + 0xffff5bb1, 17);
MD5STEP(F1, b, c, d, a, in[11] + 0x895cd7be, 22);
MD5STEP(F1, a, b, c, d, in[12] + 0x6b901122, 7);
MD5STEP(F1, d, a, b, c, in[13] + 0xfd987193, 12);
MD5STEP(F1, c, d, a, b, in[14] + 0xa679438e, 17);
MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22);
MD5STEP(F2, a, b, c, d, in[1] + 0xf61e2562, 5);
MD5STEP(F2, d, a, b, c, in[6] + 0xc040b340, 9);
MD5STEP(F2, c, d, a, b, in[11] + 0x265e5a51, 14);
MD5STEP(F2, b, c, d, a, in[0] + 0xe9b6c7aa, 20);
MD5STEP(F2, a, b, c, d, in[5] + 0xd62f105d, 5);
MD5STEP(F2, d, a, b, c, in[10] + 0x02441453, 9);
MD5STEP(F2, c, d, a, b, in[15] + 0xd8a1e681, 14);
MD5STEP(F2, b, c, d, a, in[4] + 0xe7d3fbc8, 20);
MD5STEP(F2, a, b, c, d, in[9] + 0x21e1cde6, 5);
MD5STEP(F2, d, a, b, c, in[14] + 0xc33707d6, 9);
MD5STEP(F2, c, d, a, b, in[3] + 0xf4d50d87, 14);
MD5STEP(F2, b, c, d, a, in[8] + 0x455a14ed, 20);
MD5STEP(F2, a, b, c, d, in[13] + 0xa9e3e905, 5);
MD5STEP(F2, d, a, b, c, in[2] + 0xfcefa3f8, 9);
MD5STEP(F2, c, d, a, b, in[7] + 0x676f02d9, 14);
MD5STEP(F2, b, c, d, a, in[12] + 0x8d2a4c8a, 20);
MD5STEP(F3, a, b, c, d, in[5] + 0xfffa3942, 4);
MD5STEP(F3, d, a, b, c, in[8] + 0x8771f681, 11);
MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16);
MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23);
MD5STEP(F3, a, b, c, d, in[1] + 0xa4beea44, 4);
MD5STEP(F3, d, a, b, c, in[4] + 0x4bdecfa9, 11);
MD5STEP(F3, c, d, a, b, in[7] + 0xf6bb4b60, 16);
MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23);
MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4);
MD5STEP(F3, d, a, b, c, in[0] + 0xeaa127fa, 11);
MD5STEP(F3, c, d, a, b, in[3] + 0xd4ef3085, 16);
MD5STEP(F3, b, c, d, a, in[6] + 0x04881d05, 23);
MD5STEP(F3, a, b, c, d, in[9] + 0xd9d4d039, 4);
MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11);
MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16);
MD5STEP(F3, b, c, d, a, in[2] + 0xc4ac5665, 23);
MD5STEP(F4, a, b, c, d, in[0] + 0xf4292244, 6);
MD5STEP(F4, d, a, b, c, in[7] + 0x432aff97, 10);
MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15);
MD5STEP(F4, b, c, d, a, in[5] + 0xfc93a039, 21);
MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6);
MD5STEP(F4, d, a, b, c, in[3] + 0x8f0ccc92, 10);
MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15);
MD5STEP(F4, b, c, d, a, in[1] + 0x85845dd1, 21);
MD5STEP(F4, a, b, c, d, in[8] + 0x6fa87e4f, 6);
MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10);
MD5STEP(F4, c, d, a, b, in[6] + 0xa3014314, 15);
MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21);
MD5STEP(F4, a, b, c, d, in[4] + 0xf7537e82, 6);
MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10);
MD5STEP(F4, c, d, a, b, in[2] + 0x2ad7d2bb, 15);
MD5STEP(F4, b, c, d, a, in[9] + 0xeb86d391, 21);
buf[0] += a;
buf[1] += b;
buf[2] += c;
buf[3] += d;
}
void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest)
{
MV_MD5_CONTEXT ctx;
mvMD5Init(&ctx);
mvMD5Update(&ctx, buf, len);
mvMD5Final(digest, &ctx);
}
void mvHmacMd5(unsigned char const* text, int text_len,
unsigned char const* key, int key_len,
unsigned char* digest)
{
int i;
MV_MD5_CONTEXT ctx;
unsigned char k_ipad[64+1]; /* inner padding - key XORd with ipad */
unsigned char k_opad[64+1]; /* outer padding - key XORd with opad */
/* start out by storing key in pads */
memset(k_ipad, 0, 64);
memcpy(k_ipad, key, key_len);
memset(k_opad, 0, 64);
memcpy(k_opad, key, key_len);
/* XOR key with ipad and opad values */
for (i=0; i<64; i++)
{
k_ipad[i] ^= 0x36;
k_opad[i] ^= 0x5c;
}
/* perform inner MD5 */
mvMD5Init(&ctx); /* init ctx for 1st pass */
mvMD5Update(&ctx, k_ipad, 64); /* start with inner pad */
mvMD5Update(&ctx, text, text_len); /* then text of datagram */
mvMD5Final(digest, &ctx); /* finish up 1st pass */
/* perform outer MD5 */
mvMD5Init(&ctx); /* init ctx for 2nd pass */
mvMD5Update(&ctx, k_opad, 64); /* start with outer pad */
mvMD5Update(&ctx, digest, 16); /* then results of 1st hash */
mvMD5Final(digest, &ctx); /* finish up 2nd pass */
}

93
target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvMD5.h
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@ -1,93 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __mvMD5_h__
#define __mvMD5_h__
#include "mvMD5.h"
#define MV_MD5_MAC_LEN 16
typedef struct
{
MV_U32 buf[4];
MV_U32 bits[2];
MV_U8 in[64];
} MV_MD5_CONTEXT;
void mvMD5Init(MV_MD5_CONTEXT *context);
void mvMD5Update(MV_MD5_CONTEXT *context, unsigned char const *buf,
unsigned len);
void mvMD5Final(unsigned char digest[16], MV_MD5_CONTEXT *context);
void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest);
void mvHmacMd5(unsigned char const* text, int text_len,
unsigned char const* key, int key_len,
unsigned char* digest);
#endif /* __mvMD5_h__ */

239
target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvSHA1.c
View File

@ -1,239 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "mvOs.h"
#include "mvSHA1.h"
#define SHA1HANDSOFF
typedef union
{
MV_U8 c[64];
MV_U32 l[16];
} CHAR64LONG16;
static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer);
#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits))))
#ifdef MV_CPU_LE
#define blk0(i) (block->l[i] = (rol(block->l[i], 24) & 0xFF00FF00) | \
(rol(block->l[i], 8) & 0x00FF00FF))
#else
#define blk0(i) block->l[i]
#endif
#define blk(i) (block->l[i & 15] = rol(block->l[(i + 13) & 15] ^ \
block->l[(i + 8) & 15] ^ block->l[(i + 2) & 15] ^ block->l[i & 15], 1))
/* (R0+R1), R2, R3, R4 are the different operations used in SHA1 */
#define R0(v,w,x,y,z,i) \
z += ((w & (x ^ y)) ^ y) + blk0(i) + 0x5A827999 + rol(v, 5); \
w = rol(w, 30);
#define R1(v,w,x,y,z,i) \
z += ((w & (x ^ y)) ^ y) + blk(i) + 0x5A827999 + rol(v, 5); \
w = rol(w, 30);
#define R2(v,w,x,y,z,i) \
z += (w ^ x ^ y) + blk(i) + 0x6ED9EBA1 + rol(v, 5); w = rol(w, 30);
#define R3(v,w,x,y,z,i) \
z += (((w | x) & y) | (w & x)) + blk(i) + 0x8F1BBCDC + rol(v, 5); \
w = rol(w, 30);
#define R4(v,w,x,y,z,i) \
z += (w ^ x ^ y) + blk(i) + 0xCA62C1D6 + rol(v, 5); \
w=rol(w, 30);
/* Hash a single 512-bit block. This is the core of the algorithm. */
static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer)
{
MV_U32 a, b, c, d, e;
CHAR64LONG16* block;
#ifdef SHA1HANDSOFF
static MV_U32 workspace[16];
block = (CHAR64LONG16 *) workspace;
memcpy(block, buffer, 64);
#else
block = (CHAR64LONG16 *) buffer;
#endif
/* Copy context->state[] to working vars */
a = state[0];
b = state[1];
c = state[2];
d = state[3];
e = state[4];
/* 4 rounds of 20 operations each. Loop unrolled. */
R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3);
R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7);
R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11);
R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15);
R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19);
R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23);
R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27);
R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31);
R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35);
R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39);
R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43);
R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47);
R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51);
R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55);
R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59);
R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63);
R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67);
R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71);
R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75);
R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79);
/* Add the working vars back into context.state[] */
state[0] += a;
state[1] += b;
state[2] += c;
state[3] += d;
state[4] += e;
/* Wipe variables */
a = b = c = d = e = 0;
}
void mvSHA1Init(MV_SHA1_CTX* context)
{
/* SHA1 initialization constants */
context->state[0] = 0x67452301;
context->state[1] = 0xEFCDAB89;
context->state[2] = 0x98BADCFE;
context->state[3] = 0x10325476;
context->state[4] = 0xC3D2E1F0;
context->count[0] = context->count[1] = 0;
}
/* Run your data through this. */
void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *data,
unsigned int len)
{
MV_U32 i, j;
j = (context->count[0] >> 3) & 63;
if ((context->count[0] += len << 3) < (len << 3))
context->count[1]++;
context->count[1] += (len >> 29);
if ((j + len) > 63)
{
memcpy(&context->buffer[j], data, (i = 64-j));
mvSHA1Transform(context->state, context->buffer);
for ( ; i + 63 < len; i += 64)
{
mvSHA1Transform(context->state, &data[i]);
}
j = 0;
}
else
{
i = 0;
}
memcpy(&context->buffer[j], &data[i], len - i);
}
void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX* context)
{
MV_U32 i;
MV_U8 finalcount[8];
for (i = 0; i < 8; i++)
{
finalcount[i] = (unsigned char)((context->count[(i >= 4 ? 0 : 1)] >>
((3-(i & 3)) * 8) ) & 255); /* Endian independent */
}
mvSHA1Update(context, (const unsigned char *) "\200", 1);
while ((context->count[0] & 504) != 448)
{
mvSHA1Update(context, (const unsigned char *) "\0", 1);
}
mvSHA1Update(context, finalcount, 8); /* Should cause a mvSHA1Transform()
*/
for (i = 0; i < 20; i++)
{
digest[i] = (unsigned char)
((context->state[i >> 2] >> ((3 - (i & 3)) * 8)) & 255);
}
/* Wipe variables */
i = 0;
memset(context->buffer, 0, 64);
memset(context->state, 0, 20);
memset(context->count, 0, 8);
memset(finalcount, 0, 8);
#ifdef SHA1HANDSOFF /* make SHA1Transform overwrite it's own static vars */
mvSHA1Transform(context->state, context->buffer);
#endif
}
void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest)
{
MV_SHA1_CTX ctx;
mvSHA1Init(&ctx);
mvSHA1Update(&ctx, buf, len);
mvSHA1Final(digest, &ctx);
}

88
target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvSHA1.h
View File

@ -1,88 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __mvSHA1_h__
#define __mvSHA1_h__
#include "mvSHA1.h"
#define MV_SHA1_MAC_LEN 20
typedef struct
{
MV_U32 state[5];
MV_U32 count[2];
MV_U8 buffer[64];
} MV_SHA1_CTX;
void mvSHA1Init(MV_SHA1_CTX *context);
void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *buf, unsigned int len);
void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX *context);
void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest);
#endif /* __mvSHA1_h__ */

1302
target/linux/generic/files/crypto/ocf/kirkwood/cesa_ocf_drv.c
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File diff suppressed because it is too large Load Diff

213
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mv802_3.h
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@ -1,213 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmv802_3h
#define __INCmv802_3h
/* includes */
#include "mvTypes.h"
/* Defines */
#define MV_MAX_ETH_DATA 1500
/* 802.3 types */
#define MV_IP_TYPE 0x0800
#define MV_IP_ARP_TYPE 0x0806
#define MV_APPLE_TALK_ARP_TYPE 0x80F3
#define MV_NOVELL_IPX_TYPE 0x8137
#define MV_EAPOL_TYPE 0x888e
/* Encapsulation header for RFC1042 and Ethernet_tunnel */
#define MV_RFC1042_SNAP_HEADER {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00}
#define MV_ETH_SNAP_LSB 0xF8
#define MV_MAC_ADDR_SIZE (6)
#define MV_MAC_STR_SIZE (20)
#define MV_VLAN_HLEN (4)
/* This macro checks for a multicast mac address */
#define MV_IS_MULTICAST_MAC(mac) (((mac)[0] & 0x1) == 1)
/* This macro checks for an broadcast mac address */
#define MV_IS_BROADCAST_MAC(mac) \
(((mac)[0] == 0xFF) && \
((mac)[1] == 0xFF) && \
((mac)[2] == 0xFF) && \
((mac)[3] == 0xFF) && \
((mac)[4] == 0xFF) && \
((mac)[5] == 0xFF))
/* Typedefs */
typedef struct
{
MV_U8 pDA[MV_MAC_ADDR_SIZE];
MV_U8 pSA[MV_MAC_ADDR_SIZE];
MV_U16 typeOrLen;
} MV_802_3_HEADER;
enum {
MV_IP_PROTO_NULL = 0, /* Dummy protocol for TCP */
MV_IP_PROTO_ICMP = 1, /* Internet Control Message Protocol */
MV_IP_PROTO_IGMP = 2, /* Internet Group Management Protocol */
MV_IP_PROTO_IPIP = 4, /* IPIP tunnels (older KA9Q tunnels use 94) */
MV_IP_PROTO_TCP = 6, /* Transmission Control Protocol */
MV_IP_PROTO_EGP = 8, /* Exterior Gateway Protocol */
MV_IP_PROTO_PUP = 12, /* PUP protocol */
MV_IP_PROTO_UDP = 17, /* User Datagram Protocol */
MV_IP_PROTO_IDP = 22, /* XNS IDP protocol */
MV_IP_PROTO_DCCP = 33, /* Datagram Congestion Control Protocol */
MV_IP_PROTO_IPV6 = 41, /* IPv6-in-IPv4 tunnelling */
MV_IP_PROTO_RSVP = 46, /* RSVP protocol */
MV_IP_PROTO_GRE = 47, /* Cisco GRE tunnels (rfc 1701,1702) */
MV_IP_PROTO_ESP = 50, /* Encapsulation Security Payload protocol */
MV_IP_PROTO_AH = 51, /* Authentication Header protocol */
MV_IP_PROTO_BEETPH = 94, /* IP option pseudo header for BEET */
MV_IP_PROTO_PIM = 103,
MV_IP_PROTO_COMP = 108, /* Compression Header protocol */
MV_IP_PROTO_ZERO_HOP = 114, /* Any 0 hop protocol (IANA) */
MV_IP_PROTO_SCTP = 132, /* Stream Control Transport Protocol */
MV_IP_PROTO_UDPLITE = 136, /* UDP-Lite (RFC 3828) */
MV_IP_PROTO_RAW = 255, /* Raw IP packets */
MV_IP_PROTO_MAX
};
typedef struct
{
MV_U8 version;
MV_U8 tos;
MV_U16 totalLength;
MV_U16 identifier;
MV_U16 fragmentCtrl;
MV_U8 ttl;
MV_U8 protocol;
MV_U16 checksum;
MV_U32 srcIP;
MV_U32 dstIP;
} MV_IP_HEADER;
typedef struct
{
MV_U32 spi;
MV_U32 seqNum;
} MV_ESP_HEADER;
#define MV_ICMP_ECHOREPLY 0 /* Echo Reply */
#define MV_ICMP_DEST_UNREACH 3 /* Destination Unreachable */
#define MV_ICMP_SOURCE_QUENCH 4 /* Source Quench */
#define MV_ICMP_REDIRECT 5 /* Redirect (change route) */
#define MV_ICMP_ECHO 8 /* Echo Request */
#define MV_ICMP_TIME_EXCEEDED 11 /* Time Exceeded */
#define MV_ICMP_PARAMETERPROB 12 /* Parameter Problem */
#define MV_ICMP_TIMESTAMP 13 /* Timestamp Request */
#define MV_ICMP_TIMESTAMPREPLY 14 /* Timestamp Reply */
#define MV_ICMP_INFO_REQUEST 15 /* Information Request */
#define MV_ICMP_INFO_REPLY 16 /* Information Reply */
#define MV_ICMP_ADDRESS 17 /* Address Mask Request */
#define MV_ICMP_ADDRESSREPLY 18 /* Address Mask Reply */
typedef struct
{
MV_U8 type;
MV_U8 code;
MV_U16 checksum;
MV_U16 id;
MV_U16 sequence;
} MV_ICMP_ECHO_HEADER;
typedef struct
{
MV_U16 source;
MV_U16 dest;
MV_U32 seq;
MV_U32 ack_seq;
MV_U16 flags;
MV_U16 window;
MV_U16 chksum;
MV_U16 urg_offset;
} MV_TCP_HEADER;
typedef struct
{
MV_U16 source;
MV_U16 dest;
MV_U16 len;
MV_U16 check;
} MV_UDP_HEADER;
#endif /* __INCmv802_3h */

277
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvCommon.c
View File

@ -1,277 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "mvOs.h"
#include "mv802_3.h"
#include "mvCommon.h"
/*******************************************************************************
* mvMacStrToHex - Convert MAC format string to hex.
*
* DESCRIPTION:
* This function convert MAC format string to hex.
*
* INPUT:
* macStr - MAC address string. Fornat of address string is
* uu:vv:ww:xx:yy:zz, where ":" can be any delimiter.
*
* OUTPUT:
* macHex - MAC in hex format.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_STATUS mvMacStrToHex(const char* macStr, MV_U8* macHex)
{
int i;
char tmp[3];
for(i = 0; i < MV_MAC_ADDR_SIZE; i++)
{
tmp[0] = macStr[(i * 3) + 0];
tmp[1] = macStr[(i * 3) + 1];
tmp[2] = '\0';
macHex[i] = (MV_U8) (strtol(tmp, NULL, 16));
}
return MV_OK;
}
/*******************************************************************************
* mvMacHexToStr - Convert MAC in hex format to string format.
*
* DESCRIPTION:
* This function convert MAC in hex format to string format.
*
* INPUT:
* macHex - MAC in hex format.
*
* OUTPUT:
* macStr - MAC address string. String format is uu:vv:ww:xx:yy:zz.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_STATUS mvMacHexToStr(MV_U8* macHex, char* macStr)
{
int i;
for(i = 0; i < MV_MAC_ADDR_SIZE; i++)
{
mvOsSPrintf(&macStr[i * 3], "%02x:", macHex[i]);
}
macStr[(i * 3) - 1] = '\0';
return MV_OK;
}
/*******************************************************************************
* mvSizePrint - Print the given size with size unit description.
*
* DESCRIPTION:
* This function print the given size with size unit description.
* FOr example when size paramter is 0x180000, the function prints:
* "size 1MB+500KB"
*
* INPUT:
* size - Size in bytes.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvSizePrint(MV_U32 size)
{
mvOsOutput("size ");
if(size >= _1G)
{
mvOsOutput("%3dGB ", size / _1G);
size %= _1G;
if(size)
mvOsOutput("+");
}
if(size >= _1M )
{
mvOsOutput("%3dMB ", size / _1M);
size %= _1M;
if(size)
mvOsOutput("+");
}
if(size >= _1K)
{
mvOsOutput("%3dKB ", size / _1K);
size %= _1K;
if(size)
mvOsOutput("+");
}
if(size > 0)
{
mvOsOutput("%3dB ", size);
}
}
/*******************************************************************************
* mvHexToBin - Convert hex to binary
*
* DESCRIPTION:
* This function Convert hex to binary.
*
* INPUT:
* pHexStr - hex buffer pointer.
* size - Size to convert.
*
* OUTPUT:
* pBin - Binary buffer pointer.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size)
{
int j, i;
char tmp[3];
MV_U8 byte;
for(j=0, i=0; j<size; j++, i+=2)
{
tmp[0] = pHexStr[i];
tmp[1] = pHexStr[i+1];
tmp[2] = '\0';
byte = (MV_U8) (strtol(tmp, NULL, 16) & 0xFF);
pBin[j] = byte;
}
}
void mvAsciiToHex(const char* asciiStr, char* hexStr)
{
int i=0;
while(asciiStr[i] != 0)
{
mvOsSPrintf(&hexStr[i*2], "%02x", asciiStr[i]);
i++;
}
hexStr[i*2] = 0;
}
void mvBinToHex(const MV_U8* bin, char* hexStr, int size)
{
int i;
for(i=0; i<size; i++)
{
mvOsSPrintf(&hexStr[i*2], "%02x", bin[i]);
}
hexStr[i*2] = '\0';
}
void mvBinToAscii(const MV_U8* bin, char* asciiStr, int size)
{
int i;
for(i=0; i<size; i++)
{
mvOsSPrintf(&asciiStr[i*2], "%c", bin[i]);
}
asciiStr[i*2] = '\0';
}
/*******************************************************************************
* mvLog2 -
*
* DESCRIPTION:
* Calculate the Log2 of a given number.
*
* INPUT:
* num - A number to calculate the Log2 for.
*
* OUTPUT:
* None.
*
* RETURN:
* Log 2 of the input number, or 0xFFFFFFFF if input is 0.
*
*******************************************************************************/
MV_U32 mvLog2(MV_U32 num)
{
MV_U32 result = 0;
if(num == 0)
return 0xFFFFFFFF;
while(num != 1)
{
num = num >> 1;
result++;
}
return result;
}

308
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvCommon.h
View File

@ -1,308 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvCommonh
#define __INCmvCommonh
#include "mvTypes.h"
/* Swap tool */
/* 16bit nibble swap. For example 0x1234 -> 0x2143 */
#define MV_NIBBLE_SWAP_16BIT(X) (((X&0xf) << 4) | \
((X&0xf0) >> 4) | \
((X&0xf00) << 4) | \
((X&0xf000) >> 4))
/* 32bit nibble swap. For example 0x12345678 -> 0x21436587 */
#define MV_NIBBLE_SWAP_32BIT(X) (((X&0xf) << 4) | \
((X&0xf0) >> 4) | \
((X&0xf00) << 4) | \
((X&0xf000) >> 4) | \
((X&0xf0000) << 4) | \
((X&0xf00000) >> 4) | \
((X&0xf000000) << 4) | \
((X&0xf0000000) >> 4))
/* 16bit byte swap. For example 0x1122 -> 0x2211 */
#define MV_BYTE_SWAP_16BIT(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8))
/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */
#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \
(((X)&0xff00)<<8) | \
(((X)&0xff0000)>>8) | \
(((X)&0xff000000)>>24))
/* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211 */
#define MV_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xffULL)<<56) | \
(((X)&0xff00ULL)<<40) | \
(((X)&0xff0000ULL)<<24) | \
(((X)&0xff000000ULL)<<8) | \
(((X)&0xff00000000ULL)>>8) | \
(((X)&0xff0000000000ULL)>>24) | \
(((X)&0xff000000000000ULL)>>40) | \
(((X)&0xff00000000000000ULL)>>56)))
/* Endianess macros. */
#if defined(MV_CPU_LE)
#define MV_16BIT_LE(X) (X)
#define MV_32BIT_LE(X) (X)
#define MV_64BIT_LE(X) (X)
#define MV_16BIT_BE(X) MV_BYTE_SWAP_16BIT(X)
#define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X)
#define MV_64BIT_BE(X) MV_BYTE_SWAP_64BIT(X)
#elif defined(MV_CPU_BE)
#define MV_16BIT_LE(X) MV_BYTE_SWAP_16BIT(X)
#define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X)
#define MV_64BIT_LE(X) MV_BYTE_SWAP_64BIT(X)
#define MV_16BIT_BE(X) (X)
#define MV_32BIT_BE(X) (X)
#define MV_64BIT_BE(X) (X)
#else
#error "CPU endianess isn't defined!\n"
#endif
/* Bit field definitions */
#define NO_BIT 0x00000000
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
/* Handy sizes */
#define _1K 0x00000400
#define _2K 0x00000800
#define _4K 0x00001000
#define _8K 0x00002000
#define _16K 0x00004000
#define _32K 0x00008000
#define _64K 0x00010000
#define _128K 0x00020000
#define _256K 0x00040000
#define _512K 0x00080000
#define _1M 0x00100000
#define _2M 0x00200000
#define _4M 0x00400000
#define _8M 0x00800000
#define _16M 0x01000000
#define _32M 0x02000000
#define _64M 0x04000000
#define _128M 0x08000000
#define _256M 0x10000000
#define _512M 0x20000000
#define _1G 0x40000000
#define _2G 0x80000000
/* Tclock and Sys clock define */
#define _100MHz 100000000
#define _125MHz 125000000
#define _133MHz 133333334
#define _150MHz 150000000
#define _160MHz 160000000
#define _166MHz 166666667
#define _175MHz 175000000
#define _178MHz 178000000
#define _183MHz 183333334
#define _187MHz 187000000
#define _192MHz 192000000
#define _194MHz 194000000
#define _200MHz 200000000
#define _233MHz 233333334
#define _250MHz 250000000
#define _266MHz 266666667
#define _300MHz 300000000
/* For better address window table readability */
#define EN MV_TRUE
#define DIS MV_FALSE
#define N_A -1 /* Not applicable */
/* Cache configuration options for memory (DRAM, SRAM, ... ) */
/* Memory uncached, HW or SW cache coherency is not needed */
#define MV_UNCACHED 0
/* Memory cached, HW cache coherency supported in WriteThrough mode */
#define MV_CACHE_COHER_HW_WT 1
/* Memory cached, HW cache coherency supported in WriteBack mode */
#define MV_CACHE_COHER_HW_WB 2
/* Memory cached, No HW cache coherency, Cache coherency must be in SW */
#define MV_CACHE_COHER_SW 3
/* Macro for testing aligment. Positive if number is NOT aligned */
#define MV_IS_NOT_ALIGN(number, align) ((number) & ((align) - 1))
/* Macro for alignment up. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0340 */
#define MV_ALIGN_UP(number, align) \
(((number) & ((align) - 1)) ? (((number) + (align)) & ~((align)-1)) : (number))
/* Macro for alignment down. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0320 */
#define MV_ALIGN_DOWN(number, align) ((number) & ~((align)-1))
/* This macro returns absolute value */
#define MV_ABS(number) (((int)(number) < 0) ? -(int)(number) : (int)(number))
/* Bit fields manipulation macros */
/* An integer word which its 'x' bit is set */
#define MV_BIT_MASK(bitNum) (1 << (bitNum) )
/* Checks wheter bit 'x' in integer word is set */
#define MV_BIT_CHECK(word, bitNum) ( (word) & MV_BIT_MASK(bitNum) )
/* Clear (reset) bit 'x' in integer word (RMW - Read-Modify-Write) */
#define MV_BIT_CLEAR(word, bitNum) ( (word) &= ~(MV_BIT_MASK(bitNum)) )
/* Set bit 'x' in integer word (RMW) */
#define MV_BIT_SET(word, bitNum) ( (word) |= MV_BIT_MASK(bitNum) )
/* Invert bit 'x' in integer word (RMW) */
#define MV_BIT_INV(word, bitNum) ( (word) ^= MV_BIT_MASK(bitNum) )
/* Get the min between 'a' or 'b' */
#define MV_MIN(a,b) (((a) < (b)) ? (a) : (b))
/* Get the max between 'a' or 'b' */
#define MV_MAX(a,b) (((a) < (b)) ? (b) : (a))
/* Temporary */
#define mvOsDivide(num, div) \
({ \
int i=0, rem=(num); \
\
while(rem >= (div)) \
{ \
rem -= (div); \
i++; \
} \
(i); \
})
/* Temporary */
#define mvOsReminder(num, div) \
({ \
int rem = (num); \
\
while(rem >= (div)) \
rem -= (div); \
(rem); \
})
#define MV_IP_QUAD(ipAddr) ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), \
((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF)
#define MV_IS_POWER_OF_2(num) ((num != 0) && ((num & (num - 1)) == 0))
#ifndef MV_ASMLANGUAGE
/* mvCommon API list */
MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size);
void mvAsciiToHex(const char* asciiStr, char* hexStr);
void mvBinToHex(const MV_U8* bin, char* hexStr, int size);
void mvBinToAscii(const MV_U8* bin, char* asciiStr, int size);
MV_STATUS mvMacStrToHex(const char* macStr, MV_U8* macHex);
MV_STATUS mvMacHexToStr(MV_U8* macHex, char* macStr);
void mvSizePrint(MV_U32);
MV_U32 mvLog2(MV_U32 num);
#endif /* MV_ASMLANGUAGE */
#endif /* __INCmvCommonh */

4
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt
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@ -1,4 +0,0 @@
Global HAL Version: FEROCEON_HAL_3_1_7
Unit HAL Version: 3.1.4
Description: This component includes an implementation of the unit HAL drivers

326
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDebug.c
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@ -1,326 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/* includes */
#include "mvOs.h"
#include "mv802_3.h"
#include "mvCommon.h"
#include "mvDebug.h"
/* Global variables effect on behave MV_DEBUG_PRINT and MV_DEBUG_CODE macros
* mvDebug - map of bits (one for each module) bit=1 means enable
* debug code and messages for this module
* mvModuleDebug - array of 32 bits varables one for each module
*/
MV_U32 mvDebug = 0;
MV_U32 mvDebugModules[MV_MODULE_MAX];
/* Init mvModuleDebug array to default values */
void mvDebugInit(void)
{
int bit;
mvDebug = 0;
for(bit=0; bit<MV_MODULE_MAX; bit++)
{
mvDebugModules[bit] = MV_DEBUG_FLAG_ERR | MV_DEBUG_FLAG_STATS;
mvDebug |= MV_BIT_MASK(bit);
}
}
void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable)
{
if (isEnable)
{
MV_BIT_SET(mvDebug, module);
}
else
MV_BIT_CLEAR(mvDebug, module);
}
void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags)
{
mvDebugModules[module] |= flags;
}
void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags)
{
mvDebugModules[module] &= ~flags;
}
/* Dump memory in specific format:
* address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8
*/
void mvDebugMemDump(void* addr, int size, int access)
{
int i, j;
MV_U32 memAddr = (MV_U32)addr;
if(access == 0)
access = 1;
if( (access != 4) && (access != 2) && (access != 1) )
{
mvOsPrintf("%d wrong access size. Access must be 1 or 2 or 4\n",
access);
return;
}
memAddr = MV_ALIGN_DOWN( (unsigned int)addr, 4);
size = MV_ALIGN_UP(size, 4);
addr = (void*)MV_ALIGN_DOWN( (unsigned int)addr, access);
while(size > 0)
{
mvOsPrintf("%08x: ", memAddr);
i = 0;
/* 32 bytes in the line */
while(i < 32)
{
if(memAddr >= (MV_U32)addr)
{
switch(access)
{
case 1:
if( memAddr == CPU_PHY_MEM(memAddr) )
{
mvOsPrintf("%02x ", MV_MEMIO8_READ(memAddr));
}
else
{
mvOsPrintf("%02x ", *((MV_U8*)memAddr));
}
break;
case 2:
if( memAddr == CPU_PHY_MEM(memAddr) )
{
mvOsPrintf("%04x ", MV_MEMIO16_READ(memAddr));
}
else
{
mvOsPrintf("%04x ", *((MV_U16*)memAddr));
}
break;
case 4:
if( memAddr == CPU_PHY_MEM(memAddr) )
{
mvOsPrintf("%08x ", MV_MEMIO32_READ(memAddr));
}
else
{
mvOsPrintf("%08x ", *((MV_U32*)memAddr));
}
break;
}
}
else
{
for(j=0; j<(access*2+1); j++)
mvOsPrintf(" ");
}
i += access;
memAddr += access;
size -= access;
if(size <= 0)
break;
}
mvOsPrintf("\n");
}
}
void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access)
{
if(pBufInfo == NULL)
{
mvOsPrintf("\n!!! pBufInfo = NULL\n");
return;
}
mvOsPrintf("\n*** pBufInfo=0x%x, cmdSts=0x%08x, pBuf=0x%x, bufSize=%d\n",
(unsigned int)pBufInfo,
(unsigned int)pBufInfo->cmdSts,
(unsigned int)pBufInfo->pBuff,
(unsigned int)pBufInfo->bufSize);
mvOsPrintf("pData=0x%x, byteCnt=%d, pNext=0x%x, uInfo1=0x%x, uInfo2=0x%x\n",
(unsigned int)pBufInfo->pData,
(unsigned int)pBufInfo->byteCnt,
(unsigned int)pBufInfo->pNextBufInfo,
(unsigned int)pBufInfo->userInfo1,
(unsigned int)pBufInfo->userInfo2);
if(pBufInfo->pData != NULL)
{
if(size > pBufInfo->byteCnt)
size = pBufInfo->byteCnt;
mvDebugMemDump(pBufInfo->pData, size, access);
}
}
void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access)
{
int frag, len;
if(pPktInfo == NULL)
{
mvOsPrintf("\n!!! pPktInfo = NULL\n");
return;
}
mvOsPrintf("\npPkt=%p, stat=0x%08x, numFr=%d, size=%d, pFr=%p, osInfo=0x%lx\n",
pPktInfo, pPktInfo->status, pPktInfo->numFrags, pPktInfo->pktSize,
pPktInfo->pFrags, pPktInfo->osInfo);
for(frag=0; frag<pPktInfo->numFrags; frag++)
{
mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n",
frag, pPktInfo->pFrags[frag].bufVirtPtr,
pPktInfo->pFrags[frag].bufSize);
if(size > 0)
{
len = MV_MIN((int)pPktInfo->pFrags[frag].bufSize, size);
mvDebugMemDump(pPktInfo->pFrags[frag].bufVirtPtr, len, access);
size -= len;
}
}
}
void mvDebugPrintIpAddr(MV_U32 ipAddr)
{
mvOsPrintf("%d.%d.%d.%d", ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF),
((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF));
}
void mvDebugPrintMacAddr(const MV_U8* pMacAddr)
{
int i;
mvOsPrintf("%02x", (unsigned int)pMacAddr[0]);
for(i=1; i<MV_MAC_ADDR_SIZE; i++)
{
mvOsPrintf(":%02x", pMacAddr[i]);
}
/* mvOsPrintf("\n");*/
}
/******* There are three functions deals with MV_DEBUG_TIMES structure ********/
/* Reset MV_DEBUG_TIMES entry */
void mvDebugResetTimeEntry(MV_DEBUG_TIMES* pTimeEntry, int count, char* pName)
{
pTimeEntry->begin = 0;
pTimeEntry->count = count;
pTimeEntry->end = 0;
pTimeEntry->left = pTimeEntry->count;
pTimeEntry->total = 0;
pTimeEntry->min = 0xFFFFFFFF;
pTimeEntry->max = 0x0;
strncpy(pTimeEntry->name, pName, sizeof(pTimeEntry->name)-1);
pTimeEntry->name[sizeof(pTimeEntry->name)-1] = '\0';
}
/* Print out MV_DEBUG_TIMES entry */
void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle)
{
int num;
if(isTitle == MV_TRUE)
mvOsPrintf("Event NumOfEvents TotalTime Average Min Max\n");
num = pTimeEntry->count-pTimeEntry->left;
if(num > 0)
{
mvOsPrintf("%-11s %6u 0x%08lx %6lu %6lu %6lu\n",
pTimeEntry->name, num, pTimeEntry->total, pTimeEntry->total/num,
pTimeEntry->min, pTimeEntry->max);
}
}
/* Update MV_DEBUG_TIMES entry */
void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry)
{
MV_U32 delta;
if(pTimeEntry->left > 0)
{
if(pTimeEntry->end <= pTimeEntry->begin)
{
delta = pTimeEntry->begin - pTimeEntry->end;
}
else
{
delta = ((MV_U32)0x10000 - pTimeEntry->end) + pTimeEntry->begin;
}
pTimeEntry->total += delta;
if(delta < pTimeEntry->min)
pTimeEntry->min = delta;
if(delta > pTimeEntry->max)
pTimeEntry->max = delta;
pTimeEntry->left--;
}
}

178
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDebug.h
View File

@ -1,178 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvDebugh
#define __INCmvDebugh
/* includes */
#include "mvTypes.h"
typedef enum
{
MV_MODULE_INVALID = -1,
MV_MODULE_ETH = 0,
MV_MODULE_IDMA,
MV_MODULE_XOR,
MV_MODULE_TWASI,
MV_MODULE_MGI,
MV_MODULE_USB,
MV_MODULE_CESA,
MV_MODULE_MAX
}MV_MODULE_ID;
/* Define generic flags useful for most of modules */
#define MV_DEBUG_FLAG_ALL (0)
#define MV_DEBUG_FLAG_INIT (1 << 0)
#define MV_DEBUG_FLAG_RX (1 << 1)
#define MV_DEBUG_FLAG_TX (1 << 2)
#define MV_DEBUG_FLAG_ERR (1 << 3)
#define MV_DEBUG_FLAG_TRACE (1 << 4)
#define MV_DEBUG_FLAG_DUMP (1 << 5)
#define MV_DEBUG_FLAG_CACHE (1 << 6)
#define MV_DEBUG_FLAG_IOCTL (1 << 7)
#define MV_DEBUG_FLAG_STATS (1 << 8)
extern MV_U32 mvDebug;
extern MV_U32 mvDebugModules[MV_MODULE_MAX];
#ifdef MV_DEBUG
# define MV_DEBUG_PRINT(module, flags, msg) mvOsPrintf msg
# define MV_DEBUG_CODE(module, flags, code) code
#elif defined(MV_RT_DEBUG)
# define MV_DEBUG_PRINT(module, flags, msg) \
if( (mvDebug & (1<<(module))) && \
((mvDebugModules[(module)] & (flags)) == (flags)) ) \
mvOsPrintf msg
# define MV_DEBUG_CODE(module, flags, code) \
if( (mvDebug & (1<<(module))) && \
((mvDebugModules[(module)] & (flags)) == (flags)) ) \
code
#else
# define MV_DEBUG_PRINT(module, flags, msg)
# define MV_DEBUG_CODE(module, flags, code)
#endif
/* typedefs */
/* time measurement structure used to check how much time pass between
* two points
*/
typedef struct {
char name[20]; /* name of the entry */
unsigned long begin; /* time measured on begin point */
unsigned long end; /* time measured on end point */
unsigned long total; /* Accumulated time */
unsigned long left; /* The rest measurement actions */
unsigned long count; /* Maximum measurement actions */
unsigned long min; /* Minimum time from begin to end */
unsigned long max; /* Maximum time from begin to end */
} MV_DEBUG_TIMES;
/* mvDebug.h API list */
/****** Error Recording ******/
/* Dump memory in specific format:
* address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8
*/
void mvDebugMemDump(void* addr, int size, int access);
void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access);
void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access);
void mvDebugPrintIpAddr(MV_U32 ipAddr);
void mvDebugPrintMacAddr(const MV_U8* pMacAddr);
/**** There are three functions deals with MV_DEBUG_TIMES structure ****/
/* Reset MV_DEBUG_TIMES entry */
void mvDebugResetTimeEntry(MV_DEBUG_TIMES* pTimeEntry, int count, char* name);
/* Update MV_DEBUG_TIMES entry */
void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry);
/* Print out MV_DEBUG_TIMES entry */
void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle);
/******** General ***********/
/* Change value of mvDebugPrint global variable */
void mvDebugInit(void);
void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable);
void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags);
void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags);
#endif /* __INCmvDebug.h */

225
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h
View File

@ -1,225 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvDeviceIdh
#define __INCmvDeviceIdh
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* defines */
#define MARVELL_VEN_ID 0x11ab
/* Disco-3 */
#define MV64460_DEV_ID 0x6480
#define MV64460B_DEV_ID 0x6485
#define MV64430_DEV_ID 0x6420
/* Disco-5 */
#define MV64560_DEV_ID 0x6450
/* Disco-6 */
#define MV64660_DEV_ID 0x6460
/* Orion */
#define MV_1181_DEV_ID 0x1181
#define MV_5181_DEV_ID 0x5181
#define MV_5281_DEV_ID 0x5281
#define MV_5182_DEV_ID 0x5182
#define MV_8660_DEV_ID 0x8660
#define MV_5180_DEV_ID 0x5180
#define MV_5082_DEV_ID 0x5082
#define MV_1281_DEV_ID 0x1281
#define MV_6082_DEV_ID 0x6082
#define MV_6183_DEV_ID 0x6183
#define MV_6183L_DEV_ID 0x6083
#define MV_5281_D0_REV 0x4
#define MV_5281_D0_ID ((MV_5281_DEV_ID << 16) | MV_5281_D0_REV)
#define MV_5281_D0_NAME "88F5281 D0"
#define MV_5281_D1_REV 0x5
#define MV_5281_D1_ID ((MV_5281_DEV_ID << 16) | MV_5281_D1_REV)
#define MV_5281_D1_NAME "88F5281 D1"
#define MV_5281_D2_REV 0x6
#define MV_5281_D2_ID ((MV_5281_DEV_ID << 16) | MV_5281_D2_REV)
#define MV_5281_D2_NAME "88F5281 D2"
#define MV_5181L_A0_REV 0x8 /* need for PCIE Er */
#define MV_5181_A1_REV 0x1 /* for USB Er ..*/
#define MV_5181_B0_REV 0x2
#define MV_5181_B1_REV 0x3
#define MV_5182_A1_REV 0x1
#define MV_5180N_B1_REV 0x3
#define MV_5181L_A0_ID ((MV_5181_DEV_ID << 16) | MV_5181L_A0_REV)
/* kw */
#define MV_6281_DEV_ID 0x6281
#define MV_6192_DEV_ID 0x6192
#define MV_6190_DEV_ID 0x6190
#define MV_6180_DEV_ID 0x6180
#define MV_6281_A0_REV 0x2
#define MV_6281_A0_ID ((MV_6281_DEV_ID << 16) | MV_6281_A0_REV)
#define MV_6281_A0_NAME "88F6281 A0"
#define MV_6192_A0_REV 0x2
#define MV_6192_A0_ID ((MV_6192_DEV_ID << 16) | MV_6192_A0_REV)
#define MV_6192_A0_NAME "88F6192 A0"
#define MV_6190_A0_REV 0x2
#define MV_6190_A0_ID ((MV_6190_DEV_ID << 16) | MV_6190_A0_REV)
#define MV_6190_A0_NAME "88F6190 A0"
#define MV_6180_A0_REV 0x2
#define MV_6180_A0_ID ((MV_6180_DEV_ID << 16) | MV_6180_A0_REV)
#define MV_6180_A0_NAME "88F6180 A0"
#define MV_6281_A1_REV 0x3
#define MV_6281_A1_ID ((MV_6281_DEV_ID << 16) | MV_6281_A1_REV)
#define MV_6281_A1_NAME "88F6281 A1"
#define MV_6192_A1_REV 0x3
#define MV_6192_A1_ID ((MV_6192_DEV_ID << 16) | MV_6192_A1_REV)
#define MV_6192_A1_NAME "88F6192 A1"
#define MV_6190_A1_REV 0x3
#define MV_6190_A1_ID ((MV_6190_DEV_ID << 16) | MV_6190_A1_REV)
#define MV_6190_A1_NAME "88F6190 A1"
#define MV_6180_A1_REV 0x3
#define MV_6180_A1_ID ((MV_6180_DEV_ID << 16) | MV_6180_A1_REV)
#define MV_6180_A1_NAME "88F6180 A1"
#define MV_88F6XXX_A0_REV 0x2
#define MV_88F6XXX_A1_REV 0x3
/* Disco-Duo */
#define MV_78XX0_ZY_DEV_ID 0x6381
#define MV_78XX0_ZY_NAME "MV78X00"
#define MV_78XX0_Z0_REV 0x1
#define MV_78XX0_Z0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Z0_REV)
#define MV_78XX0_Z0_NAME "78X00 Z0"
#define MV_78XX0_Y0_REV 0x2
#define MV_78XX0_Y0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Y0_REV)
#define MV_78XX0_Y0_NAME "78X00 Y0"
#define MV_78XX0_DEV_ID 0x7800
#define MV_78XX0_NAME "MV78X00"
#define MV_76100_DEV_ID 0x7610
#define MV_78200_DEV_ID 0x7820
#define MV_78100_DEV_ID 0x7810
#define MV_78XX0_A0_REV 0x1
#define MV_78XX0_A1_REV 0x2
#define MV_76100_NAME "MV76100"
#define MV_78100_NAME "MV78100"
#define MV_78200_NAME "MV78200"
#define MV_76100_A0_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A0_REV)
#define MV_78100_A0_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A0_REV)
#define MV_78200_A0_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A0_REV)
#define MV_76100_A1_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A1_REV)
#define MV_78100_A1_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A1_REV)
#define MV_78200_A1_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A1_REV)
#define MV_76100_A0_NAME "MV76100 A0"
#define MV_78100_A0_NAME "MV78100 A0"
#define MV_78200_A0_NAME "MV78200 A0"
#define MV_78XX0_A0_NAME "MV78XX0 A0"
#define MV_76100_A1_NAME "MV76100 A1"
#define MV_78100_A1_NAME "MV78100 A1"
#define MV_78200_A1_NAME "MV78200 A1"
#define MV_78XX0_A1_NAME "MV78XX0 A1"
/*MV88F632X family*/
#define MV_6321_DEV_ID 0x6321
#define MV_6322_DEV_ID 0x6322
#define MV_6323_DEV_ID 0x6323
#define MV_6321_NAME "88F6321"
#define MV_6322_NAME "88F6322"
#define MV_6323_NAME "88F6323"
#define MV_632X_A1_REV 0x2
#define MV_6321_A1_ID ((MV_6321_DEV_ID << 16) | MV_632X_A1_REV)
#define MV_6322_A1_ID ((MV_6322_DEV_ID << 16) | MV_632X_A1_REV)
#define MV_6323_A1_ID ((MV_6323_DEV_ID << 16) | MV_632X_A1_REV)
#define MV_6321_A1_NAME "88F6321 A1"
#define MV_6322_A1_NAME "88F6322 A1"
#define MV_6323_A1_NAME "88F6323 A1"
#endif /* __INCmvDeviceIdh */

73
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h
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@ -1,73 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvHalVerh
#define __INCmvHalVerh
/* Defines */
#define MV_HAL_VERSION "FEROCEON_HAL_3_1_7"
#define MV_RELEASE_BASELINE "SoCandControllers_FEROCEON_RELEASE_7_9_2009_KW_4_3_4_DD_2_1_4_6183_1_1_4"
#endif /* __INCmvHalVerh */

100
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvStack.c
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@ -1,100 +0,0 @@
/*******************************************************************************
* Copyright 2003, Marvell Semiconductor Israel LTD. *
* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. *
* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT *
* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE *
* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. *
* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, *
* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. *
* *
* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL *
* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. *
* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). *
********************************************************************************
* mvQueue.c
*
* FILENAME: $Workfile: mvStack.c $
* REVISION: $Revision: 1.1 $
* LAST UPDATE: $Modtime: $
*
* DESCRIPTION:
* This file implements simple Stack LIFO functionality.
*******************************************************************************/
/* includes */
#include "mvOs.h"
#include "mvTypes.h"
#include "mvDebug.h"
#include "mvStack.h"
/* defines */
/* Public functions */
/* Purpose: Create new stack
* Inputs:
* - MV_U32 noOfElements - maximum number of elements in the stack.
* Each element 4 bytes size
* Return: void* - pointer to created stack.
*/
void* mvStackCreate(int numOfElements)
{
MV_STACK* pStack;
MV_U32* pStackElements;
pStack = (MV_STACK*)mvOsMalloc(sizeof(MV_STACK));
pStackElements = (MV_U32*)mvOsMalloc(numOfElements*sizeof(MV_U32));
if( (pStack == NULL) || (pStackElements == NULL) )
{
mvOsPrintf("mvStack: Can't create new stack\n");
return NULL;
}
memset(pStackElements, 0, numOfElements*sizeof(MV_U32));
pStack->numOfElements = numOfElements;
pStack->stackIdx = 0;
pStack->stackElements = pStackElements;
return pStack;
}
/* Purpose: Delete existing stack
* Inputs:
* - void* stackHndl - Stack handle as returned by "mvStackCreate()" function
*
* Return: MV_STATUS MV_NOT_FOUND - Failure. StackHandle is not valid.
* MV_OK - Success.
*/
MV_STATUS mvStackDelete(void* stackHndl)
{
MV_STACK* pStack = (MV_STACK*)stackHndl;
if( (pStack == NULL) || (pStack->stackElements == NULL) )
return MV_NOT_FOUND;
mvOsFree(pStack->stackElements);
mvOsFree(pStack);
return MV_OK;
}
/* PrintOut status of the stack */
void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements)
{
int i;
MV_STACK* pStack = (MV_STACK*)stackHndl;
mvOsPrintf("StackHandle=%p, pElements=%p, numElements=%d, stackIdx=%d\n",
stackHndl, pStack->stackElements, pStack->numOfElements,
pStack->stackIdx);
if(isPrintElements == MV_TRUE)
{
for(i=0; i<pStack->stackIdx; i++)
{
mvOsPrintf("%3d. Value=0x%x\n", i, pStack->stackElements[i]);
}
}
}

140
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@ -1,140 +0,0 @@
/*******************************************************************************
* Copyright 2003, Marvell Semiconductor Israel LTD. *
* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. *
* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT *
* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE *
* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. *
* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, *
* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. *
* *
* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL *
* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. *
* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). *
********************************************************************************
* mvStack.h - Header File for :
*
* FILENAME: $Workfile: mvStack.h $
* REVISION: $Revision: 1.1 $
* LAST UPDATE: $Modtime: $
*
* DESCRIPTION:
* This file defines simple Stack (LIFO) functionality.
*
*******************************************************************************/
#ifndef __mvStack_h__
#define __mvStack_h__
/* includes */
#include "mvTypes.h"
/* defines */
/* typedefs */
/* Data structure describes general purpose Stack */
typedef struct
{
int stackIdx;
int numOfElements;
MV_U32* stackElements;
} MV_STACK;
static INLINE MV_BOOL mvStackIsFull(void* stackHndl)
{
MV_STACK* pStack = (MV_STACK*)stackHndl;
if(pStack->stackIdx == pStack->numOfElements)
return MV_TRUE;
return MV_FALSE;
}
static INLINE MV_BOOL mvStackIsEmpty(void* stackHndl)
{
MV_STACK* pStack = (MV_STACK*)stackHndl;
if(pStack->stackIdx == 0)
return MV_TRUE;
return MV_FALSE;
}
/* Purpose: Push new element to stack
* Inputs:
* - void* stackHndl - Stack handle as returned by "mvStackCreate()" function.
* - MV_U32 value - New element.
*
* Return: MV_STATUS MV_FULL - Failure. Stack is full.
* MV_OK - Success. Element is put to stack.
*/
static INLINE void mvStackPush(void* stackHndl, MV_U32 value)
{
MV_STACK* pStack = (MV_STACK*)stackHndl;
#ifdef MV_RT_DEBUG
if(pStack->stackIdx == pStack->numOfElements)
{
mvOsPrintf("mvStackPush: Stack is FULL\n");
return;
}
#endif /* MV_RT_DEBUG */
pStack->stackElements[pStack->stackIdx] = value;
pStack->stackIdx++;
}
/* Purpose: Pop element from the top of stack and copy it to "pValue"
* Inputs:
* - void* stackHndl - Stack handle as returned by "mvStackCreate()" function.
* - MV_U32 value - Element in the top of stack.
*
* Return: MV_STATUS MV_EMPTY - Failure. Stack is empty.
* MV_OK - Success. Element is removed from the stack and
* copied to pValue argument
*/
static INLINE MV_U32 mvStackPop(void* stackHndl)
{
MV_STACK* pStack = (MV_STACK*)stackHndl;
#ifdef MV_RT_DEBUG
if(pStack->stackIdx == 0)
{
mvOsPrintf("mvStackPop: Stack is EMPTY\n");
return 0;
}
#endif /* MV_RT_DEBUG */
pStack->stackIdx--;
return pStack->stackElements[pStack->stackIdx];
}
static INLINE int mvStackIndex(void* stackHndl)
{
MV_STACK* pStack = (MV_STACK*)stackHndl;
return pStack->stackIdx;
}
static INLINE int mvStackFreeElements(void* stackHndl)
{
MV_STACK* pStack = (MV_STACK*)stackHndl;
return (pStack->numOfElements - pStack->stackIdx);
}
/* mvStack.h API list */
/* Create new Stack */
void* mvStackCreate(int numOfElements);
/* Delete existing stack */
MV_STATUS mvStackDelete(void* stackHndl);
/* Print status of the stack */
void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements);
#endif /* __mvStack_h__ */

245
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvTypes.h
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@ -1,245 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvTypesh
#define __INCmvTypesh
/* Defines */
/* The following is a list of Marvell status */
#define MV_ERROR (-1)
#define MV_OK (0x00) /* Operation succeeded */
#define MV_FAIL (0x01) /* Operation failed */
#define MV_BAD_VALUE (0x02) /* Illegal value (general) */
#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */
#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */
#define MV_BAD_PTR (0x05) /* Illegal pointer value */
#define MV_BAD_SIZE (0x06) /* Illegal size */
#define MV_BAD_STATE (0x07) /* Illegal state of state machine */
#define MV_SET_ERROR (0x08) /* Set operation failed */
#define MV_GET_ERROR (0x09) /* Get operation failed */
#define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */
#define MV_NOT_FOUND (0x0B) /* Item not found */
#define MV_NO_MORE (0x0C) /* No more items found */
#define MV_NO_SUCH (0x0D) /* No such item */
#define MV_TIMEOUT (0x0E) /* Time Out */
#define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */
#define MV_NOT_SUPPORTED (0x10) /* This request is not support */
#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented */
#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */
#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */
#define MV_HW_ERROR (0x17) /* Hardware error */
#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
#define MV_NOT_READY (0x1A) /* The other side is not ready yet */
#define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */
#define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */
#define MV_NOT_STARTED (0x1D) /* Not started yet */
#define MV_BUSY (0x1E) /* Item is busy. */
#define MV_TERMINATE (0x1F) /* Item terminates it's work. */
#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */
#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */
#define MV_WRITE_PROTECT (0x22) /* Write protected */
#define MV_INVALID (int)(-1)
#define MV_FALSE 0
#define MV_TRUE (!(MV_FALSE))
#ifndef NULL
#define NULL ((void*)0)
#endif
#ifndef MV_ASMLANGUAGE
/* typedefs */
typedef char MV_8;
typedef unsigned char MV_U8;
typedef int MV_32;
typedef unsigned int MV_U32;
typedef short MV_16;
typedef unsigned short MV_U16;
#ifdef MV_PPC64
typedef long MV_64;
typedef unsigned long MV_U64;
#else
typedef long long MV_64;
typedef unsigned long long MV_U64;
#endif
typedef long MV_LONG; /* 32/64 */
typedef unsigned long MV_ULONG; /* 32/64 */
typedef int MV_STATUS;
typedef int MV_BOOL;
typedef void MV_VOID;
typedef float MV_FLOAT;
typedef int (*MV_FUNCPTR) (void); /* ptr to function returning int */
typedef void (*MV_VOIDFUNCPTR) (void); /* ptr to function returning void */
typedef double (*MV_DBLFUNCPTR) (void); /* ptr to function returning double*/
typedef float (*MV_FLTFUNCPTR) (void); /* ptr to function returning float */
typedef MV_U32 MV_KHZ;
typedef MV_U32 MV_MHZ;
typedef MV_U32 MV_HZ;
/* This enumerator describes the set of commands that can be applied on */
/* an engine (e.g. IDMA, XOR). Appling a comman depends on the current */
/* status (see MV_STATE enumerator) */
/* Start can be applied only when status is IDLE */
/* Stop can be applied only when status is IDLE, ACTIVE or PAUSED */
/* Pause can be applied only when status is ACTIVE */
/* Restart can be applied only when status is PAUSED */
typedef enum _mvCommand
{
MV_START, /* Start */
MV_STOP, /* Stop */
MV_PAUSE, /* Pause */
MV_RESTART /* Restart */
} MV_COMMAND;
/* This enumerator describes the set of state conditions. */
/* Moving from one state to other is stricted. */
typedef enum _mvState
{
MV_IDLE,
MV_ACTIVE,
MV_PAUSED,
MV_UNDEFINED_STATE
} MV_STATE;
/* This structure describes address space window. Window base can be */
/* 64 bit, window size up to 4GB */
typedef struct _mvAddrWin
{
MV_U32 baseLow; /* 32bit base low */
MV_U32 baseHigh; /* 32bit base high */
MV_U32 size; /* 32bit size */
}MV_ADDR_WIN;
/* This binary enumerator describes protection attribute status */
typedef enum _mvProtRight
{
ALLOWED, /* Protection attribute allowed */
FORBIDDEN /* Protection attribute forbidden */
}MV_PROT_RIGHT;
/* Unified struct for Rx and Tx packet operations. The user is required to */
/* be familier only with Tx/Rx descriptor command status. */
typedef struct _bufInfo
{
MV_U32 cmdSts; /* Tx/Rx command status */
MV_U16 byteCnt; /* Size of valid data in the buffer */
MV_U16 bufSize; /* Total size of the buffer */
MV_U8 *pBuff; /* Pointer to Buffer */
MV_U8 *pData; /* Pointer to data in the Buffer */
MV_U32 userInfo1; /* Tx/Rx attached user information 1 */
MV_U32 userInfo2; /* Tx/Rx attached user information 2 */
struct _bufInfo *pNextBufInfo; /* Next buffer in packet */
} BUF_INFO;
/* This structure contains information describing one of buffers
* (fragments) they are built Ethernet packet.
*/
typedef struct
{
MV_U8* bufVirtPtr;
MV_ULONG bufPhysAddr;
MV_U32 bufSize;
MV_U32 dataSize;
MV_U32 memHandle;
MV_32 bufAddrShift;
} MV_BUF_INFO;
/* This structure contains information describing Ethernet packet.
* The packet can be divided for few buffers (fragments)
*/
typedef struct
{
MV_ULONG osInfo;
MV_BUF_INFO *pFrags;
MV_U32 status;
MV_U16 pktSize;
MV_U16 numFrags;
MV_U32 ownerId;
MV_U32 fragIP;
} MV_PKT_INFO;
#endif /* MV_ASMLANGUAGE */
#endif /* __INCmvTypesh */

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#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/time.h>
#include "dbg-trace.h"
#define TRACE_ARR_LEN 800
#define STR_LEN 128
struct trace {
struct timeval tv;
char str[STR_LEN];
unsigned int callback_val1;
unsigned int callback_val2;
char valid;
};
static unsigned int (*trc_callback1) (unsigned char) = NULL;
static unsigned int (*trc_callback2) (unsigned char) = NULL;
static unsigned char trc_param1 = 0;
static unsigned char trc_param2 = 0;
struct trace *trc_arr;
static int trc_index;
static int trc_active = 0;
void TRC_START()
{
trc_active = 1;
}
void TRC_STOP()
{
trc_active = 0;
}
void TRC_INIT(void *callback1, void *callback2, unsigned char callback1_param, unsigned char callback2_param)
{
printk("Marvell debug tracing is on\n");
trc_arr = (struct trace *)kmalloc(TRACE_ARR_LEN*sizeof(struct trace),GFP_KERNEL);
if(trc_arr == NULL)
{
printk("Can't allocate Debug Trace buffer\n");
return;
}
memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace));
trc_index = 0;
trc_callback1 = callback1;
trc_callback2 = callback2;
trc_param1 = callback1_param;
trc_param2 = callback2_param;
}
void TRC_REC(char *fmt,...)
{
va_list args;
struct trace *trc = &trc_arr[trc_index];
if(trc_active == 0)
return;
do_gettimeofday(&trc->tv);
if(trc_callback1)
trc->callback_val1 = trc_callback1(trc_param1);
if(trc_callback2)
trc->callback_val2 = trc_callback2(trc_param2);
va_start(args, fmt);
vsprintf(trc->str,fmt,args);
va_end(args);
trc->valid = 1;
if((++trc_index) == TRACE_ARR_LEN) {
trc_index = 0;
}
}
void TRC_OUTPUT(void)
{
int i,j;
struct trace *p;
printk("\n\nTrace %d items\n",TRACE_ARR_LEN);
for(i=0,j=trc_index; i<TRACE_ARR_LEN; i++,j++) {
if(j == TRACE_ARR_LEN)
j = 0;
p = &trc_arr[j];
if(p->valid) {
unsigned long uoffs;
struct trace *plast;
if(p == &trc_arr[0])
plast = &trc_arr[TRACE_ARR_LEN-1];
else
plast = p-1;
if(p->tv.tv_sec == ((plast)->tv.tv_sec))
uoffs = (p->tv.tv_usec - ((plast)->tv.tv_usec));
else
uoffs = (1000000 - ((plast)->tv.tv_usec)) +
((p->tv.tv_sec - ((plast)->tv.tv_sec) - 1) * 1000000) +
p->tv.tv_usec;
printk("%03d: [+%ld usec]", j, (unsigned long)uoffs);
if(trc_callback1)
printk("[%u]",p->callback_val1);
if(trc_callback2)
printk("[%u]",p->callback_val2);
printk(": %s",p->str);
}
p->valid = 0;
}
memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace));
trc_index = 0;
}
void TRC_RELEASE(void)
{
kfree(trc_arr);
trc_index = 0;
}

24
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/dbg-trace.h
View File

@ -1,24 +0,0 @@
#ifndef _MV_DBG_TRCE_H_
#define _MV_DBG_TRCE_H_
#ifdef CONFIG_MV_DBG_TRACE
void TRC_INIT(void *callback1, void *callback2,
unsigned char callback1_param, unsigned char callback2_param);
void TRC_REC(char *fmt,...);
void TRC_OUTPUT(void);
void TRC_RELEASE(void);
void TRC_START(void);
void TRC_STOP(void);
#else
#define TRC_INIT(x1,x2,x3,x4)
#define TRC_REC(X...)
#define TRC_OUTPUT()
#define TRC_RELEASE()
#define TRC_START()
#define TRC_STOP()
#endif
#endif

2513
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c
View File

File diff suppressed because it is too large Load Diff

376
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h
View File

@ -1,376 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvBoardEnvLibh
#define __INCmvBoardEnvLibh
/* defines */
/* The below constant macros defines the board I2C EEPROM data offsets */
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "mvSysHwConfig.h"
#include "boardEnv/mvBoardEnvSpec.h"
/* DUART stuff for Tclk detection only */
#define DUART_BAUD_RATE 115200
#define MAX_CLOCK_MARGINE 5000000 /* Maximum detected clock margine */
/* Voice devices assembly modes */
#define DAISY_CHAIN_MODE 1
#define DUAL_CHIP_SELECT_MODE 0
#define INTERRUPT_TO_MPP 1
#define INTERRUPT_TO_TDM 0
#define BOARD_ETH_PORT_NUM MV_ETH_MAX_PORTS
#define BOARD_ETH_SWITCH_PORT_NUM 5
#define MV_BOARD_MAX_USB_IF 1
#define MV_BOARD_MAX_MPP 7
#define MV_BOARD_NAME_LEN 0x20
typedef struct _boardData
{
MV_U32 magic;
MV_U16 boardId;
MV_U8 boardVer;
MV_U8 boardRev;
MV_U32 reserved1;
MV_U32 reserved2;
}BOARD_DATA;
typedef enum _devBoardMppGroupClass
{
MV_BOARD_MPP_GROUP_1,
MV_BOARD_MPP_GROUP_2,
MV_BOARD_MAX_MPP_GROUP
}MV_BOARD_MPP_GROUP_CLASS;
typedef enum _devBoardMppTypeClass
{
MV_BOARD_AUTO,
MV_BOARD_TDM,
MV_BOARD_AUDIO,
MV_BOARD_RGMII,
MV_BOARD_GMII,
MV_BOARD_TS,
MV_BOARD_MII,
MV_BOARD_OTHER
}MV_BOARD_MPP_TYPE_CLASS;
typedef enum _devBoardModuleIdClass
{
MV_BOARD_MODULE_TDM_ID = 1,
MV_BOARD_MODULE_AUDIO_ID,
MV_BOARD_MODULE_RGMII_ID,
MV_BOARD_MODULE_GMII_ID,
MV_BOARD_MODULE_TS_ID,
MV_BOARD_MODULE_MII_ID,
MV_BOARD_MODULE_TDM_5CHAN_ID,
MV_BOARD_MODULE_OTHER_ID
}MV_BOARD_MODULE_ID_CLASS;
typedef struct _boardMppTypeInfo
{
MV_BOARD_MPP_TYPE_CLASS boardMppGroup1;
MV_BOARD_MPP_TYPE_CLASS boardMppGroup2;
}MV_BOARD_MPP_TYPE_INFO;
typedef enum _devBoardClass
{
BOARD_DEV_NOR_FLASH,
BOARD_DEV_NAND_FLASH,
BOARD_DEV_SEVEN_SEG,
BOARD_DEV_FPGA,
BOARD_DEV_SRAM,
BOARD_DEV_SPI_FLASH,
BOARD_DEV_OTHER,
}MV_BOARD_DEV_CLASS;
typedef enum _devTwsiBoardClass
{
BOARD_TWSI_RTC,
BOARD_DEV_TWSI_EXP,
BOARD_DEV_TWSI_SATR,
BOARD_TWSI_AUDIO_DEC,
BOARD_TWSI_OTHER
}MV_BOARD_TWSI_CLASS;
typedef enum _devGppBoardClass
{
BOARD_GPP_RTC,
BOARD_GPP_MV_SWITCH,
BOARD_GPP_USB_VBUS,
BOARD_GPP_USB_VBUS_EN,
BOARD_GPP_USB_OC,
BOARD_GPP_USB_HOST_DEVICE,
BOARD_GPP_REF_CLCK,
BOARD_GPP_VOIP_SLIC,
BOARD_GPP_LIFELINE,
BOARD_GPP_BUTTON,
BOARD_GPP_TS_BUTTON_C,
BOARD_GPP_TS_BUTTON_U,
BOARD_GPP_TS_BUTTON_D,
BOARD_GPP_TS_BUTTON_L,
BOARD_GPP_TS_BUTTON_R,
BOARD_GPP_POWER_BUTTON,
BOARD_GPP_RESTOR_BUTTON,
BOARD_GPP_WPS_BUTTON,
BOARD_GPP_HDD0_POWER,
BOARD_GPP_HDD1_POWER,
BOARD_GPP_FAN_POWER,
BOARD_GPP_RESET,
BOARD_GPP_POWER_ON_LED,
BOARD_GPP_HDD_POWER,
BOARD_GPP_SDIO_POWER,
BOARD_GPP_SDIO_DETECT,
BOARD_GPP_SDIO_WP,
BOARD_GPP_SWITCH_PHY_INT,
BOARD_GPP_TSU_DIRCTION,
BOARD_GPP_OTHER
}MV_BOARD_GPP_CLASS;
typedef struct _devCsInfo
{
MV_U8 deviceCS;
MV_U32 params;
MV_U32 devClass; /* MV_BOARD_DEV_CLASS */
MV_U8 devWidth;
}MV_DEV_CS_INFO;
#define MV_BOARD_PHY_FORCE_10MB 0x0
#define MV_BOARD_PHY_FORCE_100MB 0x1
#define MV_BOARD_PHY_FORCE_1000MB 0x2
#define MV_BOARD_PHY_SPEED_AUTO 0x3
typedef struct _boardSwitchInfo
{
MV_32 linkStatusIrq;
MV_32 qdPort[BOARD_ETH_SWITCH_PORT_NUM];
MV_32 qdCpuPort;
MV_32 smiScanMode; /* 1 for SMI_MANUAL_MODE, 0 otherwise */
MV_32 switchOnPort;
}MV_BOARD_SWITCH_INFO;
typedef struct _boardLedInfo
{
MV_U8 activeLedsNumber;
MV_U8 ledsPolarity; /* '0' or '1' to turn on led */
MV_U8* gppPinNum; /* Pointer to GPP values */
}MV_BOARD_LED_INFO;
typedef struct _boardGppInfo
{
MV_BOARD_GPP_CLASS devClass;
MV_U8 gppPinNum;
}MV_BOARD_GPP_INFO;
typedef struct _boardTwsiInfo
{
MV_BOARD_TWSI_CLASS devClass;
MV_U8 twsiDevAddr;
MV_U8 twsiDevAddrType;
}MV_BOARD_TWSI_INFO;
typedef enum _boardMacSpeed
{
BOARD_MAC_SPEED_10M,
BOARD_MAC_SPEED_100M,
BOARD_MAC_SPEED_1000M,
BOARD_MAC_SPEED_AUTO,
}MV_BOARD_MAC_SPEED;
typedef struct _boardMacInfo
{
MV_BOARD_MAC_SPEED boardMacSpeed;
MV_U8 boardEthSmiAddr;
}MV_BOARD_MAC_INFO;
typedef struct _boardMppInfo
{
MV_U32 mppGroup[MV_BOARD_MAX_MPP];
}MV_BOARD_MPP_INFO;
typedef struct _boardInfo
{
char boardName[MV_BOARD_NAME_LEN];
MV_U8 numBoardMppTypeValue;
MV_BOARD_MPP_TYPE_INFO* pBoardMppTypeValue;
MV_U8 numBoardMppConfigValue;
MV_BOARD_MPP_INFO* pBoardMppConfigValue;
MV_U32 intsGppMaskLow;
MV_U32 intsGppMaskHigh;
MV_U8 numBoardDeviceIf;
MV_DEV_CS_INFO* pDevCsInfo;
MV_U8 numBoardTwsiDev;
MV_BOARD_TWSI_INFO* pBoardTwsiDev;
MV_U8 numBoardMacInfo;
MV_BOARD_MAC_INFO* pBoardMacInfo;
MV_U8 numBoardGppInfo;
MV_BOARD_GPP_INFO* pBoardGppInfo;
MV_U8 activeLedsNumber;
MV_U8* pLedGppPin;
MV_U8 ledsPolarity; /* '0' or '1' to turn on led */
/* GPP values */
MV_U32 gppOutEnValLow;
MV_U32 gppOutEnValHigh;
MV_U32 gppOutValLow;
MV_U32 gppOutValHigh;
MV_U32 gppPolarityValLow;
MV_U32 gppPolarityValHigh;
/* Switch Configuration */
MV_BOARD_SWITCH_INFO* pSwitchInfo;
}MV_BOARD_INFO;
MV_VOID mvBoardEnvInit(MV_VOID);
MV_U32 mvBoardIdGet(MV_VOID);
MV_U16 mvBoardModelGet(MV_VOID);
MV_U16 mvBoardRevGet(MV_VOID);
MV_STATUS mvBoardNameGet(char *pNameBuff);
MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum);
MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum);
MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum);
MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum);
MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum);
MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum);
MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum);
MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum);
MV_BOOL mvBoardIsPortInGmii(MV_VOID);
MV_U32 mvBoardTclkGet(MV_VOID);
MV_U32 mvBoardSysClkGet(MV_VOID);
MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId);
MV_VOID mvBoardDebugLed(MV_U32 hexNum);
MV_32 mvBoardMppGet(MV_U32 mppGroupNum);
MV_U8 mvBoardRtcTwsiAddrTypeGet(MV_VOID);
MV_U8 mvBoardRtcTwsiAddrGet(MV_VOID);
MV_U8 mvBoardA2DTwsiAddrTypeGet(MV_VOID);
MV_U8 mvBoardA2DTwsiAddrGet(MV_VOID);
MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index);
MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index);
MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index);
MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index);
MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass);
MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass);
MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass,
MV_BOARD_MPP_TYPE_CLASS mppGroupType);
MV_VOID mvBoardMppGroupIdUpdate(MV_VOID);
MV_VOID mvBoardMppMuxSet(MV_VOID);
MV_VOID mvBoardTdmMppSet(MV_32 chType);
MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode);
MV_VOID mvBoardMppModuleTypePrint(MV_VOID);
MV_VOID mvBoardReset(MV_VOID);
MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum);
MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal);
MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data);
/* Board devices API managments */
MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass);
MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
/* Gpio Pin Connections API */
MV_32 mvBoardUSBVbusGpioPinGet(int devId);
MV_32 mvBoardUSBVbusEnGpioPinGet(int devId);
MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin);
MV_32 mvBoardResetGpioPinGet(MV_VOID);
MV_32 mvBoardRTCGpioPinGet(MV_VOID);
MV_32 mvBoardGpioIntMaskLowGet(MV_VOID);
MV_32 mvBoardGpioIntMaskHighGet(MV_VOID);
MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum);
MV_32 mvBoardSDIOGpioPinGet(MV_VOID);
MV_STATUS mvBoardSDioWPControl(MV_BOOL mode);
MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index);
MV_32 mvBoardNandWidthGet(void);
MV_STATUS mvBoardFanPowerControl(MV_BOOL mode);
MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode);
#endif /* __INCmvBoardEnvLibh */

848
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c
View File

@ -1,848 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "mvCommon.h"
#include "mvBoardEnvLib.h"
#include "mvBoardEnvSpec.h"
#include "twsi/mvTwsi.h"
#define DB_88F6281A_BOARD_PCI_IF_NUM 0x0
#define DB_88F6281A_BOARD_TWSI_DEF_NUM 0x7
#define DB_88F6281A_BOARD_MAC_INFO_NUM 0x2
#define DB_88F6281A_BOARD_GPP_INFO_NUM 0x3
#define DB_88F6281A_BOARD_MPP_CONFIG_NUM 0x1
#define DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1
#if defined(MV_NAND) && defined(MV_NAND_BOOT)
#define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1
#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
#define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2
#else
#define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1
#endif
#define DB_88F6281A_BOARD_DEBUG_LED_NUM 0x0
MV_BOARD_TWSI_INFO db88f6281AInfoBoardTwsiDev[] =
/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
{
{BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT},
{BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT},
{BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT},
{BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT},
{BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT},
{BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT},
{BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT}
};
MV_BOARD_MAC_INFO db88f6281AInfoBoardMacInfo[] =
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
{
{BOARD_MAC_SPEED_AUTO, 0x8},
{BOARD_MAC_SPEED_AUTO, 0x9}
};
MV_BOARD_MPP_TYPE_INFO db88f6281AInfoBoardMppTypeInfo[] =
/* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1,
MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */
{{MV_BOARD_AUTO, MV_BOARD_AUTO}
};
MV_BOARD_GPP_INFO db88f6281AInfoBoardGppInfo[] =
/* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */
{
{BOARD_GPP_TSU_DIRCTION, 33}
/*muxed with TDM/Audio module via IOexpender
{BOARD_GPP_SDIO_DETECT, 38},
{BOARD_GPP_USB_VBUS, 49}*/
};
MV_DEV_CS_INFO db88f6281AInfoBoardDeCsInfo[] =
/*{deviceCS, params, devType, devWidth}*/
#if defined(MV_NAND) && defined(MV_NAND_BOOT)
{{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */
#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
{
{0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */
{1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */
};
#else
{{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */
#endif
MV_BOARD_MPP_INFO db88f6281AInfoBoardMppConfigValue[] =
{{{
DB_88F6281A_MPP0_7,
DB_88F6281A_MPP8_15,
DB_88F6281A_MPP16_23,
DB_88F6281A_MPP24_31,
DB_88F6281A_MPP32_39,
DB_88F6281A_MPP40_47,
DB_88F6281A_MPP48_55
}}};
MV_BOARD_INFO db88f6281AInfo = {
"DB-88F6281A-BP", /* boardName[MAX_BOARD_NAME_LEN] */
DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
db88f6281AInfoBoardMppTypeInfo,
DB_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
db88f6281AInfoBoardMppConfigValue,
0, /* intsGppMaskLow */
0, /* intsGppMaskHigh */
DB_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
db88f6281AInfoBoardDeCsInfo,
DB_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
db88f6281AInfoBoardTwsiDev,
DB_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
db88f6281AInfoBoardMacInfo,
DB_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
db88f6281AInfoBoardGppInfo,
DB_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
NULL,
0, /* ledsPolarity */
DB_88F6281A_OE_LOW, /* gppOutEnLow */
DB_88F6281A_OE_HIGH, /* gppOutEnHigh */
DB_88F6281A_OE_VAL_LOW, /* gppOutValLow */
DB_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */
0, /* gppPolarityValLow */
BIT6, /* gppPolarityValHigh */
NULL /* pSwitchInfo */
};
#define RD_88F6281A_BOARD_PCI_IF_NUM 0x0
#define RD_88F6281A_BOARD_TWSI_DEF_NUM 0x2
#define RD_88F6281A_BOARD_MAC_INFO_NUM 0x2
#define RD_88F6281A_BOARD_GPP_INFO_NUM 0x5
#define RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1
#define RD_88F6281A_BOARD_MPP_CONFIG_NUM 0x1
#if defined(MV_NAND) && defined(MV_NAND_BOOT)
#define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1
#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
#define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2
#else
#define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1
#endif
#define RD_88F6281A_BOARD_DEBUG_LED_NUM 0x0
MV_BOARD_MAC_INFO rd88f6281AInfoBoardMacInfo[] =
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
{{BOARD_MAC_SPEED_1000M, 0xa},
{BOARD_MAC_SPEED_AUTO, 0xb}
};
MV_BOARD_SWITCH_INFO rd88f6281AInfoBoardSwitchInfo[] =
/* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4},
MV_32 qdCpuPort, MV_32 smiScanMode, MV_32 switchOnPort} */
{{38, {0, 1, 2, 3, -1}, 5, 2, 0},
{-1, {-1}, -1, -1, -1}};
MV_BOARD_TWSI_INFO rd88f6281AInfoBoardTwsiDev[] =
/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
{
{BOARD_DEV_TWSI_EXP, 0xFF, ADDR7_BIT}, /* dummy entry to align with modules indexes */
{BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}
};
MV_BOARD_MPP_TYPE_INFO rd88f6281AInfoBoardMppTypeInfo[] =
{{MV_BOARD_RGMII, MV_BOARD_TDM}
};
MV_DEV_CS_INFO rd88f6281AInfoBoardDeCsInfo[] =
/*{deviceCS, params, devType, devWidth}*/
#if defined(MV_NAND) && defined(MV_NAND_BOOT)
{{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */
#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
{
{0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */
{1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */
};
#else
{{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */
#endif
MV_BOARD_GPP_INFO rd88f6281AInfoBoardGppInfo[] =
/* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */
{{BOARD_GPP_SDIO_DETECT, 28},
{BOARD_GPP_USB_OC, 29},
{BOARD_GPP_WPS_BUTTON, 35},
{BOARD_GPP_MV_SWITCH, 38},
{BOARD_GPP_USB_VBUS, 49}
};
MV_BOARD_MPP_INFO rd88f6281AInfoBoardMppConfigValue[] =
{{{
RD_88F6281A_MPP0_7,
RD_88F6281A_MPP8_15,
RD_88F6281A_MPP16_23,
RD_88F6281A_MPP24_31,
RD_88F6281A_MPP32_39,
RD_88F6281A_MPP40_47,
RD_88F6281A_MPP48_55
}}};
MV_BOARD_INFO rd88f6281AInfo = {
"RD-88F6281A", /* boardName[MAX_BOARD_NAME_LEN] */
RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
rd88f6281AInfoBoardMppTypeInfo,
RD_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
rd88f6281AInfoBoardMppConfigValue,
0, /* intsGppMaskLow */
(1 << 3), /* intsGppMaskHigh */
RD_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
rd88f6281AInfoBoardDeCsInfo,
RD_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
rd88f6281AInfoBoardTwsiDev,
RD_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
rd88f6281AInfoBoardMacInfo,
RD_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
rd88f6281AInfoBoardGppInfo,
RD_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
NULL,
0, /* ledsPolarity */
RD_88F6281A_OE_LOW, /* gppOutEnLow */
RD_88F6281A_OE_HIGH, /* gppOutEnHigh */
RD_88F6281A_OE_VAL_LOW, /* gppOutValLow */
RD_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */
0, /* gppPolarityValLow */
BIT6, /* gppPolarityValHigh */
rd88f6281AInfoBoardSwitchInfo /* pSwitchInfo */
};
#define DB_88F6192A_BOARD_PCI_IF_NUM 0x0
#define DB_88F6192A_BOARD_TWSI_DEF_NUM 0x7
#define DB_88F6192A_BOARD_MAC_INFO_NUM 0x2
#define DB_88F6192A_BOARD_GPP_INFO_NUM 0x3
#define DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1
#define DB_88F6192A_BOARD_MPP_CONFIG_NUM 0x1
#if defined(MV_NAND) && defined(MV_NAND_BOOT)
#define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1
#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
#define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x2
#else
#define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1
#endif
#define DB_88F6192A_BOARD_DEBUG_LED_NUM 0x0
MV_BOARD_TWSI_INFO db88f6192AInfoBoardTwsiDev[] =
/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
{
{BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT},
{BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT},
{BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT},
{BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT},
{BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT},
{BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT},
{BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT}
};
MV_BOARD_MAC_INFO db88f6192AInfoBoardMacInfo[] =
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
{
{BOARD_MAC_SPEED_AUTO, 0x8},
{BOARD_MAC_SPEED_AUTO, 0x9}
};
MV_BOARD_MPP_TYPE_INFO db88f6192AInfoBoardMppTypeInfo[] =
/* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1,
MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */
{{MV_BOARD_AUTO, MV_BOARD_OTHER}
};
MV_DEV_CS_INFO db88f6192AInfoBoardDeCsInfo[] =
/*{deviceCS, params, devType, devWidth}*/
#if defined(MV_NAND) && defined(MV_NAND_BOOT)
{{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */
#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
{
{0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */
{1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */
};
#else
{{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */
#endif
MV_BOARD_GPP_INFO db88f6192AInfoBoardGppInfo[] =
/* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */
{
{BOARD_GPP_SDIO_WP, 20},
{BOARD_GPP_USB_VBUS, 22},
{BOARD_GPP_SDIO_DETECT, 23},
};
MV_BOARD_MPP_INFO db88f6192AInfoBoardMppConfigValue[] =
{{{
DB_88F6192A_MPP0_7,
DB_88F6192A_MPP8_15,
DB_88F6192A_MPP16_23,
DB_88F6192A_MPP24_31,
DB_88F6192A_MPP32_35
}}};
MV_BOARD_INFO db88f6192AInfo = {
"DB-88F6192A-BP", /* boardName[MAX_BOARD_NAME_LEN] */
DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
db88f6192AInfoBoardMppTypeInfo,
DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
db88f6192AInfoBoardMppConfigValue,
0, /* intsGppMaskLow */
(1 << 3), /* intsGppMaskHigh */
DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
db88f6192AInfoBoardDeCsInfo,
DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
db88f6192AInfoBoardTwsiDev,
DB_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
db88f6192AInfoBoardMacInfo,
DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
db88f6192AInfoBoardGppInfo,
DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
NULL,
0, /* ledsPolarity */
DB_88F6192A_OE_LOW, /* gppOutEnLow */
DB_88F6192A_OE_HIGH, /* gppOutEnHigh */
DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */
DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */
0, /* gppPolarityValLow */
0, /* gppPolarityValHigh */
NULL /* pSwitchInfo */
};
#define DB_88F6190A_BOARD_MAC_INFO_NUM 0x1
MV_BOARD_INFO db88f6190AInfo = {
"DB-88F6190A-BP", /* boardName[MAX_BOARD_NAME_LEN] */
DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
db88f6192AInfoBoardMppTypeInfo,
DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
db88f6192AInfoBoardMppConfigValue,
0, /* intsGppMaskLow */
(1 << 3), /* intsGppMaskHigh */
DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
db88f6192AInfoBoardDeCsInfo,
DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
db88f6192AInfoBoardTwsiDev,
DB_88F6190A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
db88f6192AInfoBoardMacInfo,
DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
db88f6192AInfoBoardGppInfo,
DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
NULL,
0, /* ledsPolarity */
DB_88F6192A_OE_LOW, /* gppOutEnLow */
DB_88F6192A_OE_HIGH, /* gppOutEnHigh */
DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */
DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */
0, /* gppPolarityValLow */
0, /* gppPolarityValHigh */
NULL /* pSwitchInfo */
};
#define RD_88F6192A_BOARD_PCI_IF_NUM 0x0
#define RD_88F6192A_BOARD_TWSI_DEF_NUM 0x0
#define RD_88F6192A_BOARD_MAC_INFO_NUM 0x1
#define RD_88F6192A_BOARD_GPP_INFO_NUM 0xE
#define RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1
#define RD_88F6192A_BOARD_MPP_CONFIG_NUM 0x1
#define RD_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1
#define RD_88F6192A_BOARD_DEBUG_LED_NUM 0x3
MV_U8 rd88f6192AInfoBoardDebugLedIf[] =
{17, 28, 29};
MV_BOARD_MAC_INFO rd88f6192AInfoBoardMacInfo[] =
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
{{BOARD_MAC_SPEED_AUTO, 0x8}
};
MV_BOARD_MPP_TYPE_INFO rd88f6192AInfoBoardMppTypeInfo[] =
/* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1,
MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */
{{MV_BOARD_OTHER, MV_BOARD_OTHER}
};
MV_DEV_CS_INFO rd88f6192AInfoBoardDeCsInfo[] =
/*{deviceCS, params, devType, devWidth}*/
{{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */
MV_BOARD_GPP_INFO rd88f6192AInfoBoardGppInfo[] =
/* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */
{
{BOARD_GPP_USB_VBUS_EN, 10},
{BOARD_GPP_USB_HOST_DEVICE, 11},
{BOARD_GPP_RESET, 14},
{BOARD_GPP_POWER_ON_LED, 15},
{BOARD_GPP_HDD_POWER, 16},
{BOARD_GPP_WPS_BUTTON, 24},
{BOARD_GPP_TS_BUTTON_C, 25},
{BOARD_GPP_USB_VBUS, 26},
{BOARD_GPP_USB_OC, 27},
{BOARD_GPP_TS_BUTTON_U, 30},
{BOARD_GPP_TS_BUTTON_R, 31},
{BOARD_GPP_TS_BUTTON_L, 32},
{BOARD_GPP_TS_BUTTON_D, 34},
{BOARD_GPP_FAN_POWER, 35}
};
MV_BOARD_MPP_INFO rd88f6192AInfoBoardMppConfigValue[] =
{{{
RD_88F6192A_MPP0_7,
RD_88F6192A_MPP8_15,
RD_88F6192A_MPP16_23,
RD_88F6192A_MPP24_31,
RD_88F6192A_MPP32_35
}}};
MV_BOARD_INFO rd88f6192AInfo = {
"RD-88F6192A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */
RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
rd88f6192AInfoBoardMppTypeInfo,
RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
rd88f6192AInfoBoardMppConfigValue,
0, /* intsGppMaskLow */
(1 << 3), /* intsGppMaskHigh */
RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
rd88f6192AInfoBoardDeCsInfo,
RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
NULL,
RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
rd88f6192AInfoBoardMacInfo,
RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
rd88f6192AInfoBoardGppInfo,
RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
rd88f6192AInfoBoardDebugLedIf,
0, /* ledsPolarity */
RD_88F6192A_OE_LOW, /* gppOutEnLow */
RD_88F6192A_OE_HIGH, /* gppOutEnHigh */
RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */
RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */
0, /* gppPolarityValLow */
0, /* gppPolarityValHigh */
NULL /* pSwitchInfo */
};
MV_BOARD_INFO rd88f6190AInfo = {
"RD-88F6190A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */
RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
rd88f6192AInfoBoardMppTypeInfo,
RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
rd88f6192AInfoBoardMppConfigValue,
0, /* intsGppMaskLow */
(1 << 3), /* intsGppMaskHigh */
RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
rd88f6192AInfoBoardDeCsInfo,
RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
NULL,
RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
rd88f6192AInfoBoardMacInfo,
RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
rd88f6192AInfoBoardGppInfo,
RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
rd88f6192AInfoBoardDebugLedIf,
0, /* ledsPolarity */
RD_88F6192A_OE_LOW, /* gppOutEnLow */
RD_88F6192A_OE_HIGH, /* gppOutEnHigh */
RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */
RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */
0, /* gppPolarityValLow */
0, /* gppPolarityValHigh */
NULL /* pSwitchInfo */
};
#define DB_88F6180A_BOARD_PCI_IF_NUM 0x0
#define DB_88F6180A_BOARD_TWSI_DEF_NUM 0x5
#define DB_88F6180A_BOARD_MAC_INFO_NUM 0x1
#define DB_88F6180A_BOARD_GPP_INFO_NUM 0x0
#define DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM 0x2
#define DB_88F6180A_BOARD_MPP_CONFIG_NUM 0x1
#define DB_88F6180A_BOARD_DEVICE_CONFIG_NUM 0x1
#define DB_88F6180A_BOARD_DEBUG_LED_NUM 0x0
MV_BOARD_TWSI_INFO db88f6180AInfoBoardTwsiDev[] =
/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
{
{BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT},
{BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT},
{BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT},
{BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT},
{BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT}
};
MV_BOARD_MAC_INFO db88f6180AInfoBoardMacInfo[] =
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
{{BOARD_MAC_SPEED_AUTO, 0x8}
};
MV_BOARD_GPP_INFO db88f6180AInfoBoardGppInfo[] =
/* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */
{
/* Muxed with TDM/Audio module via IOexpender
{BOARD_GPP_USB_VBUS, 6} */
};
MV_BOARD_MPP_TYPE_INFO db88f6180AInfoBoardMppTypeInfo[] =
/* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1,
MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */
{{MV_BOARD_OTHER, MV_BOARD_AUTO}
};
MV_DEV_CS_INFO db88f6180AInfoBoardDeCsInfo[] =
/*{deviceCS, params, devType, devWidth}*/
#if defined(MV_NAND_BOOT)
{{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */
#else
{{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */
#endif
MV_BOARD_MPP_INFO db88f6180AInfoBoardMppConfigValue[] =
{{{
DB_88F6180A_MPP0_7,
DB_88F6180A_MPP8_15,
DB_88F6180A_MPP16_23,
DB_88F6180A_MPP24_31,
DB_88F6180A_MPP32_39,
DB_88F6180A_MPP40_44
}}};
MV_BOARD_INFO db88f6180AInfo = {
"DB-88F6180A-BP", /* boardName[MAX_BOARD_NAME_LEN] */
DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
db88f6180AInfoBoardMppTypeInfo,
DB_88F6180A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
db88f6180AInfoBoardMppConfigValue,
0, /* intsGppMaskLow */
0, /* intsGppMaskHigh */
DB_88F6180A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
db88f6180AInfoBoardDeCsInfo,
DB_88F6180A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
db88f6180AInfoBoardTwsiDev,
DB_88F6180A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
db88f6180AInfoBoardMacInfo,
DB_88F6180A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
NULL,
DB_88F6180A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
NULL,
0, /* ledsPolarity */
DB_88F6180A_OE_LOW, /* gppOutEnLow */
DB_88F6180A_OE_HIGH, /* gppOutEnHigh */
DB_88F6180A_OE_VAL_LOW, /* gppOutValLow */
DB_88F6180A_OE_VAL_HIGH, /* gppOutValHigh */
0, /* gppPolarityValLow */
0, /* gppPolarityValHigh */
NULL /* pSwitchInfo */
};
#define RD_88F6281A_PCAC_BOARD_PCI_IF_NUM 0x0
#define RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM 0x1
#define RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM 0x1
#define RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM 0x0
#define RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM 0x1
#define RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM 0x1
#if defined(MV_NAND) && defined(MV_NAND_BOOT)
#define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1
#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
#define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x2
#else
#define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1
#endif
#define RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM 0x4
MV_U8 rd88f6281APcacInfoBoardDebugLedIf[] =
{38, 39, 40, 41};
MV_BOARD_MAC_INFO rd88f6281APcacInfoBoardMacInfo[] =
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
{{BOARD_MAC_SPEED_AUTO, 0x8}
};
MV_BOARD_TWSI_INFO rd88f6281APcacInfoBoardTwsiDev[] =
/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
{
{BOARD_TWSI_OTHER, 0xa7, ADDR7_BIT}
};
MV_BOARD_MPP_TYPE_INFO rd88f6281APcacInfoBoardMppTypeInfo[] =
{{MV_BOARD_OTHER, MV_BOARD_OTHER}
};
MV_DEV_CS_INFO rd88f6281APcacInfoBoardDeCsInfo[] =
/*{deviceCS, params, devType, devWidth}*/
#if defined(MV_NAND) && defined(MV_NAND_BOOT)
{{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */
#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
{
{0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */
{1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */
};
#else
{{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */
#endif
MV_BOARD_MPP_INFO rd88f6281APcacInfoBoardMppConfigValue[] =
{{{
RD_88F6281A_PCAC_MPP0_7,
RD_88F6281A_PCAC_MPP8_15,
RD_88F6281A_PCAC_MPP16_23,
RD_88F6281A_PCAC_MPP24_31,
RD_88F6281A_PCAC_MPP32_39,
RD_88F6281A_PCAC_MPP40_47,
RD_88F6281A_PCAC_MPP48_55
}}};
MV_BOARD_INFO rd88f6281APcacInfo = {
"RD-88F6281A-PCAC", /* boardName[MAX_BOARD_NAME_LEN] */
RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
rd88f6281APcacInfoBoardMppTypeInfo,
RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
rd88f6281APcacInfoBoardMppConfigValue,
0, /* intsGppMaskLow */
(1 << 3), /* intsGppMaskHigh */
RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
rd88f6281APcacInfoBoardDeCsInfo,
RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
rd88f6281APcacInfoBoardTwsiDev,
RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
rd88f6281APcacInfoBoardMacInfo,
RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
0,
RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
NULL,
0, /* ledsPolarity */
RD_88F6281A_PCAC_OE_LOW, /* gppOutEnLow */
RD_88F6281A_PCAC_OE_HIGH, /* gppOutEnHigh */
RD_88F6281A_PCAC_OE_VAL_LOW, /* gppOutValLow */
RD_88F6281A_PCAC_OE_VAL_HIGH, /* gppOutValHigh */
0, /* gppPolarityValLow */
0, /* gppPolarityValHigh */
NULL /* pSwitchInfo */
};
/* 6281 Sheeva Plug*/
#define SHEEVA_PLUG_BOARD_PCI_IF_NUM 0x0
#define SHEEVA_PLUG_BOARD_TWSI_DEF_NUM 0x0
#define SHEEVA_PLUG_BOARD_MAC_INFO_NUM 0x1
#define SHEEVA_PLUG_BOARD_GPP_INFO_NUM 0x0
#define SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN 0x1
#define SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM 0x1
#define SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM 0x1
#define SHEEVA_PLUG_BOARD_DEBUG_LED_NUM 0x1
MV_U8 sheevaPlugInfoBoardDebugLedIf[] =
{49};
MV_BOARD_MAC_INFO sheevaPlugInfoBoardMacInfo[] =
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
{{BOARD_MAC_SPEED_AUTO, 0x0}};
MV_BOARD_TWSI_INFO sheevaPlugInfoBoardTwsiDev[] =
/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
{{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}};
MV_BOARD_MPP_TYPE_INFO sheevaPlugInfoBoardMppTypeInfo[] =
{{MV_BOARD_OTHER, MV_BOARD_OTHER}
};
MV_DEV_CS_INFO sheevaPlugInfoBoardDeCsInfo[] =
/*{deviceCS, params, devType, devWidth}*/
{{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */
MV_BOARD_MPP_INFO sheevaPlugInfoBoardMppConfigValue[] =
{{{
RD_SHEEVA_PLUG_MPP0_7,
RD_SHEEVA_PLUG_MPP8_15,
RD_SHEEVA_PLUG_MPP16_23,
RD_SHEEVA_PLUG_MPP24_31,
RD_SHEEVA_PLUG_MPP32_39,
RD_SHEEVA_PLUG_MPP40_47,
RD_SHEEVA_PLUG_MPP48_55
}}};
MV_BOARD_INFO sheevaPlugInfo = {
"SHEEVA PLUG", /* boardName[MAX_BOARD_NAME_LEN] */
SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */
sheevaPlugInfoBoardMppTypeInfo,
SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
sheevaPlugInfoBoardMppConfigValue,
0, /* intsGppMaskLow */
0, /* intsGppMaskHigh */
SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
sheevaPlugInfoBoardDeCsInfo,
SHEEVA_PLUG_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
sheevaPlugInfoBoardTwsiDev,
SHEEVA_PLUG_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
sheevaPlugInfoBoardMacInfo,
SHEEVA_PLUG_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
0,
SHEEVA_PLUG_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
sheevaPlugInfoBoardDebugLedIf,
0, /* ledsPolarity */
RD_SHEEVA_PLUG_OE_LOW, /* gppOutEnLow */
RD_SHEEVA_PLUG_OE_HIGH, /* gppOutEnHigh */
RD_SHEEVA_PLUG_OE_VAL_LOW, /* gppOutValLow */
RD_SHEEVA_PLUG_OE_VAL_HIGH, /* gppOutValHigh */
0, /* gppPolarityValLow */
0, /* gppPolarityValHigh */
NULL /* pSwitchInfo */
};
/* Customer specific board place holder*/
#define DB_CUSTOMER_BOARD_PCI_IF_NUM 0x0
#define DB_CUSTOMER_BOARD_TWSI_DEF_NUM 0x0
#define DB_CUSTOMER_BOARD_MAC_INFO_NUM 0x0
#define DB_CUSTOMER_BOARD_GPP_INFO_NUM 0x0
#define DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN 0x0
#define DB_CUSTOMER_BOARD_MPP_CONFIG_NUM 0x0
#if defined(MV_NAND) && defined(MV_NAND_BOOT)
#define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0
#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
#define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0
#else
#define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0
#endif
#define DB_CUSTOMER_BOARD_DEBUG_LED_NUM 0x0
MV_U8 dbCustomerInfoBoardDebugLedIf[] =
{0};
MV_BOARD_MAC_INFO dbCustomerInfoBoardMacInfo[] =
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
{{BOARD_MAC_SPEED_AUTO, 0x0}};
MV_BOARD_TWSI_INFO dbCustomerInfoBoardTwsiDev[] =
/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
{{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}};
MV_BOARD_MPP_TYPE_INFO dbCustomerInfoBoardMppTypeInfo[] =
{{MV_BOARD_OTHER, MV_BOARD_OTHER}
};
MV_DEV_CS_INFO dbCustomerInfoBoardDeCsInfo[] =
/*{deviceCS, params, devType, devWidth}*/
#if defined(MV_NAND) && defined(MV_NAND_BOOT)
{{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */
#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
{
{0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */
{2, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */
};
#else
{{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */
#endif
MV_BOARD_MPP_INFO dbCustomerInfoBoardMppConfigValue[] =
{{{
DB_CUSTOMER_MPP0_7,
DB_CUSTOMER_MPP8_15,
DB_CUSTOMER_MPP16_23,
DB_CUSTOMER_MPP24_31,
DB_CUSTOMER_MPP32_39,
DB_CUSTOMER_MPP40_47,
DB_CUSTOMER_MPP48_55
}}};
MV_BOARD_INFO dbCustomerInfo = {
"DB-CUSTOMER", /* boardName[MAX_BOARD_NAME_LEN] */
DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */
dbCustomerInfoBoardMppTypeInfo,
DB_CUSTOMER_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
dbCustomerInfoBoardMppConfigValue,
0, /* intsGppMaskLow */
0, /* intsGppMaskHigh */
DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
dbCustomerInfoBoardDeCsInfo,
DB_CUSTOMER_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
dbCustomerInfoBoardTwsiDev,
DB_CUSTOMER_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
dbCustomerInfoBoardMacInfo,
DB_CUSTOMER_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
0,
DB_CUSTOMER_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
NULL,
0, /* ledsPolarity */
DB_CUSTOMER_OE_LOW, /* gppOutEnLow */
DB_CUSTOMER_OE_HIGH, /* gppOutEnHigh */
DB_CUSTOMER_OE_VAL_LOW, /* gppOutValLow */
DB_CUSTOMER_OE_VAL_HIGH, /* gppOutValHigh */
0, /* gppPolarityValLow */
0, /* gppPolarityValHigh */
NULL /* pSwitchInfo */
};
MV_BOARD_INFO* boardInfoTbl[] = {
&db88f6281AInfo,
&rd88f6281AInfo,
&db88f6192AInfo,
&rd88f6192AInfo,
&db88f6180AInfo,
&db88f6190AInfo,
&rd88f6190AInfo,
&rd88f6281APcacInfo,
&dbCustomerInfo,
&sheevaPlugInfo
};

262
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h
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@ -1,262 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvBoardEnvSpech
#define __INCmvBoardEnvSpech
#include "mvSysHwConfig.h"
/* For future use */
#define BD_ID_DATA_START_OFFS 0x0
#define BD_DETECT_SEQ_OFFS 0x0
#define BD_SYS_NUM_OFFS 0x4
#define BD_NAME_OFFS 0x8
/* I2C bus addresses */
#define MV_BOARD_CTRL_I2C_ADDR 0x0 /* Controller slave addr */
#define MV_BOARD_CTRL_I2C_ADDR_TYPE ADDR7_BIT
#define MV_BOARD_DIMM0_I2C_ADDR 0x56
#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT
#define MV_BOARD_DIMM1_I2C_ADDR 0x54
#define MV_BOARD_DIMM1_I2C_ADDR_TYPE ADDR7_BIT
#define MV_BOARD_EEPROM_I2C_ADDR 0x51
#define MV_BOARD_EEPROM_I2C_ADDR_TYPE ADDR7_BIT
#define MV_BOARD_MAIN_EEPROM_I2C_ADDR 0x50
#define MV_BOARD_MAIN_EEPROM_I2C_ADDR_TYPE ADDR7_BIT
#define MV_BOARD_MUX_I2C_ADDR_ENTRY 0x2
#define MV_BOARD_DIMM_I2C_CHANNEL 0x0
#define BOOT_FLASH_INDEX 0
#define MAIN_FLASH_INDEX 1
#define BOARD_ETH_START_PORT_NUM 0
/* Supported clocks */
#define MV_BOARD_TCLK_100MHZ 100000000
#define MV_BOARD_TCLK_125MHZ 125000000
#define MV_BOARD_TCLK_133MHZ 133333333
#define MV_BOARD_TCLK_150MHZ 150000000
#define MV_BOARD_TCLK_166MHZ 166666667
#define MV_BOARD_TCLK_200MHZ 200000000
#define MV_BOARD_SYSCLK_100MHZ 100000000
#define MV_BOARD_SYSCLK_125MHZ 125000000
#define MV_BOARD_SYSCLK_133MHZ 133333333
#define MV_BOARD_SYSCLK_150MHZ 150000000
#define MV_BOARD_SYSCLK_166MHZ 166666667
#define MV_BOARD_SYSCLK_200MHZ 200000000
#define MV_BOARD_SYSCLK_233MHZ 233333333
#define MV_BOARD_SYSCLK_250MHZ 250000000
#define MV_BOARD_SYSCLK_267MHZ 266666667
#define MV_BOARD_SYSCLK_300MHZ 300000000
#define MV_BOARD_SYSCLK_333MHZ 333333334
#define MV_BOARD_SYSCLK_400MHZ 400000000
#define MV_BOARD_REFCLK_25MHZ 25000000
/* Board specific */
/* =============================== */
/* boards ID numbers */
#define BOARD_ID_BASE 0x0
/* New board ID numbers */
#define DB_88F6281A_BP_ID (BOARD_ID_BASE)
#define DB_88F6281_BP_MLL_ID 1680
#define RD_88F6281A_ID (BOARD_ID_BASE+0x1)
#define RD_88F6281_MLL_ID 1682
#define DB_88F6192A_BP_ID (BOARD_ID_BASE+0x2)
#define RD_88F6192A_ID (BOARD_ID_BASE+0x3)
#define RD_88F6192_MLL_ID 1681
#define DB_88F6180A_BP_ID (BOARD_ID_BASE+0x4)
#define DB_88F6190A_BP_ID (BOARD_ID_BASE+0x5)
#define RD_88F6190A_ID (BOARD_ID_BASE+0x6)
#define RD_88F6281A_PCAC_ID (BOARD_ID_BASE+0x7)
#define DB_CUSTOMER_ID (BOARD_ID_BASE+0x8)
#define SHEEVA_PLUG_ID (BOARD_ID_BASE+0x9)
#define MV_MAX_BOARD_ID (SHEEVA_PLUG_ID + 1)
/* DB-88F6281A-BP */
#if defined(MV_NAND)
#define DB_88F6281A_MPP0_7 0x21111111
#else
#define DB_88F6281A_MPP0_7 0x21112220
#endif
#define DB_88F6281A_MPP8_15 0x11113311
#define DB_88F6281A_MPP16_23 0x00551111
#define DB_88F6281A_MPP24_31 0x00000000
#define DB_88F6281A_MPP32_39 0x00000000
#define DB_88F6281A_MPP40_47 0x00000000
#define DB_88F6281A_MPP48_55 0x00000000
#define DB_88F6281A_OE_LOW 0x0
#if defined(MV_TDM_5CHANNELS)
#define DB_88F6281A_OE_HIGH (BIT6)
#else
#define DB_88F6281A_OE_HIGH 0x0
#endif
#define DB_88F6281A_OE_VAL_LOW 0x0
#define DB_88F6281A_OE_VAL_HIGH 0x0
/* RD-88F6281A */
#if defined(MV_NAND)
#define RD_88F6281A_MPP0_7 0x21111111
#else
#define RD_88F6281A_MPP0_7 0x21112220
#endif
#define RD_88F6281A_MPP8_15 0x11113311
#define RD_88F6281A_MPP16_23 0x33331111
#define RD_88F6281A_MPP24_31 0x33003333
#define RD_88F6281A_MPP32_39 0x20440533
#define RD_88F6281A_MPP40_47 0x22202222
#define RD_88F6281A_MPP48_55 0x00000002
#define RD_88F6281A_OE_LOW (BIT28 | BIT29)
#define RD_88F6281A_OE_HIGH (BIT3 | BIT6 | BIT17)
#define RD_88F6281A_OE_VAL_LOW 0x0
#define RD_88F6281A_OE_VAL_HIGH 0x0
/* DB-88F6192A-BP */
#if defined(MV_NAND)
#define DB_88F6192A_MPP0_7 0x21111111
#else
#define DB_88F6192A_MPP0_7 0x21112220
#endif
#define DB_88F6192A_MPP8_15 0x11113311
#define DB_88F6192A_MPP16_23 0x00501111
#define DB_88F6192A_MPP24_31 0x00000000
#define DB_88F6192A_MPP32_35 0x00000000
#define DB_88F6192A_OE_LOW (BIT22 | BIT23)
#define DB_88F6192A_OE_HIGH 0x0
#define DB_88F6192A_OE_VAL_LOW 0x0
#define DB_88F6192A_OE_VAL_HIGH 0x0
/* RD-88F6192A */
#define RD_88F6192A_MPP0_7 0x01222222
#define RD_88F6192A_MPP8_15 0x00000011
#define RD_88F6192A_MPP16_23 0x05550000
#define RD_88F6192A_MPP24_31 0x0
#define RD_88F6192A_MPP32_35 0x0
#define RD_88F6192A_OE_LOW (BIT11 | BIT14 | BIT24 | BIT25 | BIT26 | BIT27 | BIT30 | BIT31)
#define RD_88F6192A_OE_HIGH (BIT0 | BIT2)
#define RD_88F6192A_OE_VAL_LOW 0x18400
#define RD_88F6192A_OE_VAL_HIGH 0x8
/* DB-88F6180A-BP */
#if defined(MV_NAND)
#define DB_88F6180A_MPP0_7 0x21111111
#else
#define DB_88F6180A_MPP0_7 0x01112222
#endif
#define DB_88F6180A_MPP8_15 0x11113311
#define DB_88F6180A_MPP16_23 0x00001111
#define DB_88F6180A_MPP24_31 0x0
#define DB_88F6180A_MPP32_39 0x4444c000
#define DB_88F6180A_MPP40_44 0x00044444
#define DB_88F6180A_OE_LOW 0x0
#define DB_88F6180A_OE_HIGH 0x0
#define DB_88F6180A_OE_VAL_LOW 0x0
#define DB_88F6180A_OE_VAL_HIGH 0x0
/* RD-88F6281A_PCAC */
#define RD_88F6281A_PCAC_MPP0_7 0x21111111
#define RD_88F6281A_PCAC_MPP8_15 0x00003311
#define RD_88F6281A_PCAC_MPP16_23 0x00001100
#define RD_88F6281A_PCAC_MPP24_31 0x00000000
#define RD_88F6281A_PCAC_MPP32_39 0x00000000
#define RD_88F6281A_PCAC_MPP40_47 0x00000000
#define RD_88F6281A_PCAC_MPP48_55 0x00000000
#define RD_88F6281A_PCAC_OE_LOW 0x0
#define RD_88F6281A_PCAC_OE_HIGH 0x0
#define RD_88F6281A_PCAC_OE_VAL_LOW 0x0
#define RD_88F6281A_PCAC_OE_VAL_HIGH 0x0
/* SHEEVA PLUG */
#define RD_SHEEVA_PLUG_MPP0_7 0x01111111
#define RD_SHEEVA_PLUG_MPP8_15 0x11113322
#define RD_SHEEVA_PLUG_MPP16_23 0x00001111
#define RD_SHEEVA_PLUG_MPP24_31 0x00100000
#define RD_SHEEVA_PLUG_MPP32_39 0x00000000
#define RD_SHEEVA_PLUG_MPP40_47 0x00000000
#define RD_SHEEVA_PLUG_MPP48_55 0x00000000
#define RD_SHEEVA_PLUG_OE_LOW 0x0
#define RD_SHEEVA_PLUG_OE_HIGH 0x0
#define RD_SHEEVA_PLUG_OE_VAL_LOW (BIT29)
#define RD_SHEEVA_PLUG_OE_VAL_HIGH ((~(BIT17 | BIT16 | BIT15)) | BIT14)
/* DB-CUSTOMER */
#define DB_CUSTOMER_MPP0_7 0x21111111
#define DB_CUSTOMER_MPP8_15 0x00003311
#define DB_CUSTOMER_MPP16_23 0x00001100
#define DB_CUSTOMER_MPP24_31 0x00000000
#define DB_CUSTOMER_MPP32_39 0x00000000
#define DB_CUSTOMER_MPP40_47 0x00000000
#define DB_CUSTOMER_MPP48_55 0x00000000
#define DB_CUSTOMER_OE_LOW 0x0
#define DB_CUSTOMER_OE_HIGH (~((BIT6) | (BIT7) | (BIT8) | (BIT9)))
#define DB_CUSTOMER_OE_VAL_LOW 0x0
#define DB_CUSTOMER_OE_VAL_HIGH 0x0
#endif /* __INCmvBoardEnvSpech */

320
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c
View File

@ -1,320 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "cpu/mvCpu.h"
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "ctrlEnv/mvCtrlEnvRegs.h"
#include "ctrlEnv/sys/mvCpuIfRegs.h"
/* defines */
#ifdef MV_DEBUG
#define DB(x) x
#else
#define DB(x)
#endif
/* locals */
/*******************************************************************************
* mvCpuPclkGet - Get the CPU pClk (pipe clock)
*
* DESCRIPTION:
* This routine extract the CPU core clock.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* 32bit clock cycles in MHertz.
*
*******************************************************************************/
/* 6180 have different clk reset sampling */
static MV_U32 mvCpu6180PclkGet(MV_VOID)
{
MV_U32 tmpPClkRate=0;
MV_CPU_ARM_CLK cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL;
tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET);
tmpPClkRate = tmpPClkRate & MSAR_CPUCLCK_MASK_6180;
tmpPClkRate = tmpPClkRate >> MSAR_CPUCLCK_OFFS_6180;
tmpPClkRate = cpu6180_ddr_l2_CLK[tmpPClkRate].cpuClk;
return tmpPClkRate;
}
MV_U32 mvCpuPclkGet(MV_VOID)
{
#if defined(PCLCK_AUTO_DETECT)
MV_U32 tmpPClkRate=0;
MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL;
if(mvCtrlModelGet() == MV_6180_DEV_ID)
return mvCpu6180PclkGet();
tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET);
tmpPClkRate = MSAR_CPUCLCK_EXTRACT(tmpPClkRate);
tmpPClkRate = cpuCLK[tmpPClkRate];
return tmpPClkRate;
#else
return MV_DEFAULT_PCLK
#endif
}
/*******************************************************************************
* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock)
*
* DESCRIPTION:
* This routine extract the CPU L2 clock.
*
* RETURN:
* 32bit clock cycles in Hertz.
*
*******************************************************************************/
static MV_U32 mvCpu6180L2ClkGet(MV_VOID)
{
MV_U32 L2ClkRate=0;
MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL;
L2ClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET);
L2ClkRate = L2ClkRate & MSAR_CPUCLCK_MASK_6180;
L2ClkRate = L2ClkRate >> MSAR_CPUCLCK_OFFS_6180;
L2ClkRate = _cpu6180_ddr_l2_CLK[L2ClkRate].l2Clk;
return L2ClkRate;
}
MV_U32 mvCpuL2ClkGet(MV_VOID)
{
#ifdef L2CLK_AUTO_DETECT
MV_U32 L2ClkRate, tmp, pClkRate, indexL2Rtio;
MV_U32 L2Rtio[][2] = MV_L2_CLCK_RTIO_TBL;
if(mvCtrlModelGet() == MV_6180_DEV_ID)
return mvCpu6180L2ClkGet();
pClkRate = mvCpuPclkGet();
tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET);
indexL2Rtio = MSAR_L2CLCK_EXTRACT(tmp);
L2ClkRate = ((pClkRate * L2Rtio[indexL2Rtio][1]) / L2Rtio[indexL2Rtio][0]);
return L2ClkRate;
#else
return MV_BOARD_DEFAULT_L2CLK;
#endif
}
/*******************************************************************************
* mvCpuNameGet - Get CPU name
*
* DESCRIPTION:
* This function returns a string describing the CPU model and revision.
*
* INPUT:
* None.
*
* OUTPUT:
* pNameBuff - Buffer to contain board name string. Minimum size 32 chars.
*
* RETURN:
* None.
*******************************************************************************/
MV_VOID mvCpuNameGet(char *pNameBuff)
{
MV_U32 cpuModel;
cpuModel = mvOsCpuPartGet();
/* The CPU module is indicated in the Processor Version Register (PVR) */
switch(cpuModel)
{
case CPU_PART_MRVL131:
mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell Feroceon",mvOsCpuRevGet());
break;
case CPU_PART_ARM926:
mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM926",mvOsCpuRevGet());
break;
case CPU_PART_ARM946:
mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM946",mvOsCpuRevGet());
break;
default:
mvOsSPrintf(pNameBuff,"??? (0x%04x) (Rev %d)",cpuModel,mvOsCpuRevGet());
break;
} /* switch */
return;
}
#define MV_PROC_STR_SIZE 50
static void mvCpuIfGetL2EccMode(MV_8 *buf)
{
MV_U32 regVal = MV_REG_READ(CPU_L2_CONFIG_REG);
if (regVal & BIT2)
mvOsSPrintf(buf, "L2 ECC Enabled");
else
mvOsSPrintf(buf, "L2 ECC Disabled");
}
static void mvCpuIfGetL2Mode(MV_8 *buf)
{
MV_U32 regVal = 0;
__asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
if (regVal & BIT22)
mvOsSPrintf(buf, "L2 Enabled");
else
mvOsSPrintf(buf, "L2 Disabled");
}
static void mvCpuIfGetL2PrefetchMode(MV_8 *buf)
{
MV_U32 regVal = 0;
__asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
if (regVal & BIT24)
mvOsSPrintf(buf, "L2 Prefetch Disabled");
else
mvOsSPrintf(buf, "L2 Prefetch Enabled");
}
static void mvCpuIfGetWriteAllocMode(MV_8 *buf)
{
MV_U32 regVal = 0;
__asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
if (regVal & BIT28)
mvOsSPrintf(buf, "Write Allocate Enabled");
else
mvOsSPrintf(buf, "Write Allocate Disabled");
}
static void mvCpuIfGetCpuStreamMode(MV_8 *buf)
{
MV_U32 regVal = 0;
__asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
if (regVal & BIT29)
mvOsSPrintf(buf, "CPU Streaming Enabled");
else
mvOsSPrintf(buf, "CPU Streaming Disabled");
}
static void mvCpuIfPrintCpuRegs(void)
{
MV_U32 regVal = 0;
__asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
mvOsPrintf("Extra Feature Reg = 0x%x\n",regVal);
__asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */
mvOsPrintf("Control Reg = 0x%x\n",regVal);
__asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read ID Code register */
mvOsPrintf("ID Code Reg = 0x%x\n",regVal);
__asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */
mvOsPrintf("Cache Type Reg = 0x%x\n",regVal);
}
MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index)
{
MV_U32 count = 0;
MV_8 L2_ECC_str[MV_PROC_STR_SIZE];
MV_8 L2_En_str[MV_PROC_STR_SIZE];
MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE];
MV_8 Write_Alloc_str[MV_PROC_STR_SIZE];
MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE];
mvCpuIfGetL2Mode(L2_En_str);
mvCpuIfGetL2EccMode(L2_ECC_str);
mvCpuIfGetL2PrefetchMode(L2_Prefetch_str);
mvCpuIfGetWriteAllocMode(Write_Alloc_str);
mvCpuIfGetCpuStreamMode(Cpu_Stream_str);
mvCpuIfPrintCpuRegs();
count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str);
count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str);
count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str);
count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str);
count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str);
return count;
}
MV_U32 whoAmI(MV_VOID)
{
return 0;
}

99
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h
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@ -1,99 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvCpuh
#define __INCmvCpuh
#include "mvCommon.h"
#include "mvOs.h"
#include "ctrlEnv/mvCtrlEnvSpec.h"
/* defines */
#define CPU_PART_MRVL131 0x131
#define CPU_PART_ARM926 0x926
#define CPU_PART_ARM946 0x946
#define MV_CPU_ARM_CLK_ELM_SIZE 12
#define MV_CPU_ARM_CLK_RATIO_OFF 8
#define MV_CPU_ARM_CLK_DDR_OFF 4
#ifndef MV_ASMLANGUAGE
typedef struct _mvCpuArmClk
{
MV_U32 cpuClk; /* CPU clock in MHz */
MV_U32 ddrClk; /* DDR clock in MHz */
MV_U32 l2Clk; /* CPU DDR clock ratio */
}MV_CPU_ARM_CLK;
MV_U32 mvCpuPclkGet(MV_VOID);
MV_VOID mvCpuNameGet(char *pNameBuff);
MV_U32 mvCpuL2ClkGet(MV_VOID);
MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index);
MV_U32 whoAmI(MV_VOID);
#endif /* MV_ASMLANGUAGE */
#endif /* __INCmvCpuh */

296
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c
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@ -1,296 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/*******************************************************************************
* mvCtrlEnvAddrDec.h - Marvell controller address decode library
*
* DESCRIPTION:
*
* DEPENDENCIES:
* None.
*
*******************************************************************************/
/* includes */
#include "ctrlEnv/mvCtrlEnvAddrDec.h"
#include "ctrlEnv/sys/mvAhbToMbusRegs.h"
#include "ddr2/mvDramIfRegs.h"
#include "pex/mvPexRegs.h"
#define MV_DEBUG
/* defines */
#ifdef MV_DEBUG
#define DB(x) x
#else
#define DB(x)
#endif
/* Default Attributes array */
MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY;
extern MV_TARGET *sampleAtResetTargetArray;
/* Dram\AHBToMbus\PEX share regsiter */
#define CTRL_DEC_BASE_OFFS 16
#define CTRL_DEC_BASE_MASK (0xffff << CTRL_DEC_BASE_OFFS)
#define CTRL_DEC_BASE_ALIGNMENT 0x10000
#define CTRL_DEC_SIZE_OFFS 16
#define CTRL_DEC_SIZE_MASK (0xffff << CTRL_DEC_SIZE_OFFS)
#define CTRL_DEC_SIZE_ALIGNMENT 0x10000
#define CTRL_DEC_WIN_EN BIT0
/*******************************************************************************
* mvCtrlAddrDecToReg - Get address decode register format values
*
* DESCRIPTION:
*
* INPUT:
*
* OUTPUT:
*
* RETURN:
*
*******************************************************************************/
MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, MV_DEC_REGS *pAddrDecRegs)
{
MV_U32 baseToReg=0 , sizeToReg=0;
/* BaseLow[31:16] => base register [31:16] */
baseToReg = pAddrDecWin->baseLow & CTRL_DEC_BASE_MASK;
/* Write to address decode Base Address Register */
pAddrDecRegs->baseReg &= ~CTRL_DEC_BASE_MASK;
pAddrDecRegs->baseReg |= baseToReg;
/* Get size register value according to window size */
sizeToReg = ctrlSizeToReg(pAddrDecWin->size, CTRL_DEC_SIZE_ALIGNMENT);
/* Size parameter validity check. */
if (-1 == sizeToReg)
{
return MV_BAD_PARAM;
}
/* set size */
pAddrDecRegs->sizeReg &= ~CTRL_DEC_SIZE_MASK;
pAddrDecRegs->sizeReg |= (sizeToReg << CTRL_DEC_SIZE_OFFS);
return MV_OK;
}
/*******************************************************************************
* mvCtrlRegToAddrDec - Extract address decode struct from registers.
*
* DESCRIPTION:
* This function extract address decode struct from address decode
* registers given as parameters.
*
* INPUT:
* pAddrDecRegs - Address decode register struct.
*
* OUTPUT:
* pAddrDecWin - Target window data structure.
*
* RETURN:
* MV_BAD_PARAM if address decode registers data is invalid.
*
*******************************************************************************/
MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, MV_ADDR_WIN *pAddrDecWin)
{
MV_U32 sizeRegVal;
sizeRegVal = (pAddrDecRegs->sizeReg & CTRL_DEC_SIZE_MASK) >>
CTRL_DEC_SIZE_OFFS;
pAddrDecWin->size = ctrlRegToSize(sizeRegVal, CTRL_DEC_SIZE_ALIGNMENT);
/* Extract base address */
/* Base register [31:16] ==> baseLow[31:16] */
pAddrDecWin->baseLow = pAddrDecRegs->baseReg & CTRL_DEC_BASE_MASK;
pAddrDecWin->baseHigh = 0;
return MV_OK;
}
/*******************************************************************************
* mvCtrlAttribGet -
*
* DESCRIPTION:
*
* INPUT:
*
* OUTPUT:
*
* RETURN:
*
*******************************************************************************/
MV_STATUS mvCtrlAttribGet(MV_TARGET target,
MV_TARGET_ATTRIB *targetAttrib)
{
targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib;
targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId;
return MV_OK;
}
/*******************************************************************************
* mvCtrlGetAttrib -
*
* DESCRIPTION:
*
* INPUT:
*
* OUTPUT:
*
* RETURN:
*
*******************************************************************************/
MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib)
{
MV_TARGET target;
MV_TARGET x;
for (target = SDRAM_CS0; target < MAX_TARGETS ; target ++)
{
x = MV_CHANGE_BOOT_CS(target);
if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) &&
(mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == targetAttrib->targetId))
{
/* found it */
break;
}
}
return target;
}
MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin,
MV_DEC_WIN_PARAMS *pWinParam)
{
MV_U32 baseToReg=0, sizeToReg=0;
/* BaseLow[31:16] => base register [31:16] */
baseToReg = pAddrDecWin->addrWin.baseLow & CTRL_DEC_BASE_MASK;
/* Write to address decode Base Address Register */
pWinParam->baseAddr &= ~CTRL_DEC_BASE_MASK;
pWinParam->baseAddr |= baseToReg;
/* Get size register value according to window size */
sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, CTRL_DEC_SIZE_ALIGNMENT);
/* Size parameter validity check. */
if (-1 == sizeToReg)
{
mvOsPrintf("mvCtrlAddrDecToParams: ERR. ctrlSizeToReg failed.\n");
return MV_BAD_PARAM;
}
pWinParam->size = sizeToReg;
pWinParam->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].attrib;
pWinParam->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].targetId;
return MV_OK;
}
MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam,
MV_DEC_WIN *pAddrDecWin)
{
MV_TARGET_ATTRIB targetAttrib;
pAddrDecWin->addrWin.baseLow = pWinParam->baseAddr;
/* Upper 32bit address base is supported under PCI High Address remap */
pAddrDecWin->addrWin.baseHigh = 0;
/* Prepare sizeReg to ctrlRegToSize function */
pAddrDecWin->addrWin.size = ctrlRegToSize(pWinParam->size, CTRL_DEC_SIZE_ALIGNMENT);
if (-1 == pAddrDecWin->addrWin.size)
{
DB(mvOsPrintf("mvCtrlParamsToAddrDec: ERR. ctrlRegToSize failed.\n"));
return MV_BAD_PARAM;
}
targetAttrib.targetId = pWinParam->targetId;
targetAttrib.attrib = pWinParam->attrib;
pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
return MV_OK;
}

203
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h
View File

@ -1,203 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvCtrlEnvAddrDech
#define __INCmvCtrlEnvAddrDech
/* includes */
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "ctrlEnv/mvCtrlEnvRegs.h"
/* defines */
/* DUnit attributes */
#define ATMWCR_WIN_DUNIT_CS0_OFFS 0
#define ATMWCR_WIN_DUNIT_CS0_MASK BIT0
#define ATMWCR_WIN_DUNIT_CS0_REQ (0 << ATMWCR_WIN_DUNIT_CS0_OFFS)
#define ATMWCR_WIN_DUNIT_CS1_OFFS 1
#define ATMWCR_WIN_DUNIT_CS1_MASK BIT1
#define ATMWCR_WIN_DUNIT_CS1_REQ (0 << ATMWCR_WIN_DUNIT_CS1_OFFS)
#define ATMWCR_WIN_DUNIT_CS2_OFFS 2
#define ATMWCR_WIN_DUNIT_CS2_MASK BIT2
#define ATMWCR_WIN_DUNIT_CS2_REQ (0 << ATMWCR_WIN_DUNIT_CS2_OFFS)
#define ATMWCR_WIN_DUNIT_CS3_OFFS 3
#define ATMWCR_WIN_DUNIT_CS3_MASK BIT3
#define ATMWCR_WIN_DUNIT_CS3_REQ (0 << ATMWCR_WIN_DUNIT_CS3_OFFS)
/* RUnit (Device) attributes */
#define ATMWCR_WIN_RUNIT_DEVCS0_OFFS 0
#define ATMWCR_WIN_RUNIT_DEVCS0_MASK BIT0
#define ATMWCR_WIN_RUNIT_DEVCS0_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS0_OFFS)
#define ATMWCR_WIN_RUNIT_DEVCS1_OFFS 1
#define ATMWCR_WIN_RUNIT_DEVCS1_MASK BIT1
#define ATMWCR_WIN_RUNIT_DEVCS1_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS1_OFFS)
#define ATMWCR_WIN_RUNIT_DEVCS2_OFFS 2
#define ATMWCR_WIN_RUNIT_DEVCS2_MASK BIT2
#define ATMWCR_WIN_RUNIT_DEVCS2_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS2_OFFS)
#define ATMWCR_WIN_RUNIT_BOOTCS_OFFS 4
#define ATMWCR_WIN_RUNIT_BOOTCS_MASK BIT4
#define ATMWCR_WIN_RUNIT_BOOTCS_REQ (0 << ATMWCR_WIN_RUNIT_BOOTCS_OFFS)
/* LMaster (PCI) attributes */
#define ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS 0
#define ATMWCR_WIN_LUNIT_BYTE_SWP_MASK BIT0
#define ATMWCR_WIN_LUNIT_BYTE_SWP (0 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS)
#define ATMWCR_WIN_LUNIT_BYTE_NO_SWP (1 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS)
#define ATMWCR_WIN_LUNIT_WORD_SWP_OFFS 1
#define ATMWCR_WIN_LUNIT_WORD_SWP_MASK BIT1
#define ATMWCR_WIN_LUNIT_WORD_SWP (0 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS)
#define ATMWCR_WIN_LUNIT_WORD_NO_SWP (1 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS)
#define ATMWCR_WIN_LUNIT_NO_SNOOP BIT2
#define ATMWCR_WIN_LUNIT_TYPE_OFFS 3
#define ATMWCR_WIN_LUNIT_TYPE_MASK BIT3
#define ATMWCR_WIN_LUNIT_TYPE_IO (0 << ATMWCR_WIN_LUNIT_TYPE_OFFS)
#define ATMWCR_WIN_LUNIT_TYPE_MEM (1 << ATMWCR_WIN_LUNIT_TYPE_OFFS)
#define ATMWCR_WIN_LUNIT_FORCE64_OFFS 4
#define ATMWCR_WIN_LUNIT_FORCE64_MASK BIT4
#define ATMWCR_WIN_LUNIT_FORCE64 (0 << ATMWCR_WIN_LUNIT_FORCE64_OFFS)
#define ATMWCR_WIN_LUNIT_ORDERING_OFFS 6
#define ATMWCR_WIN_LUNIT_ORDERING_MASK BIT6
#define ATMWCR_WIN_LUNIT_ORDERING (1 << ATMWCR_WIN_LUNIT_FORCE64_OFFS)
/* PEX Attributes */
#define ATMWCR_WIN_PEX_TYPE_OFFS 3
#define ATMWCR_WIN_PEX_TYPE_MASK BIT3
#define ATMWCR_WIN_PEX_TYPE_IO (0 << ATMWCR_WIN_PEX_TYPE_OFFS)
#define ATMWCR_WIN_PEX_TYPE_MEM (1 << ATMWCR_WIN_PEX_TYPE_OFFS)
/* typedefs */
/* Unsupported attributes for address decode: */
/* 2) PCI0/1_REQ64n control */
typedef struct _mvDecRegs
{
MV_U32 baseReg;
MV_U32 baseRegHigh;
MV_U32 sizeReg;
}MV_DEC_REGS;
typedef struct _mvTargetAttrib
{
MV_U8 attrib; /* chip select attributes */
MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */
}MV_TARGET_ATTRIB;
/* This structure describes address decode window */
typedef struct _mvDecWin
{
MV_TARGET target; /* Target for addr decode window */
MV_ADDR_WIN addrWin; /* Address window of target */
MV_BOOL enable; /* Window enable/disable */
}MV_DEC_WIN;
typedef struct _mvDecWinParams
{
MV_TARGET_ID targetId; /* Target ID field */
MV_U8 attrib; /* Attribute field */
MV_U32 baseAddr; /* Base address in register format */
MV_U32 size; /* Size in register format */
}MV_DEC_WIN_PARAMS;
/* mvCtrlEnvAddrDec API list */
MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin,
MV_DEC_REGS *pAddrDecRegs);
MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs,
MV_ADDR_WIN *pAddrDecWin);
MV_STATUS mvCtrlAttribGet(MV_TARGET target,
MV_TARGET_ATTRIB *targetAttrib);
MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib);
MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin,
MV_DEC_WIN_PARAMS *pWinParam);
MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam,
MV_DEC_WIN *pAddrDecWin);
#endif /* __INCmvCtrlEnvAddrDech */

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target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h
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@ -1,98 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvCtrlEnvAsmh
#define __INCmvCtrlEnvAsmh
#include "pex/mvPexRegs.h"
#define CHIP_BOND_REG 0x10034
#define PCKG_OPT_MASK_AS #3
#define PXCCARI_REVID_MASK_AS #PXCCARI_REVID_MASK
/* Read device ID into toReg bits 15:0 from 0xd0000000 */
/* defines */
#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \
MV_DV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\
and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */
/* Read device ID into toReg bits 15:0 from 0xf1000000*/
#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \
MV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\
and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */
/* Read Revision into toReg bits 7:0 0xd0000000*/
#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \
/* Read device revision */ \
MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\
and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */
/* Read Revision into toReg bits 7:0 0xf1000000*/
#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \
/* Read device revision */ \
MV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\
and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */
#endif /* __INCmvCtrlEnvAsmh */

1825
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c
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185
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h
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@ -1,185 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvCtrlEnvLibh
#define __INCmvCtrlEnvLibh
/* includes */
#include "mvSysHwConfig.h"
#include "mvCommon.h"
#include "mvTypes.h"
#include "mvOs.h"
#include "boardEnv/mvBoardEnvLib.h"
#include "ctrlEnv/mvCtrlEnvSpec.h"
#include "ctrlEnv/mvCtrlEnvRegs.h"
#include "ctrlEnv/mvCtrlEnvAddrDec.h"
/* typedefs */
/* This enumerator describes the possible HW cache coherency policies the */
/* controllers supports. */
typedef enum _mvCachePolicy
{
NO_COHERENCY, /* No HW cache coherency support */
WT_COHERENCY, /* HW cache coherency supported in Write Through policy */
WB_COHERENCY /* HW cache coherency supported in Write Back policy */
}MV_CACHE_POLICY;
/* The swapping is referred to a 64-bit words (as this is the controller */
/* internal data path width). This enumerator describes the possible */
/* data swap types. Below is an example of the data 0x0011223344556677 */
typedef enum _mvSwapType
{
MV_BYTE_SWAP, /* Byte Swap 77 66 55 44 33 22 11 00 */
MV_NO_SWAP, /* No swapping 00 11 22 33 44 55 66 77 */
MV_BYTE_WORD_SWAP, /* Both byte and word swap 33 22 11 00 77 66 55 44 */
MV_WORD_SWAP, /* Word swap 44 55 66 77 00 11 22 33 */
SWAP_TYPE_MAX /* Delimiter for this enumerator */
}MV_SWAP_TYPE;
/* This structure describes access rights for Access protection windows */
/* that can be found in IDMA, XOR, Ethernet and MPSC units. */
/* Note that the permission enumerator coresponds to its register format. */
/* For example, Read only premission is presented as "1" in register field. */
typedef enum _mvAccessRights
{
NO_ACCESS_ALLOWED = 0, /* No access allowed */
READ_ONLY = 1, /* Read only permission */
ACC_RESERVED = 2, /* Reserved access right */
FULL_ACCESS = 3, /* Read and Write permission */
MAX_ACC_RIGHTS
}MV_ACCESS_RIGHTS;
/* mcspLib.h API list */
MV_STATUS mvCtrlEnvInit(MV_VOID);
MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup);
#if defined(MV_INCLUDE_PEX)
MV_U32 mvCtrlPexMaxIfGet(MV_VOID);
#else
#define mvCtrlPexMaxIfGet() (0)
#endif
#define mvCtrlPciIfMaxIfGet() (0)
#if defined(MV_INCLUDE_GIG_ETH)
MV_U32 mvCtrlEthMaxPortGet(MV_VOID);
#endif
#if defined(MV_INCLUDE_XOR)
MV_U32 mvCtrlXorMaxChanGet(MV_VOID);
#endif
#if defined(MV_INCLUDE_USB)
MV_U32 mvCtrlUsbMaxGet(MV_VOID);
#endif
#if defined(MV_INCLUDE_NAND)
MV_U32 mvCtrlNandSupport(MV_VOID);
#endif
#if defined(MV_INCLUDE_SDIO)
MV_U32 mvCtrlSdioSupport(MV_VOID);
#endif
#if defined(MV_INCLUDE_TS)
MV_U32 mvCtrlTsSupport(MV_VOID);
#endif
#if defined(MV_INCLUDE_AUDIO)
MV_U32 mvCtrlAudioSupport(MV_VOID);
#endif
#if defined(MV_INCLUDE_TDM)
MV_U32 mvCtrlTdmSupport(MV_VOID);
#endif
MV_U16 mvCtrlModelGet(MV_VOID);
MV_U8 mvCtrlRevGet(MV_VOID);
MV_STATUS mvCtrlNameGet(char *pNameBuff);
MV_U32 mvCtrlModelRevGet(MV_VOID);
MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff);
MV_VOID mvCtrlAddrDecShow(MV_VOID);
const MV_8* mvCtrlTargetNameGet(MV_TARGET target);
MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment);
MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment);
MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment);
MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID);
MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2);
MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2);
MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable);
MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index);
MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable);
MV_BOOL mvCtrlIsBootFromSPI(MV_VOID);
MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID);
MV_BOOL mvCtrlIsBootFromNAND(MV_VOID);
#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
MV_VOID mvCtrlPwrSaveOn(MV_VOID);
MV_VOID mvCtrlPwrSaveOff(MV_VOID);
#endif
MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index);
MV_VOID mvMPPConfigToSPI(MV_VOID);
MV_VOID mvMPPConfigToDefault(MV_VOID);
#endif /* __INCmvCtrlEnvLibh */

419
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h
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@ -1,419 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvCtrlEnvRegsh
#define __INCmvCtrlEnvRegsh
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* CV Support */
#define PEX0_MEM0 PEX0_MEM
#define PCI0_MEM0 PEX0_MEM
/* Controller revision info */
#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
#define PCCRIR_REVID_OFFS 0 /* Revision ID */
#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS)
/* Controler environment registers offsets */
/* Power Managment Control */
#define POWER_MNG_MEM_CTRL_REG 0x20118
#define PMC_GESTOPMEM_OFFS(port) ((port)? 13 : 0)
#define PMC_GESTOPMEM_MASK(port) (1 << PMC_GESTOPMEM_OFFS(port))
#define PMC_GESTOPMEM_EN(port) (0 << PMC_GESTOPMEM_OFFS(port))
#define PMC_GESTOPMEM_STOP(port) (1 << PMC_GESTOPMEM_OFFS(port))
#define PMC_PEXSTOPMEM_OFFS 1
#define PMC_PEXSTOPMEM_MASK (1 << PMC_PEXSTOPMEM_OFFS)
#define PMC_PEXSTOPMEM_EN (0 << PMC_PEXSTOPMEM_OFFS)
#define PMC_PEXSTOPMEM_STOP (1 << PMC_PEXSTOPMEM_OFFS)
#define PMC_USBSTOPMEM_OFFS 2
#define PMC_USBSTOPMEM_MASK (1 << PMC_USBSTOPMEM_OFFS)
#define PMC_USBSTOPMEM_EN (0 << PMC_USBSTOPMEM_OFFS)
#define PMC_USBSTOPMEM_STOP (1 << PMC_USBSTOPMEM_OFFS)
#define PMC_DUNITSTOPMEM_OFFS 3
#define PMC_DUNITSTOPMEM_MASK (1 << PMC_DUNITSTOPMEM_OFFS)
#define PMC_DUNITSTOPMEM_EN (0 << PMC_DUNITSTOPMEM_OFFS)
#define PMC_DUNITSTOPMEM_STOP (1 << PMC_DUNITSTOPMEM_OFFS)
#define PMC_RUNITSTOPMEM_OFFS 4
#define PMC_RUNITSTOPMEM_MASK (1 << PMC_RUNITSTOPMEM_OFFS)
#define PMC_RUNITSTOPMEM_EN (0 << PMC_RUNITSTOPMEM_OFFS)
#define PMC_RUNITSTOPMEM_STOP (1 << PMC_RUNITSTOPMEM_OFFS)
#define PMC_XORSTOPMEM_OFFS(port) (5+(port*2))
#define PMC_XORSTOPMEM_MASK(port) (1 << PMC_XORSTOPMEM_OFFS(port))
#define PMC_XORSTOPMEM_EN(port) (0 << PMC_XORSTOPMEM_OFFS(port))
#define PMC_XORSTOPMEM_STOP(port) (1 << PMC_XORSTOPMEM_OFFS(port))
#define PMC_SATASTOPMEM_OFFS(port) (6+(port*5))
#define PMC_SATASTOPMEM_MASK(port) (1 << PMC_SATASTOPMEM_OFFS(port))
#define PMC_SATASTOPMEM_EN(port) (0 << PMC_SATASTOPMEM_OFFS(port))
#define PMC_SATASTOPMEM_STOP(port) (1 << PMC_SATASTOPMEM_OFFS(port))
#define PMC_SESTOPMEM_OFFS 8
#define PMC_SESTOPMEM_MASK (1 << PMC_SESTOPMEM_OFFS)
#define PMC_SESTOPMEM_EN (0 << PMC_SESTOPMEM_OFFS)
#define PMC_SESTOPMEM_STOP (1 << PMC_SESTOPMEM_OFFS)
#define PMC_AUDIOSTOPMEM_OFFS 9
#define PMC_AUDIOSTOPMEM_MASK (1 << PMC_AUDIOSTOPMEM_OFFS)
#define PMC_AUDIOSTOPMEM_EN (0 << PMC_AUDIOSTOPMEM_OFFS)
#define PMC_AUDIOSTOPMEM_STOP (1 << PMC_AUDIOSTOPMEM_OFFS)
#define POWER_MNG_CTRL_REG 0x2011C
#define PMC_GESTOPCLOCK_OFFS(port) ((port)? 19 : 0)
#define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port))
#define PMC_GESTOPCLOCK_EN(port) (1 << PMC_GESTOPCLOCK_OFFS(port))
#define PMC_GESTOPCLOCK_STOP(port) (0 << PMC_GESTOPCLOCK_OFFS(port))
#define PMC_PEXPHYSTOPCLOCK_OFFS 1
#define PMC_PEXPHYSTOPCLOCK_MASK (1 << PMC_PEXPHYSTOPCLOCK_OFFS)
#define PMC_PEXPHYSTOPCLOCK_EN (1 << PMC_PEXPHYSTOPCLOCK_OFFS)
#define PMC_PEXPHYSTOPCLOCK_STOP (0 << PMC_PEXPHYSTOPCLOCK_OFFS)
#define PMC_PEXSTOPCLOCK_OFFS 2
#define PMC_PEXSTOPCLOCK_MASK (1 << PMC_PEXSTOPCLOCK_OFFS)
#define PMC_PEXSTOPCLOCK_EN (1 << PMC_PEXSTOPCLOCK_OFFS)
#define PMC_PEXSTOPCLOCK_STOP (0 << PMC_PEXSTOPCLOCK_OFFS)
#define PMC_USBSTOPCLOCK_OFFS 3
#define PMC_USBSTOPCLOCK_MASK (1 << PMC_USBSTOPCLOCK_OFFS)
#define PMC_USBSTOPCLOCK_EN (1 << PMC_USBSTOPCLOCK_OFFS)
#define PMC_USBSTOPCLOCK_STOP (0 << PMC_USBSTOPCLOCK_OFFS)
#define PMC_SDIOSTOPCLOCK_OFFS 4
#define PMC_SDIOSTOPCLOCK_MASK (1 << PMC_SDIOSTOPCLOCK_OFFS)
#define PMC_SDIOSTOPCLOCK_EN (1 << PMC_SDIOSTOPCLOCK_OFFS)
#define PMC_SDIOSTOPCLOCK_STOP (0 << PMC_SDIOSTOPCLOCK_OFFS)
#define PMC_TSSTOPCLOCK_OFFS 5
#define PMC_TSSTOPCLOCK_MASK (1 << PMC_TSSTOPCLOCK_OFFS)
#define PMC_TSSTOPCLOCK_EN (1 << PMC_TSSTOPCLOCK_OFFS)
#define PMC_TSSTOPCLOCK_STOP (0 << PMC_TSSTOPCLOCK_OFFS)
#define PMC_AUDIOSTOPCLOCK_OFFS 9
#define PMC_AUDIOSTOPCLOCK_MASK (1 << PMC_AUDIOSTOPCLOCK_OFFS)
#define PMC_AUDIOSTOPCLOCK_EN (1 << PMC_AUDIOSTOPCLOCK_OFFS)
#define PMC_AUDIOSTOPCLOCK_STOP (0 << PMC_AUDIOSTOPCLOCK_OFFS)
#define PMC_POWERSAVE_OFFS 11
#define PMC_POWERSAVE_MASK (1 << PMC_POWERSAVE_OFFS)
#define PMC_POWERSAVE_EN (1 << PMC_POWERSAVE_OFFS)
#define PMC_POWERSAVE_STOP (0 << PMC_POWERSAVE_OFFS)
#define PMC_SATASTOPCLOCK_OFFS(port) (14+(port))
#define PMC_SATASTOPCLOCK_MASK(port) (1 << PMC_SATASTOPCLOCK_OFFS(port))
#define PMC_SATASTOPCLOCK_EN(port) (1 << PMC_SATASTOPCLOCK_OFFS(port))
#define PMC_SATASTOPCLOCK_STOP(port) (0 << PMC_SATASTOPCLOCK_OFFS(port))
#define PMC_SESTOPCLOCK_OFFS 17
#define PMC_SESTOPCLOCK_MASK (1 << PMC_SESTOPCLOCK_OFFS)
#define PMC_SESTOPCLOCK_EN (1 << PMC_SESTOPCLOCK_OFFS)
#define PMC_SESTOPCLOCK_STOP (0 << PMC_SESTOPCLOCK_OFFS)
#define PMC_TDMSTOPCLOCK_OFFS 20
#define PMC_TDMSTOPCLOCK_MASK (1 << PMC_TDMSTOPCLOCK_OFFS)
#define PMC_TDMSTOPCLOCK_EN (1 << PMC_TDMSTOPCLOCK_OFFS)
#define PMC_TDMSTOPCLOCK_STOP (0 << PMC_TDMSTOPCLOCK_OFFS)
/* Controler environment registers offsets */
#define MPP_CONTROL_REG0 0x10000
#define MPP_CONTROL_REG1 0x10004
#define MPP_CONTROL_REG2 0x10008
#define MPP_CONTROL_REG3 0x1000C
#define MPP_CONTROL_REG4 0x10010
#define MPP_CONTROL_REG5 0x10014
#define MPP_CONTROL_REG6 0x10018
#define MPP_SAMPLE_AT_RESET 0x10030
#define CHIP_BOND_REG 0x10034
#define SYSRST_LENGTH_COUNTER_REG 0x10050
#define SLCR_COUNT_OFFS 0
#define SLCR_COUNT_MASK (0x1FFFFFFF << SLCR_COUNT_OFFS)
#define SLCR_CLR_OFFS 31
#define SLCR_CLR_MASK (1 << SLCR_CLR_OFFS)
#define PCKG_OPT_MASK 0x3
#define MPP_OUTPUT_DRIVE_REG 0x100E0
#define MPP_RGMII0_OUTPUT_DRIVE_OFFS 7
#define MPP_3_3_RGMII0_OUTPUT_DRIVE (0x0 << MPP_RGMII0_OUTPUT_DRIVE_OFFS)
#define MPP_1_8_RGMII0_OUTPUT_DRIVE (0x1 << MPP_RGMII0_OUTPUT_DRIVE_OFFS)
#define MPP_RGMII1_OUTPUT_DRIVE_OFFS 15
#define MPP_3_3_RGMII1_OUTPUT_DRIVE (0x0 << MPP_RGMII1_OUTPUT_DRIVE_OFFS)
#define MPP_1_8_RGMII1_OUTPUT_DRIVE (0x1 << MPP_RGMII1_OUTPUT_DRIVE_OFFS)
#define MSAR_BOOT_MODE_OFFS 12
#define MSAR_BOOT_MODE_MASK (0x7 << MSAR_BOOT_MODE_OFFS)
#define MSAR_BOOT_NAND_WITH_BOOTROM (0x5 << MSAR_BOOT_MODE_OFFS)
#define MSAR_BOOT_SPI_WITH_BOOTROM (0x4 << MSAR_BOOT_MODE_OFFS)
#define MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM (0x2 << MSAR_BOOT_MODE_OFFS)
#define MSAR_BOOT_MODE_6180(X) (((X & 0x3000) >> 12) | \
((X & 0x2) << 1))
#define MSAR_BOOT_SPI_WITH_BOOTROM_6180 0x1
#define MSAR_BOOT_NAND_WITH_BOOTROM_6180 0x5
#define MSAR_TCLCK_OFFS 21
#define MSAR_TCLCK_MASK (0x1 << MSAR_TCLCK_OFFS)
#define MSAR_TCLCK_166 (0x1 << MSAR_TCLCK_OFFS)
#define MSAR_TCLCK_200 (0x0 << MSAR_TCLCK_OFFS)
#define MSAR_CPUCLCK_EXTRACT(X) (((X & 0x2) >> 1) | ((X & 0x400000) >> 21) | \
((X & 0x18) >> 1))
#define MSAR_CPUCLCK_OFFS_6180 2
#define MSAR_CPUCLCK_MASK_6180 (0x7 << MSAR_CPUCLCK_OFFS_6180)
#define MSAR_DDRCLCK_RTIO_OFFS 5
#define MSAR_DDRCLCK_RTIO_MASK (0xF << MSAR_DDRCLCK_RTIO_OFFS)
#define MSAR_L2CLCK_EXTRACT(X) (((X & 0x600) >> 9) | ((X & 0x80000) >> 17))
#ifndef MV_ASMLANGUAGE
/* CPU clock for 6281,6192 0->Resereved */
#define MV_CPU_CLCK_TBL { 0, 0, 0, 0, \
600000000, 0, 800000000, 1000000000, \
0, 1200000000, 0, 0, \
1500000000, 0, 0, 0}
/* DDR clock RATIO for 6281,6192 {0,0}->Reserved */
#define MV_DDR_CLCK_RTIO_TBL {\
{0, 0}, {0, 0}, {2, 1}, {0, 0}, \
{3, 1}, {0, 0}, {4, 1}, {9, 2}, \
{5, 1}, {6, 1}, {0, 0}, {0, 0}, \
{0, 0}, {0, 0}, {0, 0}, {0, 0} \
}
/* L2 clock RATIO for 6281,6192 {1,1}->Reserved */
#define MV_L2_CLCK_RTIO_TBL {\
{0, 0}, {2, 1}, {0, 0}, {3, 1}, \
{0, 0}, {0, 0}, {0, 0}, {0, 0} \
}
/* 6180 have different clk reset sampling */
/* ARM CPU, DDR, L2 clock for 6180 {0,0,0}->Reserved */
#define MV_CPU6180_DDR_L2_CLCK_TBL { \
{0, 0, 0 },\
{0, 0, 0 },\
{0, 0, 0 },\
{0, 0, 0 },\
{0, 0, 0 },\
{600000000, 200000000, 300000000 },\
{800000000, 200000000, 400000000 },\
{0, 0, 0 }\
}
/* These macros help units to identify a target Mbus Arbiter group */
#define MV_TARGET_IS_DRAM(target) \
((target >= SDRAM_CS0) && (target <= SDRAM_CS3))
#define MV_TARGET_IS_PEX0(target) \
((target >= PEX0_MEM) && (target <= PEX0_IO))
#define MV_TARGET_IS_PEX1(target) 0
#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target))
#define MV_TARGET_IS_DEVICE(target) \
((target >= DEVICE_CS0) && (target <= DEVICE_CS3))
#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0
#define MV_TARGET_IS_AS_BOOT(target) ((target) == (sampleAtResetTargetArray[ \
(mvCtrlModelGet() == MV_6180_DEV_ID)? MSAR_BOOT_MODE_6180 \
(MV_REG_READ(MPP_SAMPLE_AT_RESET)):((MV_REG_READ(MPP_SAMPLE_AT_RESET)\
& MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)]))
#define MV_CHANGE_BOOT_CS(target) (((target) == DEV_BOOCS)?\
sampleAtResetTargetArray[(mvCtrlModelGet() == MV_6180_DEV_ID)? \
MSAR_BOOT_MODE_6180(MV_REG_READ(MPP_SAMPLE_AT_RESET)): \
((MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_BOOT_MODE_MASK)\
>> MSAR_BOOT_MODE_OFFS)]:(target))
#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */
#define BOOT_TARGETS_NAME_ARRAY { \
TBL_TERM, \
TBL_TERM, \
BOOT_ROM_CS, \
TBL_TERM, \
BOOT_ROM_CS, \
BOOT_ROM_CS, \
TBL_TERM, \
TBL_TERM \
}
#define BOOT_TARGETS_NAME_ARRAY_6180 { \
TBL_TERM, \
BOOT_ROM_CS, \
TBL_TERM, \
TBL_TERM, \
TBL_TERM, \
BOOT_ROM_CS, \
TBL_TERM, \
TBL_TERM \
}
/* For old competability */
#define DEVICE_CS0 NFLASH_CS
#define DEVICE_CS1 SPI_CS
#define DEVICE_CS2 BOOT_ROM_CS
#define DEVICE_CS3 DEV_BOOCS
#define MV_BOOTDEVICE_INDEX 0
#define START_DEV_CS DEV_CS0
#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0)
#define PCI_IF0_MEM0 PEX0_MEM
#define PCI_IF0_IO PEX0_IO
/* This enumerator defines the Marvell controller target ID */
typedef enum _mvTargetId
{
DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */
DEV_TARGET_ID = 1, /* Port 1 -> Nand/SPI */
PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */
CRYPT_TARGET_ID = 3 , /* Port 3 --> Crypto Engine */
SAGE_TARGET_ID = 12 , /* Port 12 -> SAGE Unit */
MAX_TARGETS_ID
}MV_TARGET_ID;
/* This enumerator described the possible Controller paripheral targets. */
/* Controller peripherals are designated memory/IO address spaces that the */
/* controller can access. They are also refered as "targets" */
typedef enum _mvTarget
{
TBL_TERM = -1, /* none valid target, used as targets list terminator*/
SDRAM_CS0, /* SDRAM chip select 0 */
SDRAM_CS1, /* SDRAM chip select 1 */
SDRAM_CS2, /* SDRAM chip select 2 */
SDRAM_CS3, /* SDRAM chip select 3 */
PEX0_MEM, /* PCI Express 0 Memory */
PEX0_IO, /* PCI Express 0 IO */
INTER_REGS, /* Internal registers */
NFLASH_CS, /* NFLASH_CS */
SPI_CS, /* SPI_CS */
BOOT_ROM_CS, /* BOOT_ROM_CS */
DEV_BOOCS, /* DEV_BOOCS */
CRYPT_ENG, /* Crypto Engine */
#ifdef MV_INCLUDE_SAGE
SAGE_UNIT, /* SAGE Unit */
#endif
MAX_TARGETS
}MV_TARGET;
#define TARGETS_DEF_ARRAY { \
{0x0E, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \
{0x0D, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \
{0x0B, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \
{0x07, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \
{0xE8, PEX0_TARGET_ID }, /* PEX0_MEM */ \
{0xE0, PEX0_TARGET_ID }, /* PEX0_IO */ \
{0xFF, 0xFF }, /* INTER_REGS */ \
{0x2F, DEV_TARGET_ID }, /* NFLASH_CS */ \
{0x1E, DEV_TARGET_ID }, /* SPI_CS */ \
{0x1D, DEV_TARGET_ID }, /* BOOT_ROM_CS */ \
{0x1E, DEV_TARGET_ID }, /* DEV_BOOCS */ \
{0x01, CRYPT_TARGET_ID}, /* CRYPT_ENG */ \
{0x00, SAGE_TARGET_ID } \
}
#define TARGETS_NAME_ARRAY { \
"SDRAM_CS0", /* SDRAM_CS0 */ \
"SDRAM_CS1", /* SDRAM_CS1 */ \
"SDRAM_CS2", /* SDRAM_CS2 */ \
"SDRAM_CS3", /* SDRAM_CS3 */ \
"PEX0_MEM", /* PEX0_MEM */ \
"PEX0_IO", /* PEX0_IO */ \
"INTER_REGS", /* INTER_REGS */ \
"NFLASH_CS", /* NFLASH_CS */ \
"SPI_CS", /* SPI_CS */ \
"BOOT_ROM_CS", /* BOOT_ROM_CS */ \
"DEV_BOOTCS", /* DEV_BOOCS */ \
"CRYPT_ENG", /* CRYPT_ENG */ \
"SAGE_UNIT" /* SAGE_UNIT */ \
}
#endif /* MV_ASMLANGUAGE */
#endif

257
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h
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@ -1,257 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvCtrlEnvSpech
#define __INCmvCtrlEnvSpech
#include "mvDeviceId.h"
#include "mvSysHwConfig.h"
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#define MV_ARM_SOC
#define SOC_NAME_PREFIX "MV88F"
/* units base and port numbers */
#ifdef MV_ASMLANGUAGE
#define XOR_UNIT_BASE(unit) 0x60800
#else
#define MV_XOR_REG_BASE 0x60000
#define XOR_UNIT_BASE(unit) ((unit)? 0x60900:0x60800)
#endif
#define TDM_REG_BASE 0xD0000
#define USB_REG_BASE(dev) 0x50000
#define AUDIO_REG_BASE 0xA0000
#define SATA_REG_BASE 0x80000
#define MV_CESA_REG_BASE 0x3D000
#define MV_CESA_TDMA_REG_BASE 0x30000
#define MV_SDIO_REG_BASE 0x90000
#define MV_ETH_REG_BASE(port) (((port) == 0) ? 0x72000 : 0x76000)
#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100))
#define DRAM_BASE 0x0
#define CNTMR_BASE 0x20300
#define TWSI_SLAVE_BASE(chanNum) 0x11000
#define PEX_IF_BASE(pexIf) 0x40000
#define MPP_REG_BASE 0x10000
#define TSU_GLOBAL_REG_BASE 0xB4000
#define MAX_AHB_TO_MBUS_REG_BASE 0x20000
#define INTER_REGS_SIZE _1M
/* This define describes the TWSI interrupt bit and location */
#define TWSI_CPU_MAIN_INT_CAUSE_REG 0x20200
#define TWSI0_CPU_MAIN_INT_BIT (1<<29)
#define TWSI_SPEED 100000
#define MV_GPP_MAX_GROUP 2
#define MV_CNTMR_MAX_COUNTER 2
#define MV_UART_MAX_CHAN 2
#define MV_XOR_MAX_UNIT 2
#define MV_XOR_MAX_CHAN 4 /* total channels for all units together*/
#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */
#define MV_SATA_MAX_CHAN 2
#define MV_6281_MPP_MAX_MODULE 2
#define MV_6192_MPP_MAX_MODULE 1
#define MV_6190_MPP_MAX_MODULE 1
#define MV_6180_MPP_MAX_MODULE 2
#define MV_6281_MPP_MAX_GROUP 7
#define MV_6192_MPP_MAX_GROUP 4
#define MV_6190_MPP_MAX_GROUP 4
#define MV_6180_MPP_MAX_GROUP 3
#define MV_DRAM_MAX_CS 4
/* This define describes the maximum number of supported PCI\PCIX Interfaces*/
#define MV_PCI_MAX_IF 0
#define MV_PCI_START_IF 0
/* This define describes the maximum number of supported PEX Interfaces */
#define MV_INCLUDE_PEX0
#define MV_DISABLE_PEX_DEVICE_BAR
#define MV_PEX_MAX_IF 1
#define MV_PEX_START_IF MV_PCI_MAX_IF
/* This define describes the maximum number of supported PCI Interfaces */
#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF)
#define MV_ETH_MAX_PORTS 2
#define MV_6281_ETH_MAX_PORTS 2
#define MV_6192_ETH_MAX_PORTS 2
#define MV_6190_ETH_MAX_PORTS 1
#define MV_6180_ETH_MAX_PORTS 1
#define MV_IDMA_MAX_CHAN 0
#define MV_USB_MAX_PORTS 1
#define MV_USB_VERSION 1
#define MV_6281_NAND 1
#define MV_6192_NAND 1
#define MV_6190_NAND 1
#define MV_6180_NAND 0
#define MV_6281_SDIO 1
#define MV_6192_SDIO 1
#define MV_6190_SDIO 1
#define MV_6180_SDIO 1
#define MV_6281_TS 1
#define MV_6192_TS 1
#define MV_6190_TS 0
#define MV_6180_TS 0
#define MV_6281_AUDIO 1
#define MV_6192_AUDIO 1
#define MV_6190_AUDIO 0
#define MV_6180_AUDIO 1
#define MV_6281_TDM 1
#define MV_6192_TDM 1
#define MV_6190_TDM 0
#define MV_6180_TDM 0
#define MV_DEVICE_MAX_CS 4
/* Others */
#define PEX_HOST_BUS_NUM(pciIf) (pciIf)
#define PEX_HOST_DEV_NUM(pciIf) 0
#define PCI_IO(pciIf) (PEX0_IO)
#define PCI_MEM(pciIf, memNum) (PEX0_MEM0)
/* CESA version #2: One channel, 2KB SRAM, TDMA */
#if defined(MV_CESA_CHAIN_MODE_SUPPORT)
#define MV_CESA_VERSION 3
#else
#define MV_CESA_VERSION 2
#endif
#define MV_CESA_SRAM_SIZE 2*1024
/* This define describes the maximum number of supported Ethernet ports */
#define MV_ETH_VERSION 4
#define MV_ETH_MAX_RXQ 8
#define MV_ETH_MAX_TXQ 8
#define MV_ETH_PORT_SGMII { MV_FALSE, MV_FALSE }
/* This define describes the the support of USB */
#define MV_USB_VERSION 1
#define MV_INCLUDE_SDRAM_CS0
#define MV_INCLUDE_SDRAM_CS1
#define MV_INCLUDE_SDRAM_CS2
#define MV_INCLUDE_SDRAM_CS3
#define MV_INCLUDE_DEVICE_CS0
#define MV_INCLUDE_DEVICE_CS1
#define MV_INCLUDE_DEVICE_CS2
#define MV_INCLUDE_DEVICE_CS3
#define MPP_GROUP_1_TYPE {\
{0, 0, 0}, /* Reserved for AUTO */ \
{0x22220000, 0x22222222, 0x2222}, /* TDM */ \
{0x44440000, 0x00044444, 0x0000}, /* AUDIO */ \
{0x33330000, 0x33003333, 0x0033}, /* RGMII */ \
{0x33330000, 0x03333333, 0x0033}, /* GMII */ \
{0x11110000, 0x11111111, 0x0001}, /* TS */ \
{0x33330000, 0x33333333, 0x3333} /* MII */ \
}
#define MPP_GROUP_2_TYPE {\
{0, 0, 0}, /* Reserved for AUTO */ \
{0x22220000, 0x22222222, 0x22}, /* TDM */ \
{0x44440000, 0x00044444, 0x0}, /* AUDIO */ \
{0, 0, 0}, /* N_A */ \
{0, 0, 0}, /* N_A */ \
{0x11110000, 0x11111111, 0x01} /* TS */ \
}
#ifndef MV_ASMLANGUAGE
/* This enumerator defines the Marvell Units ID */
typedef enum _mvUnitId
{
DRAM_UNIT_ID,
PEX_UNIT_ID,
ETH_GIG_UNIT_ID,
USB_UNIT_ID,
IDMA_UNIT_ID,
XOR_UNIT_ID,
SATA_UNIT_ID,
TDM_UNIT_ID,
UART_UNIT_ID,
CESA_UNIT_ID,
SPI_UNIT_ID,
AUDIO_UNIT_ID,
SDIO_UNIT_ID,
TS_UNIT_ID,
MAX_UNITS_ID
}MV_UNIT_ID;
#endif
#endif /* __INCmvCtrlEnvSpech */

1048
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c
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130
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h
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@ -1,130 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvAhbToMbush
#define __INCmvAhbToMbush
/* includes */
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "ctrlEnv/sys/mvAhbToMbusRegs.h"
#include "ctrlEnv/mvCtrlEnvAddrDec.h"
/* defines */
#if defined(MV_88F1181)
/* This enumerator defines the Marvell controller possible MBUS arbiter */
/* target ports. It is used to define crossbar priority scheame (pizza) */
typedef enum _mvMBusArbTargetId
{
DRAM_MBUS_ARB_TARGET = 0, /* Port 0 -> DRAM interface */
TWSI_MBUS_ARB_TARGET = 1, /* Port 1 -> TWSI */
ARM_MBUS_ARB_TARGET = 2, /* Port 2 -> ARM */
PEX1_MBUS_ARB_TARGET = 3, /* Port 3 -> PCI Express 1 */
PEX0_MBUS_ARB_TARGET = 4, /* Port 4 -> PCI Express0 */
MAX_MBUS_ARB_TARGETS
}MV_MBUS_ARB_TARGET;
typedef struct _mvMBusArbCtrl
{
MV_BOOL starvEn;
MV_BOOL highPrio;
MV_BOOL fixedRoundRobin;
}MV_MBUS_ARB_CTRL;
#endif /* #if defined(MV_88F1181) */
typedef struct _mvAhbtoMbusDecWin
{
MV_TARGET target;
MV_ADDR_WIN addrWin; /* An address window*/
MV_BOOL enable; /* Address decode window is enabled/disabled */
}MV_AHB_TO_MBUS_DEC_WIN;
/* mvAhbToMbus.h API list */
MV_STATUS mvAhbToMbusInit(MV_VOID);
MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin);
MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin);
MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum,MV_BOOL enable);
MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrDecWin);
MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target);
MV_U32 mvAhbToMbusWinAvailGet(MV_VOID);
MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2);
#if defined(MV_88F1181)
MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray);
MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl);
MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl);
#endif /* #if defined(MV_88F1181) */
MV_VOID mvAhbToMbusAddDecShow(MV_VOID);
#endif /* __INCmvAhbToMbush */

143
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h
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@ -1,143 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvAhbToMbusRegsh
#define __INCmvAhbToMbusRegsh
/******************************/
/* ARM Address Map Registers */
/******************************/
#define MAX_AHB_TO_MBUS_WINS 9
#define MV_AHB_TO_MBUS_INTREG_WIN 8
#define AHB_TO_MBUS_WIN_CTRL_REG(winNum) (0x20000 + (winNum)*0x10)
#define AHB_TO_MBUS_WIN_BASE_REG(winNum) (0x20004 + (winNum)*0x10)
#define AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum) (0x20008 + (winNum)*0x10)
#define AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum) (0x2000C + (winNum)*0x10)
#define AHB_TO_MBUS_WIN_INTEREG_REG 0x20080
/* Window Control Register */
/* AHB_TO_MBUS_WIN_CTRL_REG (ATMWCR)*/
#define ATMWCR_WIN_ENABLE BIT0 /* Window Enable */
#define ATMWCR_WIN_TARGET_OFFS 4 /* The target interface associated
with this window*/
#define ATMWCR_WIN_TARGET_MASK (0xf << ATMWCR_WIN_TARGET_OFFS)
#define ATMWCR_WIN_ATTR_OFFS 8 /* The target interface attributes
Associated with this window */
#define ATMWCR_WIN_ATTR_MASK (0xff << ATMWCR_WIN_ATTR_OFFS)
/*
Used with the Base register to set the address window size and location
Must be programed from LSB to MSB as sequence of 1’s followed
by sequence of 0’s. The number of 1’s specifies the size of the window
in 64 KB granularity (e.g. a value of 0x00FF specifies 256 = 16 MB).
NOTE: A value of 0x0 specifies 64KB size.
*/
#define ATMWCR_WIN_SIZE_OFFS 16 /* Window Size */
#define ATMWCR_WIN_SIZE_MASK (0xffff << ATMWCR_WIN_SIZE_OFFS)
#define ATMWCR_WIN_SIZE_ALIGNMENT 0x10000
/* Window Base Register */
/* AHB_TO_MBUS_WIN_BASE_REG (ATMWBR) */
/*
Used with the size field to set the address window size and location.
Corresponds to transaction address[31:16]
*/
#define ATMWBR_BASE_OFFS 16 /* Base Address */
#define ATMWBR_BASE_MASK (0xffff << ATMWBR_BASE_OFFS)
#define ATMWBR_BASE_ALIGNMENT 0x10000
/* Window Remap Low Register */
/* AHB_TO_MBUS_WIN_REMAP_LOW_REG (ATMWRLR) */
/*
Used with the size field to specifies address bits[31:0] to be driven to
the target interface.:
target_addr[31:16] = (addr[31:16] & size[15:0]) | (remap[31:16] & ~size[15:0])
*/
#define ATMWRLR_REMAP_LOW_OFFS 16 /* Remap Address */
#define ATMWRLR_REMAP_LOW_MASK (0xffff << ATMWRLR_REMAP_LOW_OFFS)
#define ATMWRLR_REMAP_LOW_ALIGNMENT 0x10000
/* Window Remap High Register */
/* AHB_TO_MBUS_WIN_REMAP_HIGH_REG (ATMWRHR) */
/*
Specifies address bits[63:32] to be driven to the target interface.
target_addr[63:32] = (RemapHigh[31:0]
*/
#define ATMWRHR_REMAP_HIGH_OFFS 0 /* Remap Address */
#define ATMWRHR_REMAP_HIGH_MASK (0xffffffff << ATMWRHR_REMAP_HIGH_OFFS)
#endif /* __INCmvAhbToMbusRegsh */

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target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c
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120
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h
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@ -1,120 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvCpuIfh
#define __INCmvCpuIfh
/* includes */
#include "ctrlEnv/mvCtrlEnvLib.h"
#include "ctrlEnv/sys/mvCpuIfRegs.h"
#include "ctrlEnv/sys/mvAhbToMbus.h"
#include "ddr2/mvDramIf.h"
#include "ctrlEnv/sys/mvSysDram.h"
#if defined(MV_INCLUDE_PEX)
#include "pex/mvPex.h"
#endif
/* defines */
/* typedefs */
/* This structure describes CPU interface address decode window */
typedef struct _mvCpuIfDecWin
{
MV_ADDR_WIN addrWin; /* An address window*/
MV_U32 winNum; /* Window Number in the AHB To Mbus bridge */
MV_BOOL enable; /* Address decode window is enabled/disabled */
}MV_CPU_DEC_WIN;
/* mvCpuIfLib.h API list */
/* mvCpuIfLib.h API list */
MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap);
MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin);
MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin);
MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable);
MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target);
MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target);
MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target);
MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress);
#if defined(MV_INCLUDE_PEX)
MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin);
MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType);
#endif
#if defined(MV_INCLUDE_PCI)
MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin);
#endif
MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin);
MV_VOID mvCpuIfAddDecShow(MV_VOID);
#if defined(MV88F6281)
MV_STATUS mvCpuIfBridgeReorderWAInit(void);
#endif
#endif /* __INCmvCpuIfh */

163
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S
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@ -1,163 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#define MV_ASMLANGUAGE
#include "mvOsAsm.h"
#include "mvDeviceId.h"
#include "mvCtrlEnvRegs.h"
#include "mvCpuIfRegs.h"
#include "mvCtrlEnvAsm.h"
/*******************************************************************************
* mvCpuIfPreInit - Make early initialization of CPU interface.
*
* DESCRIPTION:
* The function will initialize the CPU interface parameters that must
* be initialize before any BUS activity towards the DDR interface,
* which means it must be executed from ROM. Because of that, the function
* is implemented in assembly code.
* The function configure the following CPU config register parameters:
* 1) CPU2MbusLTickDrv
* 2) CPU2MbusLTickSample.
* NOTE: This function must be called AFTER the internal register
* base is modified to INTER_REGS_BASE.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
* r11 holds return function address.
*******************************************************************************/
#define MV88F6281_PCKG_OPT 2
#define MV88F6192_PCKG_OPT 1
#define MV88F6180_PCKG_OPT 0
.globl _mvCpuIfPreInit
_mvCpuIfPreInit:
mov r11, LR /* Save link register */
/* Read device ID */
MV_CTRL_MODEL_GET_ASM(r4, r5);
/* goto calcConfigReg if device is 6281 */
ldr r5, =MV88F6281_PCKG_OPT
cmp r4, r5
beq calcConfigReg
/* goto calcConfigReg if device is 6192/6190 */
ldr r5, =MV88F6192_PCKG_OPT
cmp r4, r5
beq calcConfigReg
/* Else 6180 */
/* Get the "sample on reset" register */
MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET)
ldr r5, =MSAR_CPUCLCK_MASK_6180
and r5, r4, r5
mov r5, r5, lsr #MSAR_CPUCLCK_OFFS_6180
ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3
cmp r5, #CPU_2_DDR_CLK_1x3_1
beq setConfigReg
ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4
cmp r5, #CPU_2_DDR_CLK_1x4_1
beq setConfigReg
b setConfigReg
calcConfigReg:
/* Get the "sample on reset" register */
MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET)
ldr r5, =MSAR_DDRCLCK_RTIO_MASK
and r5, r4, r5
mov r5, r5, lsr #MSAR_DDRCLCK_RTIO_OFFS
ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3
cmp r5, #CPU_2_DDR_CLK_1x3
beq setConfigReg
ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4
cmp r5, #CPU_2_DDR_CLK_1x4
beq setConfigReg
/* Else */
ldr r4, =0
setConfigReg:
/* Read CPU Config register */
MV_REG_READ_ASM (r7, r5, CPU_CONFIG_REG)
ldr r5, =~(CCR_CPU_2_MBUSL_TICK_DRV_MASK | CCR_CPU_2_MBUSL_TICK_SMPL_MASK)
and r7, r7, r5 /* Clear register fields */
orr r7, r7, r4 /* Set the values according to the findings */
MV_REG_WRITE_ASM (r7, r5, CPU_CONFIG_REG)
done:
mov PC, r11 /* r11 is saved link register */

304
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h
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@ -1,304 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvCpuIfRegsh
#define __INCmvCpuIfRegsh
/****************************************/
/* ARM Control and Status Registers Map */
/****************************************/
#define CPU_CONFIG_REG 0x20100
#define CPU_CTRL_STAT_REG 0x20104
#define CPU_RSTOUTN_MASK_REG 0x20108
#define CPU_SYS_SOFT_RST_REG 0x2010C
#define CPU_AHB_MBUS_CAUSE_INT_REG 0x20110
#define CPU_AHB_MBUS_MASK_INT_REG 0x20114
#define CPU_FTDLL_CONFIG_REG 0x20120
#define CPU_L2_CONFIG_REG 0x20128
/* ARM Configuration register */
/* CPU_CONFIG_REG (CCR) */
/* Reset vector location */
#define CCR_VEC_INIT_LOC_OFFS 1
#define CCR_VEC_INIT_LOC_MASK BIT1
/* reset at 0x00000000 */
#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS)
/* reset at 0xFFFF0000 */
#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS)
#define CCR_AHB_ERROR_PROP_OFFS 2
#define CCR_AHB_ERROR_PROP_MASK BIT2
/* Erros are not propogated to AHB */
#define CCR_AHB_ERROR_PROP_NO_INDICATE (0 << CCR_AHB_ERROR_PROP_OFFS)
/* Erros are propogated to AHB */
#define CCR_AHB_ERROR_PROP_INDICATE (1 << CCR_AHB_ERROR_PROP_OFFS)
#define CCR_ENDIAN_INIT_OFFS 3
#define CCR_ENDIAN_INIT_MASK BIT3
#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS)
#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS)
#define CCR_INCR_EN_OFFS 4
#define CCR_INCR_EN_MASK BIT4
#define CCR_INCR_EN BIT4
#define CCR_NCB_BLOCKING_OFFS 5
#define CCR_NCB_BLOCKING_MASK (1 << CCR_NCB_BLOCKING_OFFS)
#define CCR_NCB_BLOCKING_NON (0 << CCR_NCB_BLOCKING_OFFS)
#define CCR_NCB_BLOCKING_EN (1 << CCR_NCB_BLOCKING_OFFS)
#define CCR_CPU_2_MBUSL_TICK_DRV_OFFS 8
#define CCR_CPU_2_MBUSL_TICK_DRV_MASK (0xF << CCR_CPU_2_MBUSL_TICK_DRV_OFFS)
#define CCR_CPU_2_MBUSL_TICK_SMPL_OFFS 12
#define CCR_CPU_2_MBUSL_TICK_SMPL_MASK (0xF << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)
#define CCR_ICACH_PREF_BUF_ENABLE BIT16
#define CCR_DCACH_PREF_BUF_ENABLE BIT17
/* Ratio options for CPU to DDR for 6281/6192/6190 */
#define CPU_2_DDR_CLK_1x3 4
#define CPU_2_DDR_CLK_1x4 6
/* Ratio options for CPU to DDR for 6281 only */
#define CPU_2_DDR_CLK_2x9 7
#define CPU_2_DDR_CLK_1x5 8
#define CPU_2_DDR_CLK_1x6 9
/* Ratio options for CPU to DDR for 6180 only */
#define CPU_2_DDR_CLK_1x3_1 0x5
#define CPU_2_DDR_CLK_1x4_1 0x6
/* Default values for CPU to Mbus-L DDR Interface Tick Driver and */
/* CPU to Mbus-L Tick Sample fields in CPU config register */
#define TICK_DRV_1x1 0
#define TICK_DRV_1x2 0
#define TICK_DRV_1x3 1
#define TICK_DRV_1x4 2
#define TICK_SMPL_1x1 0
#define TICK_SMPL_1x2 1
#define TICK_SMPL_1x3 0
#define TICK_SMPL_1x4 0
#define CPU_2_MBUSL_DDR_CLK_1x2 \
((TICK_DRV_1x2 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \
(TICK_SMPL_1x2 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS))
#define CPU_2_MBUSL_DDR_CLK_1x3 \
((TICK_DRV_1x3 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \
(TICK_SMPL_1x3 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS))
#define CPU_2_MBUSL_DDR_CLK_1x4 \
((TICK_DRV_1x4 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \
(TICK_SMPL_1x4 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS))
/* ARM Control and Status register */
/* CPU_CTRL_STAT_REG (CCSR) */
/*
This is used to block PCI express\PCI from access Socrates/Feroceon GP
while ARM boot is still in progress
*/
#define CCSR_PCI_ACCESS_OFFS 0
#define CCSR_PCI_ACCESS_MASK BIT0
#define CCSR_PCI_ACCESS_ENABLE (0 << CCSR_PCI_ACCESS_OFFS)
#define CCSR_PCI_ACCESS_DISBALE (1 << CCSR_PCI_ACCESS_OFFS)
#define CCSR_ARM_RESET BIT1
#define CCSR_SELF_INT BIT2
#define CCSR_BIG_ENDIAN BIT15
/* RSTOUTn Mask Register */
/* CPU_RSTOUTN_MASK_REG (CRMR) */
#define CRMR_PEX_RST_OUT_OFFS 0
#define CRMR_PEX_RST_OUT_MASK BIT0
#define CRMR_PEX_RST_OUT_ENABLE (1 << CRMR_PEX_RST_OUT_OFFS)
#define CRMR_PEX_RST_OUT_DISABLE (0 << CRMR_PEX_RST_OUT_OFFS)
#define CRMR_WD_RST_OUT_OFFS 1
#define CRMR_WD_RST_OUT_MASK BIT1
#define CRMR_WD_RST_OUT_ENABLE (1 << CRMR_WD_RST_OUT_OFFS)
#define CRMR_WD_RST_OUT_DISBALE (0 << CRMR_WD_RST_OUT_OFFS)
#define CRMR_SOFT_RST_OUT_OFFS 2
#define CRMR_SOFT_RST_OUT_MASK BIT2
#define CRMR_SOFT_RST_OUT_ENABLE (1 << CRMR_SOFT_RST_OUT_OFFS)
#define CRMR_SOFT_RST_OUT_DISBALE (0 << CRMR_SOFT_RST_OUT_OFFS)
/* System Software Reset Register */
/* CPU_SYS_SOFT_RST_REG (CSSRR) */
#define CSSRR_SYSTEM_SOFT_RST BIT0
/* AHB to Mbus Bridge Interrupt Cause Register*/
/* CPU_AHB_MBUS_CAUSE_INT_REG (CAMCIR) */
#define CAMCIR_ARM_SELF_INT BIT0
#define CAMCIR_ARM_TIMER0_INT_REQ BIT1
#define CAMCIR_ARM_TIMER1_INT_REQ BIT2
#define CAMCIR_ARM_WD_TIMER_INT_REQ BIT3
/* AHB to Mbus Bridge Interrupt Mask Register*/
/* CPU_AHB_MBUS_MASK_INT_REG (CAMMIR) */
#define CAMCIR_ARM_SELF_INT_OFFS 0
#define CAMCIR_ARM_SELF_INT_MASK BIT0
#define CAMCIR_ARM_SELF_INT_EN (1 << CAMCIR_ARM_SELF_INT_OFFS)
#define CAMCIR_ARM_SELF_INT_DIS (0 << CAMCIR_ARM_SELF_INT_OFFS)
#define CAMCIR_ARM_TIMER0_INT_REQ_OFFS 1
#define CAMCIR_ARM_TIMER0_INT_REQ_MASK BIT1
#define CAMCIR_ARM_TIMER0_INT_REQ_EN (1 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS)
#define CAMCIR_ARM_TIMER0_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS)
#define CAMCIR_ARM_TIMER1_INT_REQ_OFFS 2
#define CAMCIR_ARM_TIMER1_INT_REQ_MASK BIT2
#define CAMCIR_ARM_TIMER1_INT_REQ_EN (1 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS)
#define CAMCIR_ARM_TIMER1_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS)
#define CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS 3
#define CAMCIR_ARM_WD_TIMER_INT_REQ_MASK BIT3
#define CAMCIR_ARM_WD_TIMER_INT_REQ_EN (1 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS)
#define CAMCIR_ARM_WD_TIMER_INT_REQ_DIS (0 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS)
/* CPU FTDLL Config register (CFCR) fields */
#define CFCR_FTDLL_ICACHE_TAG_OFFS 0
#define CFCR_FTDLL_ICACHE_TAG_MASK (0x7F << CFCR_FTDLL_ICACHE_TAG_OFFS)
#define CFCR_FTDLL_DCACHE_TAG_OFFS 8
#define CFCR_FTDLL_DCACHE_TAG_MASK (0x7F << CFCR_FTDLL_DCACHE_TAG_OFFS)
#define CFCR_FTDLL_OVERWRITE_ENABLE (1 << 15)
/* For Orion 2 D2 only */
#define CFCR_MRVL_CPU_ID_OFFS 16
#define CFCR_MRVL_CPU_ID_MASK (0x1 << CFCR_MRVL_CPU_ID_OFFS)
#define CFCR_ARM_CPU_ID (0x0 << CFCR_MRVL_CPU_ID_OFFS)
#define CFCR_MRVL_CPU_ID (0x1 << CFCR_MRVL_CPU_ID_OFFS)
#define CFCR_VFP_SUB_ARC_NUM_OFFS 7
#define CFCR_VFP_SUB_ARC_NUM_MASK (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS)
#define CFCR_VFP_SUB_ARC_NUM_1 (0x0 << CFCR_VFP_SUB_ARC_NUM_OFFS)
#define CFCR_VFP_SUB_ARC_NUM_2 (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS)
/* CPU_L2_CONFIG_REG fields */
#ifdef MV_CPU_LE
#define CL2CR_L2_ECC_EN_OFFS 2
#define CL2CR_L2_WT_MODE_OFFS 4
#else
#define CL2CR_L2_ECC_EN_OFFS 26
#define CL2CR_L2_WT_MODE_OFFS 28
#endif
#define CL2CR_L2_ECC_EN_MASK (1 << CL2CR_L2_ECC_EN_OFFS)
#define CL2CR_L2_WT_MODE_MASK (1 << CL2CR_L2_WT_MODE_OFFS)
/*******************************************/
/* Main Interrupt Controller Registers Map */
/*******************************************/
#define CPU_MAIN_INT_CAUSE_REG 0x20200
#define CPU_MAIN_IRQ_MASK_REG 0x20204
#define CPU_MAIN_FIQ_MASK_REG 0x20208
#define CPU_ENPOINT_MASK_REG 0x2020C
#define CPU_MAIN_INT_CAUSE_HIGH_REG 0x20210
#define CPU_MAIN_IRQ_MASK_HIGH_REG 0x20214
#define CPU_MAIN_FIQ_MASK_HIGH_REG 0x20218
#define CPU_ENPOINT_MASK_HIGH_REG 0x2021C
/*******************************************/
/* ARM Doorbell Registers Map */
/*******************************************/
#define CPU_HOST_TO_ARM_DRBL_REG 0x20400
#define CPU_HOST_TO_ARM_MASK_REG 0x20404
#define CPU_ARM_TO_HOST_DRBL_REG 0x20408
#define CPU_ARM_TO_HOST_MASK_REG 0x2040C
/* CPU control register map */
/* Set bits means value is about to change according to new value */
#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK | CCR_AHB_ERROR_PROP_MASK)
#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00)
/* CPU Control and status defaults */
#define CPU_CTRL_STAT_DEFAULT_MASK (CCSR_PCI_ACCESS_MASK)
#define CPU_CTRL_STAT_DEFAULT (CCSR_PCI_ACCESS_ENABLE)
#endif /* __INCmvCpuIfRegsh */

324
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c
View File

@ -1,324 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "mvSysAudio.h"
/*******************************************************************************
* mvAudioWinSet - Set AUDIO target address window
*
* DESCRIPTION:
* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
* address window, also known as address decode window.
* After setting this target window, the AUDIO will be able to access the
* target within the address window.
*
* INPUT:
* winNum - AUDIO target address decode window number.
* pAddrDecWin - AUDIO target window data structure.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR if address window overlapps with other address decode windows.
* MV_BAD_PARAM if base address is invalid parameter or target is
* unknown.
*
*******************************************************************************/
MV_STATUS mvAudioWinSet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin)
{
MV_TARGET_ATTRIB targetAttribs;
MV_DEC_REGS decRegs;
/* Parameter checking */
if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN)
{
mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum);
return MV_BAD_PARAM;
}
/* check if address is aligned to the size */
if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size))
{
mvOsPrintf("mvAudioWinSet:Error setting AUDIO window %d to "\
"target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n",
winNum,
mvCtrlTargetNameGet(pAddrDecWin->target),
pAddrDecWin->addrWin.baseLow,
pAddrDecWin->addrWin.size);
return MV_ERROR;
}
decRegs.baseReg = 0;
decRegs.sizeReg = 0;
if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs))
{
mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__);
return MV_ERROR;
}
mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs);
/* set attributes */
decRegs.sizeReg &= ~MV_AUDIO_WIN_ATTR_MASK;
decRegs.sizeReg |= (targetAttribs.attrib << MV_AUDIO_WIN_ATTR_OFFSET);
/* set target ID */
decRegs.sizeReg &= ~MV_AUDIO_WIN_TARGET_MASK;
decRegs.sizeReg |= (targetAttribs.targetId << MV_AUDIO_WIN_TARGET_OFFSET);
if (pAddrDecWin->enable == MV_TRUE)
{
decRegs.sizeReg |= MV_AUDIO_WIN_ENABLE_MASK;
}
else
{
decRegs.sizeReg &= ~MV_AUDIO_WIN_ENABLE_MASK;
}
MV_REG_WRITE( MV_AUDIO_WIN_CTRL_REG(winNum), decRegs.sizeReg);
MV_REG_WRITE( MV_AUDIO_WIN_BASE_REG(winNum), decRegs.baseReg);
return MV_OK;
}
/*******************************************************************************
* mvAudioWinGet - Get AUDIO peripheral target address window.
*
* DESCRIPTION:
* Get AUDIO peripheral target address window.
*
* INPUT:
* winNum - AUDIO target address decode window number.
*
* OUTPUT:
* pAddrDecWin - AUDIO target window data structure.
*
* RETURN:
* MV_ERROR if register parameters are invalid.
*
*******************************************************************************/
MV_STATUS mvAudioWinGet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin)
{
MV_DEC_REGS decRegs;
MV_TARGET_ATTRIB targetAttrib;
/* Parameter checking */
if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN)
{
mvOsPrintf("%s : ERR. Invalid winNum %d\n",
__FUNCTION__, winNum);
return MV_NOT_SUPPORTED;
}
decRegs.baseReg = MV_REG_READ( MV_AUDIO_WIN_BASE_REG(winNum) );
decRegs.sizeReg = MV_REG_READ( MV_AUDIO_WIN_CTRL_REG(winNum) );
if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) )
{
mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__);
return MV_ERROR;
}
/* attrib and targetId */
targetAttrib.attrib = (decRegs.sizeReg & MV_AUDIO_WIN_ATTR_MASK) >>
MV_AUDIO_WIN_ATTR_OFFSET;
targetAttrib.targetId = (decRegs.sizeReg & MV_AUDIO_WIN_TARGET_MASK) >>
MV_AUDIO_WIN_TARGET_OFFSET;
pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
/* Check if window is enabled */
if(decRegs.sizeReg & MV_AUDIO_WIN_ENABLE_MASK)
{
pAddrDecWin->enable = MV_TRUE;
}
else
{
pAddrDecWin->enable = MV_FALSE;
}
return MV_OK;
}
/*******************************************************************************
* mvAudioAddrDecShow - Print the AUDIO address decode map.
*
* DESCRIPTION:
* This function print the AUDIO address decode map.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvAudioAddrDecShow(MV_VOID)
{
MV_AUDIO_DEC_WIN win;
int i;
if (MV_FALSE == mvCtrlPwrClckGet(AUDIO_UNIT_ID, 0))
return;
mvOsOutput( "\n" );
mvOsOutput( "AUDIO:\n" );
mvOsOutput( "----\n" );
for( i = 0; i < MV_AUDIO_MAX_ADDR_DECODE_WIN; i++ )
{
memset( &win, 0, sizeof(MV_AUDIO_DEC_WIN) );
mvOsOutput( "win%d - ", i );
if( mvAudioWinGet( i, &win ) == MV_OK )
{
if( win.enable )
{
mvOsOutput( "%s base %08x, ",
mvCtrlTargetNameGet(win.target), win.addrWin.baseLow );
mvOsOutput( "...." );
mvSizePrint( win.addrWin.size );
mvOsOutput( "\n" );
}
else
mvOsOutput( "disable\n" );
}
}
}
/*******************************************************************************
* mvAudioWinInit - Initialize the integrated AUDIO target address window.
*
* DESCRIPTION:
* Initialize the AUDIO peripheral target address window.
*
* INPUT:
*
*
* OUTPUT:
*
*
* RETURN:
* MV_ERROR if register parameters are invalid.
*
*******************************************************************************/
MV_STATUS mvAudioInit(MV_VOID)
{
int winNum;
MV_AUDIO_DEC_WIN audioWin;
MV_CPU_DEC_WIN cpuAddrDecWin;
MV_U32 status;
mvAudioHalInit();
/* Initiate Audio address decode */
/* First disable all address decode windows */
for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++)
{
MV_U32 regVal = MV_REG_READ(MV_AUDIO_WIN_CTRL_REG(winNum));
regVal &= ~MV_AUDIO_WIN_ENABLE_MASK;
MV_REG_WRITE(MV_AUDIO_WIN_CTRL_REG(winNum), regVal);
}
for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++)
{
/* We will set the Window to DRAM_CS0 in default */
/* first get attributes from CPU If */
status = mvCpuIfTargetWinGet(SDRAM_CS0,
&cpuAddrDecWin);
if (MV_OK != status)
{
mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__);
return MV_ERROR;
}
if (cpuAddrDecWin.enable == MV_TRUE)
{
audioWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
audioWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
audioWin.addrWin.size = cpuAddrDecWin.addrWin.size;
audioWin.enable = MV_TRUE;
audioWin.target = SDRAM_CS0;
if(MV_OK != mvAudioWinSet(winNum, &audioWin))
{
return MV_ERROR;
}
}
}
return MV_OK;
}

123
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h
View File

@ -1,123 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCMVSysAudioH
#define __INCMVSysAudioH
#include "mvCommon.h"
#include "audio/mvAudio.h"
#include "ctrlEnv/mvCtrlEnvSpec.h"
#include "ctrlEnv/sys/mvCpuIf.h"
/***********************************/
/* Audio Address Decoding registers*/
/***********************************/
#define MV_AUDIO_MAX_ADDR_DECODE_WIN 2
#define MV_AUDIO_RECORD_WIN_NUM 0
#define MV_AUDIO_PLAYBACK_WIN_NUM 1
#define MV_AUDIO_WIN_CTRL_REG(win) (AUDIO_REG_BASE + 0xA04 + ((win)<<3))
#define MV_AUDIO_WIN_BASE_REG(win) (AUDIO_REG_BASE + 0xA00 + ((win)<<3))
#define MV_AUDIO_RECORD_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_RECORD_WIN_NUM)
#define MV_AUDIO_RECORD_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_RECORD_WIN_NUM)
#define MV_AUDIO_PLAYBACK_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_PLAYBACK_WIN_NUM)
#define MV_AUDIO_PLAYBACK_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_PLAYBACK_WIN_NUM)
/* BITs in Windows 0-3 Control and Base Registers */
#define MV_AUDIO_WIN_ENABLE_BIT 0
#define MV_AUDIO_WIN_ENABLE_MASK (1<<MV_AUDIO_WIN_ENABLE_BIT)
#define MV_AUDIO_WIN_TARGET_OFFSET 4
#define MV_AUDIO_WIN_TARGET_MASK (0xF<<MV_AUDIO_WIN_TARGET_OFFSET)
#define MV_AUDIO_WIN_ATTR_OFFSET 8
#define MV_AUDIO_WIN_ATTR_MASK (0xFF<<MV_AUDIO_WIN_ATTR_OFFSET)
#define MV_AUDIO_WIN_SIZE_OFFSET 16
#define MV_AUDIO_WIN_SIZE_MASK (0xFFFF<<MV_AUDIO_WIN_SIZE_OFFSET)
#define MV_AUDIO_WIN_BASE_OFFSET 16
#define MV_AUDIO_WIN_BASE_MASK (0xFFFF<<MV_AUDIO_WIN_BASE_OFFSET)
typedef struct _mvAudioDecWin
{
MV_TARGET target;
MV_ADDR_WIN addrWin; /* An address window*/
MV_BOOL enable; /* Address decode window is enabled/disabled */
} MV_AUDIO_DEC_WIN;
MV_STATUS mvAudioInit(MV_VOID);
MV_STATUS mvAudioWinGet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin);
MV_STATUS mvAudioWinSet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin);
MV_STATUS mvAudioWinInit(MV_VOID);
MV_VOID mvAudioAddrDecShow(MV_VOID);
#endif

382
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.c
View File

@ -1,382 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "mvSysCesa.h"
#if (MV_CESA_VERSION >= 2)
MV_TARGET tdmaAddrDecPrioTable[] =
{
#if defined(MV_INCLUDE_SDRAM_CS0)
SDRAM_CS0,
#endif
#if defined(MV_INCLUDE_SDRAM_CS1)
SDRAM_CS1,
#endif
#if defined(MV_INCLUDE_SDRAM_CS2)
SDRAM_CS2,
#endif
#if defined(MV_INCLUDE_SDRAM_CS3)
SDRAM_CS3,
#endif
#if defined(MV_INCLUDE_PEX)
PEX0_MEM,
#endif
TBL_TERM
};
/*******************************************************************************
* mvCesaWinGet - Get TDMA target address window.
*
* DESCRIPTION:
* Get TDMA target address window.
*
* INPUT:
* winNum - TDMA target address decode window number.
*
* OUTPUT:
* pDecWin - TDMA target window data structure.
*
* RETURN:
* MV_ERROR if register parameters are invalid.
*
*******************************************************************************/
static MV_STATUS mvCesaWinGet(MV_U32 winNum, MV_DEC_WIN *pDecWin)
{
MV_DEC_WIN_PARAMS winParam;
MV_U32 sizeReg, baseReg;
/* Parameter checking */
if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN)
{
mvOsPrintf("%s : ERR. Invalid winNum %d\n",
__FUNCTION__, winNum);
return MV_NOT_SUPPORTED;
}
baseReg = MV_REG_READ( MV_CESA_TDMA_BASE_ADDR_REG(winNum) );
sizeReg = MV_REG_READ( MV_CESA_TDMA_WIN_CTRL_REG(winNum) );
/* Check if window is enabled */
if(sizeReg & MV_CESA_TDMA_WIN_ENABLE_MASK)
{
pDecWin->enable = MV_TRUE;
/* Extract window parameters from registers */
winParam.targetId = (sizeReg & MV_CESA_TDMA_WIN_TARGET_MASK) >> MV_CESA_TDMA_WIN_TARGET_OFFSET;
winParam.attrib = (sizeReg & MV_CESA_TDMA_WIN_ATTR_MASK) >> MV_CESA_TDMA_WIN_ATTR_OFFSET;
winParam.size = (sizeReg & MV_CESA_TDMA_WIN_SIZE_MASK) >> MV_CESA_TDMA_WIN_SIZE_OFFSET;
winParam.baseAddr = (baseReg & MV_CESA_TDMA_WIN_BASE_MASK);
/* Translate the decode window parameters to address decode struct */
if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin))
{
mvOsPrintf("Failed to translate register parameters to CESA address" \
" decode window structure\n");
return MV_ERROR;
}
}
else
{
pDecWin->enable = MV_FALSE;
}
return MV_OK;
}
/*******************************************************************************
* cesaWinOverlapDetect - Detect CESA TDMA address windows overlapping
*
* DESCRIPTION:
* An unpredicted behaviur is expected in case TDMA address decode
* windows overlapps.
* This function detects TDMA address decode windows overlapping of a
* specified window. The function does not check the window itself for
* overlapping. The function also skipps disabled address decode windows.
*
* INPUT:
* winNum - address decode window number.
* pAddrDecWin - An address decode window struct.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_TRUE - if the given address window overlap current address
* decode map,
* MV_FALSE - otherwise, MV_ERROR if reading invalid data
* from registers.
*
*******************************************************************************/
static MV_STATUS cesaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin)
{
MV_U32 winNumIndex;
MV_DEC_WIN addrDecWin;
for(winNumIndex=0; winNumIndex<MV_CESA_TDMA_ADDR_DEC_WIN; winNumIndex++)
{
/* Do not check window itself */
if (winNumIndex == winNum)
{
continue;
}
/* Get window parameters */
if (MV_OK != mvCesaWinGet(winNumIndex, &addrDecWin))
{
mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__);
return MV_ERROR;
}
/* Do not check disabled windows */
if(addrDecWin.enable == MV_FALSE)
{
continue;
}
if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin)))
{
return MV_TRUE;
}
}
return MV_FALSE;
}
/*******************************************************************************
* mvCesaTdmaWinSet - Set CESA TDMA target address window
*
* DESCRIPTION:
* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
* address window, also known as address decode window.
* After setting this target window, the CESA TDMA will be able to access the
* target within the address window.
*
* INPUT:
* winNum - CESA TDMA target address decode window number.
* pAddrDecWin - CESA TDMA target window data structure.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR - if address window overlapps with other address decode windows.
* MV_BAD_PARAM - if base address is invalid parameter or target is
* unknown.
*
*******************************************************************************/
static MV_STATUS mvCesaTdmaWinSet(MV_U32 winNum, MV_DEC_WIN *pDecWin)
{
MV_DEC_WIN_PARAMS winParams;
MV_U32 sizeReg, baseReg;
/* Parameter checking */
if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN)
{
mvOsPrintf("mvCesaTdmaWinSet: ERR. Invalid win num %d\n",winNum);
return MV_BAD_PARAM;
}
/* Check if the requested window overlapps with current windows */
if (MV_TRUE == cesaWinOverlapDetect(winNum, &pDecWin->addrWin))
{
mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum);
return MV_ERROR;
}
/* check if address is aligned to the size */
if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size))
{
mvOsPrintf("mvCesaTdmaWinSet: Error setting CESA TDMA window %d to "\
"target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n",
winNum,
mvCtrlTargetNameGet(pDecWin->target),
pDecWin->addrWin.baseLow,
pDecWin->addrWin.size);
return MV_ERROR;
}
if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams))
{
mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__);
return MV_ERROR;
}
/* set Size, Attributes and TargetID */
sizeReg = (((winParams.targetId << MV_CESA_TDMA_WIN_TARGET_OFFSET) & MV_CESA_TDMA_WIN_TARGET_MASK) |
((winParams.attrib << MV_CESA_TDMA_WIN_ATTR_OFFSET) & MV_CESA_TDMA_WIN_ATTR_MASK) |
((winParams.size << MV_CESA_TDMA_WIN_SIZE_OFFSET) & MV_CESA_TDMA_WIN_SIZE_MASK));
if (pDecWin->enable == MV_TRUE)
{
sizeReg |= MV_CESA_TDMA_WIN_ENABLE_MASK;
}
else
{
sizeReg &= ~MV_CESA_TDMA_WIN_ENABLE_MASK;
}
/* Update Base value */
baseReg = (winParams.baseAddr & MV_CESA_TDMA_WIN_BASE_MASK);
MV_REG_WRITE( MV_CESA_TDMA_WIN_CTRL_REG(winNum), sizeReg);
MV_REG_WRITE( MV_CESA_TDMA_BASE_ADDR_REG(winNum), baseReg);
return MV_OK;
}
static MV_STATUS mvCesaTdmaAddrDecInit (void)
{
MV_U32 winNum;
MV_STATUS status;
MV_CPU_DEC_WIN cpuAddrDecWin;
MV_DEC_WIN cesaWin;
MV_U32 winPrioIndex = 0;
/* First disable all address decode windows */
for(winNum=0; winNum<MV_CESA_TDMA_ADDR_DEC_WIN; winNum++)
{
MV_REG_BIT_RESET(MV_CESA_TDMA_WIN_CTRL_REG(winNum), MV_CESA_TDMA_WIN_ENABLE_MASK);
}
/* Go through all windows in user table until table terminator */
winNum = 0;
while( (tdmaAddrDecPrioTable[winPrioIndex] != TBL_TERM) &&
(winNum < MV_CESA_TDMA_ADDR_DEC_WIN) ) {
/* first get attributes from CPU If */
status = mvCpuIfTargetWinGet(tdmaAddrDecPrioTable[winPrioIndex],
&cpuAddrDecWin);
if(MV_NO_SUCH == status){
winPrioIndex++;
continue;
}
if (MV_OK != status)
{
mvOsPrintf("cesaInit: TargetWinGet failed. winNum=%d, winIdx=%d, target=%d, status=0x%x\n",
winNum, winPrioIndex, tdmaAddrDecPrioTable[winPrioIndex], status);
return MV_ERROR;
}
if (cpuAddrDecWin.enable == MV_TRUE)
{
cesaWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
cesaWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
cesaWin.addrWin.size = cpuAddrDecWin.addrWin.size;
cesaWin.enable = MV_TRUE;
cesaWin.target = tdmaAddrDecPrioTable[winPrioIndex];
#if defined(MV646xx)
/* Get the default attributes for that target window */
mvCtrlDefAttribGet(cesaWin.target, &cesaWin.addrWinAttr);
#endif /* MV646xx */
if(MV_OK != mvCesaTdmaWinSet(winNum, &cesaWin))
{
mvOsPrintf("mvCesaTdmaWinSet FAILED: winNum=%d\n",
winNum);
return MV_ERROR;
}
winNum++;
}
winPrioIndex++;
}
return MV_OK;
}
#endif /* MV_CESA_VERSION >= 2 */
MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle)
{
MV_U32 cesaCryptEngBase;
MV_CPU_DEC_WIN addrDecWin;
if(sizeof(MV_CESA_SRAM_MAP) > MV_CESA_SRAM_SIZE)
{
mvOsPrintf("mvCesaInit: Wrong SRAM map - %ld > %d\n",
sizeof(MV_CESA_SRAM_MAP), MV_CESA_SRAM_SIZE);
return MV_FAIL;
}
#if 0
if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK)
cesaCryptEngBase = addrDecWin.addrWin.baseLow;
else
{
mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n");
return MV_ERROR;
}
#else
cesaCryptEngBase = (MV_U32)pSramBase;
#endif
#if 0 /* Already done in the platform init */
#if (MV_CESA_VERSION >= 2)
mvCesaTdmaAddrDecInit();
#endif /* MV_CESA_VERSION >= 2 */
#endif
return mvCesaHalInit(numOfSession, queueDepth, pSramBase, cesaCryptEngBase,
osHandle);
}

100
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h
View File

@ -1,100 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __mvSysCesa_h__
#define __mvSysCesa_h__
#include "mvCommon.h"
#include "cesa/mvCesa.h"
#include "ctrlEnv/mvCtrlEnvSpec.h"
#include "ctrlEnv/sys/mvCpuIf.h"
/***************************** TDMA Registers *************************************/
#define MV_CESA_TDMA_ADDR_DEC_WIN 4
#define MV_CESA_TDMA_BASE_ADDR_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa00 + (win<<3))
#define MV_CESA_TDMA_WIN_CTRL_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa04 + (win<<3))
#define MV_CESA_TDMA_WIN_ENABLE_BIT 0
#define MV_CESA_TDMA_WIN_ENABLE_MASK (1 << MV_CESA_TDMA_WIN_ENABLE_BIT)
#define MV_CESA_TDMA_WIN_TARGET_OFFSET 4
#define MV_CESA_TDMA_WIN_TARGET_MASK (0xf << MV_CESA_TDMA_WIN_TARGET_OFFSET)
#define MV_CESA_TDMA_WIN_ATTR_OFFSET 8
#define MV_CESA_TDMA_WIN_ATTR_MASK (0xff << MV_CESA_TDMA_WIN_ATTR_OFFSET)
#define MV_CESA_TDMA_WIN_SIZE_OFFSET 16
#define MV_CESA_TDMA_WIN_SIZE_MASK (0xFFFF << MV_CESA_TDMA_WIN_SIZE_OFFSET)
#define MV_CESA_TDMA_WIN_BASE_OFFSET 16
#define MV_CESA_TDMA_WIN_BASE_MASK (0xFFFF << MV_CESA_TDMA_WIN_BASE_OFFSET)
MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle);
#endif

348
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c
View File

@ -1,348 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/* includes */
#include "ddr2/mvDramIf.h"
#include "ctrlEnv/sys/mvCpuIf.h"
#include "ctrlEnv/sys/mvSysDram.h"
/* #define MV_DEBUG */
#ifdef MV_DEBUG
#define DB(x) x
#else
#define DB(x)
#endif
static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin);
/*******************************************************************************
* mvDramIfWinSet - Set DRAM interface address decode window
*
* DESCRIPTION:
* This function sets DRAM interface address decode window.
*
* INPUT:
* target - System target. Use only SDRAM targets.
* pAddrDecWin - SDRAM address window structure.
*
* OUTPUT:
* None
*
* RETURN:
* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK
* otherwise.
*******************************************************************************/
MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin)
{
MV_U32 baseReg=0,sizeReg=0;
MV_U32 baseToReg=0 , sizeToReg=0;
/* Check parameters */
if (!MV_TARGET_IS_DRAM(target))
{
mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target);
return MV_BAD_PARAM;
}
/* Check if the requested window overlaps with current enabled windows */
if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin))
{
mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target);
return MV_BAD_PARAM;
}
/* check if address is aligned to the size */
if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size))
{
mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\
"\nAddress 0x%08x is unaligned to size 0x%x.\n",
target,
pAddrDecWin->addrWin.baseLow,
pAddrDecWin->addrWin.size);
return MV_ERROR;
}
/* read base register*/
baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target));
/* read size register */
sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target));
/* BaseLow[31:16] => base register [31:16] */
baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK;
/* Write to address decode Base Address Register */
baseReg &= ~SCBAR_BASE_MASK;
baseReg |= baseToReg;
/* Translate the given window size to register format */
sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT);
/* Size parameter validity check. */
if (-1 == sizeToReg)
{
mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target);
return MV_BAD_PARAM;
}
/* set size */
sizeReg &= ~SCSR_SIZE_MASK;
/* Size is located at upper 16 bits */
sizeReg |= (sizeToReg << SCSR_SIZE_OFFS);
/* enable/Disable */
if (MV_TRUE == pAddrDecWin->enable)
{
sizeReg |= SCSR_WIN_EN;
}
else
{
sizeReg &= ~SCSR_WIN_EN;
}
/* 3) Write to address decode Base Address Register */
MV_REG_WRITE(SDRAM_BASE_ADDR_REG(0,target), baseReg);
/* Write to address decode Size Register */
MV_REG_WRITE(SDRAM_SIZE_REG(0,target), sizeReg);
return MV_OK;
}
/*******************************************************************************
* mvDramIfWinGet - Get DRAM interface address decode window
*
* DESCRIPTION:
* This function gets DRAM interface address decode window.
*
* INPUT:
* target - System target. Use only SDRAM targets.
*
* OUTPUT:
* pAddrDecWin - SDRAM address window structure.
*
* RETURN:
* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK
* otherwise.
*******************************************************************************/
MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin)
{
MV_U32 baseReg,sizeReg;
MV_U32 sizeRegVal;
/* Check parameters */
if (!MV_TARGET_IS_DRAM(target))
{
mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target);
return MV_ERROR;
}
/* Read base and size registers */
sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target));
baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target));
sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS;
pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal,
SCSR_SIZE_ALIGNMENT);
/* Check if ctrlRegToSize returned OK */
if (-1 == pAddrDecWin->addrWin.size)
{
mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target);
return MV_ERROR;
}
/* Extract base address */
/* Base register [31:16] ==> baseLow[31:16] */
pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK;
pAddrDecWin->addrWin.baseHigh = 0;
if (sizeReg & SCSR_WIN_EN)
{
pAddrDecWin->enable = MV_TRUE;
}
else
{
pAddrDecWin->enable = MV_FALSE;
}
return MV_OK;
}
/*******************************************************************************
* mvDramIfWinEnable - Enable/Disable SDRAM address decode window
*
* DESCRIPTION:
* This function enable/Disable SDRAM address decode window.
*
* INPUT:
* target - System target. Use only SDRAM targets.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR in case function parameter are invalid, MV_OK otherewise.
*
*******************************************************************************/
MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable)
{
MV_DRAM_DEC_WIN addrDecWin;
/* Check parameters */
if (!MV_TARGET_IS_DRAM(target))
{
mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target);
return MV_ERROR;
}
if (enable == MV_TRUE)
{ /* First check for overlap with other enabled windows */
if (MV_OK != mvDramIfWinGet(target, &addrDecWin))
{
mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n",
target);
return MV_ERROR;
}
/* Check for overlapping */
if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin)))
{
/* No Overlap. Enable address decode winNum window */
MV_REG_BIT_SET(SDRAM_SIZE_REG(0,target), SCSR_WIN_EN);
}
else
{ /* Overlap detected */
mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n",
target);
return MV_ERROR;
}
}
else
{ /* Disable address decode winNum window */
MV_REG_BIT_RESET(SDRAM_SIZE_REG(0, target), SCSR_WIN_EN);
}
return MV_OK;
}
/*******************************************************************************
* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window
*
* DESCRIPTION:
* This function scan each SDRAM address decode window to test if it
* overlapps the given address windoow
*
* INPUT:
* target - SDRAM target where the function skips checking.
* pAddrDecWin - The tested address window for overlapping with
* SDRAM windows.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_TRUE if the given address window overlaps any enabled address
* decode map, MV_FALSE otherwise.
*
*******************************************************************************/
static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin)
{
MV_TARGET targetNum;
MV_DRAM_DEC_WIN addrDecWin;
for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++)
{
/* don't check our winNum or illegal targets */
if (targetNum == target)
{
continue;
}
/* Get window parameters */
if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin))
{
mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n");
return MV_ERROR;
}
/* Do not check disabled windows */
if (MV_FALSE == addrDecWin.enable)
{
continue;
}
if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin))
{
mvOsPrintf(
"sdramIfWinOverlap: Required target %d overlap winNum %d\n",
target, targetNum);
return MV_TRUE;
}
}
return MV_FALSE;
}

80
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h
View File

@ -1,80 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __sysDram
#define __sysDram
/* This structure describes CPU interface address decode window */
typedef struct _mvDramIfDecWin
{
MV_ADDR_WIN addrWin; /* An address window*/
MV_BOOL enable; /* Address decode window is enabled/disabled */
}MV_DRAM_DEC_WIN;
MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin);
MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin);
MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable);
#endif

658
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c
View File

@ -1,658 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "ctrlEnv/sys/mvSysGbe.h"
typedef struct _mvEthDecWin
{
MV_TARGET target;
MV_ADDR_WIN addrWin; /* An address window*/
MV_BOOL enable; /* Address decode window is enabled/disabled */
}MV_ETH_DEC_WIN;
MV_TARGET ethAddrDecPrioTap[] =
{
#if defined(MV_INCLUDE_SDRAM_CS0)
SDRAM_CS0,
#endif
#if defined(MV_INCLUDE_SDRAM_CS1)
SDRAM_CS1,
#endif
#if defined(MV_INCLUDE_SDRAM_CS2)
SDRAM_CS2,
#endif
#if defined(MV_INCLUDE_SDRAM_CS3)
SDRAM_CS3,
#endif
#if defined(MV_INCLUDE_DEVICE_CS0)
DEVICE_CS0,
#endif
#if defined(MV_INCLUDE_DEVICE_CS1)
DEVICE_CS1,
#endif
#if defined(MV_INCLUDE_DEVICE_CS2)
DEVICE_CS2,
#endif
#if defined(MV_INCLUDE_DEVICE_CS3)
DEVICE_CS3,
#endif
#if defined(MV_INCLUDE_PEX)
PEX0_IO,
#endif
TBL_TERM
};
static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin);
static MV_STATUS mvEthWinSet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin);
static MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin);
/*******************************************************************************
* mvEthWinInit - Initialize ETH address decode windows
*
* DESCRIPTION:
* This function initialize ETH window decode unit. It set the
* default address decode windows of the unit.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR if setting fail.
*******************************************************************************/
/* Configure EthDrv memory map registes. */
MV_STATUS mvEthWinInit (int port)
{
MV_U32 winNum, status, winPrioIndex=0, i, regVal=0;
MV_ETH_DEC_WIN ethWin;
MV_CPU_DEC_WIN cpuAddrDecWin;
static MV_U32 accessProtReg = 0;
#if (MV_ETH_VERSION <= 1)
static MV_BOOL isFirst = MV_TRUE;
if(isFirst == MV_FALSE)
{
MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg);
return MV_OK;
}
isFirst = MV_FALSE;
#endif /* MV_GIGA_ETH_VERSION */
/* Initiate Ethernet address decode */
/* First disable all address decode windows */
for(winNum=0; winNum<ETH_MAX_DECODE_WIN; winNum++)
{
regVal |= MV_BIT_MASK(winNum);
}
MV_REG_WRITE(ETH_BASE_ADDR_ENABLE_REG(port), regVal);
/* Go through all windows in user table until table terminator */
for (winNum=0; ((ethAddrDecPrioTap[winPrioIndex] != TBL_TERM) &&
(winNum < ETH_MAX_DECODE_WIN)); )
{
/* first get attributes from CPU If */
status = mvCpuIfTargetWinGet(ethAddrDecPrioTap[winPrioIndex],
&cpuAddrDecWin);
if(MV_NO_SUCH == status)
{
winPrioIndex++;
continue;
}
if (MV_OK != status)
{
mvOsPrintf("mvEthWinInit: ERR. mvCpuIfTargetWinGet failed\n");
return MV_ERROR;
}
if (cpuAddrDecWin.enable == MV_TRUE)
{
ethWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
ethWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
ethWin.addrWin.size = cpuAddrDecWin.addrWin.size;
ethWin.enable = MV_TRUE;
ethWin.target = ethAddrDecPrioTap[winPrioIndex];
if(MV_OK != mvEthWinSet(port, winNum, &ethWin))
{
mvOsPrintf("mvEthWinInit: ERR. mvEthWinSet failed winNum=%d\n",
winNum);
return MV_ERROR;
}
winNum++;
}
winPrioIndex ++;
}
/* set full access to all windows. */
for(i=0; i<winNum; i++)
{
accessProtReg |= (FULL_ACCESS << (i*2));
}
MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg);
return MV_OK;
}
/*******************************************************************************
* mvEthWinSet - Set ETH target address window
*
* DESCRIPTION:
* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
* address window, also known as address decode window.
* After setting this target window, the ETH will be able to access the
* target within the address window.
*
* INPUT:
* winNum - ETH to target address decode window number.
* pAddrDecWin - ETH target window data structure.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR if address window overlapps with other address decode windows.
* MV_BAD_PARAM if base address is invalid parameter or target is
* unknown.
*
*******************************************************************************/
MV_STATUS mvEthWinSet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin)
{
MV_TARGET_ATTRIB targetAttribs;
MV_DEC_REGS decRegs;
/* Parameter checking */
if (winNum >= ETH_MAX_DECODE_WIN)
{
mvOsPrintf("mvEthWinSet: ERR. Invalid win num %d\n",winNum);
return MV_BAD_PARAM;
}
/* Check if the requested window overlapps with current windows */
if (MV_TRUE == ethWinOverlapDetect(port, winNum, &pAddrDecWin->addrWin))
{
mvOsPrintf("mvEthWinSet: ERR. Window %d overlap\n", winNum);
return MV_ERROR;
}
/* check if address is aligned to the size */
if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size))
{
mvOsPrintf("mvEthWinSet: Error setting Ethernet window %d to "\
"target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n",
winNum,
mvCtrlTargetNameGet(pAddrDecWin->target),
pAddrDecWin->addrWin.baseLow,
pAddrDecWin->addrWin.size);
return MV_ERROR;
}
decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum));
decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum));
if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs))
{
mvOsPrintf("mvEthWinSet:mvCtrlAddrDecToReg Failed\n");
return MV_ERROR;
}
mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs);
/* set attributes */
decRegs.baseReg &= ~ETH_WIN_ATTR_MASK;
decRegs.baseReg |= targetAttribs.attrib << ETH_WIN_ATTR_OFFS;
/* set target ID */
decRegs.baseReg &= ~ETH_WIN_TARGET_MASK;
decRegs.baseReg |= targetAttribs.targetId << ETH_WIN_TARGET_OFFS;
/* for the safe side we disable the window before writing the new
values */
mvEthWinEnable(port, winNum, MV_FALSE);
MV_REG_WRITE(ETH_WIN_BASE_REG(port, winNum), decRegs.baseReg);
/* Write to address decode Size Register */
MV_REG_WRITE(ETH_WIN_SIZE_REG(port, winNum), decRegs.sizeReg);
/* Enable address decode target window */
if (pAddrDecWin->enable == MV_TRUE)
{
mvEthWinEnable(port, winNum, MV_TRUE);
}
return MV_OK;
}
/*******************************************************************************
* mvETHWinGet - Get dma peripheral target address window.
*
* DESCRIPTION:
* Get ETH peripheral target address window.
*
* INPUT:
* winNum - ETH to target address decode window number.
*
* OUTPUT:
* pAddrDecWin - ETH target window data structure.
*
* RETURN:
* MV_ERROR if register parameters are invalid.
*
*******************************************************************************/
MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin)
{
MV_DEC_REGS decRegs;
MV_TARGET_ATTRIB targetAttrib;
/* Parameter checking */
if (winNum >= ETH_MAX_DECODE_WIN)
{
mvOsPrintf("mvEthWinGet: ERR. Invalid winNum %d\n", winNum);
return MV_NOT_SUPPORTED;
}
decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum));
decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum));
if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin)))
{
mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n");
return MV_ERROR;
}
/* attrib and targetId */
targetAttrib.attrib =
(decRegs.baseReg & ETH_WIN_ATTR_MASK) >> ETH_WIN_ATTR_OFFS;
targetAttrib.targetId =
(decRegs.baseReg & ETH_WIN_TARGET_MASK) >> ETH_WIN_TARGET_OFFS;
pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
/* Check if window is enabled */
if (~(MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port))) & (1 << winNum) )
{
pAddrDecWin->enable = MV_TRUE;
}
else
{
pAddrDecWin->enable = MV_FALSE;
}
return MV_OK;
}
/*******************************************************************************
* mvEthWinEnable - Enable/disable a ETH to target address window
*
* DESCRIPTION:
* This function enable/disable a ETH to target address window.
* According to parameter 'enable' the routine will enable the
* window, thus enabling ETH accesses (before enabling the window it is
* tested for overlapping). Otherwise, the window will be disabled.
*
* INPUT:
* winNum - ETH to target address decode window number.
* enable - Enable/disable parameter.
*
* OUTPUT:
* N/A
*
* RETURN:
* MV_ERROR if decode window number was wrong or enabled window overlapps.
*
*******************************************************************************/
MV_STATUS mvEthWinEnable(int port, MV_U32 winNum,MV_BOOL enable)
{
MV_ETH_DEC_WIN addrDecWin;
/* Parameter checking */
if (winNum >= ETH_MAX_DECODE_WIN)
{
mvOsPrintf("mvEthTargetWinEnable:ERR. Invalid winNum%d\n",winNum);
return MV_ERROR;
}
if (enable == MV_TRUE)
{ /* First check for overlap with other enabled windows */
/* Get current window */
if (MV_OK != mvEthWinGet(port, winNum, &addrDecWin))
{
mvOsPrintf("mvEthTargetWinEnable:ERR. targetWinGet fail\n");
return MV_ERROR;
}
/* Check for overlapping */
if (MV_FALSE == ethWinOverlapDetect(port, winNum, &(addrDecWin.addrWin)))
{
/* No Overlap. Enable address decode target window */
MV_REG_BIT_RESET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum));
}
else
{ /* Overlap detected */
mvOsPrintf("mvEthTargetWinEnable:ERR. Overlap detected\n");
return MV_ERROR;
}
}
else
{ /* Disable address decode target window */
MV_REG_BIT_SET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum));
}
return MV_OK;
}
/*******************************************************************************
* mvEthWinTargetGet - Get Window number associated with target
*
* DESCRIPTION:
*
* INPUT:
*
* OUTPUT:
*
* RETURN:
* window number
*
*******************************************************************************/
MV_U32 mvEthWinTargetGet(int port, MV_TARGET target)
{
MV_ETH_DEC_WIN decWin;
MV_U32 winNum;
/* Check parameters */
if (target >= MAX_TARGETS)
{
mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target);
return 0xffffffff;
}
for (winNum=0; winNum<ETH_MAX_DECODE_WIN; winNum++)
{
if (mvEthWinGet(port, winNum,&decWin) != MV_OK)
{
mvOsPrintf("mvAhbToMbusWinTargetGet: window returned error\n");
return 0xffffffff;
}
if (decWin.enable == MV_TRUE)
{
if (decWin.target == target)
{
return winNum;
}
}
}
return 0xFFFFFFFF;
}
/*******************************************************************************
* mvEthProtWinSet - Set access protection of Ethernet to target window.
*
* DESCRIPTION:
* Each Ethernet port can be configured with access attributes for each
* of the Ethenret to target windows (address decode windows). This
* function sets access attributes to a given window for the given channel.
*
* INPUTS:
* ethPort - ETH channel number. See MV_ETH_CHANNEL enumerator.
* winNum - IETH to target address decode window number.
* access - IETH access rights. See MV_ACCESS_RIGHTS enumerator.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR in case window number is invalid or access right reserved.
*
*******************************************************************************/
MV_STATUS mvEthProtWinSet(MV_U32 portNo, MV_U32 winNum, MV_ACCESS_RIGHTS access)
{
MV_U32 protReg;
/* Parameter checking */
if(portNo >= mvCtrlEthMaxPortGet())
{
mvOsPrintf("mvEthProtWinSet:ERR. Invalid port number %d\n", portNo);
return MV_ERROR;
}
if (winNum >= ETH_MAX_DECODE_WIN)
{
mvOsPrintf("mvEthProtWinSet:ERR. Invalid winNum%d\n",winNum);
return MV_ERROR;
}
if((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS))
{
mvOsPrintf("mvEthProtWinSet:ERR. Inv access param %d\n", access);
return MV_ERROR;
}
/* Read current protection register */
protReg = MV_REG_READ(ETH_ACCESS_PROTECT_REG(portNo));
/* Clear protection window field */
protReg &= ~(ETH_PROT_WIN_MASK(winNum));
/* Set new protection field value */
protReg |= (access << (ETH_PROT_WIN_OFFS(winNum)));
/* Write protection register back */
MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(portNo), protReg);
return MV_OK;
}
/*******************************************************************************
* ethWinOverlapDetect - Detect ETH address windows overlapping
*
* DESCRIPTION:
* An unpredicted behaviur is expected in case ETH address decode
* windows overlapps.
* This function detects ETH address decode windows overlapping of a
* specified window. The function does not check the window itself for
* overlapping. The function also skipps disabled address decode windows.
*
* INPUT:
* winNum - address decode window number.
* pAddrDecWin - An address decode window struct.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_TRUE if the given address window overlap current address
* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data
* from registers.
*
*******************************************************************************/
static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin)
{
MV_U32 baseAddrEnableReg;
MV_U32 winNumIndex;
MV_ETH_DEC_WIN addrDecWin;
/* Read base address enable register. Do not check disabled windows */
baseAddrEnableReg = MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port));
for (winNumIndex=0; winNumIndex<ETH_MAX_DECODE_WIN; winNumIndex++)
{
/* Do not check window itself */
if (winNumIndex == winNum)
{
continue;
}
/* Do not check disabled windows */
if (baseAddrEnableReg & (1 << winNumIndex))
{
continue;
}
/* Get window parameters */
if (MV_OK != mvEthWinGet(port, winNumIndex, &addrDecWin))
{
mvOsPrintf("ethWinOverlapDetect: ERR. TargetWinGet failed\n");
return MV_ERROR;
}
/*
mvOsPrintf("ethWinOverlapDetect:\n
winNumIndex =%d baseHigh =0x%x baseLow=0x%x size=0x%x enable=0x%x\n",
winNumIndex,
addrDecWin.addrWin.baseHigh,
addrDecWin.addrWin.baseLow,
addrDecWin.addrWin.size,
addrDecWin.enable);
*/
if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin)))
{
return MV_TRUE;
}
}
return MV_FALSE;
}
/*******************************************************************************
* mvEthAddrDecShow - Print the Etherent address decode map.
*
* DESCRIPTION:
* This function print the Etherent address decode map.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
void mvEthPortAddrDecShow(int port)
{
MV_ETH_DEC_WIN win;
int i;
mvOsOutput( "\n" );
mvOsOutput( "ETH %d:\n", port );
mvOsOutput( "----\n" );
for( i = 0; i < ETH_MAX_DECODE_WIN; i++ )
{
memset( &win, 0, sizeof(ETH_MAX_DECODE_WIN) );
mvOsOutput( "win%d - ", i );
if( mvEthWinGet(port, i, &win ) == MV_OK )
{
if( win.enable )
{
mvOsOutput( "%s base %08x, ",
mvCtrlTargetNameGet(win.target), win.addrWin.baseLow );
mvOsOutput( "...." );
mvSizePrint( win.addrWin.size );
mvOsOutput( "\n" );
}
else
mvOsOutput( "disable\n" );
}
}
return;
}
void mvEthAddrDecShow(void)
{
int port;
for(port=0; port<mvCtrlEthMaxPortGet(); port++)
{
if (MV_FALSE == mvCtrlPwrClckGet(ETH_GIG_UNIT_ID, port)) continue;
mvEthPortAddrDecShow(port);
}
}
void mvEthInit(void)
{
MV_U32 port;
/* Power down all existing ports */
for(port=0; port<mvCtrlEthMaxPortGet(); port++)
{
if (MV_FALSE == mvCtrlPwrClckGet(ETH_GIG_UNIT_ID, port))
continue;
mvEthPortPowerUp(port);
mvEthWinInit(port);
}
mvEthHalInit();
}

113
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.h
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@ -1,113 +0,0 @@
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the two
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the General
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
available along with the File in the license.txt file or by writing to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
DISCLAIMED. The GPL License provides additional details about this warranty
disclaimer.
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef __INCmvSysGbeh
#define __INCmvSysGbeh
#include "mvCommon.h"
#include "eth/mvEth.h"
#include "ctrlEnv/mvCtrlEnvSpec.h"
#include "ctrlEnv/sys/mvCpuIf.h"
#define ETH_WIN_BASE_REG(port, win) (MV_ETH_REG_BASE(port) + 0x200 + ((win)<<3))
#define ETH_WIN_SIZE_REG(port, win) (MV_ETH_REG_BASE(port) + 0x204 + ((win)<<3))
#define ETH_WIN_REMAP_REG(port, win) (MV_ETH_REG_BASE(port) + 0x280 + ((win)<<2))
#define ETH_BASE_ADDR_ENABLE_REG(port) (MV_ETH_REG_BASE(port) + 0x290)
#define ETH_ACCESS_PROTECT_REG(port) (MV_ETH_REG_BASE(port) + 0x294)
/**** Address decode parameters ****/
/* Ethernet Base Address Register bits */
#define ETH_MAX_DECODE_WIN 6
#define ETH_MAX_HIGH_ADDR_REMAP_WIN 4
/* Ethernet Port Access Protect (EPAP) register */
/* The target associated with this window*/
#define ETH_WIN_TARGET_OFFS 0
#define ETH_WIN_TARGET_MASK (0xf << ETH_WIN_TARGET_OFFS)
/* The target attributes Associated with window */
#define ETH_WIN_ATTR_OFFS 8
#define ETH_WIN_ATTR_MASK (0xff << ETH_WIN_ATTR_OFFS)
/* Ethernet Port Access Protect Register (EPAPR) */
#define ETH_PROT_NO_ACCESS NO_ACCESS_ALLOWED
#define ETH_PROT_READ_ONLY READ_ONLY
#define ETH_PROT_FULL_ACCESS FULL_ACCESS
#define ETH_PROT_WIN_OFFS(winNum) (2 * (winNum))
#define ETH_PROT_WIN_MASK(winNum) (0x3 << ETH_PROT_WIN_OFFS(winNum))
MV_STATUS mvEthWinInit (int port);
MV_STATUS mvEthWinEnable(int port, MV_U32 winNum, MV_BOOL enable);
MV_U32 mvEthWinTargetGet(int port, MV_TARGET target);
MV_STATUS mvEthProtWinSet(MV_U32 portNo, MV_U32 winNum, MV_ACCESS_RIGHTS
access);
void mvEthPortAddrDecShow(int port);
MV_VOID mvEthAddrDecShow(MV_VOID);
void mvEthInit(void);
#endif

1697
target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.c
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