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mpc85xx: add support for Aerohive BR200-WP
The following adds the Aerohive BR200-WP router to OpenWrt under
the mpc85xx/p1010 subtarget.
Hardware:
- SoC: Freescale P1011
- NOR: Intel JS28F512M29EWH 64MB
- Memory: 2x Nanya NT5TU64M16GG-AC 128MB (Total of 256MB)
- 2.4GHz WiFi: Atheros AR9390-AL1A
- Eth1: Atheros AR8035-A PoE
- 2x LEDs
- 1x Button
- PoE PSE
Flashing:
1. Hook into UART (9600 baud) and enter U-Boot. You may need to enter a
password of administrator or AhNf?d@ta06 if prompted.
2. Once in U-Boot, tftp boot the initramfs image:
dhcp; setenv serverip 192.168.1.3;
tftpboot 0x2004000 openwrt-mpc85xx-p1010-aerohive_br200-wp-initramfs-kernel.bin;
bootm 0x2004000;
3. Once booted, scp over the sysupgrade file and sysupgrade the device
to flash LEDE to the NOR.
Note:
MAC assigns are taken from stock firmware:
Name MAC addr Mode State Chan(Width) VLAN Radio Hive SSID
-------- -------------- -------- ----- ----------- ---- ---------- ---------- ---------
Mgt0 08ea:44XX:XXc0 - U - 1 - hive0 -
Eth0 08ea:44XX:XXc0 wan U - - - - -
Eth1 08ea:44XX:XXc2 access D - - - hive0 -
Eth2 08ea:44XX:XXc3 access D - - - hive0 -
Eth3 08ea:44XX:XXc4 access D - - - hive0 -
Eth4 08ea:44XX:XXc5 access D - - - hive0 -
Wifi0 08ea:44XX:XXd0 access U 1(20MHz) - radio_ng0 - -
Wifi0.1 08ea:44XX:XXd4 access D 1(20MHz) - radio_ng0 hive0 -
Note2:
PoE PSE could be managed with `realtek-poe` package. Example port
config:
config port
option enable '1'
option id '4'
option name 'lan2'
option poe_plus '0'
option priority '2'
config port
option enable '1'
option id '3'
option name 'lan1'
option poe_plus '0'
option priority '1'
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
(switch@0 -> switch@10, Device's quickstart says LEDs are
amber and white => add function+color properties but keep
labels around, use pr_info)
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
This commit is contained in:
Pawel Dembicki
Christian Lamparter
parent
749237967a
commit
95d5a99537
@ -9,6 +9,9 @@ board_config_update
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board=$(board_name)
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case "$board" in
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aerohive,br200-wp)
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ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
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;;
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aerohive,hiveap-330|\
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enterasys,ws-ap3715i)
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ucidef_set_interfaces_lan_wan "eth1" "eth0"
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@ -20,6 +20,7 @@ CONFIG_AUDIT_ARCH=y
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CONFIG_BLK_MQ_PCI=y
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CONFIG_BOOKE=y
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CONFIG_BOOKE_WDT=y
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# CONFIG_BR200_WP is not set
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# CONFIG_BSC9131_RDB is not set
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# CONFIG_BSC9132_QDS is not set
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# CONFIG_C293_PCIE is not set
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@ -58,6 +59,7 @@ CONFIG_EDAC_ATOMIC_SCRUB=y
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CONFIG_EDAC_LEGACY_SYSFS=y
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CONFIG_EDAC_MPC85XX=y
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CONFIG_EDAC_SUPPORT=y
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# CONFIG_FIREBOX_T10 is not set
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CONFIG_FIXED_PHY=y
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CONFIG_FSL_BOOKE=y
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# CONFIG_FSL_DPAA2_SWITCH is not set
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@ -265,4 +267,3 @@ CONFIG_WATCHDOG_CORE=y
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# CONFIG_XES_MPC85xx is not set
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CONFIG_XZ_DEC_BCJ=y
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CONFIG_XZ_DEC_POWERPC=y
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# CONFIG_FIREBOX_T10 is not set
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373
target/linux/mpc85xx/files/arch/powerpc/boot/dts/br200-wp.dts
Normal file
373
target/linux/mpc85xx/files/arch/powerpc/boot/dts/br200-wp.dts
Normal file
@ -0,0 +1,373 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Aerohive BR200-WP Device Tree Source
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*
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* Based on: Aerohive HiveAP-330 Device Tree Source
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*
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* Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
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* Copyright (C) 2023 Pawel Dembicki <paweldembicki@gmail.com>
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*/
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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/include/ "fsl/p1020si-pre.dtsi"
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/ {
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model = "Aerohive BR200-WP";
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compatible = "aerohive,br200-wp";
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chosen {
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bootargs = "console=ttyS0,9600";
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bootargs-override = "console=ttyS0,9600 noinitrd";
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};
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aliases {
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led-boot = &led_attention;
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led-failsafe = &led_attention;
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led-running = &led_status;
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led-upgrade = &led_status;
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label-mac-device = &enet0;
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};
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memory {
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device_type = "memory";
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};
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cpus {
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/delete-property/ PowerPC,P1020@1; /* P1011 have one core only */
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};
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board_lbc: lbc: localbus@ffe05000 {
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reg = <0 0xffe05000 0 0x1000>;
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ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x4000000>;
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bank-width = <2>;
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device-width = <1>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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reg = <0x0 0x40000>;
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label = "dtb";
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};
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partition@40000 {
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reg = <0x40000 0x40000>;
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label = "initramfs";
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};
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partition@80000 {
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reg = <0x80000 0x27c0000>;
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label = "rootfs";
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};
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partition@2840000 {
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reg = <0x2840000 0x800000>;
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label = "kernel";
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};
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partition@3040000 {
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reg = <0x3040000 0xec0000>;
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label = "stock-jffs2";
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read-only;
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};
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partition@3f00000 {
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reg = <0x3f00000 0x20000>;
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label = "hw-info";
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read-only;
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compatible = "nvmem-cells";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_hwinfo_0: macaddr@0 {
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reg = <0x0 0x6>;
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};
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};
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partition@3f20000 {
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reg = <0x3f20000 0x20000>;
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label = "boot-info";
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read-only;
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};
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partition@3f40000 {
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reg = <0x3f40000 0x20000>;
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label = "boot-info-backup";
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read-only;
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};
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partition@3f60000 {
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reg = <0x3f60000 0x20000>;
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label = "u-boot-env";
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};
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partition@3f80000 {
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reg = <0x3f80000 0x80000>;
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label = "u-boot";
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read-only;
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};
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firmware@0 {
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reg = <0x0 0x3040000>;
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label = "firmware";
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};
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};
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};
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};
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board_soc: soc: soc@ffe00000 {
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ranges = <0x0 0x0 0xffe00000 0x100000>;
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mdio@24000 {
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phy_port1: phy@0 {
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reg = <0>;
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};
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phy_port2: phy@1 {
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reg = <1>;
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};
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phy_port3: phy@2 {
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reg = <2>;
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};
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phy_port4: phy@3 {
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reg = <3>;
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};
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phy_port5: phy@4 {
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reg = <4>;
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};
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switch@10 {
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compatible = "qca,qca8327";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x10>;
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reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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label = "lan1";
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phy-handle = <&phy_port1>;
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nvmem-cells = <&macaddr_hwinfo_0>;
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nvmem-cell-names = "mac-address";
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mac-address-increment = <2>;
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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phy-handle = <&phy_port2>;
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nvmem-cells = <&macaddr_hwinfo_0>;
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nvmem-cell-names = "mac-address";
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mac-address-increment = <3>;
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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phy-handle = <&phy_port3>;
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nvmem-cells = <&macaddr_hwinfo_0>;
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nvmem-cell-names = "mac-address";
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mac-address-increment = <4>;
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};
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port@4 {
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reg = <4>;
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label = "lan4";
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phy-handle = <&phy_port4>;
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nvmem-cells = <&macaddr_hwinfo_0>;
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nvmem-cell-names = "mac-address";
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mac-address-increment = <5>;
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};
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port@5 {
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reg = <5>;
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label = "wan";
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phy-handle = <&phy_port5>;
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nvmem-cells = <&macaddr_hwinfo_0>;
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nvmem-cell-names = "mac-address";
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};
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port@6 {
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reg = <6>;
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ethernet = <&enet0>;
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phy-mode = "rgmii-id";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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};
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mdio@25000 {
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status = "disabled";
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};
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mdio@26000 {
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status = "disabled";
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};
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enet0: ethernet@b0000 {
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status = "okay";
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phy-connection-type = "rgmii-id";
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nvmem-cells = <&macaddr_hwinfo_0>;
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nvmem-cell-names = "mac-address";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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enet1: ethernet@b1000 {
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status = "disabled";
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};
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enet2: ethernet@b2000 {
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status = "disabled";
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};
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gpio0: gpio-controller@fc00 {
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};
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usb@22000 {
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phy_type = "ulpi";
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dr_mode = "host";
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};
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usb@23000 {
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status = "disabled";
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};
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};
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pci0: pcie@ffe09000 {
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status = "disabled";
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};
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pci1: pcie@ffe0a000 {
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reg = <0x0 0xffe0a000 0x0 0x1000>;
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ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
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reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xc0000000
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0x2000000 0x0 0xc0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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ath9k: wifi@0,0 {
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reg = <0x0000 0 0 0 0>;
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#gpio-cells = <2>;
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gpio-controller;
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nvmem-cells = <&macaddr_hwinfo_0>;
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nvmem-cell-names = "mac-address";
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mac-address-increment = <16>;
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};
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};
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};
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leds {
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compatible = "gpio-leds";
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led_attention: led-0 {
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gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
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label = "amber:status";
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color = <LED_COLOR_ID_AMBER>;
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function = LED_FUNCTION_STATUS;
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};
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led_status: led-1 {
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gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
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label = "white:status";
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color = <LED_COLOR_ID_WHITE>;
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function = LED_FUNCTION_STATUS;
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};
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};
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buttons {
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compatible = "gpio-keys";
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reset {
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label = "Reset button";
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gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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/include/ "fsl/p1020si-post.dtsi"
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/ {
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chosen {
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linux,stdout-path = "/soc@ffe00000/serial@4500";
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};
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cpus {
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PowerPC,P1020@0 {
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i-cache-sets = <0x80>;
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i-cache-size = <0x8000>;
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i-cache-block-size = <0x20>;
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d-cache-sets = <0x80>;
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d-cache-size = <0x8000>;
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d-cache-block-size = <0x20>;
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clock-frequency = <0x2756cd00>;
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bus-frequency = <0x13ab6680>;
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timebase-frequency = <0x2756cd0>;
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};
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};
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memory {
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reg = <0x00 0x00 0x00 0x10000000>;
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};
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localbus@ffe05000 {
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bus-frequency = <0x13ab668>;
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};
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soc@ffe00000 {
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bus-frequency = <0x13ab6680>;
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serial@4500 {
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clock-frequency = <0x13ab6680>;
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};
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serial@4600 {
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clock-frequency = <0x13ab6680>;
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};
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};
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pcie@ffe09000 {
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clock-frequency = <0x1fca055>;
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};
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pcie@ffe0a000 {
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clock-frequency = <0x1fca055>;
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};
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};
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@ -0,0 +1,82 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Aerohive BR200-WP Board Setup
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* Copyright (C) 2023 Pawel Dembicki <paweldembicki@gmail.com>
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*
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* Based on:
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* hiveap-330.c:
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* Aerohive HiveAP-330 Board Setup
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* Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/of_platform.h>
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#include <asm/time.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <mm/mmu_decl.h>
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#include <asm/prom.h>
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#include <asm/udbg.h>
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#include <asm/mpic.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include "smp.h"
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#include "mpc85xx.h"
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void __init br200_wp_pic_init(void)
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{
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struct mpic *mpic;
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mpic = mpic_alloc(NULL, 0,
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MPIC_BIG_ENDIAN |
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MPIC_SINGLE_DEST_CPU,
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0, 256, " OpenPIC ");
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BUG_ON(mpic == NULL);
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mpic_init(mpic);
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}
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/*
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* Setup the architecture
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*/
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static void __init br200_wp_setup_arch(void)
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{
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if (ppc_md.progress)
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ppc_md.progress("br200_wp_setup_arch()", 0);
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fsl_pci_assign_primary();
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pr_info("br200-wp board from Aerohive\n");
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}
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machine_arch_initcall(br200_wp, mpc85xx_common_publish_devices);
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init br200_wp_probe(void)
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{
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if (of_machine_is_compatible("aerohive,br200-wp"))
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return 1;
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return 0;
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}
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define_machine(br200_wp) {
|
||||
.name = "P1020 RDB",
|
||||
.probe = br200_wp_probe,
|
||||
.setup_arch = br200_wp_setup_arch,
|
||||
.init_IRQ = br200_wp_pic_init,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
|
||||
#endif
|
||||
.get_irq = mpic_get_irq,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
};
|
||||
@ -14,6 +14,26 @@ define Build/spi-loader-okli
|
||||
mv "$@.new" "$@"
|
||||
endef
|
||||
|
||||
define Device/aerohive_br200-wp
|
||||
DEVICE_VENDOR := Aerohive
|
||||
DEVICE_MODEL := BR200-WP
|
||||
BLOCKSIZE := 128k
|
||||
KERNEL_NAME := simpleImage.br200-wp
|
||||
KERNEL := kernel-bin | uImage none
|
||||
KERNEL_INITRAMFS := kernel-bin | uImage none
|
||||
KERNEL_ENTRY := 0x1000000
|
||||
KERNEL_LOADADDR := 0x1000000
|
||||
KERNEL_SIZE := 8m
|
||||
IMAGES := fdt.bin sysupgrade.bin
|
||||
IMAGE/fdt.bin := append-dtb
|
||||
IMAGE/sysupgrade.bin := append-dtb | pad-to 256k | check-size 256k | \
|
||||
append-uImage-fakehdr ramdisk | pad-to 256k | check-size 512k | \
|
||||
append-rootfs | pad-rootfs $$(BLOCKSIZE) | pad-to 41216k | check-size 41216k | \
|
||||
append-kernel | append-metadata
|
||||
IMAGE_SIZE = 63m
|
||||
endef
|
||||
TARGET_DEVICES += aerohive_br200-wp
|
||||
|
||||
define Device/enterasys_ws-ap3715i
|
||||
DEVICE_VENDOR := Enterasys
|
||||
DEVICE_MODEL := WS-AP3715i
|
||||
|
||||
@ -1,8 +1,12 @@
|
||||
CONFIG_AT803X_PHY=y
|
||||
CONFIG_BR200_WP=y
|
||||
CONFIG_CMDLINE_OVERRIDE=y
|
||||
CONFIG_FIREBOX_T10=y
|
||||
# CONFIG_FSL_CORENET_CF is not set
|
||||
CONFIG_GPIO_74X164=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_NAND_FSL_IFC=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_MTD_SPLIT_FIRMWARE=y
|
||||
CONFIG_MTD_SPLIT_TPLINK_FW=y
|
||||
CONFIG_MTD_SPLIT_UIMAGE_FW=y
|
||||
@ -24,4 +28,3 @@ CONFIG_SPI_GPIO=y
|
||||
CONFIG_TL_WDR4900_V1=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_WS_AP3715I=y
|
||||
CONFIG_FIREBOX_T10=y
|
||||
@ -1,5 +1,5 @@
|
||||
BOARDNAME:=P1010
|
||||
KERNEL_IMAGES:=simpleImage.tl-wdr4900-v1 simpleImage.ws-ap3715i
|
||||
KERNEL_IMAGES:=simpleImage.br200-wp simpleImage.tl-wdr4900-v1 simpleImage.ws-ap3715i
|
||||
|
||||
define Target/Description
|
||||
Build firmware images for P1010 based boards.
|
||||
|
||||
@ -0,0 +1,57 @@
|
||||
--- a/arch/powerpc/platforms/85xx/Kconfig
|
||||
+++ b/arch/powerpc/platforms/85xx/Kconfig
|
||||
@@ -49,6 +49,16 @@ config BSC9132_QDS
|
||||
and dual StarCore SC3850 DSP cores.
|
||||
Manufacturer : Freescale Semiconductor, Inc
|
||||
|
||||
+config BR200_WP
|
||||
+ bool "Aerohive BR200-WP"
|
||||
+ select DEFAULT_UIMAGE
|
||||
+ select ARCH_REQUIRE_GPIOLIB
|
||||
+ select GPIO_MPC8XXX
|
||||
+ help
|
||||
+ This option enables support for the Aerohive BR200-WP board.
|
||||
+
|
||||
+ This board is a wireless router with a Freescale P1011 SoC.
|
||||
+
|
||||
config HIVEAP_330
|
||||
bool "Aerohive HiveAP-330"
|
||||
select DEFAULT_UIMAGE
|
||||
--- a/arch/powerpc/platforms/85xx/Makefile
|
||||
+++ b/arch/powerpc/platforms/85xx/Makefile
|
||||
@@ -12,6 +12,7 @@ obj-y += common.o
|
||||
obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o
|
||||
obj-$(CONFIG_BSC9132_QDS) += bsc913x_qds.o
|
||||
obj-$(CONFIG_C293_PCIE) += c293pcie.o
|
||||
+obj-$(CONFIG_BR200_WP) += br200-wp.o
|
||||
obj-$(CONFIG_HIVEAP_330) += hiveap-330.o
|
||||
obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
|
||||
obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
|
||||
--- a/arch/powerpc/boot/Makefile
|
||||
+++ b/arch/powerpc/boot/Makefile
|
||||
@@ -163,6 +163,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie
|
||||
src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
|
||||
src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
|
||||
src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
|
||||
+src-plat-$(CONFIG_BR200_WP) += simpleboot.c fixed-head.S
|
||||
src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
|
||||
src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
|
||||
|
||||
@@ -345,6 +346,7 @@ image-$(CONFIG_TQM8548) += cuImage.tqm
|
||||
image-$(CONFIG_TQM8555) += cuImage.tqm8555
|
||||
image-$(CONFIG_TQM8560) += cuImage.tqm8560
|
||||
image-$(CONFIG_KSI8560) += cuImage.ksi8560
|
||||
+image-$(CONFIG_BR200_WP) += simpleImage.br200-wp
|
||||
image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
|
||||
image-$(CONFIG_WS_AP3715I) += simpleImage.ws-ap3715i
|
||||
image-$(CONFIG_WS_AP3825I) += simpleImage.ws-ap3825i
|
||||
--- a/arch/powerpc/boot/wrapper
|
||||
+++ b/arch/powerpc/boot/wrapper
|
||||
@@ -326,6 +326,7 @@ adder875-redboot)
|
||||
platformo="$object/fixed-head.o $object/redboot-8xx.o"
|
||||
binary=y
|
||||
;;
|
||||
+simpleboot-br200-wp|\
|
||||
simpleboot-ws-ap3715i|\
|
||||
simpleboot-ws-ap3825i|\
|
||||
simpleboot-tl-wdr4900-v1)
|
||||
@ -16,7 +16,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
|
||||
--- a/arch/powerpc/boot/Makefile
|
||||
+++ b/arch/powerpc/boot/Makefile
|
||||
@@ -273,7 +273,6 @@ image-$(CONFIG_PPC_CHRP) += zImage.chrp
|
||||
@@ -274,7 +274,6 @@ image-$(CONFIG_PPC_CHRP) += zImage.chrp
|
||||
image-$(CONFIG_PPC_EFIKA) += zImage.chrp
|
||||
image-$(CONFIG_PPC_PMAC) += zImage.pmac
|
||||
image-$(CONFIG_PPC_HOLLY) += dtbImage.holly
|
||||
@ -24,7 +24,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
image-$(CONFIG_EPAPR_BOOT) += zImage.epapr
|
||||
|
||||
#
|
||||
@@ -407,15 +406,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
|
||||
@@ -409,15 +408,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
|
||||
$(obj)/vmlinux.strip: vmlinux
|
||||
$(STRIP) -s -R .comment $< -o $@
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user