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https://github.com/openwrt/openwrt.git
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ipq40xx: use patches that were sent upstream
Signed-off-by: John Crispin <john@phrozen.org>
This commit is contained in:
parent
e8c58e7ddd
commit
95672e0433
@ -164,7 +164,7 @@
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status = "okay";
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};
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&spi_0 {
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&blsp1_spi1 {
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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status = "okay";
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@ -193,7 +193,7 @@
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};
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};
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&spi_0 {
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&blsp1_spi1 {
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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status = "okay";
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@ -201,7 +201,7 @@
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status = "okay";
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};
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&spi_0 { /* BLSP1 QUP1 */
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&blsp1_spi1 { /* BLSP1 QUP1 */
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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status = "okay";
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@ -144,7 +144,7 @@
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status = "okay";
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};
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&spi_0 {
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&blsp1_spi1 {
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
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@ -193,7 +193,7 @@
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};
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};
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&spi_0 { /* BLSP1 QUP1 */
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&blsp1_spi1 { /* BLSP1 QUP1 */
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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status = "okay";
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@ -195,7 +195,7 @@
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};
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};
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&spi_0 { /* BLSP1 QUP1 */
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&blsp1_spi1 { /* BLSP1 QUP1 */
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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status = "okay";
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@ -157,7 +157,7 @@
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};
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};
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&spi_0 {
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&blsp1_spi1 {
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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status = "okay";
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@ -174,7 +174,7 @@
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status = "okay";
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};
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&spi_0 {
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&blsp1_spi1 {
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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status = "okay";
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@ -98,7 +98,7 @@
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status = "okay";
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};
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spi_0: spi@78b5000 {
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spi0: spi@78b5000 {
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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status = "okay";
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@ -113,7 +113,7 @@
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};
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};
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i2c_0: i2c@78b7000 { /* BLSP1 QUP2 */
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i2c0: i2c@78b7000 { /* BLSP1 QUP2 */
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pinctrl-0 = <&i2c_0_pins>;
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pinctrl-names = "default";
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@ -162,7 +162,7 @@
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status = "okay";
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};
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&spi_0 {
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&blsp1_spi1 {
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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status = "okay";
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@ -148,7 +148,7 @@
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status = "okay";
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};
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&spi_0 {
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&blsp1_spi1 {
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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status = "okay";
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@ -143,7 +143,7 @@
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vlan_tag = <0 0x20>;
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};
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&i2c_0 {
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&blsp1_i2c3{
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pinctrl-0 = <&i2c_0_pins>;
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pinctrl-names = "default";
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status = "okay";
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@ -155,7 +155,7 @@
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};
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};
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&i2c_1 {
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&blsp1_i2c4{
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pinctrl-0 = <&i2c_1_pins>;
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pinctrl-names = "default";
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status = "okay";
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@ -1,10 +1,22 @@
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Check for SCM availability before attempting to use SPM
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From 341844c7e06afccd64261719fa388339a589b0a4 Mon Sep 17 00:00:00 2001
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From: Felix Fietkau <nbd@nbd.name>
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Date: Sun, 22 Jul 2018 12:53:04 +0200
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Subject: [PATCH] soc: qcom: spm: add SCM probe dependency
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Check for SCM availability before attempting to use SPM. SPM probe will
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fail otherwise.
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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drivers/soc/qcom/spm.c | 3 +++
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1 file changed, 3 insertions(+)
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diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
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index f9d7a85b2822..53807e839664 100644
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--- a/drivers/soc/qcom/spm.c
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+++ b/drivers/soc/qcom/spm.c
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@@ -219,6 +219,9 @@ static int __init qcom_cpuidle_init(stru
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@@ -219,6 +219,9 @@ static int __init qcom_cpuidle_init(struct device_node *cpu_node, int cpu)
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cpumask_t mask;
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bool use_scm_power_down = false;
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@ -14,3 +26,6 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
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for (i = 0; ; i++) {
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state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
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if (!state_node)
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--
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2.11.0
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@ -1,23 +1,23 @@
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From 6a6c067b7ce2b3de4efbafddc134afbea3ddc1a3 Mon Sep 17 00:00:00 2001
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From 364123029d8d547336323fbd3d659ecd0bba913f Mon Sep 17 00:00:00 2001
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From: Matthew McClintock <mmcclint@codeaurora.org>
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Date: Fri, 8 Apr 2016 15:26:10 -0500
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Subject: [PATCH] qcom: ipq4019: use v2 of the kpss bringup mechanism
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Date: Mon, 23 Jul 2018 08:41:02 +0200
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Subject: [PATCH 5/8] qcom: ipq4019: use v2 of the kpss bringup mechanism
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v1 was the incorrect choice here and sometimes the board
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would not come up properly.
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Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
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Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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Changes:
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- moved L2-Cache to be a subnode of cpu0
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 32 ++++++++++++++++++++++++--------
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1 file changed, 24 insertions(+), 8 deletions(-)
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 25 +++++++++++++++++--------
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1 file changed, 17 insertions(+), 8 deletions(-)
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diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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index 93647db5d90b..06434fd02d40 100644
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -36,19 +36,27 @@
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@@ -52,7 +52,8 @@
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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@ -27,17 +27,7 @@ Changes:
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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reg = <0x0>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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operating-points-v2 = <&cpu0_opp_table>;
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+
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+ L2: l2-cache {
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+ compatible = "qcom,arch-cache";
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+ cache-level = <2>;
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+ qcom,saw = <&saw_l2>;
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+ };
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};
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@@ -71,7 +72,8 @@
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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@ -47,7 +37,7 @@ Changes:
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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reg = <0x1>;
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@@ -60,7 +68,8 @@
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@@ -82,7 +84,8 @@
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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@ -57,7 +47,7 @@ Changes:
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qcom,acc = <&acc2>;
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qcom,saw = <&saw2>;
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reg = <0x2>;
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@@ -72,7 +81,8 @@
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@@ -93,13 +96,19 @@
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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@ -67,7 +57,18 @@ Changes:
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qcom,acc = <&acc3>;
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qcom,saw = <&saw3>;
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reg = <0x3>;
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@@ -265,22 +275,22 @@
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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};
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+
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+ L2: l2-cache {
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+ compatible = "cache";
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+ cache-level = <2>;
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+ };
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};
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pmu {
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@@ -268,22 +277,22 @@
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};
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acc0: clock-controller@b088000 {
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@ -94,16 +95,6 @@ Changes:
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reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
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};
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@@ -308,6 +318,12 @@
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regulator;
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};
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--
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2.11.0
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+ saw_l2: regulator@b012000 {
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+ compatible = "qcom,saw2";
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+ reg = <0xb012000 0x1000>;
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+ regulator;
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+ };
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+
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serial@78af000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78af000 0x200>;
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@ -1,19 +1,22 @@
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From 18c3b42575a154343831aec0637aab00e19440e1 Mon Sep 17 00:00:00 2001
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From 544af73985cd14b450bb8e8a6c22b89a555ac729 Mon Sep 17 00:00:00 2001
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From: Matthew McClintock <mmcclint@codeaurora.org>
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Date: Thu, 17 Mar 2016 15:01:09 -0500
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Subject: [PATCH 17/69] qcom: ipq4019: add cpu operating points for cpufreq
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Date: Mon, 23 Jul 2018 09:10:35 +0200
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Subject: [PATCH 6/8] qcom: ipq4019: add cpu operating points for cpufreq
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support
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This adds some operating points for cpu frequeny scaling
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Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 34 ++++++++++++++++++++++++++--------
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1 file changed, 26 insertions(+), 8 deletions(-)
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -40,14 +40,7 @@
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Index: linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019.dtsi
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===================================================================
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--- linux-4.14.54.orig/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -41,14 +41,7 @@
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reg = <0x0>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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@ -29,7 +32,7 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
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};
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cpu@1 {
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@@ -59,6 +52,7 @@
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@@ -61,6 +54,7 @@
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reg = <0x1>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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@ -37,7 +40,7 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
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};
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cpu@2 {
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@@ -70,6 +64,7 @@
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@@ -73,6 +67,7 @@
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reg = <0x2>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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@ -45,7 +48,7 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
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};
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cpu@3 {
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@@ -81,6 +76,29 @@
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@@ -85,6 +80,29 @@
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reg = <0x3>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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@ -73,5 +76,5 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
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+ opp-hz = /bits/ 64 <716000000>;
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+ clock-latency-ns = <256000>;
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};
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};
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L2: l2-cache {
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@ -0,0 +1,38 @@
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From d60e006ec0e425877aacc61c7ece3da0434a8fce Mon Sep 17 00:00:00 2001
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From: Christian Lamparter <chunkeey@gmail.com>
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Date: Mon, 23 Jul 2018 16:34:54 +0200
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Subject: [PATCH 7/8] qcom: ipq4019: fix cpu0's qcom,saw2 reg value
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while compiling an ipq4019 target, dtc will complain:
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regulator@b089000 unit address format error, expected "2089000"
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The saw0 regulator reg value seems to be
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copied and pasted from qcom-ipq8064.dtsi.
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This patch fixes the reg value to match that of the
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unit address which in turn silences the warning.
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(There is no driver for qcom,saw2 right now.
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So this went unnoticed)
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Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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index 98b9850ed2a0..3289b3a6c10e 100644
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -316,7 +316,7 @@
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saw0: regulator@b089000 {
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compatible = "qcom,saw2";
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- reg = <0x02089000 0x1000>, <0x0b009000 0x1000>;
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+ reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
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regulator;
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};
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--
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2.11.0
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|
@ -1,28 +1,33 @@
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From e7748d641ae37081e2034869491f1629461ae13c Mon Sep 17 00:00:00 2001
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From 89b43d59ec8c9cda588555eb1f2754dd19ef5144 Mon Sep 17 00:00:00 2001
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From: Christian Lamparter <chunkeey@gmail.com>
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Date: Sat, 19 Nov 2016 00:58:18 +0100
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Subject: [PATCH] ARM: qcom: Add IPQ4019 SoC support
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Date: Sun, 22 Jul 2018 12:07:57 +0200
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Subject: [PATCH 8/8] ARM: qcom: Add IPQ4019 SoC support
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Add support for the Qualcomm Atheros IPQ4019 SoC.
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Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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arch/arm/Makefile | 1 +
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arch/arm/mach-qcom/Kconfig | 5 +++++
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2 files changed, 6 insertions(+)
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--- a/arch/arm/Makefile
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+++ b/arch/arm/Makefile
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@@ -149,6 +149,7 @@ textofs-$(CONFIG_SA1111) := 0x00208000
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endif
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Index: linux-4.14.54/arch/arm/Makefile
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===================================================================
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--- linux-4.14.54.orig/arch/arm/Makefile
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+++ linux-4.14.54/arch/arm/Makefile
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@@ -150,6 +150,7 @@ endif
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textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
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textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
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+textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000
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textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
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+textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000
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# Machine directory name. This list is sorted alphanumerically
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--- a/arch/arm/mach-qcom/Kconfig
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+++ b/arch/arm/mach-qcom/Kconfig
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# by CONFIG_* macro name.
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Index: linux-4.14.54/arch/arm/mach-qcom/Kconfig
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===================================================================
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--- linux-4.14.54.orig/arch/arm/mach-qcom/Kconfig
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+++ linux-4.14.54/arch/arm/mach-qcom/Kconfig
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@@ -27,4 +27,9 @@ config ARCH_MDM9615
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bool "Enable support for MDM9615"
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select CLKSRC_QCOM
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@ -0,0 +1,44 @@
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From 5f01733dc755dfadfa51b7b3c6c160e632fc6002 Mon Sep 17 00:00:00 2001
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From: John Crispin <john@phrozen.org>
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Date: Tue, 24 Jul 2018 15:09:36 +0200
|
||||
Subject: [PATCH 1/3] dt-bindings: phy-qcom-ipq4019-usb: add binding document
|
||||
|
||||
This patch adds the binding documentation for the HS/SS USB PHY found
|
||||
inside Qualcom Dakota SoCs.
|
||||
|
||||
Signed-off-by: John Crispin <john@phrozen.org>
|
||||
---
|
||||
.../bindings/phy/phy-qcom-ipq4019-usb.txt | 21 +++++++++++++++++++++
|
||||
1 file changed, 21 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
|
||||
|
||||
diff --git a/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt b/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
|
||||
new file mode 100644
|
||||
index 000000000000..362877fcafed
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
|
||||
@@ -0,0 +1,21 @@
|
||||
+Qualcom Dakota HS/SS USB PHY
|
||||
+
|
||||
+Required properties:
|
||||
+ - compatible: "qcom,usb-ss-ipq4019-phy",
|
||||
+ "qcom,usb-hs-ipq4019-phy"
|
||||
+ - reg: offset and length of the registers
|
||||
+ - #phy-cells: should be 0
|
||||
+ - resets: the reset controllers as listed below
|
||||
+ - reset-names: the names of the reset controllers
|
||||
+ "por_rst" - the POR reset line for SS and HS phys
|
||||
+ "srif_rst" - the SRIF reset line for HS phys
|
||||
+Example:
|
||||
+
|
||||
+hsphy@a8000 {
|
||||
+ compatible = "qcom,usb-hs-ipq4019-phy";
|
||||
+ phy-cells = <0>;
|
||||
+ reg = <0xa8000 0x40>;
|
||||
+ resets = <&gcc USB2_HSPHY_POR_ARES>,
|
||||
+ <&gcc USB2_HSPHY_S_ARES>;
|
||||
+ reset-names = "por_rst", "srif_rst";
|
||||
+};
|
||||
--
|
||||
2.11.0
|
||||
|
@ -1,138 +1,24 @@
|
||||
From ea5f4d6f4716f3a0bb4fc3614b7a0e8c0df1cb81 Mon Sep 17 00:00:00 2001
|
||||
From: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
Date: Thu, 17 Mar 2016 16:22:28 -0500
|
||||
Subject: [PATCH] qcom: ipq4019: add USB nodes to ipq4019 SoC device tree
|
||||
From 633f0e08498aebfdb932bd71319b4cb136709499 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <john@phrozen.org>
|
||||
Date: Tue, 24 Jul 2018 14:45:49 +0200
|
||||
Subject: [PATCH 2/3] phy: qcom-ipq4019-usb: add driver for QCOM/IPQ4019
|
||||
|
||||
This adds the SoC nodes to the ipq4019 device tree and
|
||||
enable it for the DK01.1 board.
|
||||
Add a driver to setup the USB phy on Qualcom Dakota SoCs.
|
||||
The driver sets up HS and SS phys. In case of HS some magic values need to
|
||||
be written to magic offsets. These were taken from the SDK driver.
|
||||
|
||||
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
Signed-off-by: John Crispin <john@phrozen.org>
|
||||
---
|
||||
Changes:
|
||||
- replaced space with tab
|
||||
- added sleep and mock_utmi clocks
|
||||
- added registers for usb2 and usb3 parent node
|
||||
- changed compatible to qca,ipa4019-dwc3
|
||||
- updated usb2 and usb3 names
|
||||
(included the reg - in case they become necessary later)
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 71 +++++++++++++++++++++++++++
|
||||
2 files changed, 91 insertions(+)
|
||||
drivers/phy/qualcomm/Kconfig | 7 ++
|
||||
drivers/phy/qualcomm/Makefile | 1 +
|
||||
drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c | 188 ++++++++++++++++++++++++++++
|
||||
3 files changed, 196 insertions(+)
|
||||
create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
@@ -101,5 +101,25 @@
|
||||
wifi@a800000 {
|
||||
status = "ok";
|
||||
};
|
||||
+
|
||||
+ usb3_ss_phy: ssphy@9a000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb3_hs_phy: hsphy@a6000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb3: usb3@8af8800 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb2_hs_phy: hsphy@a8000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb2: usb2@60f8800 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -539,5 +539,79 @@
|
||||
"legacy";
|
||||
status = "disabled";
|
||||
};
|
||||
+
|
||||
+ usb3_ss_phy: ssphy@9a000 {
|
||||
+ compatible = "qcom,usb-ss-ipq4019-phy";
|
||||
+ #phy-cells = <0>;
|
||||
+ reg = <0x9a000 0x800>;
|
||||
+ reg-names = "phy_base";
|
||||
+ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
|
||||
+ reset-names = "por_rst";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ usb3_hs_phy: hsphy@a6000 {
|
||||
+ compatible = "qcom,usb-hs-ipq4019-phy";
|
||||
+ #phy-cells = <0>;
|
||||
+ reg = <0xa6000 0x40>;
|
||||
+ reg-names = "phy_base";
|
||||
+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
|
||||
+ reset-names = "por_rst", "srif_rst";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ usb3@8af8800 {
|
||||
+ compatible = "qcom,dwc3";
|
||||
+ reg = <0x8af8800 0x100>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ clocks = <&gcc GCC_USB3_MASTER_CLK>,
|
||||
+ <&gcc GCC_USB3_SLEEP_CLK>,
|
||||
+ <&gcc GCC_USB3_MOCK_UTMI_CLK>;
|
||||
+ clock-names = "master", "sleep", "mock_utmi";
|
||||
+ ranges;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ dwc3@8a00000 {
|
||||
+ compatible = "snps,dwc3";
|
||||
+ reg = <0x8a00000 0xf8000>;
|
||||
+ interrupts = <0 132 0>;
|
||||
+ phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
|
||||
+ phy-names = "usb2-phy", "usb3-phy";
|
||||
+ dr_mode = "host";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb2_hs_phy: hsphy@a8000 {
|
||||
+ compatible = "qcom,usb-hs-ipq4019-phy";
|
||||
+ #phy-cells = <0>;
|
||||
+ reg = <0xa8000 0x40>;
|
||||
+ reg-names = "phy_base";
|
||||
+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
|
||||
+ reset-names = "por_rst", "srif_rst";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ usb2@60f8800 {
|
||||
+ compatible = "qcom,dwc3";
|
||||
+ reg = <0x60f8800 0x100>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ clocks = <&gcc GCC_USB2_MASTER_CLK>,
|
||||
+ <&gcc GCC_USB2_SLEEP_CLK>,
|
||||
+ <&gcc GCC_USB2_MOCK_UTMI_CLK>;
|
||||
+ clock-names = "master", "sleep", "mock_utmi";
|
||||
+ ranges;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ dwc3@6000000 {
|
||||
+ compatible = "snps,dwc3";
|
||||
+ reg = <0x6000000 0xf8000>;
|
||||
+ interrupts = <0 136 0>;
|
||||
+ phys = <&usb2_hs_phy>;
|
||||
+ phy-names = "usb2-phy";
|
||||
+ dr_mode = "host";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
};
|
||||
--- a/drivers/phy/qualcomm/Kconfig
|
||||
+++ b/drivers/phy/qualcomm/Kconfig
|
||||
Index: linux-4.14.54/drivers/phy/qualcomm/Kconfig
|
||||
===================================================================
|
||||
--- linux-4.14.54.orig/drivers/phy/qualcomm/Kconfig
|
||||
+++ linux-4.14.54/drivers/phy/qualcomm/Kconfig
|
||||
@@ -8,6 +8,13 @@ config PHY_QCOM_APQ8064_SATA
|
||||
depends on OF
|
||||
select GENERIC_PHY
|
||||
@ -147,17 +33,10 @@ Changes:
|
||||
config PHY_QCOM_IPQ806X_SATA
|
||||
tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
|
||||
depends on ARCH_QCOM
|
||||
--- a/drivers/phy/qualcomm/Makefile
|
||||
+++ b/drivers/phy/qualcomm/Makefile
|
||||
@@ -1,5 +1,6 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
|
||||
+obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
|
||||
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
|
||||
obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o
|
||||
obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
|
||||
Index: linux-4.14.54/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
|
||||
===================================================================
|
||||
--- /dev/null
|
||||
+++ b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
|
||||
+++ linux-4.14.54/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
|
||||
@@ -0,0 +1,188 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2018 John Crispin <john@phrozen.org>
|
||||
@ -347,3 +226,14 @@ Changes:
|
||||
+MODULE_DESCRIPTION("QCOM/IPQ4019 USB phy driver");
|
||||
+MODULE_AUTHOR("John Crispin <john@phrozen.org>");
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
Index: linux-4.14.54/drivers/phy/qualcomm/Makefile
|
||||
===================================================================
|
||||
--- linux-4.14.54.orig/drivers/phy/qualcomm/Makefile
|
||||
+++ linux-4.14.54/drivers/phy/qualcomm/Makefile
|
||||
@@ -1,5 +1,6 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
|
||||
+obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
|
||||
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
|
||||
obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o
|
||||
obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
|
@ -0,0 +1,130 @@
|
||||
From 1fc7d5523e21ed140fed43c4dde011a3b6d9ba08 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <john@phrozen.org>
|
||||
Date: Tue, 24 Jul 2018 14:47:55 +0200
|
||||
Subject: [PATCH 3/3] qcom: ipq4019: add USB devicetree nodes
|
||||
|
||||
This patch makes USB work on the Dakota EVB.
|
||||
|
||||
Signed-off-by: John Crispin <john@phrozen.org>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++
|
||||
2 files changed, 94 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
index 418f9a022336..2ee5f05d5a43 100644
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
@@ -109,5 +109,25 @@
|
||||
wifi@a800000 {
|
||||
status = "ok";
|
||||
};
|
||||
+
|
||||
+ usb3_ss_phy: ssphy@9a000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb3_hs_phy: hsphy@a6000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb3: usb3@8af8800 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb2_hs_phy: hsphy@a8000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ usb2: usb2@60f8800 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
};
|
||||
};
|
||||
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
index e5e52adbd5a3..e6b12129f0e4 100644
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -553,5 +553,79 @@
|
||||
"legacy";
|
||||
status = "disabled";
|
||||
};
|
||||
+
|
||||
+ usb3_ss_phy: ssphy@9a000 {
|
||||
+ compatible = "qcom,usb-ss-ipq4019-phy";
|
||||
+ #phy-cells = <0>;
|
||||
+ reg = <0x9a000 0x800>;
|
||||
+ reg-names = "phy_base";
|
||||
+ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
|
||||
+ reset-names = "por_rst";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ usb3_hs_phy: hsphy@a6000 {
|
||||
+ compatible = "qcom,usb-hs-ipq4019-phy";
|
||||
+ #phy-cells = <0>;
|
||||
+ reg = <0xa6000 0x40>;
|
||||
+ reg-names = "phy_base";
|
||||
+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
|
||||
+ reset-names = "por_rst", "srif_rst";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ usb3@8af8800 {
|
||||
+ compatible = "qcom,dwc3";
|
||||
+ reg = <0x8af8800 0x100>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ clocks = <&gcc GCC_USB3_MASTER_CLK>,
|
||||
+ <&gcc GCC_USB3_SLEEP_CLK>,
|
||||
+ <&gcc GCC_USB3_MOCK_UTMI_CLK>;
|
||||
+ clock-names = "master", "sleep", "mock_utmi";
|
||||
+ ranges;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ dwc3@8a00000 {
|
||||
+ compatible = "snps,dwc3";
|
||||
+ reg = <0x8a00000 0xf8000>;
|
||||
+ interrupts = <0 132 0>;
|
||||
+ phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
|
||||
+ phy-names = "usb2-phy", "usb3-phy";
|
||||
+ dr_mode = "host";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb2_hs_phy: hsphy@a8000 {
|
||||
+ compatible = "qcom,usb-hs-ipq4019-phy";
|
||||
+ #phy-cells = <0>;
|
||||
+ reg = <0xa8000 0x40>;
|
||||
+ reg-names = "phy_base";
|
||||
+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
|
||||
+ reset-names = "por_rst", "srif_rst";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ usb2@60f8800 {
|
||||
+ compatible = "qcom,dwc3";
|
||||
+ reg = <0x60f8800 0x100>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ clocks = <&gcc GCC_USB2_MASTER_CLK>,
|
||||
+ <&gcc GCC_USB2_SLEEP_CLK>,
|
||||
+ <&gcc GCC_USB2_MOCK_UTMI_CLK>;
|
||||
+ clock-names = "master", "sleep", "mock_utmi";
|
||||
+ ranges;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ dwc3@6000000 {
|
||||
+ compatible = "snps,dwc3";
|
||||
+ reg = <0x6000000 0xf8000>;
|
||||
+ interrupts = <0 136 0>;
|
||||
+ phys = <&usb2_hs_phy>;
|
||||
+ phy-names = "usb2-phy";
|
||||
+ dr_mode = "host";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
};
|
||||
--
|
||||
2.11.0
|
||||
|
@ -1,42 +1,89 @@
|
||||
From patchwork Mon Jan 29 05:11:16 2018
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [02/15] ARM: dts: ipq4019: Add a few peripheral nodes
|
||||
From 187519403273f0599c848d20eca9acce8b1807a5 Mon Sep 17 00:00:00 2001
|
||||
From: Sricharan R <sricharan@codeaurora.org>
|
||||
X-Patchwork-Id: 10189263
|
||||
Message-Id: <1517202689-14212-3-git-send-email-sricharan@codeaurora.org>
|
||||
To: robh+dt@kernel.org, robh@kernel.org, mark.rutland@arm.com,
|
||||
linux@armlinux.org.uk, andy.gross@linaro.org, david.brown@linaro.org,
|
||||
catalin.marinas@arm.com, will.deacon@arm.com, sboyd@codeaurora.org,
|
||||
bjorn.andersson@linaro.org, devicetree@vger.kernel.org,
|
||||
linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
|
||||
linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org
|
||||
Cc: sricharan@codeaurora.org
|
||||
Date: Mon, 29 Jan 2018 10:41:16 +0530
|
||||
Date: Fri, 25 May 2018 11:41:12 +0530
|
||||
Subject: [PATCH] ARM: dts: ipq4019: Add a few peripheral nodes
|
||||
|
||||
Now with the driver updates for some peripherals being there,
|
||||
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
|
||||
peripheral support.
|
||||
|
||||
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
|
||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
Signed-off-by: Andy Gross <andy.gross@linaro.org>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 ++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 134 insertions(+)
|
||||
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 2 +-
|
||||
arch/arm/boot/dts/qcom-ipq4019.dtsi | 156 ++++++++++++++++++++++++--
|
||||
2 files changed, 146 insertions(+), 12 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
index ef8d8c88ed7b..418f9a022336 100644
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
@@ -69,7 +69,7 @@
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
- spi_0: spi@78b5000 {
|
||||
+ spi@78b5000 {
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "ok";
|
||||
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
index 2efc8a2d41a7..737097e9fb4f 100644
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
||||
@@ -25,7 +25,9 @@
|
||||
@@ -40,8 +40,10 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
spi0 = &spi_0;
|
||||
+ spi1 = &spi_1;
|
||||
i2c0 = &i2c_0;
|
||||
+ i2c1 = &i2c_1;
|
||||
- spi0 = &spi_0;
|
||||
- i2c0 = &i2c_0;
|
||||
+ spi0 = &blsp1_spi1;
|
||||
+ spi1 = &blsp1_spi2;
|
||||
+ i2c0 = &blsp1_i2c3;
|
||||
+ i2c1 = &blsp1_i2c4;
|
||||
};
|
||||
|
||||
cpus {
|
||||
@@ -190,6 +192,22 @@
|
||||
@@ -120,6 +122,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ firmware {
|
||||
+ scm {
|
||||
+ compatible = "qcom,scm-ipq4019";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 2 0xf08>,
|
||||
@@ -165,13 +173,13 @@
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
- interrupts = <0 208 0>;
|
||||
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
blsp_dma: dma@7884000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x07884000 0x23000>;
|
||||
- interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
|
||||
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
@@ -179,7 +187,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
- spi_0: spi@78b5000 {
|
||||
+ blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
|
||||
compatible = "qcom,spi-qup-v2.2.1";
|
||||
reg = <0x78b5000 0x600>;
|
||||
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@@ -188,10 +196,26 @@
|
||||
clock-names = "core", "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -45,7 +92,7 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ spi_1: spi@78b6000 { /* BLSP1 QUP2 */
|
||||
+ blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
|
||||
+ compatible = "qcom,spi-qup-v2.2.1";
|
||||
+ reg = <0x78b6000 0x600>;
|
||||
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@ -59,7 +106,12 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -202,9 +220,24 @@
|
||||
- i2c_0: i2c@78b7000 {
|
||||
+ blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x78b7000 0x600>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@@ -200,14 +224,29 @@
|
||||
clock-names = "iface", "core";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -68,7 +120,7 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ i2c_1: i2c@78b8000 { /* BLSP1 QUP4 */
|
||||
+ blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
|
||||
+ compatible = "qcom,i2c-qup-v2.2.1";
|
||||
+ reg = <0x78b8000 0x600>;
|
||||
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@ -84,7 +136,31 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
|
||||
cryptobam: dma@8e04000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
@@ -311,6 +344,101 @@
|
||||
reg = <0x08e04000 0x20000>;
|
||||
- interrupts = <GIC_SPI 207 0>;
|
||||
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
@@ -275,7 +314,7 @@
|
||||
blsp1_uart1: serial@78af000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x78af000 0x200>;
|
||||
- interrupts = <0 107 0>;
|
||||
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
|
||||
<&gcc GCC_BLSP1_AHB_CLK>;
|
||||
@@ -287,7 +326,7 @@
|
||||
serial@78b0000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x78b0000 0x200>;
|
||||
- interrupts = <0 108 0>;
|
||||
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
|
||||
<&gcc GCC_BLSP1_AHB_CLK>;
|
||||
@@ -309,6 +348,101 @@
|
||||
reg = <0x4ab000 0x4>;
|
||||
};
|
||||
|
||||
@ -105,7 +181,7 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
+ ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
|
||||
+ 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
|
||||
+
|
||||
+ interrupts = <GIC_SPI 141 IRQ_TYPE_NONE>;
|
||||
+ interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
|
||||
+ interrupt-names = "msi";
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-map-mask = <0 0 0 0x7>;
|
||||
@ -186,3 +262,24 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
wifi0: wifi@a000000 {
|
||||
compatible = "qcom,ipq4019-wifi";
|
||||
reg = <0xa000000 0x200000>;
|
||||
@@ -342,7 +476,7 @@
|
||||
<GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
|
||||
- <GIC_SPI 168 IRQ_TYPE_NONE>;
|
||||
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
||||
"msi4", "msi5", "msi6", "msi7",
|
||||
"msi8", "msi9", "msi10", "msi11",
|
||||
@@ -384,7 +518,7 @@
|
||||
<GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
|
||||
- <GIC_SPI 169 IRQ_TYPE_NONE>;
|
||||
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
||||
"msi4", "msi5", "msi6", "msi7",
|
||||
"msi8", "msi9", "msi10", "msi11",
|
||||
--
|
||||
2.11.0
|
||||
|
@ -1,7 +1,7 @@
|
||||
From 12e9319da1adacac92930c899c99f0e1970cac11 Mon Sep 17 00:00:00 2001
|
||||
From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@googlemail.com>
|
||||
Date: Thu, 11 Mar 2018 14:41:31 +0100
|
||||
Subject: [PATCH] clk: fix apss cpu overclocking
|
||||
Date: Sun, 11 Mar 2018 14:41:31 +0100
|
||||
Subject: [PATCH 2/2] clk: fix apss cpu overclocking
|
||||
|
||||
There's an interaction issue between the clk changes:"
|
||||
clk: qcom: ipq4019: Add the apss cpu pll divider clock node
|
||||
@ -37,10 +37,16 @@ try to overclock to 761 MHz.
|
||||
|
||||
Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node")
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
Signed-off-by: John Crispin <john@phrozen.org>
|
||||
---
|
||||
drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++---
|
||||
1 file changed, 31 insertions(+), 3 deletions(-)
|
||||
|
||||
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
|
||||
index 46cb256b4aa2..4ec43f7d2e52 100644
|
||||
--- a/drivers/clk/qcom/gcc-ipq4019.c
|
||||
+++ b/drivers/clk/qcom/gcc-ipq4019.c
|
||||
@@ -1253,6 +1253,29 @@ static const struct clk_fepll_vco gcc_fe
|
||||
@@ -1253,6 +1253,29 @@ static const struct clk_fepll_vco gcc_fepll_vco = {
|
||||
.reg = 0x2f020,
|
||||
};
|
||||
|
||||
@ -70,7 +76,7 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
/*
|
||||
* Round rate function for APSS CPU PLL Clock divider.
|
||||
* It looks up the frequency table and returns the next higher frequency
|
||||
@@ -1265,7 +1288,7 @@ static long clk_cpu_div_round_rate(struc
|
||||
@@ -1265,7 +1288,7 @@ static long clk_cpu_div_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
struct clk_hw *p_hw;
|
||||
const struct freq_tbl *f;
|
||||
|
||||
@ -79,7 +85,7 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
if (!f)
|
||||
return -EINVAL;
|
||||
|
||||
@@ -1288,7 +1311,7 @@ static int clk_cpu_div_set_rate(struct c
|
||||
@@ -1288,7 +1311,7 @@ static int clk_cpu_div_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
u32 mask;
|
||||
int ret;
|
||||
|
||||
@ -96,7 +102,7 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
struct clk_fepll *pll = to_clk_fepll(hw);
|
||||
u32 cdiv, pre_div;
|
||||
u64 rate;
|
||||
@@ -1335,7 +1359,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
|
||||
@@ -1335,7 +1359,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *hw,
|
||||
rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
|
||||
do_div(rate, pre_div);
|
||||
|
||||
@ -109,3 +115,6 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
};
|
||||
|
||||
static const struct clk_ops clk_regmap_cpu_div_ops = {
|
||||
--
|
||||
2.11.0
|
||||
|
@ -1,5 +1,7 @@
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
Index: linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
===================================================================
|
||||
--- linux-4.14.54.orig/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
+++ linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
@@ -15,12 +15,39 @@
|
||||
*/
|
||||
|
||||
@ -40,9 +42,7 @@
|
||||
rng@22000 {
|
||||
status = "ok";
|
||||
};
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
@@ -93,14 +93,6 @@
|
||||
@@ -66,14 +93,6 @@
|
||||
pinctrl-names = "default";
|
||||
status = "ok";
|
||||
cs-gpios = <&tlmm 54 0>;
|
||||
@ -57,11 +57,38 @@
|
||||
};
|
||||
|
||||
serial@78af000 {
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
|
||||
@@ -19,4 +19,71 @@
|
||||
@@ -102,6 +121,22 @@
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
+ mdio@90000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ ess-switch@c000000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ ess-psgmii@98000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ edma@c080000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
usb3_ss_phy: ssphy@9a000 {
|
||||
status = "ok";
|
||||
};
|
||||
Index: linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
|
||||
===================================================================
|
||||
--- linux-4.14.54.orig/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
|
||||
+++ linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
|
||||
@@ -18,5 +18,73 @@
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
|
||||
+ compatible = "qcom,ap-dk01.1-c1", "qcom,ap-dk01.2-c1", "qcom,ipq4019";
|
||||
|
||||
+ memory {
|
||||
+ device_type = "memory";
|
||||
@ -69,7 +96,7 @@
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&spi_0 {
|
||||
+&blsp1_spi1 {
|
||||
+ mx25l25635f@0 {
|
||||
+ compatible = "mx25l25635f", "jedec,spi-nor";
|
||||
+ #address-cells = <1>;
|
||||
@ -131,38 +158,3 @@
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
|
||||
@@ -18,6 +18,7 @@
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
|
||||
+ compatible = "qcom,ap-dk01.1-c1", "qcom,ap-dk01.2-c1", "qcom,ipq4019";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
||||
@@ -121,6 +121,22 @@
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
+ mdio@90000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ ess-switch@c000000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ ess-psgmii@98000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ edma@c080000 {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
usb3_ss_phy: ssphy@9a000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
Loading…
Reference in New Issue
Block a user