diff --git a/target/linux/qualcommbe/patches-6.6/020-v6.11-PCI-qcom-Use-devm_clk_bulk_get_all-API.patch b/target/linux/qualcommbe/patches-6.6/020-v6.11-PCI-qcom-Use-devm_clk_bulk_get_all-API.patch new file mode 100644 index 00000000000..453620f3201 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/020-v6.11-PCI-qcom-Use-devm_clk_bulk_get_all-API.patch @@ -0,0 +1,388 @@ +From 652935ba05860eadaa19ac9efe7aea61fb7a3aef Mon Sep 17 00:00:00 2001 +From: Manivannan Sadhasivam +Date: Wed, 17 Apr 2024 12:32:53 +0530 +Subject: [PATCH] PCI: qcom: Use devm_clk_bulk_get_all() API +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +There is no need for the device drivers to validate the clocks defined in +Devicetree. The validation should be performed by the DT schema and the +drivers should just get all the clocks from DT. Right now the driver +hardcodes the clock info and validates them against DT which is redundant. + +So use devm_clk_bulk_get_all() that just gets all the clocks defined in DT +and get rid of all static clocks info from the driver. This simplifies the +driver. + +Link: https://lore.kernel.org/linux-pci/20240417-pci-qcom-clk-bulk-v1-1-52ca19b3d6b2@linaro.org +Signed-off-by: Manivannan Sadhasivam +Signed-off-by: Krzysztof Wilczyński +Signed-off-by: Bjorn Helgaas +--- + drivers/pci/controller/dwc/pcie-qcom.c | 177 ++++++++----------------- + 1 file changed, 58 insertions(+), 119 deletions(-) + +--- a/drivers/pci/controller/dwc/pcie-qcom.c ++++ b/drivers/pci/controller/dwc/pcie-qcom.c +@@ -151,58 +151,56 @@ + + #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) + +-#define QCOM_PCIE_1_0_0_MAX_CLOCKS 4 + struct qcom_pcie_resources_1_0_0 { +- struct clk_bulk_data clks[QCOM_PCIE_1_0_0_MAX_CLOCKS]; ++ struct clk_bulk_data *clks; ++ int num_clks; + struct reset_control *core; + struct regulator *vdda; + }; + +-#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 + #define QCOM_PCIE_2_1_0_MAX_RESETS 6 + #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 + struct qcom_pcie_resources_2_1_0 { +- struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; ++ struct clk_bulk_data *clks; ++ int num_clks; + struct reset_control_bulk_data resets[QCOM_PCIE_2_1_0_MAX_RESETS]; + int num_resets; + struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; + }; + +-#define QCOM_PCIE_2_3_2_MAX_CLOCKS 4 + #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2 + struct qcom_pcie_resources_2_3_2 { +- struct clk_bulk_data clks[QCOM_PCIE_2_3_2_MAX_CLOCKS]; ++ struct clk_bulk_data *clks; ++ int num_clks; + struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; + }; + +-#define QCOM_PCIE_2_3_3_MAX_CLOCKS 5 + #define QCOM_PCIE_2_3_3_MAX_RESETS 7 + struct qcom_pcie_resources_2_3_3 { +- struct clk_bulk_data clks[QCOM_PCIE_2_3_3_MAX_CLOCKS]; ++ struct clk_bulk_data *clks; ++ int num_clks; + struct reset_control_bulk_data rst[QCOM_PCIE_2_3_3_MAX_RESETS]; + }; + +-#define QCOM_PCIE_2_4_0_MAX_CLOCKS 4 + #define QCOM_PCIE_2_4_0_MAX_RESETS 12 + struct qcom_pcie_resources_2_4_0 { +- struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS]; ++ struct clk_bulk_data *clks; + int num_clks; + struct reset_control_bulk_data resets[QCOM_PCIE_2_4_0_MAX_RESETS]; + int num_resets; + }; + +-#define QCOM_PCIE_2_7_0_MAX_CLOCKS 15 + #define QCOM_PCIE_2_7_0_MAX_SUPPLIES 2 + struct qcom_pcie_resources_2_7_0 { +- struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS]; ++ struct clk_bulk_data *clks; + int num_clks; + struct regulator_bulk_data supplies[QCOM_PCIE_2_7_0_MAX_SUPPLIES]; + struct reset_control *rst; + }; + +-#define QCOM_PCIE_2_9_0_MAX_CLOCKS 5 + struct qcom_pcie_resources_2_9_0 { +- struct clk_bulk_data clks[QCOM_PCIE_2_9_0_MAX_CLOCKS]; ++ struct clk_bulk_data *clks; ++ int num_clks; + struct reset_control *rst; + }; + +@@ -313,21 +311,11 @@ static int qcom_pcie_get_resources_2_1_0 + if (ret) + return ret; + +- res->clks[0].id = "iface"; +- res->clks[1].id = "core"; +- res->clks[2].id = "phy"; +- res->clks[3].id = "aux"; +- res->clks[4].id = "ref"; +- +- /* iface, core, phy are required */ +- ret = devm_clk_bulk_get(dev, 3, res->clks); +- if (ret < 0) +- return ret; +- +- /* aux, ref are optional */ +- ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3); +- if (ret < 0) +- return ret; ++ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); ++ if (res->num_clks < 0) { ++ dev_err(dev, "Failed to get clocks\n"); ++ return res->num_clks; ++ } + + res->resets[0].id = "pci"; + res->resets[1].id = "axi"; +@@ -349,7 +337,7 @@ static void qcom_pcie_deinit_2_1_0(struc + { + struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; + +- clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); ++ clk_bulk_disable_unprepare(res->num_clks, res->clks); + reset_control_bulk_assert(res->num_resets, res->resets); + + writel(1, pcie->parf + PARF_PHY_CTRL); +@@ -401,7 +389,7 @@ static int qcom_pcie_post_init_2_1_0(str + val &= ~PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); + +- ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); ++ ret = clk_bulk_prepare_enable(res->num_clks, res->clks); + if (ret) + return ret; + +@@ -452,20 +440,16 @@ static int qcom_pcie_get_resources_1_0_0 + struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; +- int ret; + + res->vdda = devm_regulator_get(dev, "vdda"); + if (IS_ERR(res->vdda)) + return PTR_ERR(res->vdda); + +- res->clks[0].id = "iface"; +- res->clks[1].id = "aux"; +- res->clks[2].id = "master_bus"; +- res->clks[3].id = "slave_bus"; +- +- ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); +- if (ret < 0) +- return ret; ++ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); ++ if (res->num_clks < 0) { ++ dev_err(dev, "Failed to get clocks\n"); ++ return res->num_clks; ++ } + + res->core = devm_reset_control_get_exclusive(dev, "core"); + return PTR_ERR_OR_ZERO(res->core); +@@ -476,7 +460,7 @@ static void qcom_pcie_deinit_1_0_0(struc + struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; + + reset_control_assert(res->core); +- clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); ++ clk_bulk_disable_unprepare(res->num_clks, res->clks); + regulator_disable(res->vdda); + } + +@@ -493,7 +477,7 @@ static int qcom_pcie_init_1_0_0(struct q + return ret; + } + +- ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); ++ ret = clk_bulk_prepare_enable(res->num_clks, res->clks); + if (ret) { + dev_err(dev, "cannot prepare/enable clocks\n"); + goto err_assert_reset; +@@ -508,7 +492,7 @@ static int qcom_pcie_init_1_0_0(struct q + return 0; + + err_disable_clks: +- clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); ++ clk_bulk_disable_unprepare(res->num_clks, res->clks); + err_assert_reset: + reset_control_assert(res->core); + +@@ -556,14 +540,11 @@ static int qcom_pcie_get_resources_2_3_2 + if (ret) + return ret; + +- res->clks[0].id = "aux"; +- res->clks[1].id = "cfg"; +- res->clks[2].id = "bus_master"; +- res->clks[3].id = "bus_slave"; +- +- ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); +- if (ret < 0) +- return ret; ++ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); ++ if (res->num_clks < 0) { ++ dev_err(dev, "Failed to get clocks\n"); ++ return res->num_clks; ++ } + + return 0; + } +@@ -572,7 +553,7 @@ static void qcom_pcie_deinit_2_3_2(struc + { + struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; + +- clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); ++ clk_bulk_disable_unprepare(res->num_clks, res->clks); + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); + } + +@@ -589,7 +570,7 @@ static int qcom_pcie_init_2_3_2(struct q + return ret; + } + +- ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); ++ ret = clk_bulk_prepare_enable(res->num_clks, res->clks); + if (ret) { + dev_err(dev, "cannot prepare/enable clocks\n"); + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); +@@ -637,17 +618,11 @@ static int qcom_pcie_get_resources_2_4_0 + bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019"); + int ret; + +- res->clks[0].id = "aux"; +- res->clks[1].id = "master_bus"; +- res->clks[2].id = "slave_bus"; +- res->clks[3].id = "iface"; +- +- /* qcom,pcie-ipq4019 is defined without "iface" */ +- res->num_clks = is_ipq ? 3 : 4; +- +- ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); +- if (ret < 0) +- return ret; ++ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); ++ if (res->num_clks < 0) { ++ dev_err(dev, "Failed to get clocks\n"); ++ return res->num_clks; ++ } + + res->resets[0].id = "axi_m"; + res->resets[1].id = "axi_s"; +@@ -718,15 +693,11 @@ static int qcom_pcie_get_resources_2_3_3 + struct device *dev = pci->dev; + int ret; + +- res->clks[0].id = "iface"; +- res->clks[1].id = "axi_m"; +- res->clks[2].id = "axi_s"; +- res->clks[3].id = "ahb"; +- res->clks[4].id = "aux"; +- +- ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); +- if (ret < 0) +- return ret; ++ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); ++ if (res->num_clks < 0) { ++ dev_err(dev, "Failed to get clocks\n"); ++ return res->num_clks; ++ } + + res->rst[0].id = "axi_m"; + res->rst[1].id = "axi_s"; +@@ -747,7 +718,7 @@ static void qcom_pcie_deinit_2_3_3(struc + { + struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; + +- clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); ++ clk_bulk_disable_unprepare(res->num_clks, res->clks); + } + + static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) +@@ -777,7 +748,7 @@ static int qcom_pcie_init_2_3_3(struct q + */ + usleep_range(2000, 2500); + +- ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); ++ ret = clk_bulk_prepare_enable(res->num_clks, res->clks); + if (ret) { + dev_err(dev, "cannot prepare/enable clocks\n"); + goto err_assert_resets; +@@ -838,8 +809,6 @@ static int qcom_pcie_get_resources_2_7_0 + struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; +- unsigned int num_clks, num_opt_clks; +- unsigned int idx; + int ret; + + res->rst = devm_reset_control_array_get_exclusive(dev); +@@ -853,36 +822,11 @@ static int qcom_pcie_get_resources_2_7_0 + if (ret) + return ret; + +- idx = 0; +- res->clks[idx++].id = "aux"; +- res->clks[idx++].id = "cfg"; +- res->clks[idx++].id = "bus_master"; +- res->clks[idx++].id = "bus_slave"; +- res->clks[idx++].id = "slave_q2a"; +- +- num_clks = idx; +- +- ret = devm_clk_bulk_get(dev, num_clks, res->clks); +- if (ret < 0) +- return ret; +- +- res->clks[idx++].id = "tbu"; +- res->clks[idx++].id = "ddrss_sf_tbu"; +- res->clks[idx++].id = "aggre0"; +- res->clks[idx++].id = "aggre1"; +- res->clks[idx++].id = "noc_aggr"; +- res->clks[idx++].id = "noc_aggr_4"; +- res->clks[idx++].id = "noc_aggr_south_sf"; +- res->clks[idx++].id = "cnoc_qx"; +- res->clks[idx++].id = "sleep"; +- res->clks[idx++].id = "cnoc_sf_axi"; +- +- num_opt_clks = idx - num_clks; +- res->num_clks = idx; +- +- ret = devm_clk_bulk_get_optional(dev, num_opt_clks, res->clks + num_clks); +- if (ret < 0) +- return ret; ++ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); ++ if (res->num_clks < 0) { ++ dev_err(dev, "Failed to get clocks\n"); ++ return res->num_clks; ++ } + + return 0; + } +@@ -1073,17 +1017,12 @@ static int qcom_pcie_get_resources_2_9_0 + struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; +- int ret; +- +- res->clks[0].id = "iface"; +- res->clks[1].id = "axi_m"; +- res->clks[2].id = "axi_s"; +- res->clks[3].id = "axi_bridge"; +- res->clks[4].id = "rchng"; + +- ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); +- if (ret < 0) +- return ret; ++ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); ++ if (res->num_clks < 0) { ++ dev_err(dev, "Failed to get clocks\n"); ++ return res->num_clks; ++ } + + res->rst = devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(res->rst)) +@@ -1096,7 +1035,7 @@ static void qcom_pcie_deinit_2_9_0(struc + { + struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; + +- clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); ++ clk_bulk_disable_unprepare(res->num_clks, res->clks); + } + + static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) +@@ -1125,7 +1064,7 @@ static int qcom_pcie_init_2_9_0(struct q + + usleep_range(2000, 2500); + +- return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); ++ return clk_bulk_prepare_enable(res->num_clks, res->clks); + } + + static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) diff --git a/target/linux/qualcommbe/patches-6.6/021-v6.12-PCI-qcom-Disable-mirroring-of-DBI-and-iATU-register-.patch b/target/linux/qualcommbe/patches-6.6/021-v6.12-PCI-qcom-Disable-mirroring-of-DBI-and-iATU-register-.patch new file mode 100644 index 00000000000..34b0859f242 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/021-v6.12-PCI-qcom-Disable-mirroring-of-DBI-and-iATU-register-.patch @@ -0,0 +1,277 @@ +From 10ba0854c5e6165b58e17bda5fb671e729fecf9e Mon Sep 17 00:00:00 2001 +From: Prudhvi Yarlagadda +Date: Wed, 14 Aug 2024 15:03:38 -0700 +Subject: [PATCH] PCI: qcom: Disable mirroring of DBI and iATU register space + in BAR region +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +PARF hardware block which is a wrapper on top of DWC PCIe controller +mirrors the DBI and ATU register space. It uses PARF_SLV_ADDR_SPACE_SIZE +register to get the size of the memory block to be mirrored and uses +PARF_DBI_BASE_ADDR, PARF_ATU_BASE_ADDR registers to determine the base +address of DBI and ATU space inside the memory block that is being +mirrored. + +When a memory region which is located above the SLV_ADDR_SPACE_SIZE +boundary is used for BAR region then there could be an overlap of DBI and +ATU address space that is getting mirrored and the BAR region. This +results in DBI and ATU address space contents getting updated when a PCIe +function driver tries updating the BAR/MMIO memory region. Reference +memory map of the PCIe memory region with DBI and ATU address space +overlapping BAR region is as below. + + |---------------| + | | + | | + ------- --------|---------------| + | | |---------------| + | | | DBI | + | | |---------------|---->DBI_BASE_ADDR + | | | | + | | | | + | PCIe | |---->2*SLV_ADDR_SPACE_SIZE + | BAR/MMIO|---------------| + | Region | ATU | + | | |---------------|---->ATU_BASE_ADDR + | | | | + PCIe | |---------------| + Memory | | DBI | + Region | |---------------|---->DBI_BASE_ADDR + | | | | + | --------| | + | | |---->SLV_ADDR_SPACE_SIZE + | |---------------| + | | ATU | + | |---------------|---->ATU_BASE_ADDR + | | | + | |---------------| + | | DBI | + | |---------------|---->DBI_BASE_ADDR + | | | + | | | + ----------------|---------------| + | | + | | + | | + |---------------| + +Currently memory region beyond the SLV_ADDR_SPACE_SIZE boundary is not +used for BAR region which is why the above mentioned issue is not +encountered. This issue is discovered as part of internal testing when we +tried moving the BAR region beyond the SLV_ADDR_SPACE_SIZE boundary. Hence +we are trying to fix this. + +As PARF hardware block mirrors DBI and ATU register space after every +PARF_SLV_ADDR_SPACE_SIZE (default 0x1000000) boundary multiple, program +maximum possible size to this register by writing 0x80000000 to it(it +considers only powers of 2 as values) to avoid mirroring DBI and ATU to +BAR/MMIO region. Write the physical base address of DBI and ATU register +blocks to PARF_DBI_BASE_ADDR (default 0x0) and PARF_ATU_BASE_ADDR (default +0x1000) respectively to make sure DBI and ATU blocks are at expected +memory locations. + +The register offsets PARF_DBI_BASE_ADDR_V2, PARF_SLV_ADDR_SPACE_SIZE_V2 +and PARF_ATU_BASE_ADDR are applicable for platforms that use Qcom IP +rev 1.9.0, 2.7.0 and 2.9.0. PARF_DBI_BASE_ADDR_V2 and +PARF_SLV_ADDR_SPACE_SIZE_V2 are applicable for Qcom IP rev 2.3.3. +PARF_DBI_BASE_ADDR and PARF_SLV_ADDR_SPACE_SIZE are applicable for Qcom +IP rev 1.0.0, 2.3.2 and 2.4.0. Update init()/post_init() functions of the +respective Qcom IP versions to program applicable PARF_DBI_BASE_ADDR, +PARF_SLV_ADDR_SPACE_SIZE and PARF_ATU_BASE_ADDR register offsets. Update +the SLV_ADDR_SPACE_SZ macro to 0x80000000 to set highest bit in +PARF_SLV_ADDR_SPACE_SIZE register. + +Cache DBI and iATU physical addresses in 'struct dw_pcie' so that +pcie_qcom.c driver can program these addresses in the PARF_DBI_BASE_ADDR +and PARF_ATU_BASE_ADDR registers. + +Suggested-by: Manivannan Sadhasivam +Link: https://lore.kernel.org/linux-pci/20240814220338.1969668-1-quic_pyarlaga@quicinc.com +Signed-off-by: Prudhvi Yarlagadda +Signed-off-by: Krzysztof Wilczyński +Reviewed-by: Manivannan Sadhasivam +Reviewed-by: Mayank Rana +--- + drivers/pci/controller/dwc/pcie-designware.c | 2 + + drivers/pci/controller/dwc/pcie-designware.h | 2 + + drivers/pci/controller/dwc/pcie-qcom.c | 72 ++++++++++++++++---- + 3 files changed, 61 insertions(+), 15 deletions(-) + +--- a/drivers/pci/controller/dwc/pcie-designware.c ++++ b/drivers/pci/controller/dwc/pcie-designware.c +@@ -112,6 +112,7 @@ int dw_pcie_get_resources(struct dw_pcie + pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res); + if (IS_ERR(pci->dbi_base)) + return PTR_ERR(pci->dbi_base); ++ pci->dbi_phys_addr = res->start; + } + + /* DBI2 is mainly useful for the endpoint controller */ +@@ -134,6 +135,7 @@ int dw_pcie_get_resources(struct dw_pcie + pci->atu_base = devm_ioremap_resource(pci->dev, res); + if (IS_ERR(pci->atu_base)) + return PTR_ERR(pci->atu_base); ++ pci->atu_phys_addr = res->start; + } else { + pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; + } +--- a/drivers/pci/controller/dwc/pcie-designware.h ++++ b/drivers/pci/controller/dwc/pcie-designware.h +@@ -384,8 +384,10 @@ struct dw_pcie_ops { + struct dw_pcie { + struct device *dev; + void __iomem *dbi_base; ++ resource_size_t dbi_phys_addr; + void __iomem *dbi_base2; + void __iomem *atu_base; ++ resource_size_t atu_phys_addr; + size_t atu_size; + u32 num_ib_windows; + u32 num_ob_windows; +--- a/drivers/pci/controller/dwc/pcie-qcom.c ++++ b/drivers/pci/controller/dwc/pcie-qcom.c +@@ -43,6 +43,7 @@ + #define PARF_PHY_REFCLK 0x4c + #define PARF_CONFIG_BITS 0x50 + #define PARF_DBI_BASE_ADDR 0x168 ++#define PARF_SLV_ADDR_SPACE_SIZE 0x16c + #define PARF_MHI_CLOCK_RESET_CTRL 0x174 + #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 + #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 +@@ -50,7 +51,12 @@ + #define PARF_LTSSM 0x1b0 + #define PARF_SID_OFFSET 0x234 + #define PARF_BDF_TRANSLATE_CFG 0x24c +-#define PARF_SLV_ADDR_SPACE_SIZE 0x358 ++#define PARF_DBI_BASE_ADDR_V2 0x350 ++#define PARF_DBI_BASE_ADDR_V2_HI 0x354 ++#define PARF_SLV_ADDR_SPACE_SIZE_V2 0x358 ++#define PARF_SLV_ADDR_SPACE_SIZE_V2_HI 0x35c ++#define PARF_ATU_BASE_ADDR 0x634 ++#define PARF_ATU_BASE_ADDR_HI 0x638 + #define PARF_DEVICE_TYPE 0x1000 + #define PARF_BDF_TO_SID_TABLE_N 0x2000 + #define PARF_BDF_TO_SID_CFG 0x2c00 +@@ -105,7 +111,7 @@ + #define PHY_RX0_EQ(x) FIELD_PREP(GENMASK(26, 24), x) + + /* PARF_SLV_ADDR_SPACE_SIZE register value */ +-#define SLV_ADDR_SPACE_SZ 0x10000000 ++#define SLV_ADDR_SPACE_SZ 0x80000000 + + /* PARF_MHI_CLOCK_RESET_CTRL register fields */ + #define AHB_CLK_EN BIT(0) +@@ -285,6 +291,50 @@ static void qcom_pcie_clear_hpc(struct d + dw_pcie_dbi_ro_wr_dis(pci); + } + ++static void qcom_pcie_configure_dbi_base(struct qcom_pcie *pcie) ++{ ++ struct dw_pcie *pci = pcie->pci; ++ ++ if (pci->dbi_phys_addr) { ++ /* ++ * PARF_DBI_BASE_ADDR register is in CPU domain and require to ++ * be programmed with CPU physical address. ++ */ ++ writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + ++ PARF_DBI_BASE_ADDR); ++ writel(SLV_ADDR_SPACE_SZ, pcie->parf + ++ PARF_SLV_ADDR_SPACE_SIZE); ++ } ++} ++ ++static void qcom_pcie_configure_dbi_atu_base(struct qcom_pcie *pcie) ++{ ++ struct dw_pcie *pci = pcie->pci; ++ ++ if (pci->dbi_phys_addr) { ++ /* ++ * PARF_DBI_BASE_ADDR_V2 and PARF_ATU_BASE_ADDR registers are ++ * in CPU domain and require to be programmed with CPU ++ * physical addresses. ++ */ ++ writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + ++ PARF_DBI_BASE_ADDR_V2); ++ writel(upper_32_bits(pci->dbi_phys_addr), pcie->parf + ++ PARF_DBI_BASE_ADDR_V2_HI); ++ ++ if (pci->atu_phys_addr) { ++ writel(lower_32_bits(pci->atu_phys_addr), pcie->parf + ++ PARF_ATU_BASE_ADDR); ++ writel(upper_32_bits(pci->atu_phys_addr), pcie->parf + ++ PARF_ATU_BASE_ADDR_HI); ++ } ++ ++ writel(0x0, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_V2); ++ writel(SLV_ADDR_SPACE_SZ, pcie->parf + ++ PARF_SLV_ADDR_SPACE_SIZE_V2_HI); ++ } ++} ++ + static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) + { + u32 val; +@@ -501,8 +551,7 @@ err_assert_reset: + + static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) + { +- /* change DBI base address */ +- writel(0, pcie->parf + PARF_DBI_BASE_ADDR); ++ qcom_pcie_configure_dbi_base(pcie); + + if (IS_ENABLED(CONFIG_PCI_MSI)) { + u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); +@@ -589,8 +638,7 @@ static int qcom_pcie_post_init_2_3_2(str + val &= ~PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); + +- /* change DBI base address */ +- writel(0, pcie->parf + PARF_DBI_BASE_ADDR); ++ qcom_pcie_configure_dbi_base(pcie); + + /* MAC PHY_POWERDOWN MUX DISABLE */ + val = readl(pcie->parf + PARF_SYS_CTRL); +@@ -772,13 +820,11 @@ static int qcom_pcie_post_init_2_3_3(str + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u32 val; + +- writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); +- + val = readl(pcie->parf + PARF_PHY_CTRL); + val &= ~PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); + +- writel(0, pcie->parf + PARF_DBI_BASE_ADDR); ++ qcom_pcie_configure_dbi_atu_base(pcie); + + writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS + | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS | +@@ -874,8 +920,7 @@ static int qcom_pcie_init_2_7_0(struct q + val &= ~PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); + +- /* change DBI base address */ +- writel(0, pcie->parf + PARF_DBI_BASE_ADDR); ++ qcom_pcie_configure_dbi_atu_base(pcie); + + /* MAC PHY_POWERDOWN MUX DISABLE */ + val = readl(pcie->parf + PARF_SYS_CTRL); +@@ -1074,14 +1119,11 @@ static int qcom_pcie_post_init_2_9_0(str + u32 val; + int i; + +- writel(SLV_ADDR_SPACE_SZ, +- pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); +- + val = readl(pcie->parf + PARF_PHY_CTRL); + val &= ~PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); + +- writel(0, pcie->parf + PARF_DBI_BASE_ADDR); ++ qcom_pcie_configure_dbi_atu_base(pcie); + + writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); + writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN, diff --git a/target/linux/qualcommbe/patches-6.6/022-01-v6.11-phy-qcom-qmp-Add-missing-offsets-for-Qserdes-PLL-reg.patch b/target/linux/qualcommbe/patches-6.6/022-01-v6.11-phy-qcom-qmp-Add-missing-offsets-for-Qserdes-PLL-reg.patch new file mode 100644 index 00000000000..2b9eb62897e --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/022-01-v6.11-phy-qcom-qmp-Add-missing-offsets-for-Qserdes-PLL-reg.patch @@ -0,0 +1,28 @@ +From f1aaa788b997ba8a7810da0696e89fd3f79ecce3 Mon Sep 17 00:00:00 2001 +From: devi priya +Date: Thu, 16 May 2024 08:54:34 +0530 +Subject: [PATCH 1/3] phy: qcom-qmp: Add missing offsets for Qserdes PLL + registers. + +Add missing register offsets for Qserdes PLL. + +Reviewed-by: Abel Vesa +Signed-off-by: devi priya +Link: https://lore.kernel.org/r/20240516032436.2681828-3-quic_devipriy@quicinc.com +Signed-off-by: Vinod Koul +--- + drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h +@@ -8,6 +8,9 @@ + + /* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */ + #define QSERDES_PLL_BG_TIMER 0x00c ++#define QSERDES_PLL_SSC_EN_CENTER 0x010 ++#define QSERDES_PLL_SSC_ADJ_PER1 0x014 ++#define QSERDES_PLL_SSC_ADJ_PER2 0x018 + #define QSERDES_PLL_SSC_PER1 0x01c + #define QSERDES_PLL_SSC_PER2 0x020 + #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 diff --git a/target/linux/qualcommbe/patches-6.6/022-02-v6.11-phy-qcom-qmp-Add-missing-register-definitions-for-PC.patch b/target/linux/qualcommbe/patches-6.6/022-02-v6.11-phy-qcom-qmp-Add-missing-register-definitions-for-PC.patch new file mode 100644 index 00000000000..1b336952821 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/022-02-v6.11-phy-qcom-qmp-Add-missing-register-definitions-for-PC.patch @@ -0,0 +1,41 @@ +From 71ae2acf1d7542ecd21c6933cae8fe65d550074b Mon Sep 17 00:00:00 2001 +From: devi priya +Date: Thu, 16 May 2024 08:54:35 +0530 +Subject: [PATCH 2/3] phy: qcom-qmp: Add missing register definitions for PCS + V5 + +Add missing register offsets for PCS V5 registers. + +Reviewed-by: Abel Vesa +Signed-off-by: devi priya +Link: https://lore.kernel.org/r/20240516032436.2681828-4-quic_devipriy@quicinc.com +Signed-off-by: Vinod Koul +--- + drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h +@@ -11,8 +11,22 @@ + #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c + #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14 + #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 ++#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x44 ++#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x48 ++#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x4c ++#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x50 + #define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 ++#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1 0x5c ++#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2 0x60 ++#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4 0x68 ++#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x7c ++#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x84 ++#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x88 ++#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x8c + #define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 ++#define QPHY_V5_PCS_PCIE_EQ_CONFIG1 0xa4 + #define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 ++#define QPHY_V5_PCS_PCIE_PRESET_P10_PRE 0xc0 ++#define QPHY_V5_PCS_PCIE_PRESET_P10_POST 0xe4 + + #endif diff --git a/target/linux/qualcommbe/patches-6.6/022-03-v6.11-phy-qcom-qmp-pcie-Add-support-for-IPQ9574-g3x1-and-g.patch b/target/linux/qualcommbe/patches-6.6/022-03-v6.11-phy-qcom-qmp-pcie-Add-support-for-IPQ9574-g3x1-and-g.patch new file mode 100644 index 00000000000..25758bac548 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/022-03-v6.11-phy-qcom-qmp-pcie-Add-support-for-IPQ9574-g3x1-and-g.patch @@ -0,0 +1,358 @@ +From 2f2f5c13cc5ea87f1dd2debfd06fe5f624e5c0fd Mon Sep 17 00:00:00 2001 +From: devi priya +Date: Thu, 16 May 2024 08:54:36 +0530 +Subject: [PATCH 3/3] phy: qcom-qmp-pcie: Add support for IPQ9574 g3x1 and g3x2 + PCIEs + +Add support for a single-lane and two-lane PCIe PHYs +found on Qualcomm IPQ9574 platform. + +Reviewed-by: Abel Vesa +Co-developed-by: Anusha Rao +Signed-off-by: Anusha Rao +Signed-off-by: devi priya +Link: https://lore.kernel.org/r/20240516032436.2681828-5-quic_devipriy@quicinc.com +Signed-off-by: Vinod Koul +--- + drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 309 +++++++++++++++++++++++ + 1 file changed, 309 insertions(+) + +--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +@@ -514,6 +514,243 @@ static const struct qmp_phy_init_tbl ipq + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), + }; + ++static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10), ++}; ++ ++static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10), ++}; ++ ++static const struct qmp_phy_init_tbl ipq9574_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x73), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++}; ++ ++static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), ++}; ++ ++static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x14), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x06), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++}; ++ ++static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++}; ++ ++static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x14), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0b), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_PRE, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_POST, 0x58), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4, 0x19), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x49), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x2a), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++}; ++ + static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), +@@ -2354,6 +2591,16 @@ static const struct qmp_pcie_offsets qmp + .rx2 = 0x1800, + }; + ++static const struct qmp_pcie_offsets qmp_pcie_offsets_ipq9574 = { ++ .serdes = 0, ++ .pcs = 0x1000, ++ .pcs_misc = 0x1400, ++ .tx = 0x0200, ++ .rx = 0x0400, ++ .tx2 = 0x0600, ++ .rx2 = 0x0800, ++}; ++ + static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_20 = { + .serdes = 0x1000, + .pcs = 0x1200, +@@ -2466,6 +2713,62 @@ static const struct qmp_phy_cfg ipq6018_ + .phy_status = PHYSTATUS, + }; + ++static const struct qmp_phy_cfg ipq9574_gen3x1_pciephy_cfg = { ++ .lanes = 1, ++ ++ .offsets = &qmp_pcie_offsets_v4x1, ++ ++ .tbls = { ++ .serdes = ipq9574_gen3x1_pcie_serdes_tbl, ++ .serdes_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_serdes_tbl), ++ .tx = ipq8074_pcie_gen3_tx_tbl, ++ .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), ++ .rx = ipq9574_pcie_rx_tbl, ++ .rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl), ++ .pcs = ipq9574_gen3x1_pcie_pcs_tbl, ++ .pcs_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_tbl), ++ .pcs_misc = ipq9574_gen3x1_pcie_pcs_misc_tbl, ++ .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_misc_tbl), ++ }, ++ .reset_list = ipq8074_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), ++ .vreg_list = NULL, ++ .num_vregs = 0, ++ .regs = pciephy_v4_regs_layout, ++ ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ .pipe_clock_rate = 250000000, ++}; ++ ++static const struct qmp_phy_cfg ipq9574_gen3x2_pciephy_cfg = { ++ .lanes = 2, ++ ++ .offsets = &qmp_pcie_offsets_ipq9574, ++ ++ .tbls = { ++ .serdes = ipq9574_gen3x2_pcie_serdes_tbl, ++ .serdes_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl), ++ .tx = ipq8074_pcie_gen3_tx_tbl, ++ .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), ++ .rx = ipq9574_pcie_rx_tbl, ++ .rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl), ++ .pcs = ipq9574_gen3x2_pcie_pcs_tbl, ++ .pcs_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_tbl), ++ .pcs_misc = ipq9574_gen3x2_pcie_pcs_misc_tbl, ++ .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl), ++ }, ++ .reset_list = ipq8074_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), ++ .vreg_list = NULL, ++ .num_vregs = 0, ++ .regs = pciephy_v5_regs_layout, ++ ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ .pipe_clock_rate = 250000000, ++}; ++ + static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { + .lanes = 1, + +@@ -3718,6 +4021,12 @@ static const struct of_device_id qmp_pci + .compatible = "qcom,ipq8074-qmp-pcie-phy", + .data = &ipq8074_pciephy_cfg, + }, { ++ .compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy", ++ .data = &ipq9574_gen3x1_pciephy_cfg, ++ }, { ++ .compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy", ++ .data = &ipq9574_gen3x2_pciephy_cfg, ++ }, { + .compatible = "qcom,msm8998-qmp-pcie-phy", + .data = &msm8998_pciephy_cfg, + }, { diff --git a/target/linux/qualcommbe/patches-6.6/023-01-v6.14-arm64-dts-qcom-ipq9574-Add-PCIe-PHYs-and-controller-.patch b/target/linux/qualcommbe/patches-6.6/023-01-v6.14-arm64-dts-qcom-ipq9574-Add-PCIe-PHYs-and-controller-.patch new file mode 100644 index 00000000000..13b1d750526 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/023-01-v6.14-arm64-dts-qcom-ipq9574-Add-PCIe-PHYs-and-controller-.patch @@ -0,0 +1,468 @@ +From d80c7fbfa908e3d893a1ea7fe178dfa82ed66bf1 Mon Sep 17 00:00:00 2001 +From: devi priya +Date: Thu, 1 Aug 2024 11:18:01 +0530 +Subject: [PATCH 1/2] arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller + nodes + +Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices +found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane Gen3 +host whereas PCIe2 & PCIe3 are 2-lane Gen3 host. + +Signed-off-by: devi priya +Signed-off-by: Sricharan Ramabadhran +Link: https://lore.kernel.org/r/20240801054803.3015572-3-quic_srichara@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 420 +++++++++++++++++++++++++- + 1 file changed, 416 insertions(+), 4 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -239,6 +239,52 @@ + reg = <0x00060000 0x6000>; + }; + ++ pcie0_phy: phy@84000 { ++ compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; ++ reg = <0x00084000 0x1000>; ++ ++ clocks = <&gcc GCC_PCIE0_AUX_CLK>, ++ <&gcc GCC_PCIE0_AHB_CLK>, ++ <&gcc GCC_PCIE0_PIPE_CLK>; ++ clock-names = "aux", "cfg_ahb", "pipe"; ++ ++ assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>; ++ assigned-clock-rates = <20000000>; ++ ++ resets = <&gcc GCC_PCIE0_PHY_BCR>, ++ <&gcc GCC_PCIE0PHY_PHY_BCR>; ++ reset-names = "phy", "common"; ++ ++ #clock-cells = <0>; ++ clock-output-names = "gcc_pcie0_pipe_clk_src"; ++ ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ pcie2_phy: phy@8c000 { ++ compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy"; ++ reg = <0x0008c000 0x2000>; ++ ++ clocks = <&gcc GCC_PCIE2_AUX_CLK>, ++ <&gcc GCC_PCIE2_AHB_CLK>, ++ <&gcc GCC_PCIE2_PIPE_CLK>; ++ clock-names = "aux", "cfg_ahb", "pipe"; ++ ++ assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>; ++ assigned-clock-rates = <20000000>; ++ ++ resets = <&gcc GCC_PCIE2_PHY_BCR>, ++ <&gcc GCC_PCIE2PHY_PHY_BCR>; ++ reset-names = "phy", "common"; ++ ++ #clock-cells = <0>; ++ clock-output-names = "gcc_pcie2_pipe_clk_src"; ++ ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + rng: rng@e3000 { + compatible = "qcom,prng-ee"; + reg = <0x000e3000 0x1000>; +@@ -268,6 +314,52 @@ + assigned-clock-rates-u64 = /bits/ 64 <12000000000>; + }; + ++ pcie3_phy: phy@f4000 { ++ compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy"; ++ reg = <0x000f4000 0x2000>; ++ ++ clocks = <&gcc GCC_PCIE3_AUX_CLK>, ++ <&gcc GCC_PCIE3_AHB_CLK>, ++ <&gcc GCC_PCIE3_PIPE_CLK>; ++ clock-names = "aux", "cfg_ahb", "pipe"; ++ ++ assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>; ++ assigned-clock-rates = <20000000>; ++ ++ resets = <&gcc GCC_PCIE3_PHY_BCR>, ++ <&gcc GCC_PCIE3PHY_PHY_BCR>; ++ reset-names = "phy", "common"; ++ ++ #clock-cells = <0>; ++ clock-output-names = "gcc_pcie3_pipe_clk_src"; ++ ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ pcie1_phy: phy@fc000 { ++ compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; ++ reg = <0x000fc000 0x1000>; ++ ++ clocks = <&gcc GCC_PCIE1_AUX_CLK>, ++ <&gcc GCC_PCIE1_AHB_CLK>, ++ <&gcc GCC_PCIE1_PIPE_CLK>; ++ clock-names = "aux", "cfg_ahb", "pipe"; ++ ++ assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>; ++ assigned-clock-rates = <20000000>; ++ ++ resets = <&gcc GCC_PCIE1_PHY_BCR>, ++ <&gcc GCC_PCIE1PHY_PHY_BCR>; ++ reset-names = "phy", "common"; ++ ++ #clock-cells = <0>; ++ clock-output-names = "gcc_pcie1_pipe_clk_src"; ++ ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + qfprom: efuse@a4000 { + compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; + reg = <0x000a4000 0x5a1>; +@@ -334,10 +426,10 @@ + clocks = <&xo_board_clk>, + <&sleep_clk>, + <0>, +- <0>, +- <0>, +- <0>, +- <0>, ++ <&pcie0_phy>, ++ <&pcie1_phy>, ++ <&pcie2_phy>, ++ <&pcie3_phy>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; +@@ -777,6 +869,326 @@ + status = "disabled"; + }; + }; ++ ++ pcie1: pcie@10000000 { ++ compatible = "qcom,pcie-ipq9574"; ++ reg = <0x10000000 0xf1d>, ++ <0x10000f20 0xa8>, ++ <0x10001000 0x1000>, ++ <0x000f8000 0x4000>, ++ <0x10100000 0x1000>; ++ reg-names = "dbi", "elbi", "atu", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <1>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>, ++ <0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>; ++ ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "msi0", ++ "msi1", ++ "msi2", ++ "msi3", ++ "msi4", ++ "msi5", ++ "msi6", ++ "msi7"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 2 &intc 0 0 49 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 3 &intc 0 0 84 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 4 &intc 0 0 85 IRQ_TYPE_LEVEL_HIGH>; ++ ++ clocks = <&gcc GCC_PCIE1_AXI_M_CLK>, ++ <&gcc GCC_PCIE1_AXI_S_CLK>, ++ <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>, ++ <&gcc GCC_PCIE1_RCHNG_CLK>, ++ <&gcc GCC_PCIE1_AHB_CLK>, ++ <&gcc GCC_PCIE1_AUX_CLK>; ++ clock-names = "axi_m", ++ "axi_s", ++ "axi_bridge", ++ "rchng", ++ "ahb", ++ "aux"; ++ ++ resets = <&gcc GCC_PCIE1_PIPE_ARES>, ++ <&gcc GCC_PCIE1_CORE_STICKY_ARES>, ++ <&gcc GCC_PCIE1_AXI_S_STICKY_ARES>, ++ <&gcc GCC_PCIE1_AXI_S_ARES>, ++ <&gcc GCC_PCIE1_AXI_M_STICKY_ARES>, ++ <&gcc GCC_PCIE1_AXI_M_ARES>, ++ <&gcc GCC_PCIE1_AUX_ARES>, ++ <&gcc GCC_PCIE1_AHB_ARES>; ++ reset-names = "pipe", ++ "sticky", ++ "axi_s_sticky", ++ "axi_s", ++ "axi_m_sticky", ++ "axi_m", ++ "aux", ++ "ahb"; ++ ++ phys = <&pcie1_phy>; ++ phy-names = "pciephy"; ++ interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>, ++ <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>; ++ interconnect-names = "pcie-mem", "cpu-pcie"; ++ status = "disabled"; ++ }; ++ ++ pcie3: pcie@18000000 { ++ compatible = "qcom,pcie-ipq9574"; ++ reg = <0x18000000 0xf1d>, ++ <0x18000f20 0xa8>, ++ <0x18001000 0x1000>, ++ <0x000f0000 0x4000>, ++ <0x18100000 0x1000>; ++ reg-names = "dbi", "elbi", "atu", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <3>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <2>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>, ++ <0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>; ++ ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "msi0", ++ "msi1", ++ "msi2", ++ "msi3", ++ "msi4", ++ "msi5", ++ "msi6", ++ "msi7"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 0 189 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 2 &intc 0 0 190 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 3 &intc 0 0 191 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 4 &intc 0 0 192 IRQ_TYPE_LEVEL_HIGH>; ++ ++ clocks = <&gcc GCC_PCIE3_AXI_M_CLK>, ++ <&gcc GCC_PCIE3_AXI_S_CLK>, ++ <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>, ++ <&gcc GCC_PCIE3_RCHNG_CLK>, ++ <&gcc GCC_PCIE3_AHB_CLK>, ++ <&gcc GCC_PCIE3_AUX_CLK>; ++ clock-names = "axi_m", ++ "axi_s", ++ "axi_bridge", ++ "rchng", ++ "ahb", ++ "aux"; ++ ++ resets = <&gcc GCC_PCIE3_PIPE_ARES>, ++ <&gcc GCC_PCIE3_CORE_STICKY_ARES>, ++ <&gcc GCC_PCIE3_AXI_S_STICKY_ARES>, ++ <&gcc GCC_PCIE3_AXI_S_ARES>, ++ <&gcc GCC_PCIE3_AXI_M_STICKY_ARES>, ++ <&gcc GCC_PCIE3_AXI_M_ARES>, ++ <&gcc GCC_PCIE3_AUX_ARES>, ++ <&gcc GCC_PCIE3_AHB_ARES>; ++ reset-names = "pipe", ++ "sticky", ++ "axi_s_sticky", ++ "axi_s", ++ "axi_m_sticky", ++ "axi_m", ++ "aux", ++ "ahb"; ++ ++ phys = <&pcie3_phy>; ++ phy-names = "pciephy"; ++ interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>, ++ <&gcc MASTER_SNOC_PCIE3 &gcc SLAVE_SNOC_PCIE3>; ++ interconnect-names = "pcie-mem", "cpu-pcie"; ++ status = "disabled"; ++ }; ++ ++ pcie2: pcie@20000000 { ++ compatible = "qcom,pcie-ipq9574"; ++ reg = <0x20000000 0xf1d>, ++ <0x20000f20 0xa8>, ++ <0x20001000 0x1000>, ++ <0x00088000 0x4000>, ++ <0x20100000 0x1000>; ++ reg-names = "dbi", "elbi", "atu", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <2>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <2>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x100000>, ++ <0x02000000 0x0 0x20300000 0x20300000 0x0 0x7d00000>; ++ ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "msi0", ++ "msi1", ++ "msi2", ++ "msi3", ++ "msi4", ++ "msi5", ++ "msi6", ++ "msi7"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 0 164 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 2 &intc 0 0 165 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 3 &intc 0 0 186 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 4 &intc 0 0 187 IRQ_TYPE_LEVEL_HIGH>; ++ ++ clocks = <&gcc GCC_PCIE2_AXI_M_CLK>, ++ <&gcc GCC_PCIE2_AXI_S_CLK>, ++ <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>, ++ <&gcc GCC_PCIE2_RCHNG_CLK>, ++ <&gcc GCC_PCIE2_AHB_CLK>, ++ <&gcc GCC_PCIE2_AUX_CLK>; ++ clock-names = "axi_m", ++ "axi_s", ++ "axi_bridge", ++ "rchng", ++ "ahb", ++ "aux"; ++ ++ resets = <&gcc GCC_PCIE2_PIPE_ARES>, ++ <&gcc GCC_PCIE2_CORE_STICKY_ARES>, ++ <&gcc GCC_PCIE2_AXI_S_STICKY_ARES>, ++ <&gcc GCC_PCIE2_AXI_S_ARES>, ++ <&gcc GCC_PCIE2_AXI_M_STICKY_ARES>, ++ <&gcc GCC_PCIE2_AXI_M_ARES>, ++ <&gcc GCC_PCIE2_AUX_ARES>, ++ <&gcc GCC_PCIE2_AHB_ARES>; ++ reset-names = "pipe", ++ "sticky", ++ "axi_s_sticky", ++ "axi_s", ++ "axi_m_sticky", ++ "axi_m", ++ "aux", ++ "ahb"; ++ ++ phys = <&pcie2_phy>; ++ phy-names = "pciephy"; ++ interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>, ++ <&gcc MASTER_SNOC_PCIE2 &gcc SLAVE_SNOC_PCIE2>; ++ interconnect-names = "pcie-mem", "cpu-pcie"; ++ status = "disabled"; ++ }; ++ ++ pcie0: pci@28000000 { ++ compatible = "qcom,pcie-ipq9574"; ++ reg = <0x28000000 0xf1d>, ++ <0x28000f20 0xa8>, ++ <0x28001000 0x1000>, ++ <0x00080000 0x4000>, ++ <0x28100000 0x1000>; ++ reg-names = "dbi", "elbi", "atu", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <0>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x01000000 0x0 0x00000000 0x28200000 0x0 0x100000>, ++ <0x02000000 0x0 0x28300000 0x28300000 0x0 0x7d00000>; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "msi0", ++ "msi1", ++ "msi2", ++ "msi3", ++ "msi4", ++ "msi5", ++ "msi6", ++ "msi7"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>; ++ ++ clocks = <&gcc GCC_PCIE0_AXI_M_CLK>, ++ <&gcc GCC_PCIE0_AXI_S_CLK>, ++ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, ++ <&gcc GCC_PCIE0_RCHNG_CLK>, ++ <&gcc GCC_PCIE0_AHB_CLK>, ++ <&gcc GCC_PCIE0_AUX_CLK>; ++ clock-names = "axi_m", ++ "axi_s", ++ "axi_bridge", ++ "rchng", ++ "ahb", ++ "aux"; ++ ++ resets = <&gcc GCC_PCIE0_PIPE_ARES>, ++ <&gcc GCC_PCIE0_CORE_STICKY_ARES>, ++ <&gcc GCC_PCIE0_AXI_S_STICKY_ARES>, ++ <&gcc GCC_PCIE0_AXI_S_ARES>, ++ <&gcc GCC_PCIE0_AXI_M_STICKY_ARES>, ++ <&gcc GCC_PCIE0_AXI_M_ARES>, ++ <&gcc GCC_PCIE0_AUX_ARES>, ++ <&gcc GCC_PCIE0_AHB_ARES>; ++ reset-names = "pipe", ++ "sticky", ++ "axi_s_sticky", ++ "axi_s", ++ "axi_m_sticky", ++ "axi_m", ++ "aux", ++ "ahb"; ++ ++ phys = <&pcie0_phy>; ++ phy-names = "pciephy"; ++ interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>, ++ <&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>; ++ interconnect-names = "pcie-mem", "cpu-pcie"; ++ status = "disabled"; ++ }; ++ + }; + + thermal-zones { diff --git a/target/linux/qualcommbe/patches-6.6/023-02-v6.14-arm64-dts-qcom-ipq9574-Enable-PCIe-PHYs-and-controll.patch b/target/linux/qualcommbe/patches-6.6/023-02-v6.14-arm64-dts-qcom-ipq9574-Enable-PCIe-PHYs-and-controll.patch new file mode 100644 index 00000000000..d7b159ae27b --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/023-02-v6.14-arm64-dts-qcom-ipq9574-Enable-PCIe-PHYs-and-controll.patch @@ -0,0 +1,152 @@ +From 438d05fb9be6bcd565e713c7e8d9ffb97e5f8d1e Mon Sep 17 00:00:00 2001 +From: devi priya +Date: Thu, 1 Aug 2024 11:18:02 +0530 +Subject: [PATCH 2/2] arm64: dts: qcom: ipq9574: Enable PCIe PHYs and + controllers + +Enable the PCIe controller and PHY nodes corresponding to RDP 433. + +Signed-off-by: devi priya +Signed-off-by: Sricharan Ramabadhran +Link: https://lore.kernel.org/r/20240801054803.3015572-4-quic_srichara@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 113 ++++++++++++++++++++ + 1 file changed, 113 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +@@ -8,6 +8,7 @@ + + /dts-v1/; + ++#include + #include "ipq9574-rdp-common.dtsi" + + / { +@@ -15,6 +16,45 @@ + compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; + }; + ++&pcie1_phy { ++ status = "okay"; ++}; ++ ++&pcie1 { ++ pinctrl-0 = <&pcie1_default>; ++ pinctrl-names = "default"; ++ ++ perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; ++ wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ ++&pcie2_phy { ++ status = "okay"; ++}; ++ ++&pcie2 { ++ pinctrl-0 = <&pcie2_default>; ++ pinctrl-names = "default"; ++ ++ perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; ++ wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ ++&pcie3_phy { ++ status = "okay"; ++}; ++ ++&pcie3 { ++ pinctrl-0 = <&pcie3_default>; ++ pinctrl-names = "default"; ++ ++ perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; ++ wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ + &sdhc_1 { + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; +@@ -28,6 +68,79 @@ + }; + + &tlmm { ++ ++ pcie1_default: pcie1-default-state { ++ clkreq-n-pins { ++ pins = "gpio25"; ++ function = "pcie1_clk"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ ++ perst-n-pins { ++ pins = "gpio26"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ output-low; ++ }; ++ ++ wake-n-pins { ++ pins = "gpio27"; ++ function = "pcie1_wake"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ }; ++ ++ pcie2_default: pcie2-default-state { ++ clkreq-n-pins { ++ pins = "gpio28"; ++ function = "pcie2_clk"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ ++ perst-n-pins { ++ pins = "gpio29"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ output-low; ++ }; ++ ++ wake-n-pins { ++ pins = "gpio30"; ++ function = "pcie2_wake"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ }; ++ ++ pcie3_default: pcie3-default-state { ++ clkreq-n-pins { ++ pins = "gpio31"; ++ function = "pcie3_clk"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ ++ perst-n-pins { ++ pins = "gpio32"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-up; ++ output-low; ++ }; ++ ++ wake-n-pins { ++ pins = "gpio33"; ++ function = "pcie3_wake"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ }; ++ + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio5"; diff --git a/target/linux/qualcommbe/patches-6.6/101-arm64-dts-qcom-ipq9574-Add-SPI-nand-support.patch b/target/linux/qualcommbe/patches-6.6/101-arm64-dts-qcom-ipq9574-Add-SPI-nand-support.patch index 0b8eac37cbc..4aeb98c4290 100644 --- a/target/linux/qualcommbe/patches-6.6/101-arm64-dts-qcom-ipq9574-Add-SPI-nand-support.patch +++ b/target/linux/qualcommbe/patches-6.6/101-arm64-dts-qcom-ipq9574-Add-SPI-nand-support.patch @@ -56,7 +56,7 @@ Change in [v1] --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts -@@ -59,4 +59,47 @@ +@@ -172,4 +172,47 @@ bias-pull-down; }; }; @@ -106,7 +106,7 @@ Change in [v1] }; --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi -@@ -355,6 +355,33 @@ +@@ -447,6 +447,33 @@ reg = <0x01937000 0x21000>; }; diff --git a/target/linux/qualcommbe/patches-6.6/102-arm64-dts-qcom-ipq9574-Disable-eMMC-node.patch b/target/linux/qualcommbe/patches-6.6/102-arm64-dts-qcom-ipq9574-Disable-eMMC-node.patch index 8e362b8e602..d54dc4cf992 100644 --- a/target/linux/qualcommbe/patches-6.6/102-arm64-dts-qcom-ipq9574-Disable-eMMC-node.patch +++ b/target/linux/qualcommbe/patches-6.6/102-arm64-dts-qcom-ipq9574-Disable-eMMC-node.patch @@ -54,7 +54,7 @@ Change in [v1] --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts -@@ -24,7 +24,7 @@ +@@ -64,7 +64,7 @@ mmc-hs400-enhanced-strobe; max-frequency = <384000000>; bus-width = <8>; diff --git a/target/linux/qualcommbe/patches-6.6/105-06-arm64-dts-qcom-ipq9574-Add-nsscc-node.patch b/target/linux/qualcommbe/patches-6.6/105-06-arm64-dts-qcom-ipq9574-Add-nsscc-node.patch index fd5ed0504bf..3ec23307b03 100644 --- a/target/linux/qualcommbe/patches-6.6/105-06-arm64-dts-qcom-ipq9574-Add-nsscc-node.patch +++ b/target/linux/qualcommbe/patches-6.6/105-06-arm64-dts-qcom-ipq9574-Add-nsscc-node.patch @@ -22,8 +22,8 @@ Signed-off-by: Manikanta Mylavarapu #include / { -@@ -804,6 +806,26 @@ - status = "disabled"; +@@ -198,6 +200,26 @@ + qcom,glink-channels = "rpm_requests"; }; }; + @@ -48,4 +48,4 @@ Signed-off-by: Manikanta Mylavarapu + }; }; - thermal-zones { + reserved-memory { diff --git a/target/linux/qualcommbe/patches-6.6/200-01-arm64-dts-qcom-ipq9574-Add-PCS-UNIPHY-device-tree-su.patch b/target/linux/qualcommbe/patches-6.6/200-01-arm64-dts-qcom-ipq9574-Add-PCS-UNIPHY-device-tree-su.patch index c020957aa77..4d0966d883b 100644 --- a/target/linux/qualcommbe/patches-6.6/200-01-arm64-dts-qcom-ipq9574-Add-PCS-UNIPHY-device-tree-su.patch +++ b/target/linux/qualcommbe/patches-6.6/200-01-arm64-dts-qcom-ipq9574-Add-PCS-UNIPHY-device-tree-su.patch @@ -30,7 +30,7 @@ Signed-off-by: Lei Wei */ #include -@@ -826,6 +826,114 @@ +@@ -220,6 +220,114 @@ #power-domain-cells = <1>; #interconnect-cells = <1>; }; @@ -144,4 +144,4 @@ Signed-off-by: Lei Wei + }; }; - thermal-zones { + reserved-memory { diff --git a/target/linux/qualcommbe/patches-6.6/200-02-arm64-dts-qcom-Add-IPQ9574-MDIO-device-node.patch b/target/linux/qualcommbe/patches-6.6/200-02-arm64-dts-qcom-Add-IPQ9574-MDIO-device-node.patch index ff16521d91a..d41a54810d8 100644 --- a/target/linux/qualcommbe/patches-6.6/200-02-arm64-dts-qcom-Add-IPQ9574-MDIO-device-node.patch +++ b/target/linux/qualcommbe/patches-6.6/200-02-arm64-dts-qcom-Add-IPQ9574-MDIO-device-node.patch @@ -15,7 +15,7 @@ Signed-off-by: Luo Jie --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi -@@ -251,6 +251,8 @@ +@@ -425,6 +425,8 @@ mdio: mdio@90000 { compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio"; reg = <0x00090000 0x64>; @@ -24,7 +24,7 @@ Signed-off-by: Luo Jie #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_MDIO_AHB_CLK>; -@@ -322,6 +324,22 @@ +@@ -542,6 +544,22 @@ interrupt-controller; #interrupt-cells = <2>; diff --git a/target/linux/qualcommbe/patches-6.6/200-03-arm64-dts-qcom-Add-IPQ9574-PPE-base-device-node.patch b/target/linux/qualcommbe/patches-6.6/200-03-arm64-dts-qcom-Add-IPQ9574-PPE-base-device-node.patch index f33bb0ebddf..a99fe0129da 100644 --- a/target/linux/qualcommbe/patches-6.6/200-03-arm64-dts-qcom-Add-IPQ9574-PPE-base-device-node.patch +++ b/target/linux/qualcommbe/patches-6.6/200-03-arm64-dts-qcom-Add-IPQ9574-PPE-base-device-node.patch @@ -15,7 +15,7 @@ Signed-off-by: Luo Jie --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi -@@ -952,6 +952,44 @@ +@@ -328,6 +328,44 @@ "ch_tx"; }; }; @@ -59,4 +59,4 @@ Signed-off-by: Luo Jie + }; }; - thermal-zones { + reserved-memory { diff --git a/target/linux/qualcommbe/patches-6.6/200-04-arm64-dts-qcom-Add-EDMA-node-for-IPQ9574.patch b/target/linux/qualcommbe/patches-6.6/200-04-arm64-dts-qcom-Add-EDMA-node-for-IPQ9574.patch index 8c3a0ac6e44..8b3bdc39f55 100644 --- a/target/linux/qualcommbe/patches-6.6/200-04-arm64-dts-qcom-Add-EDMA-node-for-IPQ9574.patch +++ b/target/linux/qualcommbe/patches-6.6/200-04-arm64-dts-qcom-Add-EDMA-node-for-IPQ9574.patch @@ -14,7 +14,7 @@ Signed-off-by: Pavithra R --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi -@@ -989,6 +989,74 @@ +@@ -365,6 +365,74 @@ "nssnoc_memnoc", "memnoc_nssnoc", "memnoc_nssnoc_1"; diff --git a/target/linux/qualcommbe/patches-6.6/200-05-arm64-dts-qcom-Add-IPQ9574-RDP433-port-node.patch b/target/linux/qualcommbe/patches-6.6/200-05-arm64-dts-qcom-Add-IPQ9574-RDP433-port-node.patch index d48b34293db..5b093003d17 100644 --- a/target/linux/qualcommbe/patches-6.6/200-05-arm64-dts-qcom-Add-IPQ9574-RDP433-port-node.patch +++ b/target/linux/qualcommbe/patches-6.6/200-05-arm64-dts-qcom-Add-IPQ9574-RDP433-port-node.patch @@ -18,23 +18,8 @@ Signed-off-by: Lei Wei --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts -@@ -3,11 +3,13 @@ - * IPQ9574 RDP433 board device tree source - * - * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. -- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. -+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. - */ - - /dts-v1/; - -+#include -+ - #include "ipq9574-rdp-common.dtsi" - - / { -@@ -15,6 +17,46 @@ - compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; +@@ -55,6 +55,46 @@ + status = "okay"; }; +&mdio { @@ -80,7 +65,7 @@ Signed-off-by: Lei Wei &sdhc_1 { pinctrl-0 = <&sdc_default_state>; pinctrl-names = "default"; -@@ -103,3 +145,130 @@ +@@ -216,3 +256,130 @@ nand-ecc-step-size = <512>; }; }; @@ -213,7 +198,7 @@ Signed-off-by: Lei Wei +}; --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi -@@ -953,7 +953,7 @@ +@@ -329,7 +329,7 @@ }; }; diff --git a/target/linux/qualcommbe/patches-6.6/302-arm64-dts-qcom-Add-missing-clock-for-nsscc-from-pcs-.patch b/target/linux/qualcommbe/patches-6.6/302-arm64-dts-qcom-Add-missing-clock-for-nsscc-from-pcs-.patch index c7b7ea14b68..111b71d401d 100644 --- a/target/linux/qualcommbe/patches-6.6/302-arm64-dts-qcom-Add-missing-clock-for-nsscc-from-pcs-.patch +++ b/target/linux/qualcommbe/patches-6.6/302-arm64-dts-qcom-Add-missing-clock-for-nsscc-from-pcs-.patch @@ -21,7 +21,7 @@ Signed-off-by: Christian Marangi #include / { -@@ -832,12 +833,12 @@ +@@ -208,12 +209,12 @@ <&cmn_pll NSS_1200MHZ_CLK>, <&cmn_pll PPE_353MHZ_CLK>, <&gcc GPLL0_OUT_AUX>, diff --git a/target/linux/qualcommbe/patches-6.6/304-dts-qcom-add-AQR-NVMEM-node-for-IPQ9574-RDP433-board.patch b/target/linux/qualcommbe/patches-6.6/304-dts-qcom-add-AQR-NVMEM-node-for-IPQ9574-RDP433-board.patch index 4de13b73ab6..f897bc8992c 100644 --- a/target/linux/qualcommbe/patches-6.6/304-dts-qcom-add-AQR-NVMEM-node-for-IPQ9574-RDP433-board.patch +++ b/target/linux/qualcommbe/patches-6.6/304-dts-qcom-add-AQR-NVMEM-node-for-IPQ9574-RDP433-board.patch @@ -13,7 +13,7 @@ Signed-off-by: Christian Marangi --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts -@@ -49,11 +49,17 @@ +@@ -87,11 +87,17 @@ phy4: ethernet-phy@8 { compatible ="ethernet-phy-ieee802.3-c45"; reg = <8>; diff --git a/target/linux/qualcommbe/patches-6.6/900-arm64-dts-qcom-Add-label-to-EDMA-port-for-IPQ9574-RD.patch b/target/linux/qualcommbe/patches-6.6/900-arm64-dts-qcom-Add-label-to-EDMA-port-for-IPQ9574-RD.patch index f8c95d28d68..ab4a59469af 100644 --- a/target/linux/qualcommbe/patches-6.6/900-arm64-dts-qcom-Add-label-to-EDMA-port-for-IPQ9574-RD.patch +++ b/target/linux/qualcommbe/patches-6.6/900-arm64-dts-qcom-Add-label-to-EDMA-port-for-IPQ9574-RD.patch @@ -12,7 +12,7 @@ Signed-off-by: Christian Marangi --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts -@@ -161,6 +161,7 @@ +@@ -272,6 +272,7 @@ reg = <1>; phy-mode = "qsgmii"; managed = "in-band-status"; @@ -20,7 +20,7 @@ Signed-off-by: Christian Marangi phy-handle = <&phy0>; pcs-handle = <&pcsuniphy0_ch0>; clocks = <&nsscc NSS_CC_PORT1_MAC_CLK>, -@@ -181,6 +182,7 @@ +@@ -292,6 +293,7 @@ reg = <2>; phy-mode = "qsgmii"; managed = "in-band-status"; @@ -28,7 +28,7 @@ Signed-off-by: Christian Marangi phy-handle = <&phy1>; pcs-handle = <&pcsuniphy0_ch1>; clocks = <&nsscc NSS_CC_PORT2_MAC_CLK>, -@@ -201,6 +203,7 @@ +@@ -312,6 +314,7 @@ reg = <3>; phy-mode = "qsgmii"; managed = "in-band-status"; @@ -36,7 +36,7 @@ Signed-off-by: Christian Marangi phy-handle = <&phy2>; pcs-handle = <&pcsuniphy0_ch2>; clocks = <&nsscc NSS_CC_PORT3_MAC_CLK>, -@@ -221,6 +224,7 @@ +@@ -332,6 +335,7 @@ reg = <4>; phy-mode = "qsgmii"; managed = "in-band-status"; @@ -44,7 +44,7 @@ Signed-off-by: Christian Marangi phy-handle = <&phy3>; pcs-handle = <&pcsuniphy0_ch3>; clocks = <&nsscc NSS_CC_PORT4_MAC_CLK>, -@@ -241,6 +245,7 @@ +@@ -352,6 +356,7 @@ reg = <5>; phy-mode = "usxgmii"; managed = "in-band-status"; @@ -52,7 +52,7 @@ Signed-off-by: Christian Marangi phy-handle = <&phy4>; pcs-handle = <&pcsuniphy1_ch0>; clocks = <&nsscc NSS_CC_PORT5_MAC_CLK>, -@@ -261,6 +266,7 @@ +@@ -372,6 +377,7 @@ reg = <6>; phy-mode = "usxgmii"; managed = "in-band-status";