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ramips: add proper system clock and reset driver support for mt7621
This series of upstream patches makes the system controller node as a reset provider[1][2], and it also includes some clock and reset driver fixes[3][4]. Meanwhile, all clocks and resets properties in the SoC device tree have been updated to be compatible with the new driver. [1] https://lore.kernel.org/r/20220110114930.1406665-2-sergio.paracuellos@gmail.com [2] https://lore.kernel.org/r/20220210094859.927868-2-sergio.paracuellos@gmail.com [3] https://lore.kernel.org/r/20221217074806.3225150-1-sergio.paracuellos@gmail.com [4] https://lore.kernel.org/r/20230206083305.147582-1-sergio.paracuellos@gmail.com Tested on RAISECOM MSG1500 X.00 Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au> Signed-off-by: Shiji Yang <yangshiji66@qq.com>
This commit is contained in:
Shiji Yang
Nick Hainke
parent
df47decd60
commit
8cacf2bda8
@ -1,8 +1,9 @@
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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#include <dt-bindings/clock/mt7621-clk.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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#include <dt-bindings/reset/mt7621-reset.h>
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/ {
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#address-cells = <1>;
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@ -41,14 +42,6 @@
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bootargs = "console=ttyS0,57600";
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};
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sysclock: sysclock {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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/* FIXME: there should be way to detect this */
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clock-frequency = <50000000>;
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};
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palmbus: palmbus@1e000000 {
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compatible = "palmbus";
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reg = <0x1e000000 0x100000>;
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@ -60,6 +53,7 @@
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sysc: syscon@0 {
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compatible = "mediatek,mt7621-sysc", "syscon";
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#clock-cells = <1>;
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#reset-cells = <1>;
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ralink,memctl = <&memc>;
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clock-output-names = "xtal", "cpu", "bus",
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"50m", "125m", "150m",
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@ -88,9 +82,10 @@
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compatible = "mediatek,mt7621-i2c";
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reg = <0x900 0x100>;
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clocks = <&sysclock>;
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clocks = <&sysc MT7621_CLK_I2C>;
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clock-names = "i2c";
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resets = <&rstctrl 16>;
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resets = <&sysc MT7621_RST_I2C>;
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reset-names = "i2c";
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#address-cells = <1>;
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@ -106,9 +101,9 @@
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compatible = "mediatek,mt7621-i2s";
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reg = <0xa00 0x100>;
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clocks = <&sysclock>;
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clocks = <&sysc MT7621_CLK_I2S>;
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resets = <&rstctrl 17>;
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resets = <&sysc MT7621_RST_I2S>;
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reset-names = "i2s";
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interrupt-parent = <&gic>;
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@ -128,14 +123,14 @@
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compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
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reg = <0x500 0x10>;
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resets = <&rstctrl 28>;
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resets = <&sysc MT7621_RST_AUX_STCK>;
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reset-names = "intc";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
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};
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memc: syscon@5000 {
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memc: memory-controller@5000 {
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compatible = "mediatek,mt7621-memc", "syscon";
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reg = <0x5000 0x1000>;
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};
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@ -144,7 +139,9 @@
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compatible = "ns16550a";
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reg = <0xc00 0x100>;
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clock-frequency = <50000000>;
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clocks = <&sysc MT7621_CLK_UART1>;
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resets = <&sysc MT7621_RST_UART1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
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@ -158,7 +155,9 @@
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compatible = "ns16550a";
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reg = <0xd00 0x100>;
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clock-frequency = <50000000>;
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clocks = <&sysc MT7621_CLK_UART2>;
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resets = <&sysc MT7621_RST_UART2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
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@ -176,7 +175,9 @@
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compatible = "ns16550a";
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reg = <0xe00 0x100>;
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clock-frequency = <50000000>;
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clocks = <&sysc MT7621_CLK_UART3>;
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resets = <&sysc MT7621_RST_UART3>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
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@ -196,9 +197,10 @@
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compatible = "ralink,mt7621-spi";
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reg = <0xb00 0x100>;
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clocks = <&sysc MT7621_CLK_BUS>;
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clocks = <&sysc MT7621_CLK_SPI>;
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clock-names = "spi";
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resets = <&rstctrl 18>;
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resets = <&sysc MT7621_RST_SPI>;
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reset-names = "spi";
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#address-cells = <1>;
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@ -212,7 +214,7 @@
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compatible = "ralink,rt3883-gdma";
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reg = <0x2800 0x800>;
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resets = <&rstctrl 14>;
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resets = <&sysc MT7621_RST_GDMA>;
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reset-names = "dma";
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interrupt-parent = <&gic>;
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@ -229,7 +231,7 @@
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compatible = "mediatek,mt7621-hsdma";
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reg = <0x7000 0x1000>;
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resets = <&rstctrl 5>;
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resets = <&sysc MT7621_RST_HSDMA>;
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reset-names = "hsdma";
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interrupt-parent = <&gic>;
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@ -334,16 +336,6 @@
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};
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};
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rstctrl: rstctrl {
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compatible = "ralink,rt2880-reset";
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#reset-cells = <1>;
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};
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clkctrl: clkctrl {
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compatible = "ralink,rt2880-clock";
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#clock-cells = <1>;
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};
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sdhci: sdhci@1e130000 {
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status = "disabled";
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@ -366,7 +358,7 @@
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0x1e1d0700 0x0100>;
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reg-names = "mac", "ippc";
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clocks = <&sysclock>;
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clocks = <&sysc MT7621_CLK_XTAL>;
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clock-names = "sys_ck";
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interrupt-parent = <&gic>;
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@ -408,13 +400,6 @@
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};
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};
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nficlock: nficlock {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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};
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cpc: cpc@1fbf0000 {
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compatible = "mti,mips-cpc";
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reg = <0x1fbf0000 0x8000>;
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@ -433,7 +418,7 @@
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0x1e003800 0x800>;
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reg-names = "nfi", "ecc";
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clocks = <&nficlock>;
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clocks = <&sysc MT7621_CLK_NAND>;
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clock-names = "nfi_clk";
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};
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@ -441,14 +426,13 @@
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compatible = "mediatek,mt7621-eth";
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reg = <0x1e100000 0x10000>;
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clocks = <&sysc MT7621_CLK_FE>,
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<&sysc MT7621_CLK_ETH>;
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clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>;
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clock-names = "fe", "ethif";
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#address-cells = <1>;
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#size-cells = <0>;
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resets = <&rstctrl 6>, <&rstctrl 23>;
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resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>;
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reset-names = "fe", "eth";
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interrupt-parent = <&gic>;
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@ -486,7 +470,7 @@
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compatible = "mediatek,mt7621";
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reg = <0x1f>;
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mediatek,mcm;
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resets = <&rstctrl 2>;
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resets = <&sysc MT7621_RST_MCM>;
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reset-names = "mcm";
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interrupt-controller;
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#interrupt-cells = <1>;
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@ -578,7 +562,7 @@
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rstctrl 24>;
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resets = <&sysc MT7621_RST_PCIE0>;
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clocks = <&sysc MT7621_CLK_PCIE0>;
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phys = <&pcie0_phy 1>;
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phy-names = "pcie-phy0";
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@ -593,7 +577,7 @@
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rstctrl 25>;
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resets = <&sysc MT7621_RST_PCIE1>;
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clocks = <&sysc MT7621_CLK_PCIE1>;
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phys = <&pcie0_phy 1>;
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phy-names = "pcie-phy1";
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@ -608,7 +592,7 @@
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rstctrl 26>;
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resets = <&sysc MT7621_RST_PCIE2>;
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clocks = <&sysc MT7621_CLK_PCIE2>;
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phys = <&pcie2_phy 0>;
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phy-names = "pcie-phy2";
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@ -0,0 +1,60 @@
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From f383b0770612838e78986231710c0a3afee4db42 Mon Sep 17 00:00:00 2001
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From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Date: Mon, 10 Jan 2022 12:49:27 +0100
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Subject: [PATCH 1/2] dt-bindings: reset: add dt binding header for Mediatek MT7621 resets
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Add dt binding header for resets lines in Mediatek MT7621 SoCs.
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Acked-by: Rob Herring <robh@kernel.org>
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Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
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Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Link: https://lore.kernel.org/r/20220110114930.1406665-2-sergio.paracuellos@gmail.com
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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include/dt-bindings/reset/mt7621-reset.h | 37 ++++++++++++++++++++++++++++++++
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1 file changed, 37 insertions(+)
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create mode 100644 include/dt-bindings/reset/mt7621-reset.h
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--- /dev/null
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+++ b/include/dt-bindings/reset/mt7621-reset.h
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@@ -0,0 +1,37 @@
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+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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+/*
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+ * Copyright (c) 2021 Sergio Paracuellos
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+ * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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+ */
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+
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+#ifndef DT_BINDING_MT7621_RESET_H
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+#define DT_BINDING_MT7621_RESET_H
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+
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+#define MT7621_RST_SYS 0
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+#define MT7621_RST_MCM 2
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+#define MT7621_RST_HSDMA 5
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+#define MT7621_RST_FE 6
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+#define MT7621_RST_SPDIFTX 7
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+#define MT7621_RST_TIMER 8
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+#define MT7621_RST_INT 9
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+#define MT7621_RST_MC 10
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+#define MT7621_RST_PCM 11
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+#define MT7621_RST_PIO 13
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+#define MT7621_RST_GDMA 14
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+#define MT7621_RST_NFI 15
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+#define MT7621_RST_I2C 16
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+#define MT7621_RST_I2S 17
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+#define MT7621_RST_SPI 18
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+#define MT7621_RST_UART1 19
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+#define MT7621_RST_UART2 20
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+#define MT7621_RST_UART3 21
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+#define MT7621_RST_ETH 23
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+#define MT7621_RST_PCIE0 24
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+#define MT7621_RST_PCIE1 25
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+#define MT7621_RST_PCIE2 26
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+#define MT7621_RST_AUX_STCK 28
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+#define MT7621_RST_CRYPTO 29
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+#define MT7621_RST_SDXC 30
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+#define MT7621_RST_PPE 31
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+
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+#endif /* DT_BINDING_MT7621_RESET_H */
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@ -0,0 +1,114 @@
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From 64b2d6ffff862c0e7278198b4229e42e1abb3bb1 Mon Sep 17 00:00:00 2001
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From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Date: Mon, 10 Jan 2022 12:49:30 +0100
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Subject: [PATCH 2/2] staging: mt7621-dts: align resets with binding documentation
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Binding documentation for compatible 'mediatek,mt7621-sysc' has been updated
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to be used as a reset provider. Align reset related bits and system controller
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node with binding documentation along the dtsi file.
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Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
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Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
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Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Link: https://lore.kernel.org/r/20220110114930.1406665-5-sergio.paracuellos@gmail.com
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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drivers/staging/mt7621-dts/mt7621.dtsi | 21 +++++++++------------
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1 file changed, 9 insertions(+), 12 deletions(-)
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--- a/drivers/staging/mt7621-dts/mt7621.dtsi
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+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
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@@ -1,6 +1,7 @@
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/mt7621-clk.h>
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+#include <dt-bindings/reset/mt7621-reset.h>
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/ {
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#address-cells = <1>;
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@@ -59,6 +60,7 @@
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compatible = "mediatek,mt7621-sysc", "syscon";
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reg = <0x0 0x100>;
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#clock-cells = <1>;
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+ #reset-cells = <1>;
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ralink,memctl = <&memc>;
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clock-output-names = "xtal", "cpu", "bus",
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"50m", "125m", "150m",
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@@ -88,7 +90,7 @@
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clocks = <&sysc MT7621_CLK_I2C>;
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clock-names = "i2c";
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- resets = <&rstctrl 16>;
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+ resets = <&sysc MT7621_RST_I2C>;
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reset-names = "i2c";
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#address-cells = <1>;
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@@ -161,7 +163,7 @@
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clocks = <&sysc MT7621_CLK_SPI>;
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clock-names = "spi";
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- resets = <&rstctrl 18>;
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+ resets = <&sysc MT7621_RST_SPI>;
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reset-names = "spi";
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#address-cells = <1>;
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@@ -296,11 +298,6 @@
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};
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};
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- rstctrl: rstctrl {
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- compatible = "ralink,rt2880-reset";
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- #reset-cells = <1>;
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- };
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-
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sdhci: sdhci@1e130000 {
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status = "disabled";
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@@ -383,7 +380,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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- resets = <&rstctrl 6 &rstctrl 23>;
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+ resets = <&sysc MT7621_RST_FE &sysc MT7621_RST_ETH>;
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reset-names = "fe", "eth";
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interrupt-parent = <&gic>;
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@@ -423,7 +420,7 @@
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#size-cells = <0>;
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reg = <0>;
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mediatek,mcm;
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- resets = <&rstctrl 2>;
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+ resets = <&sysc MT7621_RST_MCM>;
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reset-names = "mcm";
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interrupt-controller;
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#interrupt-cells = <1>;
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@@ -516,7 +513,7 @@
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
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- resets = <&rstctrl 24>;
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+ resets = <&sysc MT7621_RST_PCIE0>;
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clocks = <&sysc MT7621_CLK_PCIE0>;
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phys = <&pcie0_phy 1>;
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phy-names = "pcie-phy0";
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@@ -531,7 +528,7 @@
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
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- resets = <&rstctrl 25>;
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+ resets = <&sysc MT7621_RST_PCIE1>;
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clocks = <&sysc MT7621_CLK_PCIE1>;
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phys = <&pcie0_phy 1>;
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phy-names = "pcie-phy1";
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||||
@@ -546,7 +543,7 @@
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- resets = <&rstctrl 26>;
|
||||
+ resets = <&sysc MT7621_RST_PCIE2>;
|
||||
clocks = <&sysc MT7621_CLK_PCIE2>;
|
||||
phys = <&pcie2_phy 0>;
|
||||
phy-names = "pcie-phy2";
|
||||
@ -0,0 +1,52 @@
|
||||
From 478b09fa2c00cbc40d25bc061befdf11f04a27ad Mon Sep 17 00:00:00 2001
|
||||
From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
|
||||
Date: Thu, 10 Feb 2022 10:48:58 +0100
|
||||
Subject: [PATCH 1/2] dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property
|
||||
|
||||
Make system controller a reset provider for all the peripherals in the
|
||||
MT7621 SoC adding '#reset-cells' property.
|
||||
|
||||
Acked-by: Rob Herring <robh@kernel.org>
|
||||
Acked-by: Stephen Boyd <sboyd@kernel.org>
|
||||
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220210094859.927868-2-sergio.paracuellos@gmail.com
|
||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
---
|
||||
.../devicetree/bindings/clock/mediatek,mt7621-sysc.yaml | 12 ++++++++++++
|
||||
1 file changed, 12 insertions(+)
|
||||
|
||||
--- a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
|
||||
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
|
||||
@@ -22,6 +22,11 @@ description: |
|
||||
|
||||
The clocks are provided inside a system controller node.
|
||||
|
||||
+ This node is also a reset provider for all the peripherals.
|
||||
+
|
||||
+ Reset related bits are defined in:
|
||||
+ [2]: <include/dt-bindings/reset/mt7621-reset.h>.
|
||||
+
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
@@ -37,6 +42,12 @@ properties:
|
||||
clocks.
|
||||
const: 1
|
||||
|
||||
+ "#reset-cells":
|
||||
+ description:
|
||||
+ The first cell indicates the reset bit within the register, see
|
||||
+ [2] for available resets.
|
||||
+ const: 1
|
||||
+
|
||||
ralink,memctl:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
@@ -61,6 +72,7 @@ examples:
|
||||
compatible = "mediatek,mt7621-sysc", "syscon";
|
||||
reg = <0x0 0x100>;
|
||||
#clock-cells = <1>;
|
||||
+ #reset-cells = <1>;
|
||||
ralink,memctl = <&memc>;
|
||||
clock-output-names = "xtal", "cpu", "bus",
|
||||
"50m", "125m", "150m",
|
||||
@ -0,0 +1,148 @@
|
||||
From 38a8553b0a22ed54f014d8402fedd268b529175c Mon Sep 17 00:00:00 2001
|
||||
From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
|
||||
Date: Thu, 10 Feb 2022 10:48:59 +0100
|
||||
Subject: [PATCH 2/2] clk: ralink: make system controller node a reset provider
|
||||
|
||||
MT7621 system controller node is already providing the clocks for the whole
|
||||
system but must also serve as a reset provider. Hence, add reset controller
|
||||
related code to the clock driver itself. To get resets properly ready for
|
||||
the rest of the world we need to move platform driver initialization process
|
||||
to 'arch_initcall'.
|
||||
|
||||
CC: Philipp Zabel <p.zabel@pengutronix.de>
|
||||
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
|
||||
Acked-by: Stephen Boyd <sboyd@kernel.org>
|
||||
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220210094859.927868-3-sergio.paracuellos@gmail.com
|
||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
---
|
||||
drivers/clk/ralink/clk-mt7621.c | 92 ++++++++++++++++++++++++++++++++++++++++-
|
||||
1 file changed, 91 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/clk/ralink/clk-mt7621.c
|
||||
+++ b/drivers/clk/ralink/clk-mt7621.c
|
||||
@@ -11,14 +11,17 @@
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
+#include <linux/reset-controller.h>
|
||||
#include <linux/slab.h>
|
||||
#include <dt-bindings/clock/mt7621-clk.h>
|
||||
+#include <dt-bindings/reset/mt7621-reset.h>
|
||||
|
||||
/* Configuration registers */
|
||||
#define SYSC_REG_SYSTEM_CONFIG0 0x10
|
||||
#define SYSC_REG_SYSTEM_CONFIG1 0x14
|
||||
#define SYSC_REG_CLKCFG0 0x2c
|
||||
#define SYSC_REG_CLKCFG1 0x30
|
||||
+#define SYSC_REG_RESET_CTRL 0x34
|
||||
#define SYSC_REG_CUR_CLK_STS 0x44
|
||||
#define MEMC_REG_CPU_PLL 0x648
|
||||
|
||||
@@ -398,6 +401,82 @@ free_clk_priv:
|
||||
}
|
||||
CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init);
|
||||
|
||||
+struct mt7621_rst {
|
||||
+ struct reset_controller_dev rcdev;
|
||||
+ struct regmap *sysc;
|
||||
+};
|
||||
+
|
||||
+static struct mt7621_rst *to_mt7621_rst(struct reset_controller_dev *dev)
|
||||
+{
|
||||
+ return container_of(dev, struct mt7621_rst, rcdev);
|
||||
+}
|
||||
+
|
||||
+static int mt7621_assert_device(struct reset_controller_dev *rcdev,
|
||||
+ unsigned long id)
|
||||
+{
|
||||
+ struct mt7621_rst *data = to_mt7621_rst(rcdev);
|
||||
+ struct regmap *sysc = data->sysc;
|
||||
+
|
||||
+ return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id));
|
||||
+}
|
||||
+
|
||||
+static int mt7621_deassert_device(struct reset_controller_dev *rcdev,
|
||||
+ unsigned long id)
|
||||
+{
|
||||
+ struct mt7621_rst *data = to_mt7621_rst(rcdev);
|
||||
+ struct regmap *sysc = data->sysc;
|
||||
+
|
||||
+ return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0);
|
||||
+}
|
||||
+
|
||||
+static int mt7621_reset_device(struct reset_controller_dev *rcdev,
|
||||
+ unsigned long id)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = mt7621_assert_device(rcdev, id);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ return mt7621_deassert_device(rcdev, id);
|
||||
+}
|
||||
+
|
||||
+static int mt7621_rst_xlate(struct reset_controller_dev *rcdev,
|
||||
+ const struct of_phandle_args *reset_spec)
|
||||
+{
|
||||
+ unsigned long id = reset_spec->args[0];
|
||||
+
|
||||
+ if (id == MT7621_RST_SYS || id >= rcdev->nr_resets)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ return id;
|
||||
+}
|
||||
+
|
||||
+static const struct reset_control_ops reset_ops = {
|
||||
+ .reset = mt7621_reset_device,
|
||||
+ .assert = mt7621_assert_device,
|
||||
+ .deassert = mt7621_deassert_device
|
||||
+};
|
||||
+
|
||||
+static int mt7621_reset_init(struct device *dev, struct regmap *sysc)
|
||||
+{
|
||||
+ struct mt7621_rst *rst_data;
|
||||
+
|
||||
+ rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
|
||||
+ if (!rst_data)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ rst_data->sysc = sysc;
|
||||
+ rst_data->rcdev.ops = &reset_ops;
|
||||
+ rst_data->rcdev.owner = THIS_MODULE;
|
||||
+ rst_data->rcdev.nr_resets = 32;
|
||||
+ rst_data->rcdev.of_reset_n_cells = 1;
|
||||
+ rst_data->rcdev.of_xlate = mt7621_rst_xlate;
|
||||
+ rst_data->rcdev.of_node = dev_of_node(dev);
|
||||
+
|
||||
+ return devm_reset_controller_register(dev, &rst_data->rcdev);
|
||||
+}
|
||||
+
|
||||
static int mt7621_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
@@ -424,6 +503,12 @@ static int mt7621_clk_probe(struct platf
|
||||
return ret;
|
||||
}
|
||||
|
||||
+ ret = mt7621_reset_init(dev, priv->sysc);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "Could not init reset controller\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
count = ARRAY_SIZE(mt7621_clks_base) +
|
||||
ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates);
|
||||
clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count),
|
||||
@@ -485,4 +570,9 @@ static struct platform_driver mt7621_clk
|
||||
.of_match_table = mt7621_clk_of_match,
|
||||
},
|
||||
};
|
||||
-builtin_platform_driver(mt7621_clk_driver);
|
||||
+
|
||||
+static int __init mt7621_clk_reset_init(void)
|
||||
+{
|
||||
+ return platform_driver_register(&mt7621_clk_driver);
|
||||
+}
|
||||
+arch_initcall(mt7621_clk_reset_init);
|
||||
@ -0,0 +1,43 @@
|
||||
From bb3ababe7f986900672e0048153c31aa4a21f96b Mon Sep 17 00:00:00 2001
|
||||
From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
|
||||
Date: Sat, 17 Dec 2022 08:48:06 +0100
|
||||
Subject: [PATCH] MIPS: ralink: mt7621: avoid to init common ralink reset controller
|
||||
|
||||
[ Upstream commit 76ce51798cb16738a4a28a6662e7344aaf7ef769 ]
|
||||
|
||||
Commit 38a8553b0a22 ("clk: ralink: make system controller node a reset provider")
|
||||
make system controller a reset provider for mt7621 ralink SoCs. Ralink init code
|
||||
also tries to start previous common reset controller which at the end tries to
|
||||
find device tree node 'ralink,rt2880-reset'. mt7621 device tree file is not
|
||||
using at all this node anymore. Hence avoid to init this common reset controller
|
||||
for mt7621 ralink SoCs to avoid 'Failed to find reset controller node' boot
|
||||
error trace error.
|
||||
|
||||
Fixes: 64b2d6ffff86 ("staging: mt7621-dts: align resets with binding documentation")
|
||||
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
|
||||
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
|
||||
Signed-off-by: Sasha Levin <sashal@kernel.org>
|
||||
---
|
||||
arch/mips/ralink/of.c | 4 +++-
|
||||
1 file changed, 3 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/mips/ralink/of.c
|
||||
+++ b/arch/mips/ralink/of.c
|
||||
@@ -21,6 +21,7 @@
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/prom.h>
|
||||
+#include <asm/mach-ralink/ralink_regs.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
@@ -95,7 +96,8 @@ static int __init plat_of_setup(void)
|
||||
__dt_register_buses(soc_info.compatible, "palmbus");
|
||||
|
||||
/* make sure that the reset controller is setup early */
|
||||
- ralink_rst_init();
|
||||
+ if (ralink_soc != MT762X_SOC_MT7621AT)
|
||||
+ ralink_rst_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -0,0 +1,77 @@
|
||||
From 35dcae535afc153fa83f2fe51c0812536c192c58 Mon Sep 17 00:00:00 2001
|
||||
From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
|
||||
Date: Mon, 6 Feb 2023 09:33:05 +0100
|
||||
Subject: [PATCH] clk: ralink: fix 'mt7621_gate_is_enabled()' function
|
||||
|
||||
Compiling clock driver with CONFIG_UBSAN enabled shows the following trace:
|
||||
|
||||
UBSAN: shift-out-of-bounds in drivers/clk/ralink/clk-mt7621.c:121:15
|
||||
shift exponent 131072 is too large for 32-bit type 'long unsigned int'
|
||||
CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.15.86 #0
|
||||
Stack : ...
|
||||
|
||||
Call Trace:
|
||||
[<80009a58>] show_stack+0x38/0x118
|
||||
[<8045ce04>] dump_stack_lvl+0x60/0x80
|
||||
[<80458868>] ubsan_epilogue+0x10/0x54
|
||||
[<804590e0>] __ubsan_handle_shift_out_of_bounds+0x118/0x190
|
||||
[<804c9a10>] mt7621_gate_is_enabled+0x98/0xa0
|
||||
[<804bb774>] clk_core_is_enabled+0x34/0x90
|
||||
[<80aad73c>] clk_disable_unused_subtree+0x98/0x1e4
|
||||
[<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4
|
||||
[<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4
|
||||
[<80aad900>] clk_disable_unused+0x78/0x120
|
||||
[<80002030>] do_one_initcall+0x54/0x1f0
|
||||
[<80a922a4>] kernel_init_freeable+0x280/0x31c
|
||||
[<808047c4>] kernel_init+0x20/0x118
|
||||
[<80003e58>] ret_from_kernel_thread+0x14/0x1c
|
||||
|
||||
Shifting a value (131032) larger than the type (32 bit unsigned integer)
|
||||
is undefined behaviour in C.
|
||||
|
||||
The problem is in 'mt7621_gate_is_enabled()' function which is using the
|
||||
'BIT()' kernel macro with the bit index for the clock gate to check if the
|
||||
bit is set. When the clock gates structure is created driver is already
|
||||
setting 'bit_idx' using 'BIT()' macro, so we are wrongly applying an extra
|
||||
'BIT()' mask here. Removing it solve the problem and makes this function
|
||||
correct. However when clock gating is correctly working, the kernel starts
|
||||
disabling those clocks that are not requested. Some drivers for this SoC
|
||||
are older than this clock driver itself. So to avoid the kernel to disable
|
||||
clocks that have been enabled until now, we must apply 'CLK_IS_CRITICAL'
|
||||
flag on gates initialization code.
|
||||
|
||||
Fixes: 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")
|
||||
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230206083305.147582-1-sergio.paracuellos@gmail.com
|
||||
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
||||
---
|
||||
drivers/clk/ralink/clk-mt7621.c | 10 ++++++++--
|
||||
1 file changed, 8 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/clk/ralink/clk-mt7621.c
|
||||
+++ b/drivers/clk/ralink/clk-mt7621.c
|
||||
@@ -121,7 +121,7 @@ static int mt7621_gate_is_enabled(struct
|
||||
if (regmap_read(sysc, SYSC_REG_CLKCFG1, &val))
|
||||
return 0;
|
||||
|
||||
- return val & BIT(clk_gate->bit_idx);
|
||||
+ return val & clk_gate->bit_idx;
|
||||
}
|
||||
|
||||
static const struct clk_ops mt7621_gate_ops = {
|
||||
@@ -133,8 +133,14 @@ static const struct clk_ops mt7621_gate_
|
||||
static int mt7621_gate_ops_init(struct device *dev,
|
||||
struct mt7621_gate *sclk)
|
||||
{
|
||||
+ /*
|
||||
+ * There are drivers for this SoC that are older
|
||||
+ * than clock driver and are not prepared for the clock.
|
||||
+ * We don't want the kernel to disable anything so we
|
||||
+ * add CLK_IS_CRITICAL flag here.
|
||||
+ */
|
||||
struct clk_init_data init = {
|
||||
- .flags = CLK_SET_RATE_PARENT,
|
||||
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
|
||||
.num_parents = 1,
|
||||
.parent_names = &sclk->parent_name,
|
||||
.ops = &mt7621_gate_ops,
|
||||
Loading…
Reference in New Issue
Block a user