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ipq40xx: fix ethernet vlan double tagging
As the the SoC uses implicit vlan tagging for dual MAC support, the
offload feature breaks when using double tagging.
This is backport of 9da2b56760 from trunk.
As the layout of the files has changed a cherry-pick was not possible.
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Signed-off-by: John Crispin <john@phrozen.org>
This commit is contained in:
John Crispin
parent
b9a89bf7b5
commit
8c19171255
@ -0,0 +1,193 @@
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From: Sven Eckelmann <sven@narfation.org>
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Date: Wed, 8 Feb 2017 16:26:00 +0100
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Subject: [PATCH] ipq40xx: Fix ar40xx port separation
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It is currently not possible to submit (or receive) VLAN tagged frames over
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the ar40xx PHY switch and the edma ethernet device.
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This can be worked around by disabling enable_vlan. The separation of the
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eth0 and eth1 ports is then done by the vlan_tag information from the
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device tree. But the ar40xx PHY switch then also has to parse the word3
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port bitmap (word3) from the TDP when data was received from the CPU port
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(0).
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IssueID: #2857
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Forwarded: no
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The ar40xx.c change was forwarded to Xiaofei Shen <xiaofeis@codeaurora.org>
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(QCA). But John Crispin will rewrite the driver anyway and we have to check
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later if this change is required in his driver too.
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---
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drivers/net/phy/ar40xx.c | 6 +++++-
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1 file changed, 5 insertions(+), 1 deletion(-)
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diff --git a/drivers/net/phy/ar40xx.c b/drivers/net/phy/ar40xx.c
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index e408e8f7312f749aeb29c73a589047856e9479c7..421399b9b33e6f42d4e38db3f90b0c1d514a0b79 100644
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--- a/drivers/net/phy/ar40xx.c
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+++ b/drivers/net/phy/ar40xx.c
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@@ -1200,7 +1200,11 @@ ar40xx_init_port(struct ar40xx_priv *priv, int port)
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ar40xx_rmw(priv, AR40XX_REG_PORT_STATUS(port),
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AR40XX_PORT_AUTO_LINK_EN, 0);
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- ar40xx_write(priv, AR40XX_REG_PORT_HEADER(port), 0);
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+ /* CPU port is setting headers to limit output ports */
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+ if (port == 0)
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+ ar40xx_write(priv, AR40XX_REG_PORT_HEADER(port), 0x8);
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+ else
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+ ar40xx_write(priv, AR40XX_REG_PORT_HEADER(port), 0);
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ar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), 0);
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From: Sven Eckelmann <sven@narfation.org>
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Date: Fri, 17 Mar 2017 11:00:40 +0100
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Subject: [PATCH] ipq40xx: Disable CTAG TX VLAN offloading
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The driver requires the offloading to set the VLAN specific header for the
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port selection. It can therefore not be used at the same time to offload
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the setting of the VLAN header on top of essedma interface.
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Forwarded: no
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---
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drivers/net/ethernet/qualcomm/essedma/edma_axi.c | 1 -
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1 file changed, 1 deletion(-)
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diff --git a/drivers/net/ethernet/qualcomm/essedma/edma_axi.c b/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
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index 81fc1e1b64daa41b15f21634ac1f08de0f5822a7..db184b82769f53e1554a1c51c53414ef7cadd7f6 100644
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--- a/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
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+++ b/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
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@@ -970,7 +970,6 @@ static int edma_axi_probe(struct platform_device *pdev)
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edma_netdev[i]->netdev_ops = &edma_axi_netdev_ops;
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edma_netdev[i]->max_mtu = 9000;
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edma_netdev[i]->features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM
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- | NETIF_F_HW_VLAN_CTAG_TX
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| NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_SG |
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NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GRO;
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edma_netdev[i]->hw_features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM |
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From: Sven Eckelmann <sven@narfation.org>
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Date: Fri, 17 Mar 2017 11:04:50 +0100
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Subject: [PATCH] ar40xx: Enable QinQ on the switch
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The switch used in by IPQ40xx is using VLANs by default to select the
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outgoing port. It was therefore not possible to sent or receive 802.1q
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tagged frames over the CPU port. This can be allowed by changing the port
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configuration and lookup configuration.
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The resulting VLAN-tagged frames send or received by the CPU will therefore
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look like QinQ frames. The outer VLAN tag is the port-VLAN of the port from
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which the data was received or towards which the data has to be sent. The
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inner VLAN tag (when it exists) is the VLAN which was configrued on top of
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the ethernet device.
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Forwarded: no
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---
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drivers/net/phy/ar40xx.c | 23 ++++++++++++++++++++---
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drivers/net/phy/ar40xx.h | 5 +++++
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2 files changed, 25 insertions(+), 3 deletions(-)
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diff --git a/drivers/net/phy/ar40xx.c b/drivers/net/phy/ar40xx.c
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index 421399b9b33e6f42d4e38db3f90b0c1d514a0b79..4af26638d542a9ab5ca27454ce557233bcb64575 100644
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--- a/drivers/net/phy/ar40xx.c
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+++ b/drivers/net/phy/ar40xx.c
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@@ -1247,6 +1247,10 @@ ar40xx_init_globals(struct ar40xx_priv *priv)
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t = (AR40XX_PORT0_FC_THRESH_ON_DFLT << 16) |
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AR40XX_PORT0_FC_THRESH_OFF_DFLT;
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ar40xx_write(priv, AR40XX_REG_PORT_FLOWCTRL_THRESH(0), t);
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+
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+ /* set service tag to 802.1q */
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+ t = ETH_P_8021Q | AR40XX_ESS_SERVICE_TAG_STAG;
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+ ar40xx_write(priv, AR40XX_ESS_SERVICE_TAG, t);
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}
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static void
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@@ -1572,7 +1576,11 @@ ar40xx_setup_port(struct ar40xx_priv *priv, int port, u32 members)
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u32 pvid = priv->vlan_id[priv->pvid[port]];
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if (priv->vlan) {
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- egress = AR40XX_PORT_VLAN1_OUT_MODE_UNMOD;
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+ if (priv->vlan_tagged & BIT(port))
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+ egress = AR40XX_PORT_VLAN1_OUT_MODE_TAG;
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+ else
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+ egress = AR40XX_PORT_VLAN1_OUT_MODE_UNMOD;
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+
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ingress = AR40XX_IN_SECURE;
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} else {
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egress = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH;
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@@ -1583,8 +1591,17 @@ ar40xx_setup_port(struct ar40xx_priv *priv, int port, u32 members)
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t |= pvid << AR40XX_PORT_VLAN0_DEF_CVID_S;
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ar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), t);
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- t = AR40XX_PORT_VLAN1_PORT_VLAN_PROP;
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- t |= egress << AR40XX_PORT_VLAN1_OUT_MODE_S;
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+ t = egress << AR40XX_PORT_VLAN1_OUT_MODE_S;
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+
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+ /* set CPU port to core port */
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+ if (port == 0)
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+ t |= AR40XX_PORT_VLAN1_CORE_PORT;
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+
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+ if (priv->vlan_tagged & BIT(port))
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+ t |= AR40XX_PORT_VLAN1_PORT_VLAN_PROP;
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+ else
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+ t |= AR40XX_PORT_VLAN1_PORT_TLS_MODE;
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+
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ar40xx_write(priv, AR40XX_REG_PORT_VLAN1(port), t);
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t = members;
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diff --git a/drivers/net/phy/ar40xx.h b/drivers/net/phy/ar40xx.h
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index 722bf6ae4b32fcefa33e007ae34a3202315a3fe1..7ba40ccf753fe833e6a01b32cfe1407a317d92ee 100644
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--- a/drivers/net/phy/ar40xx.h
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+++ b/drivers/net/phy/ar40xx.h
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@@ -151,6 +151,9 @@ struct ar40xx_mib_desc {
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#define AR40XX_MIB_FUNC_NO_OP 0x0
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#define AR40XX_MIB_FUNC_FLUSH 0x1
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+#define AR40XX_ESS_SERVICE_TAG 0x48
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+#define AR40XX_ESS_SERVICE_TAG_STAG BIT(17)
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+
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#define AR40XX_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
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#define AR40XX_PORT_SPEED BITS(0, 2)
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#define AR40XX_PORT_STATUS_SPEED_S 0
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@@ -179,6 +182,8 @@ struct ar40xx_mib_desc {
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#define AR40XX_PORT_VLAN0_DEF_CVID_S 16
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#define AR40XX_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8)
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+#define AR40XX_PORT_VLAN1_CORE_PORT BIT(9)
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+#define AR40XX_PORT_VLAN1_PORT_TLS_MODE BIT(7)
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#define AR40XX_PORT_VLAN1_PORT_VLAN_PROP BIT(6)
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#define AR40XX_PORT_VLAN1_OUT_MODE BITS(12, 2)
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#define AR40XX_PORT_VLAN1_OUT_MODE_S 12
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From: Sven Eckelmann <sven@narfation.org>
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Date: Wed, 29 Mar 2017 16:05:26 +0200
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Subject: [PATCH] ipq40xx: Disable NETIF_F_RXHASH support in essedma
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The NETIF_F_RXHASH requires that each skb set the hash correctly with
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skb_set_hash. essedma tries to do that but the set hash always results in
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only used CPU when RPS is allowed for all CPUs.
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Disabling RXHASH works around this problem for now.
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IssueID: #5477
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Forwarded: no
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Upstream author was informed via e-mail about the problem
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---
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drivers/net/ethernet/qualcomm/essedma/edma_axi.c | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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diff --git a/drivers/net/ethernet/qualcomm/essedma/edma_axi.c b/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
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index db184b82769f53e1554a1c51c53414ef7cadd7f6..975e119cfe6f1a8cfe54ac0eb8f8752aa4bf22af 100644
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--- a/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
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+++ b/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
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@@ -984,10 +984,10 @@ static int edma_axi_probe(struct platform_device *pdev)
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NETIF_F_GRO;
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#ifdef CONFIG_RFS_ACCEL
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- edma_netdev[i]->features |= NETIF_F_RXHASH | NETIF_F_NTUPLE;
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- edma_netdev[i]->hw_features |= NETIF_F_RXHASH | NETIF_F_NTUPLE;
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- edma_netdev[i]->vlan_features |= NETIF_F_RXHASH | NETIF_F_NTUPLE;
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- edma_netdev[i]->wanted_features |= NETIF_F_RXHASH | NETIF_F_NTUPLE;
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+ edma_netdev[i]->features |= NETIF_F_NTUPLE;
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+ edma_netdev[i]->hw_features |= NETIF_F_NTUPLE;
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+ edma_netdev[i]->vlan_features |= NETIF_F_NTUPLE;
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+ edma_netdev[i]->wanted_features |= NETIF_F_NTUPLE;
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#endif
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edma_set_ethtool_ops(edma_netdev[i]);
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