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uboot-mediatek: add support for arcadyan,mozart
Signed-off-by: John Crispin <john@phrozen.org>
This commit is contained in:
John Crispin
parent
a535cfc09e
commit
88fa1f7b1e
@ -629,6 +629,18 @@ define U-Boot/mt7986_zyxel_ex5601-t0
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DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-4k-ddr4
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endef
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define U-Boot/mt7988_arcadyan_mozart
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NAME:=Arcadyan Mozart
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BUILD_SUBTARGET:=filogic
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BUILD_DEVICES:=arcadyan_mozart
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UBOOT_CONFIG:=mt7988a_arcadyan_mozart
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UBOOT_IMAGE:=u-boot.fip
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BL2_BOOTDEV:=emmc
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BL2_SOC:=mt7988
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BL2_DDRTYPE:=comb
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DEPENDS:=+trusted-firmware-a-mt7988-emmc-comb
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endef
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define U-Boot/mt7988_bananapi_bpi-r4-emmc
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NAME:=BananaPi BPi-R4
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BUILD_SUBTARGET:=filogic
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@ -816,6 +828,7 @@ UBOOT_TARGETS := \
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mt7986_xiaomi_redmi-router-ax6000 \
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mt7986_zyxel_ex5601-t0 \
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mt7986_rfb \
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mt7988_arcadyan_mozart \
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mt7988_bananapi_bpi-r4-emmc \
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mt7988_bananapi_bpi-r4-sdmmc \
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mt7988_bananapi_bpi-r4-snand \
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@ -0,0 +1,308 @@
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--- /dev/null
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+++ b/configs/mt7988a_arcadyan_mozart_defconfig
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@@ -0,0 +1,119 @@
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+CONFIG_ARM=y
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+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
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+CONFIG_POSITION_INDEPENDENT=y
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+CONFIG_ARCH_MEDIATEK=y
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+CONFIG_TEXT_BASE=0x41e00000
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+CONFIG_SYS_MALLOC_F_LEN=0x4000
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+CONFIG_NR_DRAM_BANKS=1
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+CONFIG_ENV_SIZE=0x40000
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+CONFIG_ENV_OFFSET=0x400000
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+CONFIG_DEFAULT_DEVICE_TREE="mt7988a-arcadyan-mozart"
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+CONFIG_OF_LIBFDT_OVERLAY=y
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+CONFIG_TARGET_MT7988=y
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+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
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+CONFIG_DEBUG_UART_BASE=0x11000000
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+CONFIG_DEBUG_UART_CLOCK=40000000
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+CONFIG_ENV_OFFSET_REDUND=0x440000
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+CONFIG_SYS_LOAD_ADDR=0x50000000
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+CONFIG_PCI=y
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+CONFIG_DEBUG_UART=y
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+CONFIG_AHCI=y
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+CONFIG_FIT=y
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+CONFIG_BOOTDELAY=30
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+CONFIG_AUTOBOOT_KEYED=y
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+CONFIG_AUTOBOOT_MENU_SHOW=y
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+CONFIG_OF_SYSTEM_SETUP=y
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+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-arcadyan-mozart.dtb"
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+CONFIG_SYS_CBSIZE=512
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+CONFIG_SYS_PBSIZE=1049
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+CONFIG_LOGLEVEL=7
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+CONFIG_PRE_CONSOLE_BUFFER=y
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+CONFIG_LOG=y
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+CONFIG_BOARD_LATE_INIT=y
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+CONFIG_HUSH_PARSER=y
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+CONFIG_SYS_PROMPT="MT7988> "
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+CONFIG_CMD_CPU=y
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+CONFIG_CMD_LICENSE=y
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+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
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+CONFIG_CMD_BOOTMENU=y
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+CONFIG_CMD_ASKENV=y
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+CONFIG_CMD_ERASEENV=y
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+CONFIG_CMD_ENV_FLAGS=y
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+CONFIG_CMD_STRINGS=y
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+CONFIG_CMD_DM=y
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+CONFIG_CMD_GPIO=y
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+CONFIG_CMD_PWM=y
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+CONFIG_CMD_GPT=y
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+CONFIG_CMD_MMC=y
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+CONFIG_CMD_MTD=y
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+CONFIG_CMD_PART=y
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+CONFIG_CMD_PCI=y
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+CONFIG_CMD_SF_TEST=y
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+CONFIG_CMD_USB=y
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+CONFIG_CMD_DHCP=y
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+CONFIG_CMD_TFTPSRV=y
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+CONFIG_CMD_RARP=y
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+CONFIG_CMD_PING=y
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+CONFIG_CMD_CDP=y
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+CONFIG_CMD_SNTP=y
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+CONFIG_CMD_DNS=y
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+CONFIG_CMD_LINK_LOCAL=y
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+CONFIG_CMD_PXE=y
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+CONFIG_CMD_CACHE=y
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+CONFIG_CMD_PSTORE=y
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+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
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+CONFIG_CMD_UUID=y
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+CONFIG_CMD_HASH=y
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+CONFIG_CMD_SMC=y
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+CONFIG_CMD_EXT4=y
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+CONFIG_CMD_FAT=y
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+CONFIG_CMD_FS_GENERIC=y
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+CONFIG_CMD_FS_UUID=y
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+CONFIG_OF_EMBED=y
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+CONFIG_ENV_OVERWRITE=y
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+CONFIG_ENV_IS_IN_MMC=y
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+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
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+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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+CONFIG_USE_DEFAULT_ENV_FILE=y
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+CONFIG_DEFAULT_ENV_FILE="arcadyan_mozart_env"
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+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
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+CONFIG_VERSION_VARIABLE=y
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+CONFIG_NET_RANDOM_ETHADDR=y
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+CONFIG_NETCONSOLE=y
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+CONFIG_USE_IPADDR=y
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+CONFIG_IPADDR="192.168.1.1"
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+CONFIG_USE_SERVERIP=y
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+CONFIG_SERVERIP="192.168.1.254"
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+CONFIG_REGMAP=y
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+CONFIG_SYSCON=y
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+CONFIG_BUTTON=y
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+CONFIG_BUTTON_GPIO=y
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+CONFIG_CLK=y
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+CONFIG_GPIO_HOG=y
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+CONFIG_LED=y
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+CONFIG_LED_BLINK=y
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+CONFIG_LED_GPIO=y
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+CONFIG_SUPPORT_EMMC_BOOT=y
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+CONFIG_MMC_HS200_SUPPORT=y
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+CONFIG_MMC_MTK=y
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+CONFIG_PHY_FIXED=y
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+CONFIG_MEDIATEK_ETH=y
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+CONFIG_PHY=y
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+CONFIG_PHY_MTK_TPHY=y
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+CONFIG_PINCTRL=y
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+CONFIG_PINCONF=y
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+CONFIG_PINCTRL_MT7988=y
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+CONFIG_POWER_DOMAIN=y
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+CONFIG_MTK_POWER_DOMAIN=y
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+CONFIG_DM_REGULATOR=y
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+CONFIG_DM_REGULATOR_FIXED=y
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+CONFIG_DM_REGULATOR_GPIO=y
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+CONFIG_DM_PWM=y
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+CONFIG_PWM_MTK=y
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+CONFIG_RAM=y
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+CONFIG_SCSI=y
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+CONFIG_DM_SERIAL=y
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+CONFIG_MTK_SERIAL=y
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+CONFIG_ZSTD=y
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+CONFIG_HEXDUMP=y
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+CONFIG_LMB_MAX_REGIONS=64
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--- /dev/null
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+++ b/arcadyan_mozart_env
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@@ -0,0 +1,55 @@
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+ipaddr=192.168.1.1
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+serverip=192.168.1.254
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+loadaddr=0x50000000
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+bootargs=console=ttyS0,115200n1 pci=pcie_bus_perf root=/dev/fit0 rootwait
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+bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi
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+bootconf=config-1
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+bootconf_extra=
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+bootdelay=0
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+bootfile=openwrt-mediatek-filogic-arcadyan_mozart-initramfs.itb
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+bootfile_bl2=openwrt-mediatek-filogic-arcadyan_mozart-emmc-preloader.bin
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+bootfile_fip=openwrt-mediatek-filogic-arcadyan_mozart-emmc-bl31-uboot.fip
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+bootfile_upg=openwrt-mediatek-filogic-arcadyan_mozart-squashfs-sysupgrade.itb
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+bootled_pwr=blue:status
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+bootled_rec=red:status
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+bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
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+bootmenu_default=0
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+bootmenu_delay=0
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+bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) [0;36m[eMMC][0m
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+bootmenu_0=Initialize environment.=run _firstboot
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+bootmenu_0d=Run default boot command.=run boot_default
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+bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
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+bootmenu_2=Boot production system from eMMC.=run boot_production ; run bootmenu_confirm_return
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+bootmenu_3=Boot recovery system from eMMC.=run boot_recovery ; run bootmenu_confirm_return
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+bootmenu_4=Load production system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
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+bootmenu_5=Load recovery system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
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+bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to eMMC.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return
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+bootmenu_7=[31mLoad BL2 preloader via TFTP then write to eMMC.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
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+bootmenu_8=Reboot.=reset
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+bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset
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+boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
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+boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
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+boot_production=led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr#$bootconf#$bootconf_extra ; led $bootled_pwr off
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+boot_recovery=led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr#$bootconf#$bootconf_extra ; led $bootled_rec off
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+boot_emmc=run boot_production ; run boot_recovery
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+boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
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+boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_extra ; fi
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+boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
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+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip
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+boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2
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+boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
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+mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size
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+mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200
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+part_default=production
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+part_recovery=recovery
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+reset_factory=eraseenv && reset
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+emmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol
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+emmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol
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+emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0
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+emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800
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+emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol
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+emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol
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+_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv
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+_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
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+_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
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+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m"
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--- /dev/null
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+++ b/arch/arm/dts/mt7988a-arcadyan-mozart.dts
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@@ -0,0 +1,125 @@
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+// SPDX-License-Identifier: GPL-2.0
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+
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+/dts-v1/;
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+#include "mt7988.dtsi"
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/input/linux-event-codes.h>
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+
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+/ {
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+ model = "MediaTek / Arcadyan - Mozart";
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+ compatible = "arcadyan,mozart", "mediatek,mt7988";
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+
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+ chosen {
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+ stdout-path = &uart0;
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+ };
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+
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+ memory@40000000 {
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+ device_type = "memory";
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+ reg = <0 0x40000000 0 0x40000000>;
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+ };
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+
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+ reg_3p3v: regulator-3p3v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "fixed-3.3V";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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+
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+ reg_1p8v: regulator-1p8v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "fixed-1.8V";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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+
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+ keys {
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+ compatible = "gpio-keys";
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+
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+ wps {
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+ label = "reset";
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+ linux,code = <KEY_RESTART>;
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+ gpios = <&gpio 143 GPIO_ACTIVE_LOW>;
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+ };
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+
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+ led-red {
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+ label = "red:status";
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+ gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ led-green {
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+ label = "blue:status";
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+ gpios = <&gpio 30 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ led-blue {
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+ label = "blue:status";
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+ gpios = <&gpio 31 GPIO_ACTIVE_HIGH>;
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+ };
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+ };
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+};
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+
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+&uart0 {
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+ status = "okay";
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+};
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+
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+ð {
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+ status = "okay";
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+ mediatek,gmac-id = <0>;
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+ phy-mode = "usxgmii";
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+ mediatek,switch = "mt7988";
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+
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ pause;
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+ };
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+};
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+
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+&pinctrl {
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+ mmc0_pins_default: mmc0default {
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+ mux {
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+ function = "flash";
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+ groups = "emmc_51";
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+ };
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+
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+ conf-cmd-dat {
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+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
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+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
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+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
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+ input-enable;
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+ };
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+
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+ conf-clk {
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+ pins = "EMMC_CK";
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+ };
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+
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+ conf-dsl {
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+ pins = "EMMC_DSL";
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+ };
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+
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+ conf-rst {
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+ pins = "EMMC_RSTB";
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+ };
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+ };
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+};
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+
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+&mmc0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&mmc0_pins_default>;
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+ max-frequency = <52000000>;
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+ bus-width = <8>;
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+ cap-mmc-highspeed;
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+ cap-mmc-hw-reset;
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+ vmmc-supply = <®_3p3v>;
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+ vqmmc-supply = <®_1p8v>;
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+ non-removable;
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+ status = "okay";
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+};
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