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ramips: 6.1: mt7621-dma: add hsdma driver to files
Commit 87dd67f496f7 ("staging: mt7621-dma: remove driver from tree")
removed the mt7621-dma driver. Maintain the driver downstream in the
folder of the other mediatek drivers.
Signed-off-by: Nick Hainke <vincent@systemli.org>
This commit is contained in:
Nick Hainke
parent
0dcbe4e931
commit
88d982e3bd
758
target/linux/ramips/files/drivers/dma/mediatek/hsdma-mt7621.c
Normal file
758
target/linux/ramips/files/drivers/dma/mediatek/hsdma-mt7621.c
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@ -0,0 +1,758 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015, Michael Lee <igvtee@gmail.com>
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* MTK HSDMA support
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*/
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/irq.h>
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#include <linux/of_dma.h>
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#include <linux/reset.h>
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#include <linux/of_device.h>
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#include "../virt-dma.h"
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#define HSDMA_BASE_OFFSET 0x800
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#define HSDMA_REG_TX_BASE 0x00
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#define HSDMA_REG_TX_CNT 0x04
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#define HSDMA_REG_TX_CTX 0x08
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#define HSDMA_REG_TX_DTX 0x0c
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#define HSDMA_REG_RX_BASE 0x100
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#define HSDMA_REG_RX_CNT 0x104
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#define HSDMA_REG_RX_CRX 0x108
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#define HSDMA_REG_RX_DRX 0x10c
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#define HSDMA_REG_INFO 0x200
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#define HSDMA_REG_GLO_CFG 0x204
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#define HSDMA_REG_RST_CFG 0x208
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#define HSDMA_REG_DELAY_INT 0x20c
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#define HSDMA_REG_FREEQ_THRES 0x210
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#define HSDMA_REG_INT_STATUS 0x220
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#define HSDMA_REG_INT_MASK 0x228
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#define HSDMA_REG_SCH_Q01 0x280
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#define HSDMA_REG_SCH_Q23 0x284
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#define HSDMA_DESCS_MAX 0xfff
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#define HSDMA_DESCS_NUM 8
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#define HSDMA_DESCS_MASK (HSDMA_DESCS_NUM - 1)
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#define HSDMA_NEXT_DESC(x) (((x) + 1) & HSDMA_DESCS_MASK)
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/* HSDMA_REG_INFO */
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#define HSDMA_INFO_INDEX_MASK 0xf
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#define HSDMA_INFO_INDEX_SHIFT 24
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#define HSDMA_INFO_BASE_MASK 0xff
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#define HSDMA_INFO_BASE_SHIFT 16
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#define HSDMA_INFO_RX_MASK 0xff
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#define HSDMA_INFO_RX_SHIFT 8
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#define HSDMA_INFO_TX_MASK 0xff
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#define HSDMA_INFO_TX_SHIFT 0
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/* HSDMA_REG_GLO_CFG */
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#define HSDMA_GLO_TX_2B_OFFSET BIT(31)
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#define HSDMA_GLO_CLK_GATE BIT(30)
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#define HSDMA_GLO_BYTE_SWAP BIT(29)
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#define HSDMA_GLO_MULTI_DMA BIT(10)
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#define HSDMA_GLO_TWO_BUF BIT(9)
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#define HSDMA_GLO_32B_DESC BIT(8)
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#define HSDMA_GLO_BIG_ENDIAN BIT(7)
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#define HSDMA_GLO_TX_DONE BIT(6)
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#define HSDMA_GLO_BT_MASK 0x3
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#define HSDMA_GLO_BT_SHIFT 4
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#define HSDMA_GLO_RX_BUSY BIT(3)
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#define HSDMA_GLO_RX_DMA BIT(2)
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#define HSDMA_GLO_TX_BUSY BIT(1)
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#define HSDMA_GLO_TX_DMA BIT(0)
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#define HSDMA_BT_SIZE_16BYTES (0 << HSDMA_GLO_BT_SHIFT)
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#define HSDMA_BT_SIZE_32BYTES (1 << HSDMA_GLO_BT_SHIFT)
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#define HSDMA_BT_SIZE_64BYTES (2 << HSDMA_GLO_BT_SHIFT)
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#define HSDMA_BT_SIZE_128BYTES (3 << HSDMA_GLO_BT_SHIFT)
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#define HSDMA_GLO_DEFAULT (HSDMA_GLO_MULTI_DMA | \
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HSDMA_GLO_RX_DMA | HSDMA_GLO_TX_DMA | HSDMA_BT_SIZE_32BYTES)
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/* HSDMA_REG_RST_CFG */
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#define HSDMA_RST_RX_SHIFT 16
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#define HSDMA_RST_TX_SHIFT 0
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/* HSDMA_REG_DELAY_INT */
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#define HSDMA_DELAY_INT_EN BIT(15)
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#define HSDMA_DELAY_PEND_OFFSET 8
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#define HSDMA_DELAY_TIME_OFFSET 0
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#define HSDMA_DELAY_TX_OFFSET 16
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#define HSDMA_DELAY_RX_OFFSET 0
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#define HSDMA_DELAY_INIT(x) (HSDMA_DELAY_INT_EN | \
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((x) << HSDMA_DELAY_PEND_OFFSET))
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#define HSDMA_DELAY(x) ((HSDMA_DELAY_INIT(x) << \
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HSDMA_DELAY_TX_OFFSET) | HSDMA_DELAY_INIT(x))
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/* HSDMA_REG_INT_STATUS */
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#define HSDMA_INT_DELAY_RX_COH BIT(31)
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#define HSDMA_INT_DELAY_RX_INT BIT(30)
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#define HSDMA_INT_DELAY_TX_COH BIT(29)
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#define HSDMA_INT_DELAY_TX_INT BIT(28)
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#define HSDMA_INT_RX_MASK 0x3
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#define HSDMA_INT_RX_SHIFT 16
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#define HSDMA_INT_RX_Q0 BIT(16)
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#define HSDMA_INT_TX_MASK 0xf
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#define HSDMA_INT_TX_SHIFT 0
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#define HSDMA_INT_TX_Q0 BIT(0)
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/* tx/rx dma desc flags */
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#define HSDMA_PLEN_MASK 0x3fff
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#define HSDMA_DESC_DONE BIT(31)
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#define HSDMA_DESC_LS0 BIT(30)
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#define HSDMA_DESC_PLEN0(_x) (((_x) & HSDMA_PLEN_MASK) << 16)
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#define HSDMA_DESC_TAG BIT(15)
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#define HSDMA_DESC_LS1 BIT(14)
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#define HSDMA_DESC_PLEN1(_x) ((_x) & HSDMA_PLEN_MASK)
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/* align 4 bytes */
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#define HSDMA_ALIGN_SIZE 3
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/* align size 128bytes */
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#define HSDMA_MAX_PLEN 0x3f80
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struct hsdma_desc {
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u32 addr0;
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u32 flags;
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u32 addr1;
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u32 unused;
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};
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struct mtk_hsdma_sg {
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dma_addr_t src_addr;
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dma_addr_t dst_addr;
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u32 len;
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};
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struct mtk_hsdma_desc {
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struct virt_dma_desc vdesc;
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unsigned int num_sgs;
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struct mtk_hsdma_sg sg[1];
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};
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struct mtk_hsdma_chan {
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struct virt_dma_chan vchan;
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unsigned int id;
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dma_addr_t desc_addr;
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int tx_idx;
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int rx_idx;
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struct hsdma_desc *tx_ring;
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struct hsdma_desc *rx_ring;
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struct mtk_hsdma_desc *desc;
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unsigned int next_sg;
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};
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struct mtk_hsdam_engine {
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struct dma_device ddev;
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struct device_dma_parameters dma_parms;
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void __iomem *base;
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struct tasklet_struct task;
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volatile unsigned long chan_issued;
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struct mtk_hsdma_chan chan[1];
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};
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static inline struct mtk_hsdam_engine *mtk_hsdma_chan_get_dev(struct mtk_hsdma_chan *chan)
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{
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return container_of(chan->vchan.chan.device, struct mtk_hsdam_engine,
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ddev);
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}
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static inline struct mtk_hsdma_chan *to_mtk_hsdma_chan(struct dma_chan *c)
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{
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return container_of(c, struct mtk_hsdma_chan, vchan.chan);
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}
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static inline struct mtk_hsdma_desc *to_mtk_hsdma_desc(struct virt_dma_desc *vdesc)
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{
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return container_of(vdesc, struct mtk_hsdma_desc, vdesc);
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}
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static inline u32 mtk_hsdma_read(struct mtk_hsdam_engine *hsdma, u32 reg)
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{
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return readl(hsdma->base + reg);
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}
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static inline void mtk_hsdma_write(struct mtk_hsdam_engine *hsdma,
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unsigned int reg, u32 val)
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{
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writel(val, hsdma->base + reg);
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}
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static void mtk_hsdma_reset_chan(struct mtk_hsdam_engine *hsdma,
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struct mtk_hsdma_chan *chan)
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{
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chan->tx_idx = 0;
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chan->rx_idx = HSDMA_DESCS_NUM - 1;
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mtk_hsdma_write(hsdma, HSDMA_REG_TX_CTX, chan->tx_idx);
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mtk_hsdma_write(hsdma, HSDMA_REG_RX_CRX, chan->rx_idx);
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mtk_hsdma_write(hsdma, HSDMA_REG_RST_CFG,
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0x1 << (chan->id + HSDMA_RST_TX_SHIFT));
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mtk_hsdma_write(hsdma, HSDMA_REG_RST_CFG,
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0x1 << (chan->id + HSDMA_RST_RX_SHIFT));
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}
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static void hsdma_dump_reg(struct mtk_hsdam_engine *hsdma)
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{
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dev_dbg(hsdma->ddev.dev,
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"tbase %08x, tcnt %08x, tctx %08x, tdtx: %08x, rbase %08x, rcnt %08x, rctx %08x, rdtx %08x\n",
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mtk_hsdma_read(hsdma, HSDMA_REG_TX_BASE),
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mtk_hsdma_read(hsdma, HSDMA_REG_TX_CNT),
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mtk_hsdma_read(hsdma, HSDMA_REG_TX_CTX),
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mtk_hsdma_read(hsdma, HSDMA_REG_TX_DTX),
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mtk_hsdma_read(hsdma, HSDMA_REG_RX_BASE),
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mtk_hsdma_read(hsdma, HSDMA_REG_RX_CNT),
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mtk_hsdma_read(hsdma, HSDMA_REG_RX_CRX),
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mtk_hsdma_read(hsdma, HSDMA_REG_RX_DRX));
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dev_dbg(hsdma->ddev.dev,
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"info %08x, glo %08x, delay %08x, intr_stat %08x, intr_mask %08x\n",
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mtk_hsdma_read(hsdma, HSDMA_REG_INFO),
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mtk_hsdma_read(hsdma, HSDMA_REG_GLO_CFG),
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mtk_hsdma_read(hsdma, HSDMA_REG_DELAY_INT),
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mtk_hsdma_read(hsdma, HSDMA_REG_INT_STATUS),
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mtk_hsdma_read(hsdma, HSDMA_REG_INT_MASK));
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}
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static void hsdma_dump_desc(struct mtk_hsdam_engine *hsdma,
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struct mtk_hsdma_chan *chan)
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{
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struct hsdma_desc *tx_desc;
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struct hsdma_desc *rx_desc;
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int i;
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dev_dbg(hsdma->ddev.dev, "tx idx: %d, rx idx: %d\n",
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chan->tx_idx, chan->rx_idx);
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for (i = 0; i < HSDMA_DESCS_NUM; i++) {
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tx_desc = &chan->tx_ring[i];
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rx_desc = &chan->rx_ring[i];
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dev_dbg(hsdma->ddev.dev,
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"%d tx addr0: %08x, flags %08x, tx addr1: %08x, rx addr0 %08x, flags %08x\n",
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i, tx_desc->addr0, tx_desc->flags,
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tx_desc->addr1, rx_desc->addr0, rx_desc->flags);
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}
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}
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static void mtk_hsdma_reset(struct mtk_hsdam_engine *hsdma,
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struct mtk_hsdma_chan *chan)
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{
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int i;
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/* disable dma */
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mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, 0);
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/* disable intr */
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mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, 0);
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/* init desc value */
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for (i = 0; i < HSDMA_DESCS_NUM; i++) {
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chan->tx_ring[i].addr0 = 0;
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chan->tx_ring[i].flags = HSDMA_DESC_LS0 | HSDMA_DESC_DONE;
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}
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for (i = 0; i < HSDMA_DESCS_NUM; i++) {
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chan->rx_ring[i].addr0 = 0;
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chan->rx_ring[i].flags = 0;
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}
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/* reset */
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mtk_hsdma_reset_chan(hsdma, chan);
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/* enable intr */
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mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, HSDMA_INT_RX_Q0);
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/* enable dma */
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mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, HSDMA_GLO_DEFAULT);
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}
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static int mtk_hsdma_terminate_all(struct dma_chan *c)
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{
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struct mtk_hsdma_chan *chan = to_mtk_hsdma_chan(c);
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struct mtk_hsdam_engine *hsdma = mtk_hsdma_chan_get_dev(chan);
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unsigned long timeout;
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LIST_HEAD(head);
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spin_lock_bh(&chan->vchan.lock);
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chan->desc = NULL;
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clear_bit(chan->id, &hsdma->chan_issued);
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vchan_get_all_descriptors(&chan->vchan, &head);
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spin_unlock_bh(&chan->vchan.lock);
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vchan_dma_desc_free_list(&chan->vchan, &head);
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/* wait dma transfer complete */
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timeout = jiffies + msecs_to_jiffies(2000);
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while (mtk_hsdma_read(hsdma, HSDMA_REG_GLO_CFG) &
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(HSDMA_GLO_RX_BUSY | HSDMA_GLO_TX_BUSY)) {
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if (time_after_eq(jiffies, timeout)) {
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hsdma_dump_desc(hsdma, chan);
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mtk_hsdma_reset(hsdma, chan);
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dev_err(hsdma->ddev.dev, "timeout, reset it\n");
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break;
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}
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cpu_relax();
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}
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return 0;
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}
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static int mtk_hsdma_start_transfer(struct mtk_hsdam_engine *hsdma,
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struct mtk_hsdma_chan *chan)
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{
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dma_addr_t src, dst;
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size_t len, tlen;
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struct hsdma_desc *tx_desc, *rx_desc;
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struct mtk_hsdma_sg *sg;
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unsigned int i;
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int rx_idx;
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sg = &chan->desc->sg[0];
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len = sg->len;
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chan->desc->num_sgs = DIV_ROUND_UP(len, HSDMA_MAX_PLEN);
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/* tx desc */
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src = sg->src_addr;
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for (i = 0; i < chan->desc->num_sgs; i++) {
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tx_desc = &chan->tx_ring[chan->tx_idx];
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if (len > HSDMA_MAX_PLEN)
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tlen = HSDMA_MAX_PLEN;
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else
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tlen = len;
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if (i & 0x1) {
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tx_desc->addr1 = src;
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tx_desc->flags |= HSDMA_DESC_PLEN1(tlen);
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} else {
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tx_desc->addr0 = src;
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tx_desc->flags = HSDMA_DESC_PLEN0(tlen);
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/* update index */
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chan->tx_idx = HSDMA_NEXT_DESC(chan->tx_idx);
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}
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src += tlen;
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len -= tlen;
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}
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if (i & 0x1)
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tx_desc->flags |= HSDMA_DESC_LS0;
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else
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tx_desc->flags |= HSDMA_DESC_LS1;
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/* rx desc */
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rx_idx = HSDMA_NEXT_DESC(chan->rx_idx);
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len = sg->len;
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dst = sg->dst_addr;
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for (i = 0; i < chan->desc->num_sgs; i++) {
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rx_desc = &chan->rx_ring[rx_idx];
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if (len > HSDMA_MAX_PLEN)
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tlen = HSDMA_MAX_PLEN;
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else
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tlen = len;
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rx_desc->addr0 = dst;
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rx_desc->flags = HSDMA_DESC_PLEN0(tlen);
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dst += tlen;
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len -= tlen;
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/* update index */
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rx_idx = HSDMA_NEXT_DESC(rx_idx);
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}
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/* make sure desc and index all up to date */
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wmb();
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mtk_hsdma_write(hsdma, HSDMA_REG_TX_CTX, chan->tx_idx);
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return 0;
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}
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static int gdma_next_desc(struct mtk_hsdma_chan *chan)
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{
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struct virt_dma_desc *vdesc;
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vdesc = vchan_next_desc(&chan->vchan);
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if (!vdesc) {
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chan->desc = NULL;
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return 0;
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}
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chan->desc = to_mtk_hsdma_desc(vdesc);
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chan->next_sg = 0;
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return 1;
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}
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static void mtk_hsdma_chan_done(struct mtk_hsdam_engine *hsdma,
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struct mtk_hsdma_chan *chan)
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{
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struct mtk_hsdma_desc *desc;
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int chan_issued;
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chan_issued = 0;
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spin_lock_bh(&chan->vchan.lock);
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desc = chan->desc;
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if (likely(desc)) {
|
||||
if (chan->next_sg == desc->num_sgs) {
|
||||
list_del(&desc->vdesc.node);
|
||||
vchan_cookie_complete(&desc->vdesc);
|
||||
chan_issued = gdma_next_desc(chan);
|
||||
}
|
||||
} else {
|
||||
dev_dbg(hsdma->ddev.dev, "no desc to complete\n");
|
||||
}
|
||||
|
||||
if (chan_issued)
|
||||
set_bit(chan->id, &hsdma->chan_issued);
|
||||
spin_unlock_bh(&chan->vchan.lock);
|
||||
}
|
||||
|
||||
static irqreturn_t mtk_hsdma_irq(int irq, void *devid)
|
||||
{
|
||||
struct mtk_hsdam_engine *hsdma = devid;
|
||||
u32 status;
|
||||
|
||||
status = mtk_hsdma_read(hsdma, HSDMA_REG_INT_STATUS);
|
||||
if (unlikely(!status))
|
||||
return IRQ_NONE;
|
||||
|
||||
if (likely(status & HSDMA_INT_RX_Q0))
|
||||
tasklet_schedule(&hsdma->task);
|
||||
else
|
||||
dev_dbg(hsdma->ddev.dev, "unhandle irq status %08x\n", status);
|
||||
/* clean intr bits */
|
||||
mtk_hsdma_write(hsdma, HSDMA_REG_INT_STATUS, status);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void mtk_hsdma_issue_pending(struct dma_chan *c)
|
||||
{
|
||||
struct mtk_hsdma_chan *chan = to_mtk_hsdma_chan(c);
|
||||
struct mtk_hsdam_engine *hsdma = mtk_hsdma_chan_get_dev(chan);
|
||||
|
||||
spin_lock_bh(&chan->vchan.lock);
|
||||
if (vchan_issue_pending(&chan->vchan) && !chan->desc) {
|
||||
if (gdma_next_desc(chan)) {
|
||||
set_bit(chan->id, &hsdma->chan_issued);
|
||||
tasklet_schedule(&hsdma->task);
|
||||
} else {
|
||||
dev_dbg(hsdma->ddev.dev, "no desc to issue\n");
|
||||
}
|
||||
}
|
||||
spin_unlock_bh(&chan->vchan.lock);
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *mtk_hsdma_prep_dma_memcpy(
|
||||
struct dma_chan *c, dma_addr_t dest, dma_addr_t src,
|
||||
size_t len, unsigned long flags)
|
||||
{
|
||||
struct mtk_hsdma_chan *chan = to_mtk_hsdma_chan(c);
|
||||
struct mtk_hsdma_desc *desc;
|
||||
|
||||
if (len <= 0)
|
||||
return NULL;
|
||||
|
||||
desc = kzalloc(sizeof(*desc), GFP_ATOMIC);
|
||||
if (!desc) {
|
||||
dev_err(c->device->dev, "alloc memcpy decs error\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
desc->sg[0].src_addr = src;
|
||||
desc->sg[0].dst_addr = dest;
|
||||
desc->sg[0].len = len;
|
||||
|
||||
return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
|
||||
}
|
||||
|
||||
static enum dma_status mtk_hsdma_tx_status(struct dma_chan *c,
|
||||
dma_cookie_t cookie,
|
||||
struct dma_tx_state *state)
|
||||
{
|
||||
return dma_cookie_status(c, cookie, state);
|
||||
}
|
||||
|
||||
static void mtk_hsdma_free_chan_resources(struct dma_chan *c)
|
||||
{
|
||||
vchan_free_chan_resources(to_virt_chan(c));
|
||||
}
|
||||
|
||||
static void mtk_hsdma_desc_free(struct virt_dma_desc *vdesc)
|
||||
{
|
||||
kfree(container_of(vdesc, struct mtk_hsdma_desc, vdesc));
|
||||
}
|
||||
|
||||
static void mtk_hsdma_tx(struct mtk_hsdam_engine *hsdma)
|
||||
{
|
||||
struct mtk_hsdma_chan *chan;
|
||||
|
||||
if (test_and_clear_bit(0, &hsdma->chan_issued)) {
|
||||
chan = &hsdma->chan[0];
|
||||
if (chan->desc)
|
||||
mtk_hsdma_start_transfer(hsdma, chan);
|
||||
else
|
||||
dev_dbg(hsdma->ddev.dev, "chan 0 no desc to issue\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void mtk_hsdma_rx(struct mtk_hsdam_engine *hsdma)
|
||||
{
|
||||
struct mtk_hsdma_chan *chan;
|
||||
int next_idx, drx_idx, cnt;
|
||||
|
||||
chan = &hsdma->chan[0];
|
||||
next_idx = HSDMA_NEXT_DESC(chan->rx_idx);
|
||||
drx_idx = mtk_hsdma_read(hsdma, HSDMA_REG_RX_DRX);
|
||||
|
||||
cnt = (drx_idx - next_idx) & HSDMA_DESCS_MASK;
|
||||
if (!cnt)
|
||||
return;
|
||||
|
||||
chan->next_sg += cnt;
|
||||
chan->rx_idx = (chan->rx_idx + cnt) & HSDMA_DESCS_MASK;
|
||||
|
||||
/* update rx crx */
|
||||
wmb();
|
||||
mtk_hsdma_write(hsdma, HSDMA_REG_RX_CRX, chan->rx_idx);
|
||||
|
||||
mtk_hsdma_chan_done(hsdma, chan);
|
||||
}
|
||||
|
||||
static void mtk_hsdma_tasklet(struct tasklet_struct *t)
|
||||
{
|
||||
struct mtk_hsdam_engine *hsdma = from_tasklet(hsdma, t, task);
|
||||
|
||||
mtk_hsdma_rx(hsdma);
|
||||
mtk_hsdma_tx(hsdma);
|
||||
}
|
||||
|
||||
static int mtk_hsdam_alloc_desc(struct mtk_hsdam_engine *hsdma,
|
||||
struct mtk_hsdma_chan *chan)
|
||||
{
|
||||
int i;
|
||||
|
||||
chan->tx_ring = dma_alloc_coherent(hsdma->ddev.dev,
|
||||
2 * HSDMA_DESCS_NUM *
|
||||
sizeof(*chan->tx_ring),
|
||||
&chan->desc_addr, GFP_ATOMIC | __GFP_ZERO);
|
||||
if (!chan->tx_ring)
|
||||
goto no_mem;
|
||||
|
||||
chan->rx_ring = &chan->tx_ring[HSDMA_DESCS_NUM];
|
||||
|
||||
/* init tx ring value */
|
||||
for (i = 0; i < HSDMA_DESCS_NUM; i++)
|
||||
chan->tx_ring[i].flags = HSDMA_DESC_LS0 | HSDMA_DESC_DONE;
|
||||
|
||||
return 0;
|
||||
no_mem:
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
static void mtk_hsdam_free_desc(struct mtk_hsdam_engine *hsdma,
|
||||
struct mtk_hsdma_chan *chan)
|
||||
{
|
||||
if (chan->tx_ring) {
|
||||
dma_free_coherent(hsdma->ddev.dev,
|
||||
2 * HSDMA_DESCS_NUM * sizeof(*chan->tx_ring),
|
||||
chan->tx_ring, chan->desc_addr);
|
||||
chan->tx_ring = NULL;
|
||||
chan->rx_ring = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
static int mtk_hsdma_init(struct mtk_hsdam_engine *hsdma)
|
||||
{
|
||||
struct mtk_hsdma_chan *chan;
|
||||
int ret;
|
||||
u32 reg;
|
||||
|
||||
/* init desc */
|
||||
chan = &hsdma->chan[0];
|
||||
ret = mtk_hsdam_alloc_desc(hsdma, chan);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* tx */
|
||||
mtk_hsdma_write(hsdma, HSDMA_REG_TX_BASE, chan->desc_addr);
|
||||
mtk_hsdma_write(hsdma, HSDMA_REG_TX_CNT, HSDMA_DESCS_NUM);
|
||||
/* rx */
|
||||
mtk_hsdma_write(hsdma, HSDMA_REG_RX_BASE, chan->desc_addr +
|
||||
(sizeof(struct hsdma_desc) * HSDMA_DESCS_NUM));
|
||||
mtk_hsdma_write(hsdma, HSDMA_REG_RX_CNT, HSDMA_DESCS_NUM);
|
||||
/* reset */
|
||||
mtk_hsdma_reset_chan(hsdma, chan);
|
||||
|
||||
/* enable rx intr */
|
||||
mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, HSDMA_INT_RX_Q0);
|
||||
|
||||
/* enable dma */
|
||||
mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, HSDMA_GLO_DEFAULT);
|
||||
|
||||
/* hardware info */
|
||||
reg = mtk_hsdma_read(hsdma, HSDMA_REG_INFO);
|
||||
dev_info(hsdma->ddev.dev, "rx: %d, tx: %d\n",
|
||||
(reg >> HSDMA_INFO_RX_SHIFT) & HSDMA_INFO_RX_MASK,
|
||||
(reg >> HSDMA_INFO_TX_SHIFT) & HSDMA_INFO_TX_MASK);
|
||||
|
||||
hsdma_dump_reg(hsdma);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mtk_hsdma_uninit(struct mtk_hsdam_engine *hsdma)
|
||||
{
|
||||
struct mtk_hsdma_chan *chan;
|
||||
|
||||
/* disable dma */
|
||||
mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, 0);
|
||||
|
||||
/* disable intr */
|
||||
mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, 0);
|
||||
|
||||
/* free desc */
|
||||
chan = &hsdma->chan[0];
|
||||
mtk_hsdam_free_desc(hsdma, chan);
|
||||
|
||||
/* tx */
|
||||
mtk_hsdma_write(hsdma, HSDMA_REG_TX_BASE, 0);
|
||||
mtk_hsdma_write(hsdma, HSDMA_REG_TX_CNT, 0);
|
||||
/* rx */
|
||||
mtk_hsdma_write(hsdma, HSDMA_REG_RX_BASE, 0);
|
||||
mtk_hsdma_write(hsdma, HSDMA_REG_RX_CNT, 0);
|
||||
/* reset */
|
||||
mtk_hsdma_reset_chan(hsdma, chan);
|
||||
}
|
||||
|
||||
static const struct of_device_id mtk_hsdma_of_match[] = {
|
||||
{ .compatible = "mediatek,mt7621-hsdma" },
|
||||
{ },
|
||||
};
|
||||
|
||||
static int mtk_hsdma_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
struct mtk_hsdma_chan *chan;
|
||||
struct mtk_hsdam_engine *hsdma;
|
||||
struct dma_device *dd;
|
||||
int ret;
|
||||
int irq;
|
||||
void __iomem *base;
|
||||
|
||||
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
match = of_match_device(mtk_hsdma_of_match, &pdev->dev);
|
||||
if (!match)
|
||||
return -EINVAL;
|
||||
|
||||
hsdma = devm_kzalloc(&pdev->dev, sizeof(*hsdma), GFP_KERNEL);
|
||||
if (!hsdma)
|
||||
return -EINVAL;
|
||||
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
hsdma->base = base + HSDMA_BASE_OFFSET;
|
||||
tasklet_setup(&hsdma->task, mtk_hsdma_tasklet);
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0)
|
||||
return -EINVAL;
|
||||
ret = devm_request_irq(&pdev->dev, irq, mtk_hsdma_irq,
|
||||
0, dev_name(&pdev->dev), hsdma);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to request irq\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
device_reset(&pdev->dev);
|
||||
|
||||
dd = &hsdma->ddev;
|
||||
dma_cap_set(DMA_MEMCPY, dd->cap_mask);
|
||||
dd->copy_align = HSDMA_ALIGN_SIZE;
|
||||
dd->device_free_chan_resources = mtk_hsdma_free_chan_resources;
|
||||
dd->device_prep_dma_memcpy = mtk_hsdma_prep_dma_memcpy;
|
||||
dd->device_terminate_all = mtk_hsdma_terminate_all;
|
||||
dd->device_tx_status = mtk_hsdma_tx_status;
|
||||
dd->device_issue_pending = mtk_hsdma_issue_pending;
|
||||
dd->dev = &pdev->dev;
|
||||
dd->dev->dma_parms = &hsdma->dma_parms;
|
||||
dma_set_max_seg_size(dd->dev, HSDMA_MAX_PLEN);
|
||||
INIT_LIST_HEAD(&dd->channels);
|
||||
|
||||
chan = &hsdma->chan[0];
|
||||
chan->id = 0;
|
||||
chan->vchan.desc_free = mtk_hsdma_desc_free;
|
||||
vchan_init(&chan->vchan, dd);
|
||||
|
||||
/* init hardware */
|
||||
ret = mtk_hsdma_init(hsdma);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to alloc ring descs\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = dma_async_device_register(dd);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to register dma device\n");
|
||||
goto err_uninit_hsdma;
|
||||
}
|
||||
|
||||
ret = of_dma_controller_register(pdev->dev.of_node,
|
||||
of_dma_xlate_by_chan_id, hsdma);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to register of dma controller\n");
|
||||
goto err_unregister;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, hsdma);
|
||||
|
||||
return 0;
|
||||
|
||||
err_unregister:
|
||||
dma_async_device_unregister(dd);
|
||||
err_uninit_hsdma:
|
||||
mtk_hsdma_uninit(hsdma);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mtk_hsdma_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct mtk_hsdam_engine *hsdma = platform_get_drvdata(pdev);
|
||||
|
||||
mtk_hsdma_uninit(hsdma);
|
||||
|
||||
of_dma_controller_free(pdev->dev.of_node);
|
||||
dma_async_device_unregister(&hsdma->ddev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver mtk_hsdma_driver = {
|
||||
.probe = mtk_hsdma_probe,
|
||||
.remove = mtk_hsdma_remove,
|
||||
.driver = {
|
||||
.name = KBUILD_MODNAME,
|
||||
.of_match_table = mtk_hsdma_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(mtk_hsdma_driver);
|
||||
|
||||
MODULE_AUTHOR("Michael Lee <igvtee@gmail.com>");
|
||||
MODULE_DESCRIPTION("MTK HSDMA driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@ -101,7 +101,7 @@ define KernelPackage/hsdma-mtk
|
||||
CONFIG_MTK_HSDMA
|
||||
FILES:= \
|
||||
$(LINUX_DIR)/drivers/dma/virt-dma.ko \
|
||||
$(LINUX_DIR)/drivers/staging/mt7621-dma/hsdma-mt7621.ko
|
||||
$(LINUX_DIR)/drivers/dma/mediatek/hsdma-mt7621.ko
|
||||
AUTOLOAD:=$(call AutoLoad,53,hsdma-mt7621)
|
||||
endef
|
||||
|
||||
|
||||
@ -0,0 +1,44 @@
|
||||
From d94fc5ce1dc395747c3934ecffcdec0396583755 Mon Sep 17 00:00:00 2001
|
||||
From: Nick Hainke <vincent@systemli.org>
|
||||
Date: Fri, 26 May 2023 19:46:33 +0200
|
||||
Subject: [PATCH] dmaengine: mediatek: add HSDMA support for mt7621
|
||||
|
||||
Commit 87dd67f496f7 ("staging: mt7621-dma: remove driver from tree")
|
||||
removed the mt7621-dma driver. Move the driver from staging to the
|
||||
folder "drivers/dma/mediatek" containing already other mediatek dma
|
||||
driver implementations and maintain it downstream in OpenWrt.
|
||||
|
||||
This patch will not be sent to upstream linux. It is just a workaround.
|
||||
|
||||
Signed-off-by: Nick Hainke <vincent@systemli.org>
|
||||
---
|
||||
drivers/dma/mediatek/Kconfig | 6 ++++++
|
||||
drivers/dma/mediatek/Makefile | 1 +
|
||||
2 files changed, 7 insertions(+)
|
||||
|
||||
diff --git a/drivers/dma/mediatek/Kconfig b/drivers/dma/mediatek/Kconfig
|
||||
index 7a46a5455957..1a24d73ce87f 100644
|
||||
--- a/drivers/dma/mediatek/Kconfig
|
||||
+++ b/drivers/dma/mediatek/Kconfig
|
||||
@@ -36,3 +36,9 @@ config MTK_UART_APDMA
|
||||
When SERIAL_8250_MT6577 is enabled, and if you want to use DMA,
|
||||
you can enable the config. The DMA engine can only be used
|
||||
with MediaTek SoCs.
|
||||
+
|
||||
+config MTK_HSDMA
|
||||
+ tristate "MTK HSDMA support"
|
||||
+ depends on RALINK && SOC_MT7621
|
||||
+ select DMA_ENGINE
|
||||
+ select DMA_VIRTUAL_CHANNELS
|
||||
diff --git a/drivers/dma/mediatek/Makefile b/drivers/dma/mediatek/Makefile
|
||||
index 5ba39a5edc13..784af039b7c0 100644
|
||||
--- a/drivers/dma/mediatek/Makefile
|
||||
+++ b/drivers/dma/mediatek/Makefile
|
||||
@@ -2,3 +2,4 @@
|
||||
obj-$(CONFIG_MTK_UART_APDMA) += mtk-uart-apdma.o
|
||||
obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
|
||||
obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o
|
||||
+obj-$(CONFIG_MTK_HSDMA) += hsdma-mt7621.o
|
||||
--
|
||||
2.40.1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user