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ath79: add NAND driver for MikroTik RB91xG series
Main part is copied from ar71xx original driver rb91x_nand written by Gabor Juhos <juhosg@openwrt.org>. What is done: * Support of kernel 5.4 and 5.10, * DTS support, * New gpio API (gpiod_*) support. Reviewed-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Signed-off-by: Denis Kalashnikov <denis281089@gmail.com>
This commit is contained in:
Denis Kalashnikov
Koen Vandeputte
parent
7b8931678c
commit
820e660cd7
375
target/linux/ath79/files/drivers/mtd/nand/raw/rb91x_nand.c
Normal file
375
target/linux/ath79/files/drivers/mtd/nand/raw/rb91x_nand.c
Normal file
@ -0,0 +1,375 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* MikroTik RB91x NAND flash driver
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*
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* Main part is copied from original driver written by Gabor Juhos.
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*
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* Copyright (C) 2013-2014 Gabor Juhos <juhosg@openwrt.org>
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*/
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/*
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* WARNING: to speed up NAND reading/writing we are working with SoC GPIO
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* controller registers directly -- not through standard GPIO API.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/platform_device.h>
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#include <linux/gpio/consumer.h>
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#include <linux/version.h>
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#include <linux/of_platform.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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/* Bit masks for NAND data lines in ath79 gpio 32-bit register */
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#define RB91X_NAND_NRW_BIT BIT(12)
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#define RB91X_NAND_DATA_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) \
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| BIT(13) | BIT(14) | BIT(15))
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#define RB91X_NAND_LOW_DATA_MASK 0x1f
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#define RB91X_NAND_HIGH_DATA_MASK 0xe0
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#define RB91X_NAND_HIGH_DATA_SHIFT 8
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enum rb91x_nand_gpios {
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RB91X_NAND_READ,/* Read */
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RB91X_NAND_RDY, /* NAND Ready */
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RB91X_NAND_NCE, /* Chip Enable. Active low */
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RB91X_NAND_CLE, /* Command Latch Enable */
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RB91X_NAND_ALE, /* Address Latch Enable */
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RB91X_NAND_NRW, /* Read/Write. Active low */
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RB91X_NAND_NLE, /* Latch Enable. Active low */
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RB91X_NAND_GPIOS,
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};
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struct rb91x_nand_drvdata {
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struct nand_chip chip;
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struct device *dev;
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struct gpio_desc **gpio;
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void __iomem *ath79_gpio_base;
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};
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static inline void rb91x_nand_latch_lock(struct rb91x_nand_drvdata *drvdata,
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int lock)
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{
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gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_NLE], lock);
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}
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static int rb91x_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *oobregion)
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{
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switch (section) {
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case 0:
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oobregion->offset = 8;
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oobregion->length = 3;
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return 0;
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case 1:
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oobregion->offset = 13;
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oobregion->length = 3;
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return 0;
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default:
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return -ERANGE;
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}
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}
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static int rb91x_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *oobregion)
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{
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switch (section) {
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case 0:
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oobregion->offset = 0;
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oobregion->length = 4;
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return 0;
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case 1:
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oobregion->offset = 4;
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oobregion->length = 1;
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return 0;
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case 2:
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oobregion->offset = 6;
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oobregion->length = 2;
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return 0;
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case 3:
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oobregion->offset = 11;
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oobregion->length = 2;
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return 0;
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default:
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return -ERANGE;
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}
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}
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static const struct mtd_ooblayout_ops rb91x_nand_ecclayout_ops = {
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.ecc = rb91x_ooblayout_ecc,
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.free = rb91x_ooblayout_free,
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};
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static void rb91x_nand_write(struct rb91x_nand_drvdata *drvdata,
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const u8 *buf,
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unsigned len)
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{
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void __iomem *base = drvdata->ath79_gpio_base;
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u32 oe_reg;
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u32 out_reg;
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u32 out;
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unsigned i;
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rb91x_nand_latch_lock(drvdata, 1);
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oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
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out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
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/* Set data lines to output mode */
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__raw_writel(oe_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRW_BIT),
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base + AR71XX_GPIO_REG_OE);
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out = out_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRW_BIT);
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for (i = 0; i != len; i++) {
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u32 data;
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data = (buf[i] & RB91X_NAND_HIGH_DATA_MASK) <<
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RB91X_NAND_HIGH_DATA_SHIFT;
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data |= buf[i] & RB91X_NAND_LOW_DATA_MASK;
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data |= out;
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__raw_writel(data, base + AR71XX_GPIO_REG_OUT);
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/* Deactivate WE line */
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data |= RB91X_NAND_NRW_BIT;
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__raw_writel(data, base + AR71XX_GPIO_REG_OUT);
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/* Flush write */
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__raw_readl(base + AR71XX_GPIO_REG_OUT);
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}
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/* Restore registers */
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__raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
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__raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
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/* Flush write */
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__raw_readl(base + AR71XX_GPIO_REG_OUT);
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rb91x_nand_latch_lock(drvdata, 0);
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}
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static void rb91x_nand_read(struct rb91x_nand_drvdata *drvdata,
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u8 *read_buf,
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unsigned len)
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{
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void __iomem *base = drvdata->ath79_gpio_base;
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u32 oe_reg;
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u32 out_reg;
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unsigned i;
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/* Enable read mode */
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gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_READ], 1);
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rb91x_nand_latch_lock(drvdata, 1);
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/* Save registers */
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oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
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out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
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/* Set data lines to input mode */
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__raw_writel(oe_reg | RB91X_NAND_DATA_BITS,
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base + AR71XX_GPIO_REG_OE);
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for (i = 0; i < len; i++) {
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u32 in;
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u8 data;
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/* Activate RE line */
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__raw_writel(RB91X_NAND_NRW_BIT, base + AR71XX_GPIO_REG_CLEAR);
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/* Flush write */
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__raw_readl(base + AR71XX_GPIO_REG_CLEAR);
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/* Read input lines */
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in = __raw_readl(base + AR71XX_GPIO_REG_IN);
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/* Deactivate RE line */
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__raw_writel(RB91X_NAND_NRW_BIT, base + AR71XX_GPIO_REG_SET);
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data = (in & RB91X_NAND_LOW_DATA_MASK);
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data |= (in >> RB91X_NAND_HIGH_DATA_SHIFT) &
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RB91X_NAND_HIGH_DATA_MASK;
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read_buf[i] = data;
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}
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/* Restore registers */
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__raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
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__raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
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/* Flush write */
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__raw_readl(base + AR71XX_GPIO_REG_OUT);
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rb91x_nand_latch_lock(drvdata, 0);
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/* Disable read mode */
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gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_READ], 0);
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}
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static int rb91x_nand_dev_ready(struct nand_chip *chip)
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{
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struct rb91x_nand_drvdata *drvdata = (struct rb91x_nand_drvdata *)(chip->priv);
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return gpiod_get_value_cansleep(drvdata->gpio[RB91X_NAND_RDY]);
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}
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static void rb91x_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
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unsigned int ctrl)
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{
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struct rb91x_nand_drvdata *drvdata = chip->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_CLE],
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(ctrl & NAND_CLE) ? 1 : 0);
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gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_ALE],
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(ctrl & NAND_ALE) ? 1 : 0);
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gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_NCE],
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(ctrl & NAND_NCE) ? 1 : 0);
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}
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if (cmd != NAND_CMD_NONE) {
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u8 t = cmd;
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rb91x_nand_write(drvdata, &t, 1);
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}
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}
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static u8 rb91x_nand_read_byte(struct nand_chip *chip)
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{
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u8 data = 0xff;
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rb91x_nand_read(chip->priv, &data, 1);
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return data;
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}
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static void rb91x_nand_read_buf(struct nand_chip *chip, u8 *buf, int len)
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{
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rb91x_nand_read(chip->priv, buf, len);
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}
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static void rb91x_nand_write_buf(struct nand_chip *chip, const u8 *buf, int len)
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{
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rb91x_nand_write(chip->priv, buf, len);
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}
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static void rb91x_nand_release(struct rb91x_nand_drvdata *drvdata)
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{
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
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mtd_device_unregister(nand_to_mtd(&drvdata->chip));
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nand_cleanup(&drvdata->chip);
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#else
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nand_release(&drvdata->chip);
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#endif
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}
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static int rb91x_nand_probe(struct platform_device *pdev)
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{
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struct rb91x_nand_drvdata *drvdata;
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struct mtd_info *mtd;
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int r;
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struct device *dev = &pdev->dev;
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struct gpio_descs *gpios;
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drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
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if (!drvdata)
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return -ENOMEM;
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platform_set_drvdata(pdev, drvdata);
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gpios = gpiod_get_array(dev, NULL, GPIOD_OUT_LOW);
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if (IS_ERR(gpios)) {
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dev_err(dev, "failed to get gpios: %d\n", (int)gpios);
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return -EINVAL;
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}
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if (gpios->ndescs != RB91X_NAND_GPIOS) {
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dev_err(dev, "expected %d gpios\n", RB91X_NAND_GPIOS);
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return -EINVAL;
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}
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drvdata->gpio = gpios->desc;
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gpiod_direction_input(drvdata->gpio[RB91X_NAND_RDY]);
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drvdata->ath79_gpio_base = ioremap(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
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drvdata->dev = dev;
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drvdata->chip.priv = drvdata;
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drvdata->chip.legacy.cmd_ctrl = rb91x_nand_cmd_ctrl;
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drvdata->chip.legacy.dev_ready = rb91x_nand_dev_ready;
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drvdata->chip.legacy.read_byte = rb91x_nand_read_byte;
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drvdata->chip.legacy.write_buf = rb91x_nand_write_buf;
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drvdata->chip.legacy.read_buf = rb91x_nand_read_buf;
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drvdata->chip.legacy.chip_delay = 25;
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
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drvdata->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
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drvdata->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
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#else
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drvdata->chip.ecc.mode = NAND_ECC_SOFT;
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drvdata->chip.ecc.algo = NAND_ECC_HAMMING;
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#endif
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drvdata->chip.options = NAND_NO_SUBPAGE_WRITE;
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r = nand_scan(&drvdata->chip, 1);
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if (r) {
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dev_err(dev, "nand_scan() failed: %d\n", r);
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return r;
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}
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mtd = nand_to_mtd(&drvdata->chip);
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mtd->dev.parent = dev;
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mtd_set_of_node(mtd, dev->of_node);
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mtd->owner = THIS_MODULE;
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if (mtd->writesize == 512)
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mtd_set_ooblayout(mtd, &rb91x_nand_ecclayout_ops);
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r = mtd_device_register(mtd, NULL, 0);
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if (r) {
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dev_err(dev, "mtd_device_register() failed: %d\n",
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r);
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goto err_release_nand;
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}
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return 0;
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err_release_nand:
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rb91x_nand_release(drvdata);
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return r;
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}
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static int rb91x_nand_remove(struct platform_device *pdev)
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{
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struct rb91x_nand_drvdata *drvdata = platform_get_drvdata(pdev);
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rb91x_nand_release(drvdata);
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return 0;
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}
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static const struct of_device_id rb91x_nand_match[] = {
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{ .compatible = "mikrotik,rb91x-nand" },
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{},
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};
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MODULE_DEVICE_TABLE(of, rb91x_nand_match);
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static struct platform_driver rb91x_nand_driver = {
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.probe = rb91x_nand_probe,
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.remove = rb91x_nand_remove,
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.driver = {
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.name = "rb91x-nand",
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.owner = THIS_MODULE,
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.of_match_table = rb91x_nand_match,
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},
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};
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module_platform_driver(rb91x_nand_driver);
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MODULE_DESCRIPTION("MikrotTik RB91x NAND flash driver");
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MODULE_VERSION(DRV_VERSION);
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MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
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MODULE_AUTHOR("Denis Kalashnikov <denis281089@gmail.com>");
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MODULE_LICENSE("GPL v2");
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@ -15,6 +15,7 @@ CONFIG_MTD_NAND_AR934X=y
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CONFIG_MTD_NAND_CORE=y
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CONFIG_MTD_NAND_ECC=y
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CONFIG_MTD_NAND_RB4XX=y
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CONFIG_MTD_NAND_RB91X=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_ROUTERBOOT_PARTS=y
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CONFIG_MTD_SPI_NAND=y
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@ -24,3 +24,26 @@
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obj-$(CONFIG_GPIO_LOGICVC) += gpio-logicvc.o
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obj-$(CONFIG_GPIO_LOONGSON1) += gpio-loongson1.o
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obj-$(CONFIG_GPIO_LOONGSON) += gpio-loongson.o
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--- a/drivers/mtd/nand/raw/Kconfig
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+++ b/drivers/mtd/nand/raw/Kconfig
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@@ -571,4 +571,10 @@ config MTD_NAND_RB4XX
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Enables support for the NAND flash chip on Mikrotik Routerboard
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RB4xx series.
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+config MTD_NAND_RB91X
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+ tristate "MikroTik RB91x NAND driver support"
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+ depends on ATH79 && MTD_RAW_NAND
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+ help
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+ Enables support for the NAND flash chip on MikroTik RB91x series.
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+
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endif # MTD_RAW_NAND
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--- a/drivers/mtd/nand/raw/Makefile
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+++ b/drivers/mtd/nand/raw/Makefile
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@@ -60,6 +60,7 @@ obj-$(CONFIG_MTD_NAND_CADENCE) += caden
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obj-$(CONFIG_MTD_NAND_ARASAN) += arasan-nand-controller.o
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obj-$(CONFIG_MTD_NAND_AR934X) += ar934x_nand.o
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obj-$(CONFIG_MTD_NAND_RB4XX) += nand_rb4xx.o
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+obj-$(CONFIG_MTD_NAND_RB91X) += rb91x_nand.o
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nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o
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nand-objs += nand_onfi.o
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@ -1,3 +1,24 @@
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--- a/drivers/mtd/nand/raw/Kconfig
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+++ b/drivers/mtd/nand/raw/Kconfig
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@@ -559,4 +559,8 @@ config MTD_NAND_RB4XX
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Enables support for the NAND flash chip on Mikrotik Routerboard
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RB4xx series.
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+config MTD_NAND_RB91X
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+ tristate "MikroTik RB91x NAND driver support"
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+ depends on ATH79 && MTD_RAW_NAND
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+
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endif # MTD_RAW_NAND
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--- a/drivers/mtd/nand/raw/Makefile
|
||||
+++ b/drivers/mtd/nand/raw/Makefile
|
||||
@@ -59,6 +59,7 @@ obj-$(CONFIG_MTD_NAND_STM32_FMC2) += stm
|
||||
obj-$(CONFIG_MTD_NAND_MESON) += meson_nand.o
|
||||
obj-$(CONFIG_MTD_NAND_AR934X) += ar934x_nand.o
|
||||
obj-$(CONFIG_MTD_NAND_RB4XX) += nand_rb4xx.o
|
||||
+obj-$(CONFIG_MTD_NAND_RB91X) += rb91x_nand.o
|
||||
|
||||
nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o
|
||||
nand-objs += nand_onfi.o
|
||||
--- a/drivers/gpio/Kconfig
|
||||
+++ b/drivers/gpio/Kconfig
|
||||
@@ -130,6 +130,10 @@ config GPIO_ATH79
|
||||
|
||||
Loading…
Reference in New Issue
Block a user