mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-24 07:46:48 +00:00
bcm63xx: add basic bcm6362 support
Signed-off-by: Jonas Gorski <jonas.gorski+openwrt@gmail.com> SVN-Revision: 32923
This commit is contained in:
Jonas Gorski
parent
dcd339ac9d
commit
820c224029
@ -11,6 +11,7 @@ CONFIG_BCM63XX_CPU_6338=y
|
|||||||
CONFIG_BCM63XX_CPU_6345=y
|
CONFIG_BCM63XX_CPU_6345=y
|
||||||
CONFIG_BCM63XX_CPU_6348=y
|
CONFIG_BCM63XX_CPU_6348=y
|
||||||
CONFIG_BCM63XX_CPU_6358=y
|
CONFIG_BCM63XX_CPU_6358=y
|
||||||
|
# CONFIG_BCM63XX_CPU_6362 is not set
|
||||||
CONFIG_BCM63XX_CPU_6368=y
|
CONFIG_BCM63XX_CPU_6368=y
|
||||||
CONFIG_BCM63XX_ENET=y
|
CONFIG_BCM63XX_ENET=y
|
||||||
CONFIG_BCM63XX_PHY=y
|
CONFIG_BCM63XX_PHY=y
|
||||||
|
|||||||
@ -0,0 +1,497 @@
|
|||||||
|
From 27ebbb819b1f92d52309276b29b7a56e362e5c4d Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jonas Gorski <jonas.gorski@gmail.com>
|
||||||
|
Date: Mon, 21 Nov 2011 00:48:52 +0100
|
||||||
|
Subject: [PATCH 54/84] MIPS: BCM63XX: add basic BCM6362 support
|
||||||
|
|
||||||
|
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
|
||||||
|
---
|
||||||
|
arch/mips/bcm63xx/Kconfig | 4 +
|
||||||
|
arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +-
|
||||||
|
arch/mips/bcm63xx/cpu.c | 52 ++++++++-
|
||||||
|
arch/mips/bcm63xx/irq.c | 19 +++
|
||||||
|
arch/mips/bcm63xx/prom.c | 2 +
|
||||||
|
arch/mips/bcm63xx/setup.c | 3 +
|
||||||
|
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 139 +++++++++++++++++++++
|
||||||
|
arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 2 +
|
||||||
|
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 59 +++++++++
|
||||||
|
arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 +
|
||||||
|
10 files changed, 281 insertions(+), 2 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/bcm63xx/Kconfig
|
||||||
|
+++ b/arch/mips/bcm63xx/Kconfig
|
||||||
|
@@ -25,6 +25,10 @@ config BCM63XX_CPU_6358
|
||||||
|
bool "support 6358 CPU"
|
||||||
|
select HW_HAS_PCI
|
||||||
|
|
||||||
|
+config BCM63XX_CPU_6362
|
||||||
|
+ bool "support 6362 CPU"
|
||||||
|
+ select HW_HAS_PCI
|
||||||
|
+
|
||||||
|
config BCM63XX_CPU_6368
|
||||||
|
bool "support 6368 CPU"
|
||||||
|
select HW_HAS_PCI
|
||||||
|
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
|
||||||
|
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
|
||||||
|
@@ -764,7 +764,7 @@ void __init board_prom_init(void)
|
||||||
|
/* read base address of boot chip select (0)
|
||||||
|
* 6328 does not have MPI but boots from a fixed address
|
||||||
|
*/
|
||||||
|
- if (BCMCPU_IS_6328())
|
||||||
|
+ if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
|
||||||
|
val = 0x18000000;
|
||||||
|
else {
|
||||||
|
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
|
||||||
|
--- a/arch/mips/bcm63xx/cpu.c
|
||||||
|
+++ b/arch/mips/bcm63xx/cpu.c
|
||||||
|
@@ -71,6 +71,15 @@ static const int bcm6358_irqs[] = {
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
+static const unsigned long bcm6362_regs_base[] = {
|
||||||
|
+ __GEN_CPU_REGS_TABLE(6362)
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static const int bcm6362_irqs[] = {
|
||||||
|
+ __GEN_CPU_IRQ_TABLE(6362)
|
||||||
|
+
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
static const unsigned long bcm6368_regs_base[] = {
|
||||||
|
__GEN_CPU_REGS_TABLE(6368)
|
||||||
|
};
|
||||||
|
@@ -169,6 +178,42 @@ static unsigned int detect_cpu_clock(voi
|
||||||
|
return (16 * 1000000 * n1 * n2) / m1;
|
||||||
|
}
|
||||||
|
|
||||||
|
+ case BCM6362_CPU_ID:
|
||||||
|
+ {
|
||||||
|
+ unsigned int tmp, mips_pll_fcvo;
|
||||||
|
+
|
||||||
|
+ tmp = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
|
||||||
|
+ mips_pll_fcvo = (tmp & STRAPBUS_6362_FCVO_MASK)
|
||||||
|
+ >> STRAPBUS_6362_FCVO_SHIFT;
|
||||||
|
+ switch (mips_pll_fcvo) {
|
||||||
|
+ case 0x03:
|
||||||
|
+ case 0x0b:
|
||||||
|
+ case 0x13:
|
||||||
|
+ case 0x1b:
|
||||||
|
+ return 240000000;
|
||||||
|
+ case 0x04:
|
||||||
|
+ case 0x0c:
|
||||||
|
+ case 0x14:
|
||||||
|
+ case 0x1c:
|
||||||
|
+ return 160000000;
|
||||||
|
+ case 0x05:
|
||||||
|
+ case 0x0e:
|
||||||
|
+ case 0x16:
|
||||||
|
+ case 0x1e:
|
||||||
|
+ case 0x1f:
|
||||||
|
+ return 400000000;
|
||||||
|
+ case 0x06:
|
||||||
|
+ return 440000000;
|
||||||
|
+ case 0x07:
|
||||||
|
+ case 0x17:
|
||||||
|
+ return 384000000;
|
||||||
|
+ case 0x15:
|
||||||
|
+ case 0x1d:
|
||||||
|
+ return 200000000;
|
||||||
|
+ default:
|
||||||
|
+ return 320000000;
|
||||||
|
+ }
|
||||||
|
+ }
|
||||||
|
case BCM6368_CPU_ID:
|
||||||
|
{
|
||||||
|
unsigned int tmp, p1, p2, ndiv, m1;
|
||||||
|
@@ -205,7 +250,7 @@ static unsigned int detect_memory_size(v
|
||||||
|
unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
- if (BCMCPU_IS_6328())
|
||||||
|
+ if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
|
||||||
|
return bcm_ddr_readl(DDR_CSEND_REG) << 24;
|
||||||
|
|
||||||
|
if (BCMCPU_IS_6345()) {
|
||||||
|
@@ -280,6 +325,11 @@ void __init bcm63xx_cpu_init(void)
|
||||||
|
bcm63xx_regs_base = bcm6328_regs_base;
|
||||||
|
bcm63xx_irqs = bcm6328_irqs;
|
||||||
|
break;
|
||||||
|
+ case BCM6362_CPU_ID:
|
||||||
|
+ expected_cpu_id = BCM6362_CPU_ID;
|
||||||
|
+ bcm63xx_regs_base = bcm6362_regs_base;
|
||||||
|
+ bcm63xx_irqs = bcm6362_irqs;
|
||||||
|
+ break;
|
||||||
|
case BCM6368_CPU_ID:
|
||||||
|
expected_cpu_id = BCM6368_CPU_ID;
|
||||||
|
bcm63xx_regs_base = bcm6368_regs_base;
|
||||||
|
--- a/arch/mips/bcm63xx/irq.c
|
||||||
|
+++ b/arch/mips/bcm63xx/irq.c
|
||||||
|
@@ -82,6 +82,14 @@ static void __internal_irq_unmask_64(uns
|
||||||
|
#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6358
|
||||||
|
#define ext_irq_cfg_reg2 0
|
||||||
|
#endif
|
||||||
|
+#ifdef CONFIG_BCM63XX_CPU_6362
|
||||||
|
+#define irq_stat_reg PERF_IRQSTAT_6362_REG
|
||||||
|
+#define irq_mask_reg PERF_IRQMASK_6362_REG
|
||||||
|
+#define irq_bits 64
|
||||||
|
+#define is_ext_irq_cascaded 1
|
||||||
|
+#define ext_irq_start (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
|
||||||
|
+#define ext_irq_end (BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE)
|
||||||
|
+#endif
|
||||||
|
#ifdef CONFIG_BCM63XX_CPU_6368
|
||||||
|
#define irq_stat_reg PERF_IRQSTAT_6368_REG
|
||||||
|
#define irq_mask_reg PERF_IRQMASK_6368_REG
|
||||||
|
@@ -170,6 +178,16 @@ static void bcm63xx_init_irq(void)
|
||||||
|
ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
|
||||||
|
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
|
||||||
|
break;
|
||||||
|
+ case BCM6362_CPU_ID:
|
||||||
|
+ irq_stat_addr += PERF_IRQSTAT_6362_REG;
|
||||||
|
+ irq_mask_addr += PERF_IRQMASK_6362_REG;
|
||||||
|
+ irq_bits = 64;
|
||||||
|
+ ext_irq_count = 4;
|
||||||
|
+ is_ext_irq_cascaded = 1;
|
||||||
|
+ ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
|
||||||
|
+ ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
|
||||||
|
+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
|
||||||
|
+ break;
|
||||||
|
case BCM6368_CPU_ID:
|
||||||
|
irq_stat_addr += PERF_IRQSTAT_6368_REG;
|
||||||
|
irq_mask_addr += PERF_IRQMASK_6368_REG;
|
||||||
|
@@ -457,6 +475,7 @@ static int bcm63xx_external_irq_set_type
|
||||||
|
case BCM6338_CPU_ID:
|
||||||
|
case BCM6345_CPU_ID:
|
||||||
|
case BCM6358_CPU_ID:
|
||||||
|
+ case BCM6362_CPU_ID:
|
||||||
|
case BCM6368_CPU_ID:
|
||||||
|
if (levelsense)
|
||||||
|
reg |= EXTIRQ_CFG_LEVELSENSE(irq);
|
||||||
|
--- a/arch/mips/bcm63xx/prom.c
|
||||||
|
+++ b/arch/mips/bcm63xx/prom.c
|
||||||
|
@@ -36,6 +36,8 @@ void __init prom_init(void)
|
||||||
|
mask = CKCTL_6348_ALL_SAFE_EN;
|
||||||
|
else if (BCMCPU_IS_6358())
|
||||||
|
mask = CKCTL_6358_ALL_SAFE_EN;
|
||||||
|
+ else if (BCMCPU_IS_6362())
|
||||||
|
+ mask = CKCTL_6362_ALL_SAFE_EN;
|
||||||
|
else if (BCMCPU_IS_6368())
|
||||||
|
mask = CKCTL_6368_ALL_SAFE_EN;
|
||||||
|
else
|
||||||
|
--- a/arch/mips/bcm63xx/setup.c
|
||||||
|
+++ b/arch/mips/bcm63xx/setup.c
|
||||||
|
@@ -83,6 +83,9 @@ void bcm63xx_machine_reboot(void)
|
||||||
|
case BCM6358_CPU_ID:
|
||||||
|
perf_regs[0] = PERF_EXTIRQ_CFG_REG_6358;
|
||||||
|
break;
|
||||||
|
+ case BCM6362_CPU_ID:
|
||||||
|
+ perf_regs[0] = PERF_EXTIRQ_CFG_REG_6362;
|
||||||
|
+ break;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < 2; i++) {
|
||||||
|
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
|
||||||
|
@@ -14,6 +14,7 @@
|
||||||
|
#define BCM6345_CPU_ID 0x6345
|
||||||
|
#define BCM6348_CPU_ID 0x6348
|
||||||
|
#define BCM6358_CPU_ID 0x6358
|
||||||
|
+#define BCM6362_CPU_ID 0x6362
|
||||||
|
#define BCM6368_CPU_ID 0x6368
|
||||||
|
|
||||||
|
void __init bcm63xx_cpu_init(void);
|
||||||
|
@@ -86,6 +87,20 @@ unsigned int bcm63xx_get_cpu_freq(void);
|
||||||
|
# define BCMCPU_IS_6358() (0)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
+#ifdef CONFIG_BCM63XX_CPU_6362
|
||||||
|
+# ifdef bcm63xx_get_cpu_id
|
||||||
|
+# undef bcm63xx_get_cpu_id
|
||||||
|
+# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
|
||||||
|
+# define BCMCPU_RUNTIME_DETECT
|
||||||
|
+# else
|
||||||
|
+# define bcm63xx_get_cpu_id() BCM6362_CPU_ID
|
||||||
|
+# endif
|
||||||
|
+# define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
|
||||||
|
+#else
|
||||||
|
+# define BCMCPU_IS_6362() (0)
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
+
|
||||||
|
#ifdef CONFIG_BCM63XX_CPU_6368
|
||||||
|
# ifdef bcm63xx_get_cpu_id
|
||||||
|
# undef bcm63xx_get_cpu_id
|
||||||
|
@@ -402,6 +417,62 @@ enum bcm63xx_regs_set {
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
+ * 6362 register sets base address
|
||||||
|
+ */
|
||||||
|
+#define BCM_6362_DSL_LMEM_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6362_PERF_BASE (0xb0000000)
|
||||||
|
+#define BCM_6362_TIMER_BASE (0xb0000040)
|
||||||
|
+#define BCM_6362_WDT_BASE (0xb000005c)
|
||||||
|
+#define BCM_6362_UART0_BASE (0xb0000100)
|
||||||
|
+#define BCM_6362_UART1_BASE (0xb0000120)
|
||||||
|
+#define BCM_6362_GPIO_BASE (0xb0000080)
|
||||||
|
+#define BCM_6362_SPI_BASE (0xb0000800)
|
||||||
|
+#define BCM_6362_HSSPI_BASE (0xb0001000)
|
||||||
|
+#define BCM_6362_UDC0_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6362_USBDMA_BASE (0xb000c000)
|
||||||
|
+#define BCM_6362_OHCI0_BASE (0xb0002600)
|
||||||
|
+#define BCM_6362_OHCI_PRIV_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6362_USBH_PRIV_BASE (0xb0002700)
|
||||||
|
+#define BCM_6362_USBD_BASE (0xb0002400)
|
||||||
|
+#define BCM_6362_MPI_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6362_PCMCIA_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6362_PCIE_BASE (0xb0e40000)
|
||||||
|
+#define BCM_6362_SDRAM_REGS_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6362_DSL_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6362_UBUS_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6362_ENET0_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6362_ENET1_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6362_ENETDMA_BASE (0xb000d800)
|
||||||
|
+#define BCM_6362_ENETDMAC_BASE (0xb000da00)
|
||||||
|
+#define BCM_6362_ENETDMAS_BASE (0xb000dc00)
|
||||||
|
+#define BCM_6362_ENETSW_BASE (0xb0e00000)
|
||||||
|
+#define BCM_6362_EHCI0_BASE (0xb0002500)
|
||||||
|
+#define BCM_6362_SDRAM_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6362_MEMC_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6362_DDR_BASE (0xb0003000)
|
||||||
|
+#define BCM_6362_M2M_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6362_ATM_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6362_XTM_BASE (0xb0007800)
|
||||||
|
+#define BCM_6362_XTMDMA_BASE (0xb000b800)
|
||||||
|
+#define BCM_6362_XTMDMAC_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6362_XTMDMAS_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6362_PCM_BASE (0xb000a800)
|
||||||
|
+#define BCM_6362_PCMDMA_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6362_PCMDMAC_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6362_PCMDMAS_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6362_RNG_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6362_MISC_BASE (0xb0001800)
|
||||||
|
+
|
||||||
|
+#define BCM_6362_NAND_REG_BASE (0xb0000200)
|
||||||
|
+#define BCM_6362_NAND_CACHE_BASE (0xb0000600)
|
||||||
|
+#define BCM_6362_LED_BASE (0xb0001900)
|
||||||
|
+#define BCM_6362_IPSEC_BASE (0xb0002800)
|
||||||
|
+#define BCM_6362_IPSEC_DMA_BASE (0xb000d000)
|
||||||
|
+#define BCM_6362_WLAN_CHIPCOMMON_BASE (0xb0004000)
|
||||||
|
+#define BCM_6362_WLAN_D11_BASE (0xb0005000)
|
||||||
|
+#define BCM_6362_WLAN_SHIM_BASE (0xb0007000)
|
||||||
|
+
|
||||||
|
+/*
|
||||||
|
* 6368 register sets base address
|
||||||
|
*/
|
||||||
|
#define BCM_6368_DSL_LMEM_BASE (0xdeadbeef)
|
||||||
|
@@ -557,6 +628,9 @@ static inline unsigned long bcm63xx_regs
|
||||||
|
#ifdef CONFIG_BCM63XX_CPU_6358
|
||||||
|
__GEN_RSET(6358)
|
||||||
|
#endif
|
||||||
|
+#ifdef CONFIG_BCM63XX_CPU_6362
|
||||||
|
+ __GEN_RSET(6362)
|
||||||
|
+#endif
|
||||||
|
#ifdef CONFIG_BCM63XX_CPU_6368
|
||||||
|
__GEN_RSET(6368)
|
||||||
|
#endif
|
||||||
|
@@ -777,6 +851,71 @@ enum bcm63xx_irq {
|
||||||
|
#define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
|
||||||
|
|
||||||
|
/*
|
||||||
|
+ * 6362 irqs
|
||||||
|
+ */
|
||||||
|
+#define BCM_6362_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
|
||||||
|
+
|
||||||
|
+#define BCM_6362_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
|
||||||
|
+#define BCM_6362_SPI_IRQ (IRQ_INTERNAL_BASE + 2)
|
||||||
|
+#define BCM_6362_UART0_IRQ (IRQ_INTERNAL_BASE + 3)
|
||||||
|
+#define BCM_6362_UART1_IRQ (IRQ_INTERNAL_BASE + 4)
|
||||||
|
+#define BCM_6362_DSL_IRQ (IRQ_INTERNAL_BASE + 28)
|
||||||
|
+#define BCM_6362_UDC0_IRQ 0
|
||||||
|
+#define BCM_6362_ENET0_IRQ 0
|
||||||
|
+#define BCM_6362_ENET1_IRQ 0
|
||||||
|
+#define BCM_6362_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 14)
|
||||||
|
+#define BCM_6362_HSSPI_IRQ (IRQ_INTERNAL_BASE + 5)
|
||||||
|
+#define BCM_6362_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
|
||||||
|
+#define BCM_6362_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
|
||||||
|
+#define BCM_6362_USBD_IRQ (IRQ_INTERNAL_BASE + 11)
|
||||||
|
+#define BCM_6362_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 20)
|
||||||
|
+#define BCM_6362_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 21)
|
||||||
|
+#define BCM_6362_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 22)
|
||||||
|
+#define BCM_6362_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 23)
|
||||||
|
+#define BCM_6362_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 24)
|
||||||
|
+#define BCM_6362_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 25)
|
||||||
|
+#define BCM_6362_PCMCIA_IRQ 0
|
||||||
|
+#define BCM_6362_ENET0_RXDMA_IRQ 0
|
||||||
|
+#define BCM_6362_ENET0_TXDMA_IRQ 0
|
||||||
|
+#define BCM_6362_ENET1_RXDMA_IRQ 0
|
||||||
|
+#define BCM_6362_ENET1_TXDMA_IRQ 0
|
||||||
|
+#define BCM_6362_PCI_IRQ (IRQ_INTERNAL_BASE + 30)
|
||||||
|
+#define BCM_6362_ATM_IRQ 0
|
||||||
|
+#define BCM_6362_ENETSW_RXDMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 0)
|
||||||
|
+#define BCM_6362_ENETSW_RXDMA1_IRQ (BCM_6362_HIGH_IRQ_BASE + 1)
|
||||||
|
+#define BCM_6362_ENETSW_RXDMA2_IRQ (BCM_6362_HIGH_IRQ_BASE + 2)
|
||||||
|
+#define BCM_6362_ENETSW_RXDMA3_IRQ (BCM_6362_HIGH_IRQ_BASE + 3)
|
||||||
|
+#define BCM_6362_ENETSW_TXDMA0_IRQ 0
|
||||||
|
+#define BCM_6362_ENETSW_TXDMA1_IRQ 0
|
||||||
|
+#define BCM_6362_ENETSW_TXDMA2_IRQ 0
|
||||||
|
+#define BCM_6362_ENETSW_TXDMA3_IRQ 0
|
||||||
|
+#define BCM_6362_XTM_IRQ 0
|
||||||
|
+#define BCM_6362_XTM_DMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 12)
|
||||||
|
+
|
||||||
|
+#define BCM_6362_RING_OSC_IRQ (IRQ_INTERNAL_BASE + 1)
|
||||||
|
+#define BCM_6362_WLAN_GPIO_IRQ (IRQ_INTERNAL_BASE + 6)
|
||||||
|
+#define BCM_6362_WLAN_IRQ (IRQ_INTERNAL_BASE + 7)
|
||||||
|
+#define BCM_6362_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8)
|
||||||
|
+#define BCM_6362_NAND_IRQ (IRQ_INTERNAL_BASE + 12)
|
||||||
|
+#define BCM_6362_PCM_IRQ (IRQ_INTERNAL_BASE + 13)
|
||||||
|
+#define BCM_6362_DG_IRQ (IRQ_INTERNAL_BASE + 15)
|
||||||
|
+#define BCM_6362_EPHY_ENERGY0_IRQ (IRQ_INTERNAL_BASE + 16)
|
||||||
|
+#define BCM_6362_EPHY_ENERGY1_IRQ (IRQ_INTERNAL_BASE + 17)
|
||||||
|
+#define BCM_6362_EPHY_ENERGY2_IRQ (IRQ_INTERNAL_BASE + 18)
|
||||||
|
+#define BCM_6362_EPHY_ENERGY3_IRQ (IRQ_INTERNAL_BASE + 19)
|
||||||
|
+#define BCM_6362_IPSEC_DMA0_IRQ (IRQ_INTERNAL_BASE + 26)
|
||||||
|
+#define BCM_6362_IPSEC_DMA1_IRQ (IRQ_INTERNAL_BASE + 27)
|
||||||
|
+#define BCM_6362_FAP0_IRQ (IRQ_INTERNAL_BASE + 29)
|
||||||
|
+#define BCM_6362_PCM_DMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 4)
|
||||||
|
+#define BCM_6362_PCM_DMA1_IRQ (BCM_6362_HIGH_IRQ_BASE + 5)
|
||||||
|
+#define BCM_6362_DECT0_IRQ (BCM_6362_HIGH_IRQ_BASE + 6)
|
||||||
|
+#define BCM_6362_DECT1_IRQ (BCM_6362_HIGH_IRQ_BASE + 7)
|
||||||
|
+#define BCM_6362_EXT_IRQ0 (BCM_6362_HIGH_IRQ_BASE + 8)
|
||||||
|
+#define BCM_6362_EXT_IRQ1 (BCM_6362_HIGH_IRQ_BASE + 9)
|
||||||
|
+#define BCM_6362_EXT_IRQ2 (BCM_6362_HIGH_IRQ_BASE + 10)
|
||||||
|
+#define BCM_6362_EXT_IRQ3 (BCM_6362_HIGH_IRQ_BASE + 11)
|
||||||
|
+
|
||||||
|
+/*
|
||||||
|
* 6368 irqs
|
||||||
|
*/
|
||||||
|
#define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
|
||||||
|
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
|
||||||
|
@@ -17,6 +17,8 @@ static inline unsigned long bcm63xx_gpio
|
||||||
|
return 8;
|
||||||
|
case BCM6345_CPU_ID:
|
||||||
|
return 16;
|
||||||
|
+ case BCM6362_CPU_ID:
|
||||||
|
+ return 48;
|
||||||
|
case BCM6368_CPU_ID:
|
||||||
|
return 38;
|
||||||
|
case BCM6348_CPU_ID:
|
||||||
|
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||||
|
@@ -107,6 +107,39 @@
|
||||||
|
CKCTL_6358_USBSU_EN | \
|
||||||
|
CKCTL_6358_EPHY_EN)
|
||||||
|
|
||||||
|
+#define CKCTL_6362_ADSL_QPROC_EN (1 << 1)
|
||||||
|
+#define CKCTL_6362_ADSL_AFE_EN (1 << 2)
|
||||||
|
+#define CKCTL_6362_ADSL_EN (1 << 3)
|
||||||
|
+#define CKCTL_6362_MIPS_EN (1 << 4)
|
||||||
|
+#define CKCTL_6362_WLAN_OCP_EN (1 << 5)
|
||||||
|
+#define CKCTL_6362_SWPKT_USB_EN (1 << 7)
|
||||||
|
+#define CKCTL_6362_SWPKT_SAR_EN (1 << 8)
|
||||||
|
+#define CKCTL_6362_SAR_EN (1 << 9)
|
||||||
|
+#define CKCTL_6362_ROBOSW_EN (1 << 10)
|
||||||
|
+#define CKCTL_6362_PCM_EN (1 << 11)
|
||||||
|
+#define CKCTL_6362_USBD_EN (1 << 12)
|
||||||
|
+#define CKCTL_6362_USBH_EN (1 << 13)
|
||||||
|
+#define CKCTL_6362_IPSEC_EN (1 << 14)
|
||||||
|
+#define CKCTL_6362_SPI_EN (1 << 15)
|
||||||
|
+#define CKCTL_6362_HSSPI_EN (1 << 16)
|
||||||
|
+#define CKCTL_6362_PCIE_EN (1 << 17)
|
||||||
|
+#define CKCTL_6362_FAP_EN (1 << 18)
|
||||||
|
+#define CKCTL_6362_PHYMIPS_EN (1 << 19)
|
||||||
|
+#define CKCTL_6362_NAND_EN (1 << 20)
|
||||||
|
+
|
||||||
|
+#define CKCTL_6362_ALL_SAFE_EN (CKCTL_6362_PHYMIPS_EN | \
|
||||||
|
+ CKCTL_6362_ADSL_QPROC_EN | \
|
||||||
|
+ CKCTL_6362_ADSL_AFE_EN | \
|
||||||
|
+ CKCTL_6362_ADSL_EN | \
|
||||||
|
+ CKCTL_6362_SAR_EN | \
|
||||||
|
+ CKCTL_6362_PCM_EN | \
|
||||||
|
+ CKCTL_6362_IPSEC_EN | \
|
||||||
|
+ CKCTL_6362_USBD_EN | \
|
||||||
|
+ CKCTL_6362_USBH_EN | \
|
||||||
|
+ CKCTL_6362_ROBOSW_EN | \
|
||||||
|
+ CKCTL_6362_PCIE_EN)
|
||||||
|
+
|
||||||
|
+
|
||||||
|
#define CKCTL_6368_VDSL_QPROC_EN (1 << 2)
|
||||||
|
#define CKCTL_6368_VDSL_AFE_EN (1 << 3)
|
||||||
|
#define CKCTL_6368_VDSL_BONDING_EN (1 << 4)
|
||||||
|
@@ -148,6 +181,7 @@
|
||||||
|
#define PERF_IRQMASK_6345_REG 0xc
|
||||||
|
#define PERF_IRQMASK_6348_REG 0xc
|
||||||
|
#define PERF_IRQMASK_6358_REG 0xc
|
||||||
|
+#define PERF_IRQMASK_6362_REG 0x20
|
||||||
|
#define PERF_IRQMASK_6368_REG 0x20
|
||||||
|
|
||||||
|
/* Interrupt Status register */
|
||||||
|
@@ -156,6 +190,7 @@
|
||||||
|
#define PERF_IRQSTAT_6345_REG 0x10
|
||||||
|
#define PERF_IRQSTAT_6348_REG 0x10
|
||||||
|
#define PERF_IRQSTAT_6358_REG 0x10
|
||||||
|
+#define PERF_IRQSTAT_6362_REG 0x28
|
||||||
|
#define PERF_IRQSTAT_6368_REG 0x28
|
||||||
|
|
||||||
|
/* External Interrupt Configuration register */
|
||||||
|
@@ -164,6 +199,7 @@
|
||||||
|
#define PERF_EXTIRQ_CFG_REG_6345 0x14
|
||||||
|
#define PERF_EXTIRQ_CFG_REG_6348 0x14
|
||||||
|
#define PERF_EXTIRQ_CFG_REG_6358 0x14
|
||||||
|
+#define PERF_EXTIRQ_CFG_REG_6362 0x18
|
||||||
|
#define PERF_EXTIRQ_CFG_REG_6368 0x18
|
||||||
|
|
||||||
|
#define PERF_EXTIRQ_CFG_REG2_6368 0x1c
|
||||||
|
@@ -191,6 +227,7 @@
|
||||||
|
/* Soft Reset register */
|
||||||
|
#define PERF_SOFTRESET_REG 0x28
|
||||||
|
#define PERF_SOFTRESET_6328_REG 0x10
|
||||||
|
+#define PERF_SOFTRESET_6362_REG 0x10
|
||||||
|
#define PERF_SOFTRESET_6368_REG 0x10
|
||||||
|
|
||||||
|
#define SOFTRESET_6328_SPI_MASK (1 << 0)
|
||||||
|
@@ -244,6 +281,22 @@
|
||||||
|
SOFTRESET_6348_ACLC_MASK | \
|
||||||
|
SOFTRESET_6348_ADSLMIPSPLL_MASK)
|
||||||
|
|
||||||
|
+#define SOFTRESET_6362_SPI_MASK (1 << 0)
|
||||||
|
+#define SOFTRESET_6362_IPSEC_MASK (1 << 1)
|
||||||
|
+#define SOFTRESET_6362_EPHY_MASK (1 << 2)
|
||||||
|
+#define SOFTRESET_6362_SAR_MASK (1 << 3)
|
||||||
|
+#define SOFTRESET_6362_ENETSW_MASK (1 << 4)
|
||||||
|
+#define SOFTRESET_6362_USBS_MASK (1 << 5)
|
||||||
|
+#define SOFTRESET_6362_USBH_MASK (1 << 6)
|
||||||
|
+#define SOFTRESET_6362_PCM_MASK (1 << 7)
|
||||||
|
+#define SOFTRESET_6362_PCIE_CORE_MASK (1 << 8)
|
||||||
|
+#define SOFTRESET_6362_PCIE_MASK (1 << 9)
|
||||||
|
+#define SOFTRESET_6362_PCIE_EXT_MASK (1 << 10)
|
||||||
|
+#define SOFTRESET_6362_WLAN_SHIM_MASK (1 << 11)
|
||||||
|
+#define SOFTRESET_6362_DDR_PHY_MASK (1 << 12)
|
||||||
|
+#define SOFTRESET_6362_FAP_MASK (1 << 13)
|
||||||
|
+#define SOFTRESET_6362_WLAN_UBUS_MASK (1 << 14)
|
||||||
|
+
|
||||||
|
#define SOFTRESET_6368_SPI_MASK (1 << 0)
|
||||||
|
#define SOFTRESET_6368_MPI_MASK (1 << 3)
|
||||||
|
#define SOFTRESET_6368_EPHY_MASK (1 << 6)
|
||||||
|
@@ -1174,6 +1227,12 @@
|
||||||
|
#define SERDES_PCIE_EN (1 << 0)
|
||||||
|
#define SERDES_PCIE_EXD_EN (1 << 15)
|
||||||
|
|
||||||
|
+#define MISC_STRAPBUS_6362_REG 0x14
|
||||||
|
+#define STRAPBUS_6362_FCVO_SHIFT 1
|
||||||
|
+#define STRAPBUS_6362_FCVO_MASK (0x1f << STRAPBUS_6362_FCVO_SHIFT)
|
||||||
|
+#define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15)
|
||||||
|
+#define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15)
|
||||||
|
+
|
||||||
|
#define MISC_STRAPBUS_6328_REG 0x240
|
||||||
|
#define STRAPBUS_6328_FCVO_SHIFT 7
|
||||||
|
#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
|
||||||
|
--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
|
||||||
|
@@ -19,6 +19,7 @@ static inline int is_bcm63xx_internal_re
|
||||||
|
return 1;
|
||||||
|
break;
|
||||||
|
case BCM6328_CPU_ID:
|
||||||
|
+ case BCM6362_CPU_ID:
|
||||||
|
case BCM6368_CPU_ID:
|
||||||
|
if (offset >= 0xb0000000 && offset < 0xb1000000)
|
||||||
|
return 1;
|
||||||
@ -0,0 +1,110 @@
|
|||||||
|
From e49546bf3f255f028d0877ceeb7ed6466fe37d8a Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jonas Gorski <jonas.gorski@gmail.com>
|
||||||
|
Date: Mon, 21 Nov 2011 00:53:26 +0100
|
||||||
|
Subject: [PATCH 56/84] MIPS: BCM63XX: enable pcie for BCM6362
|
||||||
|
|
||||||
|
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
|
||||||
|
---
|
||||||
|
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 3 +-
|
||||||
|
arch/mips/pci/pci-bcm63xx.c | 57 +++++++++++++++------
|
||||||
|
2 files changed, 44 insertions(+), 16 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||||
|
@@ -1223,7 +1223,8 @@
|
||||||
|
/*************************************************************************
|
||||||
|
* _REG relative to RSET_MISC
|
||||||
|
*************************************************************************/
|
||||||
|
-#define MISC_SERDES_CTRL_REG 0x0
|
||||||
|
+#define MISC_SERDES_CTRL_6328_REG 0x0
|
||||||
|
+#define MISC_SERDES_CTRL_6362_REG 0x4
|
||||||
|
#define SERDES_PCIE_EN (1 << 0)
|
||||||
|
#define SERDES_PCIE_EXD_EN (1 << 15)
|
||||||
|
|
||||||
|
--- a/arch/mips/pci/pci-bcm63xx.c
|
||||||
|
+++ b/arch/mips/pci/pci-bcm63xx.c
|
||||||
|
@@ -118,35 +118,61 @@ void __iomem *pci_iospace_start;
|
||||||
|
static void __init bcm63xx_reset_pcie(void)
|
||||||
|
{
|
||||||
|
u32 val;
|
||||||
|
+ u32 reg;
|
||||||
|
+ u32 mask;
|
||||||
|
|
||||||
|
/* enable clock */
|
||||||
|
+
|
||||||
|
+ if (BCMCPU_IS_6328())
|
||||||
|
+ mask = CKCTL_6328_PCIE_EN;
|
||||||
|
+ else
|
||||||
|
+ mask = CKCTL_6362_PCIE_EN;
|
||||||
|
+
|
||||||
|
val = bcm_perf_readl(PERF_CKCTL_REG);
|
||||||
|
- val |= CKCTL_6328_PCIE_EN;
|
||||||
|
+ val |= mask;
|
||||||
|
bcm_perf_writel(val, PERF_CKCTL_REG);
|
||||||
|
|
||||||
|
/* enable SERDES */
|
||||||
|
- val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
|
||||||
|
+
|
||||||
|
+ if (BCMCPU_IS_6328())
|
||||||
|
+ reg = MISC_SERDES_CTRL_6328_REG;
|
||||||
|
+ else
|
||||||
|
+ reg = MISC_SERDES_CTRL_6362_REG;
|
||||||
|
+
|
||||||
|
+ val = bcm_misc_readl(reg);
|
||||||
|
val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
|
||||||
|
- bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
|
||||||
|
+ bcm_misc_writel(val, reg);
|
||||||
|
|
||||||
|
/* reset the PCIe core */
|
||||||
|
- val = bcm_perf_readl(PERF_SOFTRESET_6328_REG);
|
||||||
|
+ if (BCMCPU_IS_6328()) {
|
||||||
|
+ reg = PERF_SOFTRESET_6328_REG;
|
||||||
|
+ mask = SOFTRESET_6328_PCIE_MASK | SOFTRESET_6328_PCIE_CORE_MASK
|
||||||
|
+ | SOFTRESET_6328_PCIE_HARD_MASK;
|
||||||
|
+ } else {
|
||||||
|
+ reg = PERF_SOFTRESET_6362_REG;
|
||||||
|
+ mask = SOFTRESET_6362_PCIE_MASK | SOFTRESET_6362_PCIE_CORE_MASK;
|
||||||
|
+ }
|
||||||
|
+ val = bcm_perf_readl(reg);
|
||||||
|
+ val &= ~mask;
|
||||||
|
+
|
||||||
|
+ if (BCMCPU_IS_6328())
|
||||||
|
+ val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
|
||||||
|
+ else
|
||||||
|
+ val &= ~SOFTRESET_6362_PCIE_EXT_MASK;
|
||||||
|
|
||||||
|
- val &= ~SOFTRESET_6328_PCIE_MASK;
|
||||||
|
- val &= ~SOFTRESET_6328_PCIE_CORE_MASK;
|
||||||
|
- val &= ~SOFTRESET_6328_PCIE_HARD_MASK;
|
||||||
|
- val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
|
||||||
|
- bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
|
||||||
|
+ bcm_perf_writel(val, reg);
|
||||||
|
mdelay(10);
|
||||||
|
|
||||||
|
- val |= SOFTRESET_6328_PCIE_MASK;
|
||||||
|
- val |= SOFTRESET_6328_PCIE_CORE_MASK;
|
||||||
|
- val |= SOFTRESET_6328_PCIE_HARD_MASK;
|
||||||
|
- bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
|
||||||
|
+ val |= mask;
|
||||||
|
+ bcm_perf_writel(val, reg);
|
||||||
|
mdelay(10);
|
||||||
|
|
||||||
|
- val |= SOFTRESET_6328_PCIE_EXT_MASK;
|
||||||
|
- bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
|
||||||
|
+ if (BCMCPU_IS_6328())
|
||||||
|
+ val |= SOFTRESET_6328_PCIE_EXT_MASK;
|
||||||
|
+ else
|
||||||
|
+ val |= SOFTRESET_6362_PCIE_EXT_MASK;
|
||||||
|
+
|
||||||
|
+ bcm_perf_writel(val, reg);
|
||||||
|
mdelay(200);
|
||||||
|
}
|
||||||
|
|
||||||
|
@@ -332,6 +358,7 @@ static int __init bcm63xx_pci_init(void)
|
||||||
|
|
||||||
|
switch (bcm63xx_get_cpu_id()) {
|
||||||
|
case BCM6328_CPU_ID:
|
||||||
|
+ case BCM6362_CPU_ID:
|
||||||
|
return bcm63xx_register_pcie();
|
||||||
|
case BCM6348_CPU_ID:
|
||||||
|
case BCM6358_CPU_ID:
|
||||||
@ -15,7 +15,7 @@ Subject: [PATCH 24/63] MIPS: BCM63XX: register ohci device.
|
|||||||
|
|
||||||
--- a/arch/mips/bcm63xx/Kconfig
|
--- a/arch/mips/bcm63xx/Kconfig
|
||||||
+++ b/arch/mips/bcm63xx/Kconfig
|
+++ b/arch/mips/bcm63xx/Kconfig
|
||||||
@@ -8,26 +8,25 @@ config BCM63XX_CPU_6328
|
@@ -8,22 +8,20 @@ config BCM63XX_CPU_6328
|
||||||
config BCM63XX_CPU_6338
|
config BCM63XX_CPU_6338
|
||||||
bool "support 6338 CPU"
|
bool "support 6338 CPU"
|
||||||
select HW_HAS_PCI
|
select HW_HAS_PCI
|
||||||
@ -39,6 +39,9 @@ Subject: [PATCH 24/63] MIPS: BCM63XX: register ohci device.
|
|||||||
select HW_HAS_PCI
|
select HW_HAS_PCI
|
||||||
+ select USB_ARCH_HAS_OHCI if USB_SUPPORT
|
+ select USB_ARCH_HAS_OHCI if USB_SUPPORT
|
||||||
|
|
||||||
|
config BCM63XX_CPU_6362
|
||||||
|
bool "support 6362 CPU"
|
||||||
|
@@ -32,6 +30,7 @@ config BCM63XX_CPU_6362
|
||||||
config BCM63XX_CPU_6368
|
config BCM63XX_CPU_6368
|
||||||
bool "support 6368 CPU"
|
bool "support 6368 CPU"
|
||||||
select HW_HAS_PCI
|
select HW_HAS_PCI
|
||||||
|
|||||||
@ -15,13 +15,15 @@ Subject: [PATCH 26/63] MIPS: BCM63XX: register ehci device.
|
|||||||
|
|
||||||
--- a/arch/mips/bcm63xx/Kconfig
|
--- a/arch/mips/bcm63xx/Kconfig
|
||||||
+++ b/arch/mips/bcm63xx/Kconfig
|
+++ b/arch/mips/bcm63xx/Kconfig
|
||||||
@@ -22,11 +22,13 @@ config BCM63XX_CPU_6358
|
@@ -22,6 +22,7 @@ config BCM63XX_CPU_6358
|
||||||
bool "support 6358 CPU"
|
bool "support 6358 CPU"
|
||||||
select HW_HAS_PCI
|
select HW_HAS_PCI
|
||||||
select USB_ARCH_HAS_OHCI if USB_SUPPORT
|
select USB_ARCH_HAS_OHCI if USB_SUPPORT
|
||||||
+ select USB_ARCH_HAS_EHCI if USB_SUPPORT
|
+ select USB_ARCH_HAS_EHCI if USB_SUPPORT
|
||||||
|
|
||||||
config BCM63XX_CPU_6368
|
config BCM63XX_CPU_6362
|
||||||
|
bool "support 6362 CPU"
|
||||||
|
@@ -31,6 +32,7 @@ config BCM63XX_CPU_6368
|
||||||
bool "support 6368 CPU"
|
bool "support 6368 CPU"
|
||||||
select HW_HAS_PCI
|
select HW_HAS_PCI
|
||||||
select USB_ARCH_HAS_OHCI if USB_SUPPORT
|
select USB_ARCH_HAS_OHCI if USB_SUPPORT
|
||||||
|
|||||||
@ -11,7 +11,7 @@
|
|||||||
bcm_gpio_writel(val, GPIO_MODE_REG);
|
bcm_gpio_writel(val, GPIO_MODE_REG);
|
||||||
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||||
@@ -510,6 +510,8 @@
|
@@ -563,6 +563,8 @@
|
||||||
#define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
|
#define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
|
||||||
#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
|
#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
|
||||||
#define GPIO_MODE_6358_UTOPIA (1 << 12)
|
#define GPIO_MODE_6358_UTOPIA (1 << 12)
|
||||||
|
|||||||
@ -50,7 +50,7 @@ Subject: [PATCH 30/63] bcm63xx_enet: split dma registers access.
|
|||||||
if (ret)
|
if (ret)
|
||||||
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
|
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
|
||||||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
|
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
|
||||||
@@ -157,7 +157,9 @@ enum bcm63xx_regs_set {
|
@@ -172,7 +172,9 @@ enum bcm63xx_regs_set {
|
||||||
#define BCM_6358_RSET_SPI_SIZE 1804
|
#define BCM_6358_RSET_SPI_SIZE 1804
|
||||||
#define BCM_6368_RSET_SPI_SIZE 1804
|
#define BCM_6368_RSET_SPI_SIZE 1804
|
||||||
#define RSET_ENET_SIZE 2048
|
#define RSET_ENET_SIZE 2048
|
||||||
|
|||||||
@ -205,7 +205,7 @@ Subject: [PATCH 31/63] bcm63xx_enet: add support for bcm6368 internal ethernet s
|
|||||||
#endif /* ! BCM63XX_DEV_ENET_H_ */
|
#endif /* ! BCM63XX_DEV_ENET_H_ */
|
||||||
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||||
@@ -750,10 +750,60 @@
|
@@ -803,10 +803,60 @@
|
||||||
* _REG relative to RSET_ENETSW
|
* _REG relative to RSET_ENETSW
|
||||||
*************************************************************************/
|
*************************************************************************/
|
||||||
|
|
||||||
|
|||||||
@ -10,7 +10,7 @@ Subject: [PATCH 54/81] bcm63xx_enet: enable rgmii clock on external ports
|
|||||||
|
|
||||||
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||||
@@ -779,6 +779,19 @@
|
@@ -832,6 +832,19 @@
|
||||||
#define ENETSW_PORTOV_FDX_MASK (1 << 1)
|
#define ENETSW_PORTOV_FDX_MASK (1 << 1)
|
||||||
#define ENETSW_PORTOV_LINKUP_MASK (1 << 0)
|
#define ENETSW_PORTOV_LINKUP_MASK (1 << 0)
|
||||||
|
|
||||||
|
|||||||
@ -84,7 +84,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
|
|||||||
return -ENODEV;
|
return -ENODEV;
|
||||||
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||||
@@ -555,6 +555,7 @@
|
@@ -608,6 +608,7 @@
|
||||||
#define GPIO_STRAPBUS_REG 0x40
|
#define GPIO_STRAPBUS_REG 0x40
|
||||||
#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
|
#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
|
||||||
#define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
|
#define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
|
||||||
@ -92,8 +92,8 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
|
|||||||
#define STRAPBUS_6368_BOOT_SEL_MASK 0x3
|
#define STRAPBUS_6368_BOOT_SEL_MASK 0x3
|
||||||
#define STRAPBUS_6368_BOOT_SEL_NAND 0
|
#define STRAPBUS_6368_BOOT_SEL_NAND 0
|
||||||
#define STRAPBUS_6368_BOOT_SEL_SERIAL 1
|
#define STRAPBUS_6368_BOOT_SEL_SERIAL 1
|
||||||
@@ -1240,6 +1241,7 @@
|
@@ -1300,6 +1301,7 @@
|
||||||
#define SERDES_PCIE_EXD_EN (1 << 15)
|
#define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15)
|
||||||
|
|
||||||
#define MISC_STRAPBUS_6328_REG 0x240
|
#define MISC_STRAPBUS_6328_REG 0x240
|
||||||
+#define STRAPBUS_6328_HSSPI_CLK_FAST (1 << 4)
|
+#define STRAPBUS_6328_HSSPI_CLK_FAST (1 << 4)
|
||||||
|
|||||||
@ -0,0 +1,50 @@
|
|||||||
|
From d9666553a10ea85ea64e3e8784a42167a1709ed5 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jonas Gorski <jonas.gorski@gmail.com>
|
||||||
|
Date: Mon, 21 Nov 2011 00:48:52 +0100
|
||||||
|
Subject: [PATCH 55/84] MIPS: BCM63XX: add flash detection for BCM6362
|
||||||
|
|
||||||
|
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
|
||||||
|
---
|
||||||
|
arch/mips/bcm63xx/dev-flash.c | 13 ++++++++++++-
|
||||||
|
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 1 +
|
||||||
|
2 files changed, 13 insertions(+), 1 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/bcm63xx/dev-flash.c
|
||||||
|
+++ b/arch/mips/bcm63xx/dev-flash.c
|
||||||
|
@@ -100,6 +100,17 @@ static int __init bcm63xx_detect_flash_t
|
||||||
|
return BCM63XX_FLASH_TYPE_PARALLEL;
|
||||||
|
else
|
||||||
|
return BCM63XX_FLASH_TYPE_SERIAL;
|
||||||
|
+ case BCM6362_CPU_ID:
|
||||||
|
+ val = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
|
||||||
|
+ if (val & STRAPBUS_6362_HSSPI_CLK_FAST)
|
||||||
|
+ bcm63xx_spi_flash_info[0].max_speed_hz = 50000000;
|
||||||
|
+ else
|
||||||
|
+ bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
|
||||||
|
+
|
||||||
|
+ if (val & STRAPBUS_6362_BOOT_SEL_SERIAL)
|
||||||
|
+ return BCM63XX_FLASH_TYPE_SERIAL;
|
||||||
|
+ else
|
||||||
|
+ return BCM63XX_FLASH_TYPE_NAND;
|
||||||
|
case BCM6368_CPU_ID:
|
||||||
|
val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
|
||||||
|
if (val & STRAPBUS_6368_SPI_CLK_FAST)
|
||||||
|
@@ -136,7 +147,7 @@ int __init bcm63xx_flash_register(void)
|
||||||
|
|
||||||
|
return platform_device_register(&mtd_dev);
|
||||||
|
case BCM63XX_FLASH_TYPE_SERIAL:
|
||||||
|
- if (BCMCPU_IS_6328())
|
||||||
|
+ if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
|
||||||
|
bcm63xx_flash_data.max_transfer_len = HSSPI_BUFFER_LEN;
|
||||||
|
|
||||||
|
return spi_register_board_info(bcm63xx_spi_flash_info,
|
||||||
|
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||||
|
@@ -1296,6 +1296,7 @@
|
||||||
|
|
||||||
|
#define MISC_STRAPBUS_6362_REG 0x14
|
||||||
|
#define STRAPBUS_6362_FCVO_SHIFT 1
|
||||||
|
+#define STRAPBUS_6362_HSSPI_CLK_FAST (1 << 13)
|
||||||
|
#define STRAPBUS_6362_FCVO_MASK (0x1f << STRAPBUS_6362_FCVO_SHIFT)
|
||||||
|
#define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15)
|
||||||
|
#define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15)
|
||||||
@ -44,11 +44,24 @@ Subject: [PATCH 38/59] MIPS: BCM63XX: store the flash type in global variable
|
|||||||
else
|
else
|
||||||
- return BCM63XX_FLASH_TYPE_SERIAL;
|
- return BCM63XX_FLASH_TYPE_SERIAL;
|
||||||
+ bcm63xx_attached_flash = BCM63XX_FLASH_TYPE_SERIAL;
|
+ bcm63xx_attached_flash = BCM63XX_FLASH_TYPE_SERIAL;
|
||||||
|
+ break;
|
||||||
|
case BCM6362_CPU_ID:
|
||||||
|
val = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
|
||||||
|
if (val & STRAPBUS_6362_HSSPI_CLK_FAST)
|
||||||
|
@@ -108,9 +113,10 @@ static int __init bcm63xx_detect_flash_t
|
||||||
|
bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
|
||||||
|
|
||||||
|
if (val & STRAPBUS_6362_BOOT_SEL_SERIAL)
|
||||||
|
- return BCM63XX_FLASH_TYPE_SERIAL;
|
||||||
|
+ bcm63xx_attached_flash = BCM63XX_FLASH_TYPE_SERIAL;
|
||||||
|
else
|
||||||
|
- return BCM63XX_FLASH_TYPE_NAND;
|
||||||
|
+ bcm63xx_attached_flash = BCM63XX_FLASH_TYPE_NAND;
|
||||||
+ break;
|
+ break;
|
||||||
case BCM6368_CPU_ID:
|
case BCM6368_CPU_ID:
|
||||||
val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
|
val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
|
||||||
if (val & STRAPBUS_6368_SPI_CLK_FAST)
|
if (val & STRAPBUS_6368_SPI_CLK_FAST)
|
||||||
@@ -107,25 +112,32 @@ static int __init bcm63xx_detect_flash_t
|
@@ -118,25 +124,32 @@ static int __init bcm63xx_detect_flash_t
|
||||||
|
|
||||||
switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
|
switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
|
||||||
case STRAPBUS_6368_BOOT_SEL_NAND:
|
case STRAPBUS_6368_BOOT_SEL_NAND:
|
||||||
@ -87,7 +100,7 @@ Subject: [PATCH 38/59] MIPS: BCM63XX: store the flash type in global variable
|
|||||||
case BCM63XX_FLASH_TYPE_PARALLEL:
|
case BCM63XX_FLASH_TYPE_PARALLEL:
|
||||||
/* read base address of boot chip select (0) */
|
/* read base address of boot chip select (0) */
|
||||||
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
|
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
|
||||||
@@ -146,7 +158,7 @@ int __init bcm63xx_flash_register(void)
|
@@ -157,7 +170,7 @@ int __init bcm63xx_flash_register(void)
|
||||||
return -ENODEV;
|
return -ENODEV;
|
||||||
default:
|
default:
|
||||||
pr_err("flash detection failed for BCM%x: %d\n",
|
pr_err("flash detection failed for BCM%x: %d\n",
|
||||||
|
|||||||
@ -46,7 +46,7 @@ Subject: [PATCH 69/80] MIPS: BCM63XX: pass caldata info to flash
|
|||||||
};
|
};
|
||||||
|
|
||||||
static struct spi_board_info bcm63xx_spi_flash_info[] = {
|
static struct spi_board_info bcm63xx_spi_flash_info[] = {
|
||||||
@@ -130,10 +134,13 @@ static int __init bcm63xx_detect_flash_t
|
@@ -142,10 +146,13 @@ static int __init bcm63xx_detect_flash_t
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
@ -0,0 +1,56 @@
|
|||||||
|
From ed225910f0e062d9c28d5cf216f97b3cf457a8c5 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jonas Gorski <jonas.gorski@gmail.com>
|
||||||
|
Date: Mon, 21 Nov 2011 00:55:49 +0100
|
||||||
|
Subject: [PATCH 58/81] MIPS: BCM63XX: wire up the HS SPI controller for BCM6362
|
||||||
|
|
||||||
|
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
|
||||||
|
---
|
||||||
|
arch/mips/bcm63xx/clk.c | 2 ++
|
||||||
|
arch/mips/bcm63xx/dev-hsspi.c | 7 +++++--
|
||||||
|
.../include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h | 1 +
|
||||||
|
3 files changed, 8 insertions(+), 2 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/bcm63xx/clk.c
|
||||||
|
+++ b/arch/mips/bcm63xx/clk.c
|
||||||
|
@@ -218,6 +218,8 @@ static void hsspi_set(struct clk *clk, i
|
||||||
|
|
||||||
|
if (BCMCPU_IS_6328())
|
||||||
|
mask = CKCTL_6328_HSSPI_EN;
|
||||||
|
+ else if (BCMCPU_IS_6362())
|
||||||
|
+ mask = CKCTL_6362_HSSPI_EN;
|
||||||
|
else
|
||||||
|
return;
|
||||||
|
|
||||||
|
--- a/arch/mips/bcm63xx/dev-hsspi.c
|
||||||
|
+++ b/arch/mips/bcm63xx/dev-hsspi.c
|
||||||
|
@@ -43,7 +43,7 @@ static struct platform_device bcm63xx_hs
|
||||||
|
int __init bcm63xx_hsspi_register(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
- if (!BCMCPU_IS_6328())
|
||||||
|
+ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362())
|
||||||
|
return -ENODEV;
|
||||||
|
|
||||||
|
spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI);
|
||||||
|
@@ -51,7 +51,10 @@ int __init bcm63xx_hsspi_register(void)
|
||||||
|
spi_resources[0].end += RSET_HSSPI_SIZE - 1;
|
||||||
|
spi_resources[1].start = bcm63xx_get_irq_number(IRQ_HSSPI);
|
||||||
|
|
||||||
|
- spi_pdata.speed_hz = HSSPI_PLL_HZ_6328;
|
||||||
|
+ if (BCMCPU_IS_6328())
|
||||||
|
+ spi_pdata.speed_hz = HSSPI_PLL_HZ_6328;
|
||||||
|
+ else
|
||||||
|
+ spi_pdata.speed_hz = HSSPI_PLL_HZ;
|
||||||
|
|
||||||
|
return platform_device_register(&bcm63xx_hsspi_device);
|
||||||
|
}
|
||||||
|
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
|
||||||
|
@@ -16,6 +16,7 @@ struct bcm63xx_hsspi_pdata {
|
||||||
|
#define bcm_hsspi_writel(v, o) bcm_rset_writel(RSET_HSSPI, (v), (o))
|
||||||
|
|
||||||
|
#define HSSPI_PLL_HZ_6328 133333333
|
||||||
|
+#define HSSPI_PLL_HZ 400000000
|
||||||
|
|
||||||
|
#define HSSPI_BUFFER_LEN 512
|
||||||
|
|
||||||
@ -0,0 +1,101 @@
|
|||||||
|
From eef84812bc7ffd590da6ad6b83bfeebaa43a7055 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jonas Gorski <jonas.gorski@gmail.com>
|
||||||
|
Date: Thu, 5 Jul 2012 21:19:20 +0200
|
||||||
|
Subject: [PATCH 58/84] MIPS: BCM63XX: enable SPI controller for BCM6362
|
||||||
|
|
||||||
|
---
|
||||||
|
arch/mips/bcm63xx/clk.c | 2 ++
|
||||||
|
arch/mips/bcm63xx/dev-spi.c | 11 ++++++++++-
|
||||||
|
.../include/asm/mach-bcm63xx/bcm63xx_dev_spi.h | 3 +++
|
||||||
|
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 16 ++++++++++++++++
|
||||||
|
4 files changed, 31 insertions(+), 1 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/bcm63xx/clk.c
|
||||||
|
+++ b/arch/mips/bcm63xx/clk.c
|
||||||
|
@@ -199,6 +199,8 @@ static void spi_set(struct clk *clk, int
|
||||||
|
mask = CKCTL_6348_SPI_EN;
|
||||||
|
else if (BCMCPU_IS_6358())
|
||||||
|
mask = CKCTL_6358_SPI_EN;
|
||||||
|
+ else if (BCMCPU_IS_6362())
|
||||||
|
+ mask = CKCTL_6362_SPI_EN;
|
||||||
|
else
|
||||||
|
/* BCMCPU_IS_6368 */
|
||||||
|
mask = CKCTL_6368_SPI_EN;
|
||||||
|
--- a/arch/mips/bcm63xx/dev-spi.c
|
||||||
|
+++ b/arch/mips/bcm63xx/dev-spi.c
|
||||||
|
@@ -34,6 +34,10 @@ static const unsigned long bcm6358_regs_
|
||||||
|
__GEN_SPI_REGS_TABLE(6358)
|
||||||
|
};
|
||||||
|
|
||||||
|
+static const unsigned long bcm6362_regs_spi[] = {
|
||||||
|
+ __GEN_SPI_REGS_TABLE(6362)
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
static const unsigned long bcm6368_regs_spi[] = {
|
||||||
|
__GEN_SPI_REGS_TABLE(6368)
|
||||||
|
};
|
||||||
|
@@ -49,6 +53,8 @@ static __init void bcm63xx_spi_regs_init
|
||||||
|
bcm63xx_regs_spi = bcm6348_regs_spi;
|
||||||
|
if (BCMCPU_IS_6358())
|
||||||
|
bcm63xx_regs_spi = bcm6358_regs_spi;
|
||||||
|
+ if (BCMCPU_IS_6362())
|
||||||
|
+ bcm63xx_regs_spi = bcm6362_regs_spi;
|
||||||
|
if (BCMCPU_IS_6368())
|
||||||
|
bcm63xx_regs_spi = bcm6368_regs_spi;
|
||||||
|
}
|
||||||
|
@@ -99,6 +105,9 @@ int __init bcm63xx_spi_register(void)
|
||||||
|
/* Set bus frequency */
|
||||||
|
spi_pdata.speed_hz = clk_get_rate(periph_clk);
|
||||||
|
|
||||||
|
+ if (BCMCPU_IS_6362())
|
||||||
|
+ spi_pdata.bus_num = 1;
|
||||||
|
+
|
||||||
|
spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
|
||||||
|
spi_resources[0].end = spi_resources[0].start;
|
||||||
|
spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
|
||||||
|
@@ -110,7 +119,7 @@ int __init bcm63xx_spi_register(void)
|
||||||
|
spi_pdata.msg_ctl_width = SPI_6338_MSG_CTL_WIDTH;
|
||||||
|
}
|
||||||
|
|
||||||
|
- if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
|
||||||
|
+ if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {
|
||||||
|
spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
|
||||||
|
spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
|
||||||
|
spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;
|
||||||
|
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
|
||||||
|
@@ -81,6 +81,9 @@ static inline unsigned long bcm63xx_spir
|
||||||
|
#ifdef CONFIG_BCM63XX_CPU_6358
|
||||||
|
__GEN_SPI_RSET(6358)
|
||||||
|
#endif
|
||||||
|
+#ifdef CONFIG_BCM63XX_CPU_6362
|
||||||
|
+ __GEN_SPI_RSET(6362)
|
||||||
|
+#endif
|
||||||
|
#ifdef CONFIG_BCM63XX_CPU_6368
|
||||||
|
__GEN_SPI_RSET(6368)
|
||||||
|
#endif
|
||||||
|
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||||
|
@@ -1215,6 +1215,22 @@
|
||||||
|
#define SPI_6358_MSG_TAIL 0x709
|
||||||
|
#define SPI_6358_RX_TAIL 0x70B
|
||||||
|
|
||||||
|
+/* BCM 6362 SPI core */
|
||||||
|
+#define SPI_6362_MSG_CTL 0x00 /* 16-bits register */
|
||||||
|
+#define SPI_6362_MSG_DATA 0x02
|
||||||
|
+#define SPI_6362_MSG_DATA_SIZE 0x21e
|
||||||
|
+#define SPI_6362_RX_DATA 0x400
|
||||||
|
+#define SPI_6362_RX_DATA_SIZE 0x220
|
||||||
|
+#define SPI_6362_CMD 0x700 /* 16-bits register */
|
||||||
|
+#define SPI_6362_INT_STATUS 0x702
|
||||||
|
+#define SPI_6362_INT_MASK_ST 0x703
|
||||||
|
+#define SPI_6362_INT_MASK 0x704
|
||||||
|
+#define SPI_6362_ST 0x705
|
||||||
|
+#define SPI_6362_CLK_CFG 0x706
|
||||||
|
+#define SPI_6362_FILL_BYTE 0x707
|
||||||
|
+#define SPI_6362_MSG_TAIL 0x709
|
||||||
|
+#define SPI_6362_RX_TAIL 0x70B
|
||||||
|
+
|
||||||
|
/* BCM 6358 SPI core */
|
||||||
|
#define SPI_6368_MSG_CTL 0x00 /* 16-bits register */
|
||||||
|
#define SPI_6368_MSG_CTL_WIDTH 16
|
||||||
@ -0,0 +1,84 @@
|
|||||||
|
From fb9e98936590637c26b66d60137a7b44b329a254 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jonas Gorski <jonas.gorski@gmail.com>
|
||||||
|
Date: Sun, 12 Feb 2012 14:40:56 +0100
|
||||||
|
Subject: [PATCH 59/84] MIPS: BCM63XX: enable USB for BCM6362
|
||||||
|
|
||||||
|
BCM6362 has the same USB controller as BCM6368.
|
||||||
|
|
||||||
|
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
|
||||||
|
---
|
||||||
|
arch/mips/bcm63xx/Kconfig | 2 ++
|
||||||
|
arch/mips/bcm63xx/clk.c | 4 ++++
|
||||||
|
arch/mips/bcm63xx/dev-usb-ehci.c | 3 ++-
|
||||||
|
arch/mips/bcm63xx/dev-usb-ohci.c | 2 +-
|
||||||
|
drivers/usb/host/ehci-bcm63xx.c | 2 +-
|
||||||
|
drivers/usb/host/ohci-bcm63xx.c | 2 +-
|
||||||
|
6 files changed, 11 insertions(+), 4 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/bcm63xx/Kconfig
|
||||||
|
+++ b/arch/mips/bcm63xx/Kconfig
|
||||||
|
@@ -27,6 +27,8 @@ config BCM63XX_CPU_6358
|
||||||
|
config BCM63XX_CPU_6362
|
||||||
|
bool "support 6362 CPU"
|
||||||
|
select HW_HAS_PCI
|
||||||
|
+ select USB_ARCH_HAS_OHCI if USB_SUPPORT
|
||||||
|
+ select USB_ARCH_HAS_EHCI if USB_SUPPORT
|
||||||
|
|
||||||
|
config BCM63XX_CPU_6368
|
||||||
|
bool "support 6368 CPU"
|
||||||
|
--- a/arch/mips/bcm63xx/clk.c
|
||||||
|
+++ b/arch/mips/bcm63xx/clk.c
|
||||||
|
@@ -178,6 +178,8 @@ static void usbh_set(struct clk *clk, in
|
||||||
|
{
|
||||||
|
if (BCMCPU_IS_6348())
|
||||||
|
bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
|
||||||
|
+ else if (BCMCPU_IS_6362())
|
||||||
|
+ bcm_hwclock_set(CKCTL_6362_USBH_EN, enable);
|
||||||
|
else if (BCMCPU_IS_6368())
|
||||||
|
bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
|
||||||
|
}
|
||||||
|
--- a/arch/mips/bcm63xx/dev-usb-ehci.c
|
||||||
|
+++ b/arch/mips/bcm63xx/dev-usb-ehci.c
|
||||||
|
@@ -39,7 +39,8 @@ static struct platform_device bcm63xx_eh
|
||||||
|
|
||||||
|
int __init bcm63xx_ehci_register(void)
|
||||||
|
{
|
||||||
|
- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368())
|
||||||
|
+ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6358() && !BCMCPU_IS_6362() &&
|
||||||
|
+ !BCMCPU_IS_6368())
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0);
|
||||||
|
--- a/arch/mips/bcm63xx/dev-usb-ohci.c
|
||||||
|
+++ b/arch/mips/bcm63xx/dev-usb-ohci.c
|
||||||
|
@@ -40,7 +40,7 @@ static struct platform_device bcm63xx_oh
|
||||||
|
int __init bcm63xx_ohci_register(void)
|
||||||
|
{
|
||||||
|
if (!BCMCPU_IS_6328() && !BCMCPU_IS_6348() && !BCMCPU_IS_6358() &&
|
||||||
|
- !BCMCPU_IS_6368())
|
||||||
|
+ !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
ohci_resources[0].start = bcm63xx_regset_address(RSET_OHCI0);
|
||||||
|
--- a/drivers/usb/host/ehci-bcm63xx.c
|
||||||
|
+++ b/drivers/usb/host/ehci-bcm63xx.c
|
||||||
|
@@ -99,7 +99,7 @@ static int __devinit ehci_hcd_bcm63xx_dr
|
||||||
|
bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020,
|
||||||
|
USBH_PRIV_TEST_6358_REG);
|
||||||
|
|
||||||
|
- } else if (BCMCPU_IS_6328() || BCMCPU_IS_6368()) {
|
||||||
|
+ } else if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {
|
||||||
|
|
||||||
|
reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);
|
||||||
|
reg &= ~USBH_PRIV_SWAP_EHCI_DATA_MASK;
|
||||||
|
--- a/drivers/usb/host/ohci-bcm63xx.c
|
||||||
|
+++ b/drivers/usb/host/ohci-bcm63xx.c
|
||||||
|
@@ -94,7 +94,7 @@ static int __devinit ohci_hcd_bcm63xx_dr
|
||||||
|
bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020,
|
||||||
|
USBH_PRIV_TEST_6358_REG);
|
||||||
|
|
||||||
|
- } else if (BCMCPU_IS_6328() || BCMCPU_IS_6368()) {
|
||||||
|
+ } else if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {
|
||||||
|
reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);
|
||||||
|
reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK;
|
||||||
|
reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK;
|
||||||
@ -0,0 +1,77 @@
|
|||||||
|
From bf9d506bd144b95f8bb4127350ab2db5fba9c12e Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jonas Gorski <jonas.gorski@gmail.com>
|
||||||
|
Date: Sun, 8 Jul 2012 21:07:12 +0200
|
||||||
|
Subject: [PATCH 60/84] MIPS: BCM63XX: enable enetsw for BCM6362
|
||||||
|
|
||||||
|
---
|
||||||
|
arch/mips/bcm63xx/clk.c | 7 ++++++-
|
||||||
|
arch/mips/bcm63xx/dev-enet.c | 6 ++++--
|
||||||
|
.../include/asm/mach-bcm63xx/bcm63xx_dev_enet.h | 1 +
|
||||||
|
3 files changed, 11 insertions(+), 3 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/mips/bcm63xx/clk.c
|
||||||
|
+++ b/arch/mips/bcm63xx/clk.c
|
||||||
|
@@ -120,11 +120,13 @@ static void enetsw_set(struct clk *clk,
|
||||||
|
{
|
||||||
|
u32 mask;
|
||||||
|
|
||||||
|
- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6368())
|
||||||
|
+ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
|
||||||
|
return;
|
||||||
|
|
||||||
|
if (BCMCPU_IS_6328())
|
||||||
|
mask = CKCTL_6328_ROBOSW_EN;
|
||||||
|
+ else if (BCMCPU_IS_6362())
|
||||||
|
+ mask = CKCTL_6362_ROBOSW_EN;
|
||||||
|
else
|
||||||
|
mask = CKCTL_6368_ROBOSW_EN | CKCTL_6368_SWPKT_USB_EN |
|
||||||
|
CKCTL_6368_SWPKT_SAR_EN;
|
||||||
|
@@ -137,6 +139,9 @@ static void enetsw_set(struct clk *clk,
|
||||||
|
if (BCMCPU_IS_6328()) {
|
||||||
|
reg = PERF_SOFTRESET_6328_REG;
|
||||||
|
mask = SOFTRESET_6328_ENETSW_MASK;
|
||||||
|
+ } else if (BCMCPU_IS_6362()) {
|
||||||
|
+ reg = PERF_SOFTRESET_6362_REG;
|
||||||
|
+ mask = SOFTRESET_6362_ENETSW_MASK;
|
||||||
|
} else {
|
||||||
|
reg = PERF_SOFTRESET_6368_REG;
|
||||||
|
mask = SOFTRESET_6368_ENETSW_MASK;
|
||||||
|
--- a/arch/mips/bcm63xx/dev-enet.c
|
||||||
|
+++ b/arch/mips/bcm63xx/dev-enet.c
|
||||||
|
@@ -141,7 +141,7 @@ static int __init register_shared(void)
|
||||||
|
shared_res[0].end = shared_res[0].start;
|
||||||
|
shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
|
||||||
|
|
||||||
|
- if (BCMCPU_IS_6328() || BCMCPU_IS_6368())
|
||||||
|
+ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
|
||||||
|
chan_count = 32;
|
||||||
|
else
|
||||||
|
chan_count = 16;
|
||||||
|
@@ -224,7 +224,7 @@ bcm63xx_enetsw_register(const struct bcm
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6368())
|
||||||
|
+ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
|
||||||
|
return -ENODEV;
|
||||||
|
|
||||||
|
ret = register_shared();
|
||||||
|
@@ -243,6 +243,8 @@ bcm63xx_enetsw_register(const struct bcm
|
||||||
|
|
||||||
|
if (BCMCPU_IS_6328())
|
||||||
|
enetsw_pd.num_ports = ENETSW_PORTS_6328;
|
||||||
|
+ else if (BCMCPU_IS_6362())
|
||||||
|
+ enetsw_pd.num_ports = ENETSW_PORTS_6362;
|
||||||
|
else if (BCMCPU_IS_6368())
|
||||||
|
enetsw_pd.num_ports = ENETSW_PORTS_6368;
|
||||||
|
|
||||||
|
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
|
||||||
|
@@ -44,6 +44,7 @@ struct bcm63xx_enet_platform_data {
|
||||||
|
*/
|
||||||
|
#define ENETSW_MAX_PORT 6
|
||||||
|
#define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
|
||||||
|
+#define ENETSW_PORTS_6362 6 /* 4 FE PHY + 2 RGMII */
|
||||||
|
#define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
|
||||||
|
|
||||||
|
#define ENETSW_RGMII_PORT0 4
|
||||||
@ -106,7 +106,7 @@
|
|||||||
#include <bcm63xx_cpu.h>
|
#include <bcm63xx_cpu.h>
|
||||||
#include <bcm63xx_dev_flash.h>
|
#include <bcm63xx_dev_flash.h>
|
||||||
#include <bcm63xx_dev_hsspi.h>
|
#include <bcm63xx_dev_hsspi.h>
|
||||||
@@ -150,6 +151,13 @@ int __init bcm63xx_flash_register(int nu
|
@@ -162,6 +163,13 @@ int __init bcm63xx_flash_register(int nu
|
||||||
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
|
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
|
||||||
val &= MPI_CSBASE_BASE_MASK;
|
val &= MPI_CSBASE_BASE_MASK;
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user