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mvebu: refresh patches for 6.1

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Remove the following patches:
100-ARM-dts-turris-omnia-configure-LED-0-pin-function-to [1]
101-ARM-dts-turris-omnia-enable-LED-controller-node [2]
702-net-next-ethernet-marvell-mvnetaMQPrioOffload [3]
703-net-next-ethernet-marvell-mvnetaMQPrioFlag [4]
704-net-next-ethernet-marvell-mvnetaMQPrioQueue [5]
705-net-next-ethernet-marvell-mvnetaMQPrioTCOffload [6]
710-v6.2-phy-marvell-phy-mvebu-a3700-comphy-Reset-COMPHY-regi [7]

Manually rebased:
902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU

All other patches automatically rebased

[1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=94a29bffdd59498382131fd428fed221f5c96def
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=40624346b7ae0c2b1209fc9993ea30699e512c50
[3] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=75fa71e3acadbb4ab5eda18505277eb9a1f69b23
[4] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=e7ca75fe6662f78bfeb0112671c812e4c7b8e214
[5] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=e9f7099d0730341b24c057acbf545dd019581db6
[6] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=2551dc9e398c37a15e52122d385c29a8b06be45f
[7] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=cd1e1735aeab49abc679218a79ee764c0d394880

Signed-off-by: Stefan Kalscheuer <stefan@stklcode.de>
This commit is contained in:
Stefan Kalscheuer 2023-06-18 17:01:00 +02:00 committed by Alexander Couzens
parent 04f6d674f6
commit 7f257296ec
26 changed files with 41 additions and 552 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
target/linux/mvebu/patches-6.1/100-ARM-dts-turris-omnia-configure-LED-0-pin-function-to.patch
View File

@ -1,38 +0,0 @@
From 81c0004a6433ff90fa6129418802c3c367e453c2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Mon, 4 Jul 2022 13:36:21 +0200
Subject: [PATCH 1/5] ARM: dts: turris-omnia: configure LED[0] pin function to
link/activity
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The marvell PHY driver changes the LED[0] pin function to "On - 1000
Mbps Link, Off - Else".
Turris Omnia expects that the function is "On - Link, Blink - Activity,
Off - No link".
Use the `marvell,reg-init` DT property to change the function.
In the future, once netdev trigger will support HW offloading, we will
be able to have this configured via the combination of PHY driver and
leds-turris-omnia driver.
Signed-off-by: Marek Behún <kabel@kernel.org>
---
arch/arm/boot/dts/armada-385-turris-omnia.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
@@ -396,7 +396,8 @@
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
- marvell,reg-init = <3 18 0 0x4985>;
+ marvell,reg-init = <3 18 0 0x4985>,
+ <3 16 0xfff0 0x0001>;
/* irq is connected to &pcawan pin 7 */
};

6
target/linux/mvebu/patches-6.1/100-aardvark-workaround-PCIe.patch
View File

@ -48,7 +48,7 @@ Cc: stable@vger.kernel.org
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -210,6 +210,8 @@ enum {
@@ -212,6 +212,8 @@ enum {
};
#define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44)
@ -57,7 +57,7 @@ Cc: stable@vger.kernel.org
/* PCIe core controller registers */
#define CTRL_CORE_BASE_ADDR 0x18000
@@ -558,6 +560,11 @@ static void advk_pcie_setup_hw(struct ad
@@ -560,6 +562,11 @@ static void advk_pcie_setup_hw(struct ad
PCIE_CORE_CTRL2_TD_ENABLE;
advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
@ -69,7 +69,7 @@ Cc: stable@vger.kernel.org
/* Set lane X1 */
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
reg &= ~LANE_CNT_MSK;
@@ -1580,6 +1587,9 @@ static irqreturn_t advk_pcie_irq_handler
@@ -1661,6 +1668,9 @@ static irqreturn_t advk_pcie_irq_handler
struct advk_pcie *pcie = arg;
u32 status;

48
target/linux/mvebu/patches-6.1/101-ARM-dts-turris-omnia-enable-LED-controller-node.patch
View File

@ -1,48 +0,0 @@
From fed7cef5e4f2df8c6a79bebf5da1fdd3783ff6f3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Mon, 4 Jul 2022 13:36:22 +0200
Subject: [PATCH] ARM: dts: turris-omnia: enable LED controller node
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The LED controller node is disabled because the leds-turris-omnia driver
does not support setting the LED blinking to be controlled by the MCU.
The patches for that have now been sent [1], so let's enable the node.
[1] https://lore.kernel.org/linux-leds/20220704105955.15474-1-kabel@kernel.org/T/
Signed-off-by: Marek Behún <kabel@kernel.org>
---
arch/arm/boot/dts/armada-385-turris-omnia.dts | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
@@ -194,15 +194,13 @@
reg = <0x2b>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "okay";
/*
* LEDs are controlled by MCU (STM32F0) at
* address 0x2b.
*
- * The driver does not support HW control mode
- * for the LEDs yet. Disable the LEDs for now.
- *
- * Also LED functions are not stable yet:
+ * LED functions are not stable yet:
* - there are 3 LEDs connected via MCU to PCIe
* ports. One of these ports supports mSATA.
* There is no mSATA nor PCIe function.
@@ -213,7 +211,6 @@
* B. Again there is no such function defined.
* For now we use LED_FUNCTION_INDICATOR
*/
- status = "disabled";
multi-led@0 {
reg = <0x0>;

4
target/linux/mvebu/patches-6.1/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch
View File

@ -28,7 +28,7 @@ Signed-off-by: Michael Gray <michael.gray@lantisproject.com>
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1727,6 +1727,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
@@ -1586,6 +1586,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
The command-line arguments provided by the boot loader will be
appended to the the device tree bootargs property.
@ -258,7 +258,7 @@ Signed-off-by: Michael Gray <michael.gray@lantisproject.com>
static int kernel_init(void *);
extern void init_IRQ(void);
@@ -991,6 +995,18 @@ asmlinkage __visible void __init __no_sa
@@ -992,6 +996,18 @@ asmlinkage __visible void __init __no_sa
page_alloc_init();
pr_notice("Kernel command line: %s\n", saved_command_line);

2
target/linux/mvebu/patches-6.1/301-mvebu-armada-38x-enable-libata-leds.patch
View File

@ -1,6 +1,6 @@
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -67,6 +67,7 @@ config MACH_ARMADA_38X
@@ -66,6 +66,7 @@ config MACH_ARMADA_38X
select HAVE_ARM_TWD if SMP
select MACH_MVEBU_V7
select PINCTRL_ARMADA_38X

2
target/linux/mvebu/patches-6.1/302-add_powertables.patch
View File

@ -667,7 +667,7 @@
pinctrl-0 = <&sdhci_pins>;
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -225,12 +225,100 @@
@@ -223,12 +223,100 @@
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";

4
target/linux/mvebu/patches-6.1/306-ARM-mvebu-385-ap-Add-partitions.patch
View File

@ -5,8 +5,8 @@ Subject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/armada-385-db-ap.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
arch/arm/boot/dts/armada-385-db-ap.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/arch/arm/boot/dts/armada-385-db-ap.dts
+++ b/arch/arm/boot/dts/armada-385-db-ap.dts

2
target/linux/mvebu/patches-6.1/307-armada-xp-linksys-mamba-broken-idle.patch
View File

@ -1,6 +1,6 @@
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -485,3 +485,7 @@
@@ -483,3 +483,7 @@
};
};
};

2
target/linux/mvebu/patches-6.1/308-armada-xp-linksys-mamba-wan.patch
View File

@ -1,6 +1,6 @@
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -387,7 +387,7 @@
@@ -385,7 +385,7 @@
port@4 {
reg = <4>;

2
target/linux/mvebu/patches-6.1/309-linksys-status-led.patch
View File

@ -39,7 +39,7 @@
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = &uart0;
@@ -197,7 +204,7 @@
@@ -195,7 +202,7 @@
pinctrl-0 = <&power_led_pin>;
pinctrl-names = "default";

4
target/linux/mvebu/patches-6.1/312-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch
View File

@ -5,8 +5,8 @@ Subject: ARM: dts: armada388-clearfog: emmc on clearfog base
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/boot/dts/armada-388-clearfog-base.dts | 1 +
.../dts/armada-38x-solidrun-microsom-emmc.dtsi | 62 ++++++++++++++++++++++
.../arm/boot/dts/armada-388-clearfog-base.dts | 1 +
.../armada-38x-solidrun-microsom-emmc.dtsi | 62 +++++++++++++++++++
2 files changed, 63 insertions(+)
create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi

4
target/linux/mvebu/patches-6.1/315-armada-xp-linksys-mamba-resize-kernel.patch
View File

@ -11,7 +11,7 @@ Signed-off-by: Tad Davanzo <tad@spotco.us>
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -456,9 +456,9 @@
@@ -454,9 +454,9 @@
reg = <0xa00000 0x2800000>; /* 40MB */
};
@ -23,7 +23,7 @@ Signed-off-by: Tad Davanzo <tad@spotco.us>
};
/* kernel2 overlaps with rootfs2 by design */
@@ -467,9 +467,9 @@
@@ -465,9 +465,9 @@
reg = <0x3200000 0x2800000>; /* 40MB */
};

4
target/linux/mvebu/patches-6.1/316-armada-370-dts-fix-crypto-engine.patch
View File

@ -1,6 +1,6 @@
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -234,7 +234,7 @@
@@ -254,7 +254,7 @@
clocks = <&gateclk 23>;
clock-names = "cesa0";
marvell,crypto-srams = <&crypto_sram>;
@ -9,7 +9,7 @@
};
};
@@ -255,12 +255,17 @@
@@ -275,12 +275,17 @@
* cpuidle workaround.
*/
idle-sram@0 {

4
target/linux/mvebu/patches-6.1/700-mvneta-tx-queue-workaround.patch
View File

@ -9,7 +9,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -5006,6 +5006,16 @@ static int mvneta_setup_tc(struct net_de
@@ -5222,6 +5222,16 @@ static int mvneta_setup_tc(struct net_de
}
}
@ -26,7 +26,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
static const struct net_device_ops mvneta_netdev_ops = {
.ndo_open = mvneta_open,
.ndo_stop = mvneta_stop,
@@ -5016,6 +5026,9 @@ static const struct net_device_ops mvnet
@@ -5232,6 +5242,9 @@ static const struct net_device_ops mvnet
.ndo_fix_features = mvneta_fix_features,
.ndo_get_stats64 = mvneta_get_stats64,
.ndo_eth_ioctl = mvneta_ioctl,

66
target/linux/mvebu/patches-6.1/702-net-next-ethernet-marvell-mvnetaMQPrioOffload.patch
View File

@ -1,66 +0,0 @@
From 75fa71e3acadbb4ab5eda18505277eb9a1f69b23 Mon Sep 17 00:00:00 2001
From: Maxime Chevallier <maxime.chevallier@bootlin.com>
Date: Fri, 26 Nov 2021 12:20:53 +0100
Subject: net: mvneta: Use struct tc_mqprio_qopt_offload for MQPrio
configuration
The struct tc_mqprio_qopt_offload is a container for struct tc_mqprio_qopt,
that allows passing extra parameters, such as traffic shaping. This commit
converts the current mqprio code to that new struct.
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/ethernet/marvell/mvneta.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
(limited to 'drivers/net/ethernet/marvell/mvneta.c')
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -38,6 +38,7 @@
#include <net/ipv6.h>
#include <net/tso.h>
#include <net/page_pool.h>
+#include <net/pkt_cls.h>
#include <linux/bpf_trace.h>
/* Registers */
@@ -4966,14 +4967,14 @@ static void mvneta_setup_rx_prio_map(str
}
static int mvneta_setup_mqprio(struct net_device *dev,
- struct tc_mqprio_qopt *qopt)
+ struct tc_mqprio_qopt_offload *mqprio)
{
struct mvneta_port *pp = netdev_priv(dev);
u8 num_tc;
int i;
- qopt->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
- num_tc = qopt->num_tc;
+ mqprio->qopt.hw = TC_MQPRIO_HW_OFFLOAD_TCS;
+ num_tc = mqprio->qopt.num_tc;
if (num_tc > rxq_number)
return -EINVAL;
@@ -4984,13 +4985,15 @@ static int mvneta_setup_mqprio(struct ne
return 0;
}
- memcpy(pp->prio_tc_map, qopt->prio_tc_map, sizeof(pp->prio_tc_map));
+ memcpy(pp->prio_tc_map, mqprio->qopt.prio_tc_map,
+ sizeof(pp->prio_tc_map));
mvneta_setup_rx_prio_map(pp);
- netdev_set_num_tc(dev, qopt->num_tc);
- for (i = 0; i < qopt->num_tc; i++)
- netdev_set_tc_queue(dev, i, qopt->count[i], qopt->offset[i]);
+ netdev_set_num_tc(dev, mqprio->qopt.num_tc);
+ for (i = 0; i < mqprio->qopt.num_tc; i++)
+ netdev_set_tc_queue(dev, i, mqprio->qopt.count[i],
+ mqprio->qopt.offset[i]);
return 0;
}

30
target/linux/mvebu/patches-6.1/703-net-next-ethernet-marvell-mvnetaMQPrioFlag.patch
View File

@ -1,30 +0,0 @@
From e7ca75fe6662f78bfeb0112671c812e4c7b8e214 Mon Sep 17 00:00:00 2001
From: Maxime Chevallier <maxime.chevallier@bootlin.com>
Date: Fri, 26 Nov 2021 12:20:54 +0100
Subject: net: mvneta: Don't force-set the offloading flag
The qopt->hw flag is set by the TC code according to the offloading mode
asked by user. Don't force-set it in the driver, but instead read it to
make sure we do what's asked.
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/ethernet/marvell/mvneta.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
(limited to 'drivers/net/ethernet/marvell/mvneta.c')
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -4973,7 +4973,9 @@ static int mvneta_setup_mqprio(struct ne
u8 num_tc;
int i;
- mqprio->qopt.hw = TC_MQPRIO_HW_OFFLOAD_TCS;
+ if (mqprio->qopt.hw != TC_MQPRIO_HW_OFFLOAD_TCS)
+ return 0;
+
num_tc = mqprio->qopt.num_tc;
if (num_tc > rxq_number)

97
target/linux/mvebu/patches-6.1/704-net-next-ethernet-marvell-mvnetaMQPrioQueue.patch
View File

@ -1,97 +0,0 @@
From e9f7099d0730341b24c057acbf545dd019581db6 Mon Sep 17 00:00:00 2001
From: Maxime Chevallier <maxime.chevallier@bootlin.com>
Date: Fri, 26 Nov 2021 12:20:55 +0100
Subject: net: mvneta: Allow having more than one queue per TC
The current mqprio implementation assumed that we are only using one
queue per TC. Use the offset and count parameters to allow using
multiple queues per TC. In that case, the controller will use a standard
round-robin algorithm to pick queues assigned to the same TC, with the
same priority.
This only applies to VLAN priorities in ingress traffic, each TC
corresponding to a vlan priority.
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/ethernet/marvell/mvneta.c | 35 ++++++++++++++++++++---------------
1 file changed, 20 insertions(+), 15 deletions(-)
(limited to 'drivers/net/ethernet/marvell/mvneta.c')
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -498,7 +498,6 @@ struct mvneta_port {
u8 mcast_count[256];
u16 tx_ring_size;
u16 rx_ring_size;
- u8 prio_tc_map[8];
phy_interface_t phy_interface;
struct device_node *dn;
@@ -4955,13 +4954,12 @@ static void mvneta_clear_rx_prio_map(str
mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, 0);
}
-static void mvneta_setup_rx_prio_map(struct mvneta_port *pp)
+static void mvneta_map_vlan_prio_to_rxq(struct mvneta_port *pp, u8 pri, u8 rxq)
{
- u32 val = 0;
- int i;
+ u32 val = mvreg_read(pp, MVNETA_VLAN_PRIO_TO_RXQ);
- for (i = 0; i < rxq_number; i++)
- val |= MVNETA_VLAN_PRIO_RXQ_MAP(i, pp->prio_tc_map[i]);
+ val &= ~MVNETA_VLAN_PRIO_RXQ_MAP(pri, 0x7);
+ val |= MVNETA_VLAN_PRIO_RXQ_MAP(pri, rxq);
mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, val);
}
@@ -4970,8 +4968,8 @@ static int mvneta_setup_mqprio(struct ne
struct tc_mqprio_qopt_offload *mqprio)
{
struct mvneta_port *pp = netdev_priv(dev);
+ int rxq, tc;
u8 num_tc;
- int i;
if (mqprio->qopt.hw != TC_MQPRIO_HW_OFFLOAD_TCS)
return 0;
@@ -4981,21 +4979,28 @@ static int mvneta_setup_mqprio(struct ne
if (num_tc > rxq_number)
return -EINVAL;
+ mvneta_clear_rx_prio_map(pp);
+
if (!num_tc) {
- mvneta_clear_rx_prio_map(pp);
netdev_reset_tc(dev);
return 0;
}
- memcpy(pp->prio_tc_map, mqprio->qopt.prio_tc_map,
- sizeof(pp->prio_tc_map));
+ netdev_set_num_tc(dev, mqprio->qopt.num_tc);
- mvneta_setup_rx_prio_map(pp);
+ for (tc = 0; tc < mqprio->qopt.num_tc; tc++) {
+ netdev_set_tc_queue(dev, tc, mqprio->qopt.count[tc],
+ mqprio->qopt.offset[tc]);
+
+ for (rxq = mqprio->qopt.offset[tc];
+ rxq < mqprio->qopt.count[tc] + mqprio->qopt.offset[tc];
+ rxq++) {
+ if (rxq >= rxq_number)
+ return -EINVAL;
- netdev_set_num_tc(dev, mqprio->qopt.num_tc);
- for (i = 0; i < mqprio->qopt.num_tc; i++)
- netdev_set_tc_queue(dev, i, mqprio->qopt.count[i],
- mqprio->qopt.offset[i]);
+ mvneta_map_vlan_prio_to_rxq(pp, tc, rxq);
+ }
+ }
return 0;
}

182
target/linux/mvebu/patches-6.1/705-net-next-ethernet-marvell-mvnetaMQPrioTCOffload.patch
View File

@ -1,182 +0,0 @@
From 2551dc9e398c37a15e52122d385c29a8b06be45f Mon Sep 17 00:00:00 2001
From: Maxime Chevallier <maxime.chevallier@bootlin.com>
Date: Fri, 26 Nov 2021 12:20:56 +0100
Subject: net: mvneta: Add TC traffic shaping offload
The mvneta controller is able to do some tocken-bucket per-queue traffic
shaping. This commit adds support for setting these using the TC mqprio
interface.
The token-bucket parameters are customisable, but the current
implementation configures them to have a 10kbps resolution for the
rate limitation, since it allows to cover the whole range of max_rate
values from 10kbps to 5Gbps with 10kbps increments.
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/ethernet/marvell/mvneta.c | 120 +++++++++++++++++++++++++++++++++-
1 file changed, 119 insertions(+), 1 deletion(-)
(limited to 'drivers/net/ethernet/marvell/mvneta.c')
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -248,12 +248,39 @@
#define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
#define MVNETA_PORT_TX_RESET 0x3cf0
#define MVNETA_PORT_TX_DMA_RESET BIT(0)
+#define MVNETA_TXQ_CMD1_REG 0x3e00
+#define MVNETA_TXQ_CMD1_BW_LIM_SEL_V1 BIT(3)
+#define MVNETA_TXQ_CMD1_BW_LIM_EN BIT(0)
+#define MVNETA_REFILL_NUM_CLK_REG 0x3e08
+#define MVNETA_REFILL_MAX_NUM_CLK 0x0000ffff
#define MVNETA_TX_MTU 0x3e0c
#define MVNETA_TX_TOKEN_SIZE 0x3e14
#define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
+#define MVNETA_TXQ_BUCKET_REFILL_REG(q) (0x3e20 + ((q) << 2))
+#define MVNETA_TXQ_BUCKET_REFILL_PERIOD_MASK 0x3ff00000
+#define MVNETA_TXQ_BUCKET_REFILL_PERIOD_SHIFT 20
+#define MVNETA_TXQ_BUCKET_REFILL_VALUE_MAX 0x0007ffff
#define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
#define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
+/* The values of the bucket refill base period and refill period are taken from
+ * the reference manual, and adds up to a base resolution of 10Kbps. This allows
+ * to cover all rate-limit values from 10Kbps up to 5Gbps
+ */
+
+/* Base period for the rate limit algorithm */
+#define MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS 100
+
+/* Number of Base Period to wait between each bucket refill */
+#define MVNETA_TXQ_BUCKET_REFILL_PERIOD 1000
+
+/* The base resolution for rate limiting, in bps. Any max_rate value should be
+ * a multiple of that value.
+ */
+#define MVNETA_TXQ_RATE_LIMIT_RESOLUTION (NSEC_PER_SEC / \
+ (MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS * \
+ MVNETA_TXQ_BUCKET_REFILL_PERIOD))
+
#define MVNETA_LPI_CTRL_0 0x2cc0
#define MVNETA_LPI_CTRL_1 0x2cc4
#define MVNETA_LPI_REQUEST_ENABLE BIT(0)
@@ -4964,11 +4991,74 @@ static void mvneta_map_vlan_prio_to_rxq(
mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, val);
}
+static int mvneta_enable_per_queue_rate_limit(struct mvneta_port *pp)
+{
+ unsigned long core_clk_rate;
+ u32 refill_cycles;
+ u32 val;
+
+ core_clk_rate = clk_get_rate(pp->clk);
+ if (!core_clk_rate)
+ return -EINVAL;
+
+ refill_cycles = MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS /
+ (NSEC_PER_SEC / core_clk_rate);
+
+ if (refill_cycles > MVNETA_REFILL_MAX_NUM_CLK)
+ return -EINVAL;
+
+ /* Enable bw limit algorithm version 3 */
+ val = mvreg_read(pp, MVNETA_TXQ_CMD1_REG);
+ val &= ~(MVNETA_TXQ_CMD1_BW_LIM_SEL_V1 | MVNETA_TXQ_CMD1_BW_LIM_EN);
+ mvreg_write(pp, MVNETA_TXQ_CMD1_REG, val);
+
+ /* Set the base refill rate */
+ mvreg_write(pp, MVNETA_REFILL_NUM_CLK_REG, refill_cycles);
+
+ return 0;
+}
+
+static void mvneta_disable_per_queue_rate_limit(struct mvneta_port *pp)
+{
+ u32 val = mvreg_read(pp, MVNETA_TXQ_CMD1_REG);
+
+ val |= (MVNETA_TXQ_CMD1_BW_LIM_SEL_V1 | MVNETA_TXQ_CMD1_BW_LIM_EN);
+ mvreg_write(pp, MVNETA_TXQ_CMD1_REG, val);
+}
+
+static int mvneta_setup_queue_rates(struct mvneta_port *pp, int queue,
+ u64 min_rate, u64 max_rate)
+{
+ u32 refill_val, rem;
+ u32 val = 0;
+
+ /* Convert to from Bps to bps */
+ max_rate *= 8;
+
+ if (min_rate)
+ return -EINVAL;
+
+ refill_val = div_u64_rem(max_rate, MVNETA_TXQ_RATE_LIMIT_RESOLUTION,
+ &rem);
+
+ if (rem || !refill_val ||
+ refill_val > MVNETA_TXQ_BUCKET_REFILL_VALUE_MAX)
+ return -EINVAL;
+
+ val = refill_val;
+ val |= (MVNETA_TXQ_BUCKET_REFILL_PERIOD <<
+ MVNETA_TXQ_BUCKET_REFILL_PERIOD_SHIFT);
+
+ mvreg_write(pp, MVNETA_TXQ_BUCKET_REFILL_REG(queue), val);
+
+ return 0;
+}
+
static int mvneta_setup_mqprio(struct net_device *dev,
struct tc_mqprio_qopt_offload *mqprio)
{
struct mvneta_port *pp = netdev_priv(dev);
- int rxq, tc;
+ int rxq, txq, tc, ret;
u8 num_tc;
if (mqprio->qopt.hw != TC_MQPRIO_HW_OFFLOAD_TCS)
@@ -4982,6 +5072,7 @@ static int mvneta_setup_mqprio(struct ne
mvneta_clear_rx_prio_map(pp);
if (!num_tc) {
+ mvneta_disable_per_queue_rate_limit(pp);
netdev_reset_tc(dev);
return 0;
}
@@ -5002,6 +5093,33 @@ static int mvneta_setup_mqprio(struct ne
}
}
+ if (mqprio->shaper != TC_MQPRIO_SHAPER_BW_RATE) {
+ mvneta_disable_per_queue_rate_limit(pp);
+ return 0;
+ }
+
+ if (mqprio->qopt.num_tc > txq_number)
+ return -EINVAL;
+
+ ret = mvneta_enable_per_queue_rate_limit(pp);
+ if (ret)
+ return ret;
+
+ for (tc = 0; tc < mqprio->qopt.num_tc; tc++) {
+ for (txq = mqprio->qopt.offset[tc];
+ txq < mqprio->qopt.count[tc] + mqprio->qopt.offset[tc];
+ txq++) {
+ if (txq >= txq_number)
+ return -EINVAL;
+
+ ret = mvneta_setup_queue_rates(pp, txq,
+ mqprio->min_rate[tc],
+ mqprio->max_rate[tc]);
+ if (ret)
+ return ret;
+ }
+ }
+
return 0;
}

50
target/linux/mvebu/patches-6.1/710-v6.2-phy-marvell-phy-mvebu-a3700-comphy-Reset-COMPHY-regi.patch
View File

@ -1,50 +0,0 @@
From b01d622d76134e9401970ffd3fbbb9a7051f976a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
Date: Tue, 20 Sep 2022 14:11:54 +0200
Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Reset COMPHY registers
before USB 3.0 power on
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Turris MOX board with older ARM Trusted Firmware version v1.5 is not able
to detect any USB 3.0 device connected to USB-A port on Mox-A module after
commit 0a6fc70d76bd ("phy: marvell: phy-mvebu-a3700-comphy: Remove broken
reset support"). On the other hand USB 2.0 devices connected to the same
USB-A port are working fine.
It looks as if the older firmware configures COMPHY registers for USB 3.0
somehow incompatibly for kernel driver. Experiments show that resetting
COMPHY registers via setting SFT_RST auto-clearing bit in COMPHY_SFT_RESET
register fixes this issue.
Reset the COMPHY in mvebu_a3700_comphy_usb3_power_on() function as a first
step after selecting COMPHY lane and USB 3.0 function. With this change
Turris MOX board can successfully detect USB 3.0 devices again.
Before the above mentioned commit this reset was implemented in PHY reset
method, so this is the reason why there was no issue with older firmware
version then.
Fixes: 0a6fc70d76bd ("phy: marvell: phy-mvebu-a3700-comphy: Remove broken reset support")
Reported-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Shin'ichiro Kawasaki <shinichiro.kawasaki@wdc.com>
Link: https://lore.kernel.org/r/20220920121154.30115-1-pali@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 3 +++
1 file changed, 3 insertions(+)
--- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
@@ -826,6 +826,9 @@ mvebu_a3700_comphy_usb3_power_on(struct
if (ret)
return ret;
+ /* COMPHY register reset (cleared automatically) */
+ comphy_lane_reg_set(lane, COMPHY_SFT_RESET, SFT_RST, SFT_RST);
+
/*
* 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The
* register belong to UTMI module, so it is set in UTMI phy driver.

6
target/linux/mvebu/patches-6.1/801-pci-mvebu-time-out-reset-on-link-up.patch
View File

@ -13,7 +13,7 @@ Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -1023,6 +1023,7 @@ static int mvebu_pcie_powerup(struct mve
@@ -1414,6 +1414,7 @@ static int mvebu_pcie_powerup(struct mve
if (port->reset_gpio) {
u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
@ -21,7 +21,7 @@ Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
of_property_read_u32(port->dn, "reset-delay-us",
&reset_udelay);
@@ -1030,7 +1031,13 @@ static int mvebu_pcie_powerup(struct mve
@@ -1421,7 +1422,13 @@ static int mvebu_pcie_powerup(struct mve
udelay(100);
gpiod_set_value_cansleep(port->reset_gpio, 0);
@ -36,7 +36,7 @@ Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
}
return 0;
@@ -1190,15 +1197,16 @@ static int mvebu_pcie_probe(struct platf
@@ -1538,15 +1545,16 @@ static int mvebu_pcie_probe(struct platf
if (!child)
continue;

2
target/linux/mvebu/patches-6.1/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch
View File

@ -207,7 +207,7 @@ Cc: Robert Marko <robert.marko@sartura.hr>
+ };
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -519,6 +519,8 @@ patternProperties:
@@ -579,6 +579,8 @@ patternProperties:
description: IC Plus Corp.
"^idt,.*":
description: Integrated Device Technologies, Inc.

16
target/linux/mvebu/patches-6.1/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch
View File

@ -16,17 +16,17 @@ Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Robert Marko <robert.marko@sartura.hr>
---
drivers/mfd/Kconfig | 8 +
drivers/mfd/Kconfig | 9 +
drivers/mfd/Makefile | 1 +
drivers/mfd/iei-wt61p803-puzzle.c | 908 ++++++++++++++++++++++++
include/linux/mfd/iei-wt61p803-puzzle.h | 66 ++
4 files changed, 983 insertions(+)
4 files changed, 984 insertions(+)
create mode 100644 drivers/mfd/iei-wt61p803-puzzle.c
create mode 100644 include/linux/mfd/iei-wt61p803-puzzle.h
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -2189,6 +2189,15 @@ config SGI_MFD_IOC3
@@ -2221,6 +2221,15 @@ config SGI_MFD_IOC3
If you have an SGI Origin, Octane, or a PCI IOC3 card,
then say Y. Otherwise say N.
@ -44,14 +44,14 @@ Cc: Robert Marko <robert.marko@sartura.hr>
depends on SPI_MASTER
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -237,6 +237,7 @@ obj-$(CONFIG_MFD_DLN2) += dln2.o
obj-$(CONFIG_MFD_RT4831) += rt4831.o
@@ -244,6 +244,7 @@ obj-$(CONFIG_MFD_RT4831) += rt4831.o
obj-$(CONFIG_MFD_RT5033) += rt5033.o
obj-$(CONFIG_MFD_RT5120) += rt5120.o
obj-$(CONFIG_MFD_SKY81452) += sky81452.o
+obj-$(CONFIG_MFD_IEI_WT61P803_PUZZLE) += iei-wt61p803-puzzle.o
+obj-$(CONFIG_MFD_IEI_WT61P803_PUZZLE) += iei-wt61p803-puzzle.o
intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o
obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
obj-$(CONFIG_INTEL_SOC_PMIC) += intel_soc_pmic_crc.o
obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o
--- /dev/null
+++ b/drivers/mfd/iei-wt61p803-puzzle.c
@@ -0,0 +1,908 @@

8
target/linux/mvebu/patches-6.1/903-drivers-hwmon-Add-the-IEI-WT61P803-PUZZLE-HWMON-driv.patch
View File

@ -20,13 +20,13 @@ Cc: Robert Marko <robert.marko@sartura.hr>
---
drivers/hwmon/Kconfig | 8 +
drivers/hwmon/Makefile | 1 +
drivers/hwmon/iei-wt61p803-puzzle-hwmon.c | 413 ++++++++++++++++++++++
3 files changed, 422 insertions(+)
drivers/hwmon/iei-wt61p803-puzzle-hwmon.c | 445 ++++++++++++++++++++++
3 files changed, 454 insertions(+)
create mode 100644 drivers/hwmon/iei-wt61p803-puzzle-hwmon.c
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -732,6 +732,14 @@ config SENSORS_IBMPOWERNV
@@ -755,6 +755,14 @@ config SENSORS_IBMPOWERNV
This driver can also be built as a module. If so, the module
will be called ibmpowernv.
@ -43,7 +43,7 @@ Cc: Robert Marko <robert.marko@sartura.hr>
depends on IIO
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -84,6 +84,7 @@ obj-$(CONFIG_SENSORS_HIH6130) += hih6130
@@ -87,6 +87,7 @@ obj-$(CONFIG_SENSORS_HIH6130) += hih6130
obj-$(CONFIG_SENSORS_ULTRA45) += ultra45_env.o
obj-$(CONFIG_SENSORS_I5500) += i5500_temp.o
obj-$(CONFIG_SENSORS_I5K_AMB) += i5k_amb.o

4
target/linux/mvebu/patches-6.1/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch
View File

@ -30,7 +30,7 @@ Cc: Robert Marko <robert.marko@sartura.hr>
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -306,6 +306,14 @@ config LEDS_IPAQ_MICRO
@@ -299,6 +299,14 @@ config LEDS_IPAQ_MICRO
Choose this option if you want to use the notification LED on
Compaq/HP iPAQ h3100 and h3600.
@ -47,7 +47,7 @@ Cc: Robert Marko <robert.marko@sartura.hr>
depends on LEDS_CLASS
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx.
@@ -32,6 +32,7 @@ obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx.
obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o
obj-$(CONFIG_LEDS_IP30) += leds-ip30.o
obj-$(CONFIG_LEDS_IPAQ_MICRO) += leds-ipaq-micro.o

4
target/linux/mvebu/patches-6.1/906-Documentation-hwmon-Add-iei-wt61p803-puzzle-hwmon-dr.patch
View File

@ -64,11 +64,11 @@ Cc: Robert Marko <robert.marko@sartura.hr>
+================= == =====================================================
--- a/Documentation/hwmon/index.rst
+++ b/Documentation/hwmon/index.rst
@@ -74,6 +74,7 @@ Hardware Monitoring Kernel Drivers
@@ -77,6 +77,7 @@ Hardware Monitoring Kernel Drivers
ibmaem
ibm-cffps
ibmpowernv
+ iei-wt61p803-puzzle-hwmon
ina209
ina2xx
ina3221
ina238

2
target/linux/mvebu/patches-6.1/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch
View File

@ -16,7 +16,7 @@ Cc: Robert Marko <robert.marko@sartura.hr>
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9063,6 +9063,22 @@ F: include/net/nl802154.h
@@ -9900,6 +9900,22 @@ F: include/net/nl802154.h
F: net/ieee802154/
F: net/mac802154/